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rtl8188eu: Convert C90 comments to kernel form for hal/*.c

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-07-10 13:25:07 -05:00
parent e5113c831c
commit fe06a8b006
30 changed files with 4334 additions and 6166 deletions
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22
hal/Hal8188EPwrSeq.c
View file

@ -24,21 +24,21 @@
/*
drivers should parse below arrays and do the corresponding actions
*/
//3 Power on Array
/* 3 Power on Array */
WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_CARDEMU_TO_ACT
RTL8188E_TRANS_END
};
//3Radio off Array
/* 3Radio off Array */
WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_END
};
//3Card Disable Array
/* 3Card Disable Array */
WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
@ -46,7 +46,7 @@ WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8
RTL8188E_TRANS_END
};
//3 Card Enable Array
/* 3 Card Enable Array */
WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_CARDDIS_TO_CARDEMU
@ -54,7 +54,7 @@ WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL81
RTL8188E_TRANS_END
};
//3Suspend Array
/* 3Suspend Array */
WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
@ -62,7 +62,7 @@ WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_
RTL8188E_TRANS_END
};
//3 Resume Array
/* 3 Resume Array */
WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_SUS_TO_CARDEMU
@ -71,7 +71,7 @@ WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_T
};
//3HWPDN Array
/* 3HWPDN Array */
WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
@ -79,18 +79,18 @@ WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TR
RTL8188E_TRANS_END
};
//3 Enter LPS
/* 3 Enter LPS */
WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
//FW behavior
/* FW behavior */
RTL8188E_TRANS_ACT_TO_LPS
RTL8188E_TRANS_END
};
//3 Leave LPS
/* 3 Leave LPS */
WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
{
//FW behavior
/* FW behavior */
RTL8188E_TRANS_LPS_TO_ACT
RTL8188E_TRANS_END
};

273
hal/Hal8188ERateAdaptive.c
View file

@ -15,137 +15,136 @@ Major Change History:
--*/
#include "odm_precomp.h"
//#if ( DM_ODM_SUPPORT_TYPE == ODM_MP)
//#include "Mp_Precomp.h"
//#endif
/* if ( DM_ODM_SUPPORT_TYPE == ODM_MP) */
/* include "Mp_Precomp.h" */
/* endif */
#if (RATE_ADAPTIVE_SUPPORT == 1)
// Rate adaptive parameters
/* Rate adaptive parameters */
static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0
{6,5,4,3,0,4},//86 , idx=1
{6,5,4,2,0,4},//81 , idx=2
{8,7,6,4,0,6},//75 , idx=3
{10,9,8,6,0,8},//71 , idx=4
{10,9,8,4,0,8},//66 , idx=5
{10,9,8,2,0,8},//62 , idx=6
{10,9,8,0,0,8},//59 , idx=7
{18,17,16,8,0,16},//53 , idx=8
{26,25,24,16,0,24},//50 , idx=9
{34,33,32,24,0,32},//47 , idx=0x0a
//{34,33,32,16,0,32},//43 , idx=0x0b
//{34,33,32,8,0,32},//40 , idx=0x0c
//{34,33,28,8,0,32},//37 , idx=0x0d
//{34,33,20,8,0,32},//32 , idx=0x0e
//{34,32,24,8,0,32},//26 , idx=0x0f
//{49,48,32,16,0,48},//20 , idx=0x10
//{49,48,24,0,0,48},//17 , idx=0x11
//{49,47,16,16,0,48},//15 , idx=0x12
//{49,44,16,16,0,48},//12 , idx=0x13
//{49,40,16,0,0,48},//9 , idx=0x14
{34,31,28,20,0,32},//43 , idx=0x0b
{34,31,27,18,0,32},//40 , idx=0x0c
{34,31,26,16,0,32},//37 , idx=0x0d
{34,30,22,16,0,32},//32 , idx=0x0e
{34,30,24,16,0,32},//26 , idx=0x0f
{49,46,40,16,0,48},//20 , idx=0x10
{49,45,32,0,0,48},//17 , idx=0x11
{49,45,22,18,0,48},//15 , idx=0x12
{49,40,24,16,0,48},//12 , idx=0x13
{49,32,18,12,0,48},//9 , idx=0x14
{49,22,18,14,0,48},//6 , idx=0x15
{49,16,16,0,0,48}};//3 //3, idx=0x16
static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {
{5,4,3,2,0,3},/* 92 , idx=0 */
{6,5,4,3,0,4},/* 86 , idx=1 */
{6,5,4,2,0,4},/* 81 , idx=2 */
{8,7,6,4,0,6},/* 75 , idx=3 */
{10,9,8,6,0,8},/* 71 , idx=4 */
{10,9,8,4,0,8},/* 66 , idx=5 */
{10,9,8,2,0,8},/* 62 , idx=6 */
{10,9,8,0,0,8},/* 59 , idx=7 */
{18,17,16,8,0,16},/* 53 , idx=8 */
{26,25,24,16,0,24},/* 50 , idx=9 */
{34,33,32,24,0,32},/* 47 , idx=0x0a */
{34,31,28,20,0,32},/* 43 , idx=0x0b */
{34,31,27,18,0,32},/* 40 , idx=0x0c */
{34,31,26,16,0,32},/* 37 , idx=0x0d */
{34,30,22,16,0,32},/* 32 , idx=0x0e */
{34,30,24,16,0,32},/* 26 , idx=0x0f */
{49,46,40,16,0,48},/* 20 , idx=0x10 */
{49,45,32,0,0,48},/* 17 , idx=0x11 */
{49,45,22,18,0,48},/* 15 , idx=0x12 */
{49,40,24,16,0,48},/* 12 , idx=0x13 */
{49,32,18,12,0,48},/* 9 , idx=0x14 */
{49,22,18,14,0,48},/* 6 , idx=0x15 */
{49,16,16,0,0,48}};/* 3, idx=0x16 */
static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up
static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; /* 12% for rate up */
static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {
{4,4,4,5,4,4,5,7,7,7,8,0x0a, /* SS>TH */
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SS<TH
5,5,7,7,8,0x0b,0x0d,0x0f}, /* 0329 R01 */
{0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, /* SS<TH */
0x0e,0x0f,0x10,0x10,0x11,0x14,0x14,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x10,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x14, // SS>TH
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {
0x10,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x14, /* SS>TH */
0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
static u1Byte RSSI_THRESHOLD[RATESIZE] = {
0,0,0,0,
0,0,0,0,0,0x24,0x26,0x2a,
0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};
#else
// wilson modify
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
/* wilson modify */
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {
{4,4,4,5,4,4,5,7,7,7,8,0x0a, /* SS>TH */
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SS<TH
5,5,7,7,8,0x0b,0x0d,0x0f}, /* 0329 R01 */
{0x0a,0x0a,0x0b,0x0c,0x0a,
0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, /* SS<TH */
0x0b,0x0c,0x0d,0x0e,0x0f,0x11,0x13,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, // SS>TH
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {
0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,
0x0f,0x0f,0x10,0x12,0x13,0x14, /* SS>TH */
0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
static u1Byte RSSI_THRESHOLD[RATESIZE] = {
0,0,0,0,
0,0,0,0,0,0x24,0x26,0x2a,
0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};
#endif
/*static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
0,0,0,0,0,0x24,0x26,0x2a,
0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/
static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16,
static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {
4,4,8,16,
24,36,48,72,96,144,192,216,
60,80,100,160,240,400,560,640,
300,320,480,720,1000,1200,1600,2000};
static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8,
static u2Byte N_THRESHOLD_LOW[RATESIZE] = {
2,2,4,8,
12,18,24,36,48,72,96,108,
30,40,50,80,120,200,280,320,
150,160,240,360,500,600,800,1000};
static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
static u1Byte TRYING_NECESSARY[RATESIZE] = {
2,2,2,2,
2,2,3,3,4,4,5,7,
4,4,7,10,10,12,12,18,
5,7,7,8,11,18,36,60}; // 0329 // 1207
5,7,7,8,11,18,36,60}; /* 0329 1207 */
static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
static u1Byte DROPING_NECESSARY[RATESIZE] = {
1,1,1,1,
1,2,3,4,5,6,7,8,
1,2,3,4,5,6,7,8,
5,6,7,8,9,10,11,12};
static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode
0x0f8ff010, // 1: 40M GN mode
0x0f8ff005, // 2: BN mode/ 40M BGN mode
0x0f8ff000, // 3: N mode
0x00000ff5, // 4: BG mode
0x00000ff0, // 5: G mode
0x0000000d, // 6: B mode
0, // 7:
0, // 8:
0, // 9:
0, // 10:
0, // 11:
0, // 12:
0, // 13:
0, // 14:
0, // 15:
static u4Byte INIT_RATE_FALLBACK_TABLE[16]={
0x0f8ff015, /* 0: 40M BGN mode */
0x0f8ff010, /* 1: 40M GN mode */
0x0f8ff005, /* 2: BN mode/ 40M BGN mode */
0x0f8ff000, /* 3: N mode */
0x00000ff5, /* 4: BG mode */
0x00000ff0, /* 5: G mode */
0x0000000d, /* 6: B mode */
0, /* 7: */
0, /* 8: */
0, /* 9: */
0, /* 10: */
0, /* 11: */
0, /* 12: */
0, /* 13: */
0, /* 14: */
0, /* 15: */
};
static u1Byte PendingForRateUpFail[5] = {2,10,24,40,60};
static u2Byte DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms
static u2Byte DynamicTxRPTTiming[6] = {
0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; /* 200ms-1200ms */
// End Rate adaptive parameters
/* End Rate adaptive parameters */
static void
odm_SetTxRPTTiming_8188E(
static void odm_SetTxRPTTiming_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo,
u1Byte extend
@ -157,14 +156,14 @@ odm_SetTxRPTTiming_8188E(
if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
break;
if (extend==0) // back to default timing
idx=0; //200ms
else if (extend==1) {// increase the timing
if (extend==0) /* back to default timing */
idx=0; /* 200ms */
else if (extend==1) {/* increase the timing */
idx+=1;
if (idx>5)
idx=5;
}
else if (extend==2) {// decrease the timing
else if (extend==2) {/* decrease the timing */
if (idx!=0)
idx-=1;
}
@ -173,8 +172,7 @@ odm_SetTxRPTTiming_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime=0x%x\n", pRaInfo->RptTime));
}
static int
odm_RateDown_8188E(
static int odm_RateDown_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
)
@ -195,41 +193,28 @@ odm_RateDown_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n",
RateID, LowestRate, HighestRate, pRaInfo->RateSGI));
if (RateID > HighestRate)
{
if (RateID > HighestRate) {
RateID=HighestRate;
}
else if (pRaInfo->RateSGI)
{
} else if (pRaInfo->RateSGI) {
pRaInfo->RateSGI=0;
}
else if (RateID > LowestRate)
{
if (RateID > 0)
{
for (i=RateID-1; i>LowestRate;i--)
{
if (pRaInfo->RAUseRate & BIT(i))
{
} else if (RateID > LowestRate) {
if (RateID > 0) {
for (i=RateID-1; i>LowestRate;i--) {
if (pRaInfo->RAUseRate & BIT(i)) {
RateID=i;
goto RateDownFinish;
}
}
}
}
else if (RateID <= LowestRate)
{
} else if (RateID <= LowestRate) {
RateID = LowestRate;
}
RateDownFinish:
if (pRaInfo->RAWaitingCounter==1){
pRaInfo->RAWaitingCounter+=1;
pRaInfo->RAPendingCounter+=1;
}
else if (pRaInfo->RAWaitingCounter==0){
}
else{
} else if (pRaInfo->RAWaitingCounter==0){
} else {
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
@ -246,8 +231,7 @@ RateDownFinish:
return 0;
}
static int
odm_RateUp_8188E(
static int odm_RateUp_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
)
@ -256,8 +240,7 @@ odm_RateUp_8188E(
u1Byte i;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E()\n"));
if (NULL == pRaInfo)
{
if (NULL == pRaInfo) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n"));
return -1;
}
@ -269,39 +252,29 @@ odm_RateUp_8188E(
if (pRaInfo->RAWaitingCounter==1){
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
else if (pRaInfo->RAWaitingCounter>1){
} else if (pRaInfo->RAWaitingCounter>1){
pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA;
goto RateUpfinish;
}
odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 0);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E():Decrease RPT Timing\n"));
if (RateID < HighestRate)
{
for (i=RateID+1; i<=HighestRate; i++)
{
if (pRaInfo->RAUseRate & BIT(i))
{
if (RateID < HighestRate) {
for (i=RateID+1; i<=HighestRate; i++) {
if (pRaInfo->RAUseRate & BIT(i)) {
RateID=i;
goto RateUpfinish;
}
}
}
else if (RateID == HighestRate)
{
} else if (RateID == HighestRate) {
if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1))
pRaInfo->RateSGI = 1;
else if ((pRaInfo->SGIEnable) !=1 )
pRaInfo->RateSGI = 0;
}
else //if ((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate))
{
} else {
RateID = HighestRate;
}
RateUpfinish:
//if (pRaInfo->RAWaitingCounter==10)
if (pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter]))
pRaInfo->RAWaitingCounter=0;
else
@ -321,25 +294,23 @@ static void odm_ResetRaCounter_8188E(PODM_RA_INFO_T pRaInfo){
pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1;
}
static void
odm_RateDecision_8188E(
PDM_ODM_T pDM_Odm,
static void odm_RateDecision_8188E(PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
//u4Byte pool_retry;
/* u4Byte pool_retry; */
static u1Byte DynamicTxRPTTimingCounter=0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E()\n"));
if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits
if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) /* STA used and data packet exits */
{
if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
// Start RA decision
/* Start RA decision */
if (pRaInfo->PreRate > pRaInfo->HighestRate)
RateID = pRaInfo->HighestRate;
else
@ -348,11 +319,10 @@ odm_RateDecision_8188E(
RtyPtID=0;
else
RtyPtID=1;
PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page
PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" NscDown init is %d\n", pRaInfo->NscDown));
//pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP;
pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0];
pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1];
pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2];
@ -366,7 +336,7 @@ odm_RateDecision_8188E(
else
pRaInfo->NscDown=0;
// rate up
/* rate up */
PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" NscUp init is %d\n", pRaInfo->NscUp));
@ -388,7 +358,6 @@ odm_RateDecision_8188E(
pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI));
if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID]))
odm_RateDown_8188E(pDM_Odm,pRaInfo);
//else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retry<POOL_RETRY_TH[RateID]))
else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])
odm_RateUp_8188E(pDM_Odm,pRaInfo);
@ -406,7 +375,7 @@ odm_RateDecision_8188E(
DynamicTxRPTTimingCounter=0;
}
pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120
pRaInfo->PreRate = pRaInfo->DecisionRate; /* YJ,add,120120 */
odm_ResetRaCounter_8188E( pRaInfo);
}
@ -418,7 +387,7 @@ odm_ARFBRefresh_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
)
{ // Wilson 2011/10/26
{ /* Wilson 2011/10/26 */
u4Byte MaskFromReg;
s1Byte i;
@ -465,7 +434,7 @@ odm_ARFBRefresh_8188E(
pRaInfo->RAUseRate=(pRaInfo->RateMask);
break;
}
// Highest rate
/* Highest rate */
if (pRaInfo->RAUseRate){
for (i=RATESIZE;i>=0;i--)
{
@ -478,7 +447,7 @@ odm_ARFBRefresh_8188E(
else{
pRaInfo->HighestRate=0;
}
// Lowest rate
/* Lowest rate */
if (pRaInfo->RAUseRate){
for (i=0;i<RATESIZE;i++)
{
@ -648,7 +617,7 @@ ODM_RASupport_Init(
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n"));
// 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!!
/* 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! */
if (pDM_Odm->SupportICType == ODM_RTL8188E)
pDM_Odm->RaSupport88E = true;
@ -664,8 +633,8 @@ ODM_RAInfo_Init(
{
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
#if 1
u1Byte WirelessMode=0xFF; //invalid value
u1Byte max_rate_idx = 0x13; //MCS7
u1Byte WirelessMode=0xFF; /* invalid value */
u1Byte max_rate_idx = 0x13; /* MCS7 */
if (pDM_Odm->pWirelessMode!=NULL){
WirelessMode=*(pDM_Odm->pWirelessMode);
}
@ -679,7 +648,6 @@ ODM_RAInfo_Init(
max_rate_idx = 0x03;
}
//printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__func__,WirelessMode,max_rate_idx);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x\n",
WirelessMode,max_rate_idx));
@ -702,7 +670,7 @@ ODM_RAInfo_Init(
pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2;
pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2;
pRaInfo->RateSGI=0;
pRaInfo->Active=1; //Active is not used at present. by page, 110819
pRaInfo->Active=1; /* Active is not used at present. by page, 110819 */
pRaInfo->RptTime = 0x927c;
pRaInfo->DROP=0;
pRaInfo->RTY[0]=0;
@ -714,9 +682,9 @@ ODM_RAInfo_Init(
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
#if POWER_TRAINING_ACTIVE == 1
pRaInfo->PTActive=1; // Active when this STA is use
pRaInfo->PTActive=1; /* Active when this STA is use */
pRaInfo->PTTryState=0;
pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS
pRaInfo->PTStage=5; /* Need to fill into HW_PWR_STATUS */
pRaInfo->PTSmoothFactor=192;
pRaInfo->PTStopCount=0;
pRaInfo->PTPreRate=0;
@ -917,14 +885,14 @@ ODM_RA_TxRPT2Handle_8188E(
if (pRAInfo->RAstage<5){
odm_RateDecision_8188E(pDM_Odm,pRAInfo);
}
else if (pRAInfo->RAstage==5){ // Power training try state
else if (pRAInfo->RAstage==5){ /* Power training try state */
odm_PTTryState_8188E(pRAInfo);
}
else {// RAstage==6
else {/* RAstage==6 */
odm_PTDecision_8188E(pRAInfo);
}
// Stage_RA counter
/* Stage_RA counter */
if (pRAInfo->RAstage<=5)
pRAInfo->RAstage++;
else
@ -1082,5 +1050,4 @@ ODM_RA_TxRPT2Handle_8188E(
return;
}
#endif

83
hal/HalHWImg8188E_BB.c
View file

@ -212,7 +212,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
PADAPTER Adapter = pDM_Odm->Adapter;
struct xmit_frame *pxmit_frame;
u8 bndy_cnt=1;
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
@ -228,14 +228,14 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
return HAL_STATUS_FAILURE;
}
}
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -245,16 +245,16 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -262,9 +262,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
@ -278,7 +278,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
@ -295,31 +295,30 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
}
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__func__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
if (rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
printk("~~~ %s Success !!!\n",__func__);
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
printk("~~~ %s IOL_exec_cmds Failed !!!\n",__func__);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
rst = HAL_STATUS_FAILURE;
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
@ -547,7 +546,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
struct cmd_cmp cmpdata[ArrayLen];
u4Byte cmpdata_idx=0;
#endif
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
hex += interfaceValue << 8;
@ -563,7 +562,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
return HAL_STATUS_FAILURE;
}
}
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
@ -571,7 +570,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
u4Byte v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -611,16 +610,16 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -628,9 +627,9 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
@ -672,7 +671,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
@ -689,7 +688,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__func__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
/* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__func__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */
if (rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
@ -709,27 +708,22 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
}
printk("### %s data compared !!###\n",__func__);
//if (rst == HAL_STATUS_FAILURE)
{//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
}
else{
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
} else {
rst = HAL_STATUS_FAILURE;
printk("~~~ IOL Config %s Failed !!!\n",__func__);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
@ -856,19 +850,16 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
u4Byte v2 = Array[i+1];
u4Byte v3 = Array[i+2];
// this line is a line of pure_body
if ( v1 < 0xCDCDCDCD )
{
/* this line is a line of pure_body */
if ( v1 < 0xCDCDCDCD ) {
odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3);
continue;
}
else
{ // this line is the start of branch
} else { /* this line is the start of branch */
if ( !CheckCondition(Array[i], hex) )
{ // don't need the hw_body
i += 2; // skip the pair of expression
{ /* don't need the hw_body */
i += 2; /* skip the pair of expression */
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+2];
@ -885,6 +876,4 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
}
#endif // end of HWIMG_SUPPORT
#endif /* end of HWIMG_SUPPORT */

43
hal/HalHWImg8188E_MAC.c
View file

@ -177,7 +177,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
struct cmd_cmp cmpdata[ArrayLen];
u4Byte cmpdata_idx=0;
#endif
#endif //CONFIG_IOL_IOREG_CFG
#endif /* CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
hex += interfaceValue << 8;
@ -195,14 +195,14 @@ ODM_ReadAndConfig_MAC_REG_8188E(
}
}
#endif //CONFIG_IOL_IOREG_CFG
#endif /* CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -219,16 +219,16 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#endif
}
else
#endif //endif CONFIG_IOL_IOREG_CFG
#endif /* endif CONFIG_IOL_IOREG_CFG */
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -236,9 +236,9 @@ ODM_ReadAndConfig_MAC_REG_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
@ -257,7 +257,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#endif
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
}
@ -276,17 +276,14 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__func__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
if (rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
if (rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
#ifdef CONFIG_IOL_IOREG_CFG_DBG
printk("~~~ IOL Config MAC Success !!!\n");
//compare writed data
/* compare written data */
{
u4Byte idx;
u1Byte cdata;
// HAL_STATUS_FAILURE;
/* HAL_STATUS_FAILURE; */
printk(" MAC data compare => array_len:%d\n",cmpdata_idx);
for (idx=0;idx< cmpdata_idx;idx++)
{
@ -294,35 +291,35 @@ ODM_ReadAndConfig_MAC_REG_8188E(
if (cdata != cmpdata[idx].value){
printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n",
cmpdata[idx].addr,cmpdata[idx].value,cdata);
//rst = HAL_STATUS_FAILURE;
/* rst = HAL_STATUS_FAILURE; */
}
}
//dump data from TX packet buffer
//if (rst == HAL_STATUS_FAILURE)
/* dump data from TX packet buffer */
/* if (rst == HAL_STATUS_FAILURE) */
{
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
printk("~~~ MAC IOL_exec_cmds Failed !!!\n");
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
rst = HAL_STATUS_FAILURE;
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
#endif // end of HWIMG_SUPPORT
#endif /* end of HWIMG_SUPPORT */

32
hal/HalHWImg8188E_RF.c
View file

@ -184,7 +184,7 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
struct cmd_cmp cmpdata[ArrayLen];
u4Byte cmpdata_idx=0;
#endif
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
@ -201,14 +201,14 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
return HAL_STATUS_FAILURE;
}
}
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -246,16 +246,16 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -263,9 +263,9 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
@ -308,7 +308,7 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
@ -325,7 +325,6 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
}
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__func__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
if (rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
@ -345,12 +344,11 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
}
}
printk("### %s data compared !!###\n",__func__);
//if (rst == HAL_STATUS_FAILURE)
{//dump data from TX packet buffer
{/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
@ -358,16 +356,16 @@ HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
printk("~~~ IOL Config %s Failed !!!\n",__func__);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
#endif // end of HWIMG_SUPPORT
#endif /* end of HWIMG_SUPPORT */

257
hal/HalPhyRf.c
View file

@ -35,11 +35,9 @@ phy_PathAStandBy(
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
}
//1 7. IQK
//#define MAX_TOLERANCE 5
//#define IQK_DELAY_TIME 1 //ms
/* 1 7. IQK */
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
u1Byte /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_IQK_8192C(
PADAPTER pAdapter,
bool configPathB
@ -52,7 +50,7 @@ phy_PathA_IQK_8192C(
RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
//path-A IQK setting
/* path-A IQK setting */
RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
if (pAdapter->interfaceIndex == 0)
{
@ -70,7 +68,7 @@ phy_PathA_IQK_8192C(
PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
//path-B IQK setting
/* path-B IQK setting */
if (configPathB)
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
@ -82,23 +80,23 @@ phy_PathA_IQK_8192C(
PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
}
//LO calibration setting
/* LO calibration setting */
RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
if (IS_HARDWARE_TYPE_8192D(pAdapter))
PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
else
PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
//One shot, path A LOK & IQK
/* One shot, path A LOK & IQK */
RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
// delay x ms
/* delay x ms */
RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
PlatformStallExecution(IQK_DELAY_TIME*1000);
// Check failed
/* Check failed */
regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
@ -112,10 +110,10 @@ phy_PathA_IQK_8192C(
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
else //if Tx not OK, ignore Rx
else /* if Tx not OK, ignore Rx */
return result;
if (!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
if (!(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
@ -127,7 +125,7 @@ phy_PathA_IQK_8192C(
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
u1Byte /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathB_IQK_8192C(
PADAPTER pAdapter
)
@ -136,16 +134,16 @@ phy_PathB_IQK_8192C(
u1Byte result = 0x00;
RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n"));
//One shot, path B LOK & IQK
/* One shot, path B LOK & IQK */
RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
// delay x ms
/* delay x ms */
RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME));
PlatformStallExecution(IQK_DELAY_TIME*1000);
// Check failed
/* Check failed */
regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord);
@ -213,7 +211,7 @@ phy_PathAFillIQKMatrix(
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
//path B IQK result + 3
/* path B IQK result + 3 */
if (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType92D == BAND_ON_5G)
Y += 3;
@ -249,7 +247,7 @@ phy_PathBFillIQKMatrix(
bool bIQKOK,
s4Byte result[][8],
u1Byte final_candidate,
bool bTxOnly //do Tx only
bool bTxOnly /* do Tx only */
)
{
u4Byte Oldval_1, X, TX1_A, reg;
@ -280,7 +278,7 @@ phy_PathBFillIQKMatrix(
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
if (pHalData->CurrentBandType92D == BAND_ON_5G)
Y += 3; //temp modify for preformance
Y += 3; /* temp modify for preformance */
TX1_C = (Y * Oldval_1) >> 8;
RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
@ -315,7 +313,7 @@ phy_SimularityCompare_92C(
{
u4Byte i, j, diff, SimularityBitMap, bound = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
u1Byte final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
bool bResult = true, is2T = IS_92C_SERIAL( pHalData->VersionID);
if (is2T)
@ -357,13 +355,13 @@ phy_SimularityCompare_92C(
}
return bResult;
}
else if (!(SimularityBitMap & 0x0F)) //path A OK
else if (!(SimularityBitMap & 0x0F)) /* path A OK */
{
for (i = 0; i < 4; i++)
result[3][i] = result[c1][i];
return false;
}
else if (!(SimularityBitMap & 0xF0) && is2T) //path B OK
else if (!(SimularityBitMap & 0xF0) && is2T) /* path B OK */
{
for (i = 4; i < 8; i++)
result[3][i] = result[c1][i];
@ -416,7 +414,7 @@ phy_IQCalibrate_8192C(
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
//since 92C & 92D have the different define in IQK_BB_REG
/* since 92C & 92D have the different define in IQK_BB_REG */
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
@ -424,7 +422,7 @@ phy_IQCalibrate_8192C(
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
};
u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal
u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { /* for normal */
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable,
@ -440,12 +438,12 @@ phy_IQCalibrate_8192C(
retryCount = 2;
//Neil Chen--2011--05--19--
//3 Path Div
/* Neil Chen--2011--05--19-- */
/* 3 Path Div */
u1Byte rfPathSwitch=0x0;
// Note: IQ calibration must be performed after loading
// PHY_REG.txt , and radio_a, radio_b.txt
/* Note: IQ calibration must be performed after loading */
/* PHY_REG.txt , and radio_a, radio_b.txt */
u4Byte bbvalue;
@ -456,7 +454,7 @@ phy_IQCalibrate_8192C(
RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
// Save ADDA parameters, turn Path A ADDA on
/* Save ADDA parameters, turn Path A ADDA on */
phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
if (IS_HARDWARE_TYPE_8192D(pAdapter))
@ -470,24 +468,24 @@ phy_IQCalibrate_8192C(
if (IS_HARDWARE_TYPE_8192D(pAdapter)){
//==============================
//3 Path Diversity
////Neil Chen--2011--05--20
/* */
/* 3 Path Diversity */
/* Neil Chen--2011--05--20 */
rfPathSwitch =(u1Byte) (PHY_QueryBBReg(pAdapter, 0xB30, bMaskDWord)>>27);
//rfPathSwitch = (u1Byte) DataB30;
/* rfPathSwitch = (u1Byte) DataB30; */
rfPathSwitch = rfPathSwitch&(0x01);
if (rfPathSwitch) // Path Div On
if (rfPathSwitch) /* Path Div On */
{
phy_PathADDAOn(pAdapter, ADDA_REG, true, is2T);
//DbgPrint("=STEP= change ADDA Path from B to A Path\n");
/* DbgPrint("=STEP= change ADDA Path from B to A Path\n"); */
}
else
{
phy_PathADDAOn(pAdapter, ADDA_REG, false, is2T);
}
//3 end
//=====================================
/* 3 end */
/* */
PHY_SetBBReg(pAdapter, rPdp_AntA, bMaskDWord, 0x01017038);
}
@ -498,7 +496,7 @@ phy_IQCalibrate_8192C(
}
if (!pHalData->bRfPiEnable){
// Switch BB to PI mode to do IQ Calibration.
/* Switch BB to PI mode to do IQ Calibration. */
phy_PIModeSwitch(pAdapter, true);
}
@ -522,7 +520,7 @@ phy_IQCalibrate_8192C(
PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
}
//MAC settings
/* MAC settings */
phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
if (IS_HARDWARE_TYPE_8192D(pAdapter))
@ -536,7 +534,7 @@ phy_IQCalibrate_8192C(
}
else
{
//Page B init
/* Page B init */
PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
if (is2T)
@ -544,7 +542,7 @@ phy_IQCalibrate_8192C(
PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
}
}
// IQ calibration setting
/* IQ calibration setting */
RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00);
@ -560,7 +558,7 @@ phy_IQCalibrate_8192C(
result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
break;
}
else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
else if (i == (retryCount-1) && PathAOK == 0x01) /* Tx IQK OK */
{
RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
@ -576,7 +574,7 @@ phy_IQCalibrate_8192C(
if (is2T){
phy_PathAStandBy(pAdapter);
// Turn Path B ADDA on
/* Turn Path B ADDA on */
phy_PathADDAOn(pAdapter, ADDA_REG, false, is2T);
for (i = 0 ; i < retryCount ; i++){
@ -589,7 +587,7 @@ phy_IQCalibrate_8192C(
result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
break;
}
else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK
else if (i == (retryCount - 1) && PathBOK == 0x01) /* Tx IQK OK */
{
RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n"));
result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
@ -602,24 +600,24 @@ phy_IQCalibrate_8192C(
}
}
//Back to BB mode, load original value
/* Back to BB mode, load original value */
RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n"));
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0);
if (t!=0)
{
if (!pHalData->bRfPiEnable){
// Switch back BB to SI mode after finish IQ Calibration.
/* Switch back BB to SI mode after finish IQ Calibration. */
phy_PIModeSwitch(pAdapter, false);
}
// Reload ADDA power saving parameters
/* Reload ADDA power saving parameters */
phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
// Reload MAC parameters
/* Reload MAC parameters */
phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
// Reload BB parameters
/* Reload BB parameters */
if (IS_HARDWARE_TYPE_8192D(pAdapter))
{
if (is2T)
@ -632,13 +630,13 @@ phy_IQCalibrate_8192C(
if (!IS_HARDWARE_TYPE_8192D(pAdapter))
{
// Restore RX initial gain
/* Restore RX initial gain */
PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
if (is2T){
PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
}
}
//load 0xe30 IQC default value
/* load 0xe30 IQC default value */
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
@ -656,56 +654,55 @@ phy_LCCalibrate92C(
{
u1Byte tmpReg;
u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//Check continuous TX and Packet TX
/* Check continuous TX and Packet TX */
tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03);
if ((tmpReg&0x70) != 0) //Deal with contisuous TX case
PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX
else // Deal with Packet TX case
PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues
if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
else /* Deal with Packet TX case */
PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); /* block all queues */
if ((tmpReg&0x70) != 0)
{
//1. Read original RF mode
//Path-A
/* 1. Read original RF mode */
/* Path-A */
RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
//Path-B
/* Path-B */
if (is2T)
RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
//2. Set RF mode = standby mode
//Path-A
/* 2. Set RF mode = standby mode */
/* Path-A */
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
//Path-B
/* Path-B */
if (is2T)
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
}
//3. Read RF reg18
/* 3. Read RF reg18 */
LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
//4. Set LC calibration begin bit15
/* 4. Set LC calibration begin bit15 */
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
delay_ms(100);
//Restore original situation
if ((tmpReg&0x70) != 0) //Deal with contisuous TX case
/* Restore original situation */
if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
{
//Path-A
/* Path-A */
PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg);
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
//Path-B
/* Path-B */
if (is2T)
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
}
else // Deal with Packet TX case
else /* Deal with Packet TX case */
{
PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00);
}
@ -734,7 +731,7 @@ phy_LCCalibrate(
//Analog Pre-distortion calibration
/* Analog Pre-distortion calibration */
#define APK_BB_REG_NUM 8
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
@ -786,7 +783,7 @@ phy_APCalibrate_8192C(
};
u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /* path settings equal to path b settings */
{0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
};
@ -796,11 +793,11 @@ phy_APCalibrate_8192C(
};
u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /* path settings equal to path b settings */
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
};
u4Byte AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
0x04db25a4, 0x0b1b25a4}; /* path A on path B off / path A off path B on */
u4Byte APK_offset[PATH_NUM] = {
rConfig_AntA, rConfig_AntB};
@ -835,8 +832,8 @@ phy_APCalibrate_8192C(
0x00050006
};
u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; /* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */
/* u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; */
s4Byte BB_offset, delta_V, delta_offset;
@ -855,12 +852,12 @@ if (pAdapter->registrypriv.mp_mode == 1)
if (!is2T)
pathbound = 1;
//2 FOR NORMAL CHIP SETTINGS
/* 2 FOR NORMAL CHIP SETTINGS */
// Temporarily do not allow normal driver to do the following settings because these offset
// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
/* Temporarily do not allow normal driver to do the following settings because these offset */
/* and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal */
/* will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the */
/* root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. */
#if MP_DRIVER != 1
return;
#endif
@ -868,7 +865,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
if (pAdapter->registrypriv.mp_mode != 1)
return;
//settings adjust for normal chip
/* settings adjust for normal chip */
for (index = 0; index < PATH_NUM; index ++)
{
APK_offset[index] = APK_normal_offset[index];
@ -888,18 +885,18 @@ if (pAdapter->registrypriv.mp_mode == 1)
apkbound = 6;
//save BB default value
/* save BB default value */
for (index = 0; index < APK_BB_REG_NUM ; index++)
{
if (index == 0) //skip
if (index == 0) /* skip */
continue;
BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord);
}
//save MAC default value
/* save MAC default value */
phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
//save AFE default value
/* save AFE default value */
phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
for (path = 0; path < pathbound; path++)
@ -908,9 +905,9 @@ if (pAdapter->registrypriv.mp_mode == 1)
if (path == RF_PATH_A)
{
//path A APK
//load APK setting
//path-A
/* path A APK */
/* load APK setting */
/* path-A */
offset = rPdp_AntA;
for (index = 0; index < 11; index ++)
{
@ -931,10 +928,10 @@ if (pAdapter->registrypriv.mp_mode == 1)
offset += 0x04;
}
//page-B1
/* page-B1 */
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
//path A
/* path A */
offset = rPdp_AntA;
for (index = 0; index < 16; index++)
{
@ -947,9 +944,9 @@ if (pAdapter->registrypriv.mp_mode == 1)
}
else if (path == RF_PATH_B)
{
//path B APK
//load APK setting
//path-B
/* path B APK */
/* load APK setting */
/* path-B */
offset = rPdp_AntB;
for (index = 0; index < 10; index ++)
{
@ -964,7 +961,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
offset = rConfig_AntA;
index = 11;
for (; index < 13; index ++) //offset 0xb68, 0xb6c
for (; index < 13; index ++) /* offset 0xb68, 0xb6c */
{
PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
@ -972,10 +969,10 @@ if (pAdapter->registrypriv.mp_mode == 1)
offset += 0x04;
}
//page-B1
/* page-B1 */
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
//path B
/* path B */
offset = 0xb60;
for (index = 0; index < 16; index++)
{
@ -987,21 +984,21 @@ if (pAdapter->registrypriv.mp_mode == 1)
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
}
//save RF default value
/* save RF default value */
regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask);
//Path A AFE all on, path B AFE All off or vise versa
/* Path A AFE all on, path B AFE All off or vise versa */
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord)));
//BB to AP mode
/* BB to AP mode */
if (path == 0)
{
for (index = 0; index < APK_BB_REG_NUM ; index++)
{
if (index == 0) //skip
if (index == 0) /* skip */
continue;
else if (index < 5)
PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
@ -1014,7 +1011,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
}
else //path B
else /* path B */
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
@ -1023,14 +1020,14 @@ if (pAdapter->registrypriv.mp_mode == 1)
RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord)));
//MAC settings
/* MAC settings */
phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
if (path == RF_PATH_A) //Path B to standby mode
if (path == RF_PATH_A) /* Path B to standby mode */
{
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000);
}
else //Path A to standby mode
else /* Path A to standby mode */
{
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000);
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
@ -1043,10 +1040,10 @@ if (pAdapter->registrypriv.mp_mode == 1)
else if (delta_offset > 12)
delta_offset = 12;
//AP calibration
/* AP calibration */
for (index = 0; index < APK_BB_REG_NUM; index++)
{
if (index != 1) //only DO PA11+PAD01001, AP RF setting
if (index != 1) /* only DO PA11+PAD01001, AP RF setting */
continue;
tmpReg = APK_RF_init_value[path][index];
@ -1055,7 +1052,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
{
BB_offset = (tmpReg & 0xF0000) >> 16;
if (!(tmpReg & BIT15)) //sign bit 0
if (!(tmpReg & BIT15)) /* sign bit 0 */
{
BB_offset = -BB_offset;
}
@ -1091,7 +1088,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg);
RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask)));
// PA11+PAD01111, one shot
/* PA11+PAD01111, one shot */
i = 0;
do
{
@ -1122,22 +1119,22 @@ if (pAdapter->registrypriv.mp_mode == 1)
}
}
//reload MAC default value
/* reload MAC default value */
phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
//reload BB default value
/* reload BB default value */
for (index = 0; index < APK_BB_REG_NUM ; index++)
{
if (index == 0) //skip
if (index == 0) /* skip */
continue;
PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]);
}
//reload AFE default value
/* reload AFE default value */
phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
//reload RF path default value
/* reload RF path default value */
for (path = 0; path < pathbound; path++)
{
PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]);
@ -1147,7 +1144,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101);
}
//note no index == 0
/* note no index == 0 */
if (APK_result[path][1] > 6)
APK_result[path][1] = 6;
RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
@ -1185,7 +1182,7 @@ PHY_IQCalibrate_8192C(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
s4Byte result[4][8]; //last is final result
s4Byte result[4][8]; /* last is final result */
u1Byte i, final_candidate, Indexforchannel;
bool bPathAOK, bPathBOK;
s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
@ -1210,7 +1207,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
}
#endif
//ignore IQK when continuous Tx
/* ignore IQK when continuous Tx */
if (bStartContTx || bSingleTone || bCarrierSuppression)
return;
@ -1248,10 +1245,8 @@ if (pAdapter->registrypriv.mp_mode == 1)
RTPRINT(FINIT, INIT_IQK, ("IQK !!!interface %d currentband %d ishardwareD %d\n", pAdapter->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter)));
AcquireCCKAndRWPageAControl(pAdapter);
// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));
for (i=0; i<3; i++)
{
// if (IS_HARDWARE_TYPE_8192C(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter))
if (!IS_HARDWARE_TYPE_8192D(pAdapter))
{
if (IS_92C_SERIAL( pHalData->VersionID))
@ -1260,7 +1255,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
}
else
{
// For 88C 1T1R
/* For 88C 1T1R */
phy_IQCalibrate_8192C(pAdapter, result, i, false);
}
}
@ -1313,7 +1308,6 @@ if (pAdapter->registrypriv.mp_mode == 1)
}
}
}
// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n"));
ReleaseCCKAndRWPageAControl(pAdapter);
for (i=0; i<4; i++)
@ -1345,8 +1339,8 @@ if (pAdapter->registrypriv.mp_mode == 1)
}
else
{
RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value
RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value
RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; /* X default value */
RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; /* Y default value */
}
if ((RegE94 != 0)/*&&(RegEA4 != 0)*/)
@ -1413,7 +1407,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
return;
#endif
//ignore LCK when continuous Tx
/* ignore LCK when continuous Tx */
if (bStartContTx || bSingleTone || bCarrierSuppression)
return;
@ -1439,13 +1433,12 @@ if (pAdapter->registrypriv.mp_mode == 1)
RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType92D, timecount));
//if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID))
if (IS_2T2R(pHalData->VersionID))
{
phy_LCCalibrate(pAdapter, true);
}
else{
// For 88C 1T1R
/* For 88C 1T1R */
phy_LCCalibrate(pAdapter, false);
}
@ -1464,7 +1457,7 @@ PHY_APCalibrate_8192C(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25
/* default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 */
return;
#if DISABLE_BB_RF
@ -1483,7 +1476,7 @@ PHY_APCalibrate_8192C(
phy_APCalibrate_8192C(pAdapter, delta, true);
}
else{
// For 88C 1T1R
/* For 88C 1T1R */
phy_APCalibrate_8192C(pAdapter, delta, false);
}
}
@ -1492,9 +1485,9 @@ PHY_APCalibrate_8192C(
#endif
//3============================================================
//3 IQ Calibration
//3============================================================
/* 3============================================================ */
/* 3 IQ Calibration */
/* 3============================================================ */
void
ODM_ResetIQKResult(
@ -1509,7 +1502,7 @@ ODM_ResetIQKResult(
return;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
//0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc
/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
for (i = 0; i < IQK_Matrix_Settings_NUM; i++)
{

632
hal/HalPhyRf_8188e.c
View file

File diff suppressed because it is too large Load diff

42
hal/HalPwrSeqCmd.c
View file

@ -40,15 +40,15 @@ Major Change History:
#include <gspi_ops.h>
#endif
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
/* */
/* Description: */
/* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
/* */
/* Assumption: */
/* We should follow specific format which was released from HW SD. */
/* */
/* 2011.07.07, added by Roger. */
/* */
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
@ -61,7 +61,7 @@ u8 HalPwrSeqCmdParsing(
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 pollingCount = 0; /* polling autoload done. */
u32 maxPollingCnt = 5000;
do {
@ -78,7 +78,7 @@ u8 HalPwrSeqCmdParsing(
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
@ -94,19 +94,19 @@ u8 HalPwrSeqCmdParsing(
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
/* */
/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
/* 2011.07.07. */
/* */
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
{
// Read Back SDIO Local value
/* Read Back SDIO Local value */
value = SdioLocalCmd52Read1Byte(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
/* Write Back SDIO Local value */
SdioLocalCmd52Write1Byte(padapter, offset, value);
}
else
@ -116,13 +116,13 @@ u8 HalPwrSeqCmdParsing(
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
// Read the value from system register
/* Read the value from system register */
value = rtw_read8(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
/* Write the value back to sytem register */
rtw_write8(padapter, offset, value);
}
break;
@ -167,7 +167,7 @@ u8 HalPwrSeqCmdParsing(
break;
case PWR_CMD_END:
// When this command is parsed, end the process
/* When this command is parsed, end the process */
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return true;
break;
@ -178,7 +178,7 @@ u8 HalPwrSeqCmdParsing(
}
}
AryIdx++;//Add Array Index
AryIdx++;/* Add Array Index */
}while (1);
return true;

202
hal/hal_com.c
View file

@ -85,12 +85,12 @@ void dump_chip_info(HAL_VERSION ChipVersion)
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
u8 //return the final channel plan decision
u8 /* return the final channel plan decision */
hal_com_get_channel_plan(
PADAPTER padapter,
u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
u8 sw_channel_plan, //channel plan from SW (registry/module param)
u8 def_channel_plan, //channel plan used when the former two is invalid
u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */
u8 sw_channel_plan, /* channel plan from SW (registry/module param) */
u8 def_channel_plan, /* channel plan used when the former two is invalid */
bool AutoLoadFail
)
{
@ -121,35 +121,47 @@ u8 MRateToHwRate(u8 rate)
{
u8 ret = DESC_RATE1M;
switch (rate)
{
// CCK and OFDM non-HT rates
case IEEE80211_CCK_RATE_1MB: ret = DESC_RATE1M; break;
case IEEE80211_CCK_RATE_2MB: ret = DESC_RATE2M; break;
case IEEE80211_CCK_RATE_5MB: ret = DESC_RATE5_5M; break;
case IEEE80211_CCK_RATE_11MB: ret = DESC_RATE11M; break;
case IEEE80211_OFDM_RATE_6MB: ret = DESC_RATE6M; break;
case IEEE80211_OFDM_RATE_9MB: ret = DESC_RATE9M; break;
case IEEE80211_OFDM_RATE_12MB: ret = DESC_RATE12M; break;
case IEEE80211_OFDM_RATE_18MB: ret = DESC_RATE18M; break;
case IEEE80211_OFDM_RATE_24MB: ret = DESC_RATE24M; break;
case IEEE80211_OFDM_RATE_36MB: ret = DESC_RATE36M; break;
case IEEE80211_OFDM_RATE_48MB: ret = DESC_RATE48M; break;
case IEEE80211_OFDM_RATE_54MB: ret = DESC_RATE54M; break;
// HT rates since here
//case MGN_MCS0: ret = DESC_RATEMCS0; break;
//case MGN_MCS1: ret = DESC_RATEMCS1; break;
//case MGN_MCS2: ret = DESC_RATEMCS2; break;
//case MGN_MCS3: ret = DESC_RATEMCS3; break;
//case MGN_MCS4: ret = DESC_RATEMCS4; break;
//case MGN_MCS5: ret = DESC_RATEMCS5; break;
//case MGN_MCS6: ret = DESC_RATEMCS6; break;
//case MGN_MCS7: ret = DESC_RATEMCS7; break;
default: break;
switch (rate) {
/* CCK and OFDM non-HT rates */
case IEEE80211_CCK_RATE_1MB:
ret = DESC_RATE1M;
break;
case IEEE80211_CCK_RATE_2MB:
ret = DESC_RATE2M;
break;
case IEEE80211_CCK_RATE_5MB:
ret = DESC_RATE5_5M;
break;
case IEEE80211_CCK_RATE_11MB:
ret = DESC_RATE11M;
break;
case IEEE80211_OFDM_RATE_6MB:
ret = DESC_RATE6M;
break;
case IEEE80211_OFDM_RATE_9MB:
ret = DESC_RATE9M;
break;
case IEEE80211_OFDM_RATE_12MB:
ret = DESC_RATE12M;
break;
case IEEE80211_OFDM_RATE_18MB:
ret = DESC_RATE18M;
break;
case IEEE80211_OFDM_RATE_24MB:
ret = DESC_RATE24M;
break;
case IEEE80211_OFDM_RATE_36MB:
ret = DESC_RATE36M;
break;
case IEEE80211_OFDM_RATE_48MB:
ret = DESC_RATE48M;
break;
case IEEE80211_OFDM_RATE_54MB:
ret = DESC_RATE54M;
break;
default:
break;
}
return ret;
}
@ -207,65 +219,58 @@ void HalSetBrateCfg(
}
}
static void
_OneOutPipeMapping(
PADAPTER pAdapter
)
static void _OneOutPipeMapping(PADAPTER pAdapter)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
static void
_TwoOutPipeMapping(
PADAPTER pAdapter,
bool bWIFICfg
)
static void _TwoOutPipeMapping(PADAPTER pAdapter, bool bWIFICfg)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg){ //WMM
if (bWIFICfg){ /* WMM */
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 0, 1, 0, 1, 0, 0, 0, 0, 0 };
//0:H, 1:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
else{//typical setting
else{/* typical setting */
//BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 1, 0, 0, 0, 0, 0, 0, 0 };
//0:H, 1:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
@ -278,39 +283,36 @@ static void _ThreeOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg){//for WMM
if (bWIFICfg){/* for WMM */
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H, 1:N, 2:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:N, 2:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
else{//typical setting
} else {/* typical setting */
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:N, 2:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 2, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H, 1:N, 2:L
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
}

10
hal/hal_intf.c
View file

@ -68,7 +68,7 @@ void rtw_hal_dm_init(_adapter *padapter)
}
void rtw_hal_dm_deinit(_adapter *padapter)
{
// cancel dm timer
/* cancel dm timer */
if (padapter->HalFunc.dm_deinit)
padapter->HalFunc.dm_deinit(padapter);
}
@ -103,7 +103,7 @@ uint rtw_hal_init(_adapter *padapter)
return status;
}
// before init mac0, driver must init mac1 first to avoid usb rx error.
/* before init mac0, driver must init mac1 first to avoid usb rx error. */
if ((padapter->pbuddy_adapter != NULL) && (padapter->DualMacConcurrent == true)
&& (padapter->adapter_type == PRIMARY_ADAPTER))
{
@ -306,7 +306,7 @@ void rtw_hal_update_ra_mask(_adapter *padapter, u32 mac_id, u8 rssi_level)
psta = pstapriv->sta_aid[(mac_id-1) - 1];
#endif
if (psta)
add_RATid(padapter, psta, 0);//todo: based on rssi_level
add_RATid(padapter, psta, 0);/* todo: based on rssi_level */
}
else
{
@ -423,7 +423,7 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
return _FAIL;
}
#endif //CONFIG_HOSTAPD_MLME
#endif /* CONFIG_HOSTAPD_MLME */
#ifdef DBG_CONFIG_ERROR_DETECT
void rtw_hal_sreset_init(_adapter *padapter)
@ -465,7 +465,7 @@ u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
return status;
}
#endif //DBG_CONFIG_ERROR_DETECT
#endif /* DBG_CONFIG_ERROR_DETECT */
#ifdef CONFIG_IOL
int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)

3053
hal/odm.c
View file

File diff suppressed because it is too large Load diff

294
hal/odm_HWConfig.c
View file

@ -18,9 +18,9 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
@ -51,10 +51,10 @@ static u1Byte odm_QueryRxPwrPercentage(s1Byte AntPower)
}
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
//
// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
// IF other SW team do not support the feature, remove this section.??
//
/* */
/* 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. */
/* IF other SW team do not support the feature, remove this section.?? */
/* */
static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
PDM_ODM_T pDM_Odm,
s4Byte CurrSig
@ -62,13 +62,13 @@ static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
{
s4Byte RetSig;
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
//if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE)
/* if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) */
{
// Step 1. Scale mapping.
// 20100611 Joseph: Re-tunning RSSI presentation for Lenovo.
// 20100426 Joseph: Modify Signal strength mapping.
// This modification makes the RSSI indication similar to Intel solution.
// 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE.
/* Step 1. Scale mapping. */
/* 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. */
/* 20100426 Joseph: Modify Signal strength mapping. */
/* This modification makes the RSSI indication similar to Intel solution. */
/* 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. */
if (CurrSig >= 54 && CurrSig <= 100)
RetSig = 100;
else if (CurrSig>=42 && CurrSig <= 53)
@ -88,7 +88,7 @@ static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
else if (CurrSig <= 8)
RetSig = 19;
}
#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP)
#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP) */
return RetSig;
}
@ -99,9 +99,9 @@ static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
{
s4Byte RetSig;
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
//if (pDM_Odm->SupportInterface == ODM_ITRF_USB)
/* if (pDM_Odm->SupportInterface == ODM_ITRF_USB) */
{
// Netcore request this modification because 2009.04.13 SU driver use it.
/* Netcore request this modification because 2009.04.13 SU driver use it. */
if (CurrSig >= 31 && CurrSig <= 100)
{
RetSig = 100;
@ -147,7 +147,7 @@ static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
RetSig = CurrSig;
}
}
#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP)
#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP) */
return RetSig;
}
@ -162,7 +162,7 @@ odm_SignalScaleMapping_92CSeries(
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE)
{
// Step 1. Scale mapping.
/* Step 1. Scale mapping. */
if (CurrSig >= 61 && CurrSig <= 100)
{
RetSig = 90 + ((CurrSig - 60) / 4);
@ -252,14 +252,14 @@ odm_SignalScaleMapping(
)
{
if ( (pDM_Odm->SupportPlatform == ODM_MP) &&
(pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO
(pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore
(pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && /* USB & SDIO */
(pDM_Odm->PatchID==10))/* pMgntInfo->CustomerID == RT_CID_819x_Netcore */
{
return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig);
}
else if ( (pDM_Odm->SupportPlatform == ODM_MP) &&
(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) &&
(pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo)
(pDM_Odm->PatchID==19))/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo) */
{
return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig);
}
@ -270,7 +270,7 @@ odm_SignalScaleMapping(
}
#endif
//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
PDM_ODM_T pDM_Odm,
u1Byte isCCKrate,
@ -281,10 +281,10 @@ static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
{
u1Byte SQ;
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
// mapping to 5 bars for vista signal strength
// signal quality in driver will be displayed to signal strength
/* mapping to 5 bars for vista signal strength */
/* signal quality in driver will be displayed to signal strength */
if (isCCKrate){
// in vista.
/* in vista. */
if (PWDB_ALL >= 50)
SQ = 100;
else if (PWDB_ALL >= 35 && PWDB_ALL < 50)
@ -296,11 +296,11 @@ static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
else
SQ = 20;
}
else{//OFDM rate
else{/* OFDM rate */
// mapping to 5 bars for vista signal strength
// signal quality in driver will be displayed to signal strength
// in vista.
/* mapping to 5 bars for vista signal strength */
/* signal quality in driver will be displayed to signal strength */
/* in vista. */
if (RSSI >= 50)
SQ = 100;
else if (RSSI >= 35 && RSSI < 50)
@ -321,15 +321,15 @@ odm_EVMdbToPercentage(
s1Byte Value
)
{
//
// -33dB~0dB to 0%~99%
//
/* */
/* -33dB~0dB to 0%~99% */
/* */
s1Byte ret_val;
ret_val = Value;
//ret_val /= 2;
/* ret_val /= 2; */
//ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val));
/* ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val)); */
if (ret_val >= 0)
ret_val = 0;
@ -378,43 +378,43 @@ odm_RxPhyStatus92CSeries_Parsing(
u1Byte cck_agc_rpt;
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
//
// (1)Hardware does not provide RSSI for CCK
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
/* */
/* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
/* */
cck_highpwr = pDM_Odm->bCckHighPower;
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ;
//2011.11.28 LukeLee: 88E use different LNA & VGA gain table
//The RSSI formula should be modified according to the gain table
//In 88E, cck_highpwr is always set to 1
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
/* The RSSI formula should be modified according to the gain table */
/* In 88E, cck_highpwr is always set to 1 */
if (pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) {
LNA_idx = ((cck_agc_rpt & 0xE0) >>5);
VGA_idx = (cck_agc_rpt & 0x1F);
switch (LNA_idx) {
case 7:
if (VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2
rx_pwr_all = -100 + 2*(27-VGA_idx); /* VGA_idx = 27~2 */
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0
rx_pwr_all = -48 + 2*(2-VGA_idx); /* VGA_idx = 2~0 */
break;
case 5:
rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5
rx_pwr_all = -42 + 2*(7-VGA_idx); /* VGA_idx = 7~5 */
break;
case 4:
rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4
rx_pwr_all = -36 + 2*(7-VGA_idx); /* VGA_idx = 7~4 */
break;
case 3:
rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0
rx_pwr_all = -24 + 2*(7-VGA_idx); /* VGA_idx = 7~0 */
break;
case 2:
if (cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0
rx_pwr_all = -12 + 2*(5-VGA_idx); /* VGA_idx = 5~0 */
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
break;
@ -446,9 +446,9 @@ odm_RxPhyStatus92CSeries_Parsing(
report =(cck_agc_rpt & 0xc0)>>6;
switch (report)
{
// 03312009 modified by cosa
// Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion
// Note: different RF with the different RNA gain.
/* 03312009 modified by cosa */
/* Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion */
/* Note: different RF with the different RNA gain. */
case 0x3:
rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
break;
@ -465,8 +465,8 @@ odm_RxPhyStatus92CSeries_Parsing(
}
else
{
//report = pDrvInfo->cfosho[0] & 0x60;
//report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60;
/* report = pDrvInfo->cfosho[0] & 0x60; */
/* report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; */
report = (cck_agc_rpt & 0x60)>>5;
switch (report)
@ -488,7 +488,7 @@ odm_RxPhyStatus92CSeries_Parsing(
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
//Modification for ext-LNA board
/* Modification for ext-LNA board */
if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR)
{
if ((cck_agc_rpt>>7) == 0){
@ -502,13 +502,13 @@ odm_RxPhyStatus92CSeries_Parsing(
PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12);
}
//CCK modification
/* CCK modification */
if (PWDB_ALL > 25 && PWDB_ALL <= 60)
PWDB_ALL += 6;
//else if (PWDB_ALL <= 25)
// PWDB_ALL += 8;
/* else if (PWDB_ALL <= 25) */
/* PWDB_ALL += 8; */
}
else//Modification for int-LNA board
else/* Modification for int-LNA board */
{
if (PWDB_ALL > 99)
PWDB_ALL -= 8;
@ -522,14 +522,14 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL;
pPhyInfo->RecvSignalPower = rx_pwr_all;
#endif
//
// (3) Get Signal Quality (EVM)
//
/* */
/* (3) Get Signal Quality (EVM) */
/* */
if (pPktinfo->bPacketMatchBSSID)
{
u1Byte SQ,SQ_rpt;
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0);
}
else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){
@ -547,27 +547,27 @@ odm_RxPhyStatus92CSeries_Parsing(
}
//DbgPrint("cck SQ = %d\n", SQ);
/* DbgPrint("cck SQ = %d\n", SQ); */
pPhyInfo->SignalQuality = SQ;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
}
}
else //is OFDM rate
else /* is OFDM rate */
{
pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++;
//
// (1)Get RSSI for HT rate
//
/* */
/* (1)Get RSSI for HT rate */
/* */
for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
{
// 2008/01/30 MH we will judge RF RX path now.
/* 2008/01/30 MH we will judge RF RX path now. */
if (pDM_Odm->RFPathRxEnable & BIT(i))
rf_rx_num++;
//else
//continue;
/* else */
/* continue; */
rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110;
@ -578,9 +578,9 @@ odm_RxPhyStatus92CSeries_Parsing(
/* Translate DBM to percentage. */
RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]);
total_rssi += RSSI;
//RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));
/* RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */
//Modification for ext-LNA board
/* Modification for ext-LNA board */
if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR)
{
if ((pPhyStaRpt->path_agc[i].trsw) == 1)
@ -595,7 +595,7 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI;
#if (DM_ODM_SUPPORT_TYPE & (/*ODM_MP|*/ODM_CE|ODM_AP|ODM_ADSL))
//Get Rx snr value in DB
/* Get Rx snr value in DB */
pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2);
#endif
@ -613,17 +613,17 @@ odm_RxPhyStatus92CSeries_Parsing(
}
//
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
/* */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
/* */
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1)& 0x7f) -110;
//RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n", PWDB_ALL));
/* RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n", PWDB_ALL)); */
PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
//RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n",PWDB_ALL));
/* RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n",PWDB_ALL)); */
pPhyInfo->RxPWDBAll = PWDB_ALL;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll));
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); */
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT;
pPhyInfo->RxPower = rx_pwr_all;
@ -631,30 +631,30 @@ odm_RxPhyStatus92CSeries_Parsing(
#endif
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){
//do nothing
/* do nothing */
}
else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo
//
// (3)EVM of HT rate
//
else{/* pMgntInfo->CustomerID != RT_CID_819x_Lenovo */
/* */
/* (3)EVM of HT rate */
/* */
if (pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15)
Max_spatial_stream = 2; //both spatial stream make sense
Max_spatial_stream = 2; /* both spatial stream make sense */
else
Max_spatial_stream = 1; //only spatial stream 1 makes sense
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
for (i=0; i<Max_spatial_stream; i++)
{
// Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
// fill most significant bit to "zero" when doing shifting operation which may change a negative
// value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
EVM = odm_EVMdbToPercentage((pPhyStaRpt->stream_rxevm[i])); //dbm
/* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
/* fill most significant bit to "zero" when doing shifting operation which may change a negative */
/* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
EVM = odm_EVMdbToPercentage((pPhyStaRpt->stream_rxevm[i])); /* dbm */
//RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",
//GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM));
/* RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", */
/* GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); */
if (pPktinfo->bPacketMatchBSSID)
{
if (i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only
if (i==ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
{
pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff);
}
@ -665,15 +665,15 @@ odm_RxPhyStatus92CSeries_Parsing(
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
//UI BSS List signal strength(in percentage), make it good looking, from 0~100.
//It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
/* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
/* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
if (isCCKrate)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
// 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/
pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, PWDB_ALL));//PWDB_ALL;
/* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */
pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, PWDB_ALL));/* PWDB_ALL; */
#else
pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL;
pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/* PWDB_ALL; */
#endif
}
else
@ -681,8 +681,8 @@ odm_RxPhyStatus92CSeries_Parsing(
if (rf_rx_num != 0)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
// 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/
pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, total_rssi/=rf_rx_num));//PWDB_ALL;
/* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */
pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, total_rssi/=rf_rx_num));/* PWDB_ALL; */
#else
pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num));
#endif
@ -690,10 +690,10 @@ odm_RxPhyStatus92CSeries_Parsing(
}
#endif
//For 92C/92D HW (Hybrid) Antenna Diversity
/* For 92C/92D HW (Hybrid) Antenna Diversity */
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
pDM_SWAT_Table->antsel = pPhyStaRpt->ant_sel;
//For 88E HW Antenna Diversity
/* For 88E HW Antenna Diversity */
pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel;
pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b;
pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2;
@ -726,8 +726,8 @@ static void odm_Process_RSSIForDM(
if (pPktinfo->StationID == 0xFF)
return;
// 2011/11/17 MH Need to debug
//if (pDM_Odm->SupportPlatform == ODM_MP)
/* 2011/11/17 MH Need to debug */
/* if (pDM_Odm->SupportPlatform == ODM_MP) */
{
}
@ -749,15 +749,15 @@ static void odm_Process_RSSIForDM(
{
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
//if (pPktinfo->bPacketBeacon)
//{
// DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate);
//}
/* if (pPktinfo->bPacketBeacon) */
/* */
/* DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate); */
/* */
ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID, pPhyInfo->RxPWDBAll, isCCKrate);
}
}
#endif
//-----------------Smart Antenna Debug Message------------------//
/* Smart Antenna Debug Message------------------ */
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
@ -768,14 +768,14 @@ static void odm_Process_RSSIForDM(
{
if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
{
if (pPktinfo->bPacketToSelf) //(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))
if (pPktinfo->bPacketToSelf) /* pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) */
{
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
pDM_FatTable->antSumRSSI[antsel_tr_mux] += pPhyInfo->RxPWDBAll;
pDM_FatTable->antRSSIcnt[antsel_tr_mux]++;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll));
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",
//pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); */
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", */
/* pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); */
}
}
@ -785,8 +785,8 @@ static void odm_Process_RSSIForDM(
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",
// pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", */
/* pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); */
ODM_AntselStatistics_88E(pDM_Odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll);
}
@ -794,8 +794,8 @@ static void odm_Process_RSSIForDM(
}
#endif
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
//-----------------Smart Antenna Debug Message------------------//
#endif /* if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
/* Smart Antenna Debug Message------------------ */
UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK;
UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM;
@ -804,15 +804,15 @@ static void odm_Process_RSSIForDM(
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
if (!isCCKrate)//ofdm rate
if (!isCCKrate)/* ofdm rate */
{
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
}
else
{
//DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n",
//pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]);
/* DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n", */
/* pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); */
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B])
@ -835,8 +835,8 @@ static void odm_Process_RSSIForDM(
RSSI_Ave = RSSI_max - 3;
}
//1 Process OFDM RSSI
if (UndecoratedSmoothedOFDM <= 0) // initialize
/* 1 Process OFDM RSSI */
if (UndecoratedSmoothedOFDM <= 0) /* initialize */
{
UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll;
}
@ -864,8 +864,8 @@ static void odm_Process_RSSIForDM(
{
RSSI_Ave = pPhyInfo->RxPWDBAll;
//1 Process CCK RSSI
if (UndecoratedSmoothedCCK <= 0) // initialize
/* 1 Process CCK RSSI */
if (UndecoratedSmoothedCCK <= 0) /* initialize */
{
UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll;
}
@ -888,9 +888,9 @@ static void odm_Process_RSSIForDM(
pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1;
}
//if (pEntry)
/* if (pEntry) */
{
//2011.07.28 LukeLee: modified to prevent unstable CCK RSSI
/* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
if (pEntry->rssi_stat.ValidBit >= 64)
pEntry->rssi_stat.ValidBit = 64;
else
@ -916,9 +916,9 @@ static void odm_Process_RSSIForDM(
pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM;
pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
//DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting);
//DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n",
// UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK);
/* DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); */
/* DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", */
/* UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); */
}
@ -926,9 +926,9 @@ static void odm_Process_RSSIForDM(
}
//
// Endianness before calling this API
//
/* */
/* Endianness before calling this API */
/* */
static void
ODM_PhyStatusQuery_92CSeries(
PDM_ODM_T pDM_Odm,
@ -945,7 +945,7 @@ ODM_PhyStatusQuery_92CSeries(
pPktinfo);
if (pDM_Odm->RSSI_test == true) {
// Select the packets to do RSSI checking for antenna switching.
/* Select the packets to do RSSI checking for antenna switching. */
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo);
} else {
@ -956,9 +956,9 @@ ODM_PhyStatusQuery_92CSeries(
//
// Endianness before calling this API
//
/* */
/* Endianness before calling this API */
/* */
static void
ODM_PhyStatusQuery_JaguarSeries(
PDM_ODM_T pDM_Odm,
@ -982,7 +982,7 @@ ODM_PhyStatusQuery(
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
// For future use.
/* For future use. */
void
ODM_MacStatusQuery(
PDM_ODM_T pDM_Odm,
@ -993,7 +993,7 @@ ODM_MacStatusQuery(
bool bPacketBeacon
)
{
// 2011/10/19 Driver team will handle in the future.
/* 2011/10/19 Driver team will handle in the future. */
}
@ -1006,7 +1006,7 @@ ODM_ConfigRFWithHeaderFile(
ODM_RF_RADIO_PATH_E eRFPath
)
{
//RT_STATUS rtStatus = RT_STATUS_SUCCESS;
/* RT_STATUS rtStatus = RT_STATUS_SUCCESS; */
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
@ -1021,21 +1021,21 @@ ODM_ConfigRFWithHeaderFile(
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath));
//rtStatus = RT_STATUS_SUCCESS;
/* rtStatus = RT_STATUS_SUCCESS; */
#endif
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
if (eRFPath == ODM_RF_PATH_A)
READ_AND_CONFIG(8188E,_RadioA_1T_);
//else if (eRFPath == ODM_RF_PATH_B)
// READ_AND_CONFIG(8188E,_RadioB_1T_);
/* else if (eRFPath == ODM_RF_PATH_B) */
/* READ_AND_CONFIG(8188E,_RadioB_1T_); */
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n"));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath));
//rtStatus = RT_STATUS_SUCCESS;
/* rtStatus = RT_STATUS_SUCCESS; */
#endif
return HAL_STATUS_SUCCESS;
}
@ -1072,10 +1072,10 @@ ODM_ConfigBBWithHeaderFile(
{
READ_AND_CONFIG(8188E,_PHY_REG_1T_);
}
// else if (ConfigType == ODM_BaseBand_Config_PHY_REG_MP)
// {
//READ_AND_CONFIG(8188E,_PHY_REG_MP_);
// }
/* else if (ConfigType == ODM_BaseBand_Config_PHY_REG_MP) */
/* { */
/* READ_AND_CONFIG(8188E,_PHY_REG_MP_); */
/* } */
else if (ConfigType == CONFIG_BB_AGC_TAB)
{
READ_AND_CONFIG(8188E,_AGC_TAB_1T_);
@ -1114,4 +1114,4 @@ ODM_ConfigMACWithHeaderFile(
}
#endif // end of (#if DM_ODM_SUPPORT_TYPE)
#endif /* end of (#if DM_ODM_SUPPORT_TYPE) */

437
hal/odm_RTL8188E.c
View file

@ -18,9 +18,9 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
@ -38,7 +38,7 @@ ODM_DIG_LowerBound_88E(
pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d\n",pDM_DigTable->AntDiv_RSSI_max));
}
//If only one Entry connected
/* If only one Entry connected */
@ -56,31 +56,28 @@ odm_RX_HWAntDivInit(
if (*(pDM_Odm->mp_mode) == 1)
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* 1:CG, 0:CS */
return;
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n"));
//MAC Setting
/* MAC Setting */
value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
//Pin Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
//OFDM Settings
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
//CCK Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
/* CCK Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); /* antenna mapping table */
}
static void
@ -95,8 +92,8 @@ odm_TRX_HWAntDivInit(
if (*(pDM_Odm->mp_mode) == 1)
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */
return;
}
@ -104,34 +101,31 @@ odm_TRX_HWAntDivInit(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n"));
//MAC Setting
/* MAC Setting */
value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
//Pin Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
//OFDM Settings
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
//CCK Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
//Tx Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
/* CCK Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
/* Tx Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
//antenna mapping table
if (!pDM_Odm->bIsMPChip) //testchip
/* antenna mapping table */
if (!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
}
else //MPchip
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
else /* MPchip */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
}
static void
@ -163,33 +157,31 @@ odm_FastAntTrainingInit(
pDM_FatTable->TrainIdx = 0;
pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
//MAC Setting
/* MAC Setting */
value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
//value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
//PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
//Match MAC ADDR
/* Match MAC ADDR */
ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
//antenna mapping table
/* antenna mapping table */
if (AntCombination == 2)
{
if (!pDM_Odm->bIsMPChip) //testchip
if (!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
}
else //MPchip
else /* MPchip */
{
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
@ -197,19 +189,19 @@ odm_FastAntTrainingInit(
}
else if (AntCombination == 7)
{
if (!pDM_Odm->bIsMPChip) //testchip
if (!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */
}
else //MPchip
else /* MPchip */
{
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
@ -222,27 +214,15 @@ odm_FastAntTrainingInit(
}
}
//Default Ant Setting when no fast training
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX
/* Default Ant Setting when no fast training */
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); /* Default RX */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); /* Optional RX */
/* ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); Default TX */
//Enter Traing state
ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
//SW Control
//PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
//PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
//PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
//PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
//PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
//PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
/* Enter Traing state */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
}
void
@ -250,20 +230,9 @@ ODM_AntennaDiversityInit_88E(
PDM_ODM_T pDM_Odm
)
{
/*
//2012.03.27 LukeLee: For temp use, should be removed later
//pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
//{
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
//pHalData->AntDivCfg = 1;
//}
*/
if (pDM_Odm->SupportICType != ODM_RTL8188E)
return;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n",
// pDM_Odm->AntDivType, pHalData->AntDivCfg));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"true":"false")));
@ -298,16 +267,16 @@ ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant)
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); /* Resp Tx */
}
else if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
}
}
pDM_FatTable->RxIdleAnt = Ant;
@ -352,11 +321,9 @@ ODM_SetTxAntByTxInfo_88E(
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
// macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
}
}
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
#else/* (DM_ODM_SUPPORT_TYPE == ODM_AP) */
void
ODM_SetTxAntByTxInfo_88E(
PDM_ODM_T pDM_Odm
@ -426,7 +393,7 @@ odm_HWAntDiv(
pEntry = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(pEntry))
{
//2 Caculate RSSI per Antenna
/* 2 Caculate RSSI per Antenna */
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT;
@ -434,14 +401,14 @@ odm_HWAntDiv(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
//2 Select MaxRSSI for DIG
/* 2 Select MaxRSSI for DIG */
LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
AntDivMaxRSSI = LocalMaxRSSI;
if (LocalMaxRSSI > MaxRSSI)
MaxRSSI = LocalMaxRSSI;
//2 Select RX Idle Antenna
/* 2 Select RX Idle Antenna */
if ((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
Main_RSSI = Aux_RSSI;
else if ((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
@ -456,7 +423,7 @@ odm_HWAntDiv(
#if TX_BY_REG
#else
//2 Select TRX Antenna
/* 2 Select TRX Antenna */
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i);
#endif
@ -467,7 +434,7 @@ odm_HWAntDiv(
pDM_FatTable->AuxAnt_Cnt[i] = 0;
}
//2 Set RX Idle Antenna
/* 2 Set RX Idle Antenna */
ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt);
pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
@ -483,12 +450,12 @@ odm_SetNextMACAddrTarget(
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
PSTA_INFO_T pEntry;
//u1Byte Bssid[6];
/* u1Byte Bssid[6]; */
u4Byte value32, i;
//
//2012.03.26 LukeLee: The MAC address is changed according to MACID in turn
//
/* */
/* 2012.03.26 LukeLee: The MAC address is changed according to MACID in turn */
/* */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n"));
if (pDM_Odm->bLinked)
{
@ -502,7 +469,7 @@ odm_SetNextMACAddrTarget(
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if (IS_STA_VALID(pEntry))
{
//Match MAC ADDR
/* Match MAC ADDR */
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4];
#else
@ -547,11 +514,11 @@ odm_FastAntTraining(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));
//1 TRAINING STATE
/* 1 TRAINING STATE */
if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n"));
//2 Caculate RSSI per Antenna
/* 2 Caculate RSSI per Antenna */
for (i=0; i<7; i++)
{
if (pDM_FatTable->antRSSIcnt[i] == 0)
@ -571,23 +538,21 @@ odm_FastAntTraining(
i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i]));
}
//2 Select TRX Antenna
/* 2 Select TRX Antenna */
if (bPktFilterMacth == false)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); /* RegE08[16]=1'b0 disable fast training */
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); /* RegC50[7]=1'b0 disable HW AntDiv */
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%d\n",TargetAnt,MaxRSSI));
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); /* RegE08[16]=1'b0 disable fast training */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); /* Default RX is Omni, Optional RX is the best decision by FAT */
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;
pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;
@ -595,11 +560,11 @@ odm_FastAntTraining(
if (TargetAnt == 0)
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); /* RegC50[7]=1'b0 disable HW AntDiv */
}
//2 Reset Counter
/* 2 Reset Counter */
for (i=0; i<7; i++)
{
pDM_FatTable->antSumRSSI[i] = 0;
@ -610,19 +575,19 @@ odm_FastAntTraining(
return;
}
//1 NORMAL STATE
/* 1 NORMAL STATE */
if (pDM_FatTable->FAT_State == FAT_NORMAL_STATE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n"));
odm_SetNextMACAddrTarget(pDM_Odm);
//2 Prepare Training
/* 2 Prepare Training */
pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); /* RegE08[16]=1'b1 enable fast training */
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));
ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms
ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); /* ms */
}
@ -638,8 +603,6 @@ odm_FastAntTrainingCallback(
PADAPTER padapter = pDM_Odm->Adapter;
if (padapter->net_closed == true)
return;
//if (*pDM_Odm->pbNet_closed == true)
// return;
#endif
#if USE_WORKITEM
@ -665,10 +628,7 @@ ODM_AntennaDiversity_88E(
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if ((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
{
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n"));
return;
}
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
if (pDM_Odm->bLinked){
if (pDM_Odm->Adapter->registrypriv.force_ant != 0)
@ -707,10 +667,10 @@ ODM_AntennaDiversity_88E(
if (pDM_FatTable->bBecomeLinked == true)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); /* Enable CCK AntDiv */
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
}
return;
@ -720,16 +680,14 @@ ODM_AntennaDiversity_88E(
if (pDM_FatTable->bBecomeLinked ==false)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
//Because HW AntDiv is disabled before Link, we enable HW AntDiv after link
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv
//ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); /* Enable CCK AntDiv */
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
#if TX_BY_REG
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from Reg */
#else
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
#endif
}
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
@ -746,48 +704,7 @@ ODM_AntennaDiversity_88E(
#endif
}
/*
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
void
odm_FastAntTrainingCallback(
PRT_TIMER pTimer
)
{
PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
//#if DEV_BUS_TYPE==RT_PCI_INTERFACE
//#if USE_WORKITEM
//PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem);
//#else
odm_FastAntTraining(&pHalData->DM_OutSrc);
//#endif
//#else
//PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem);
//#endif
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void odm_FastAntTrainingCallback(void *FunctionContext)
{
PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext;
PADAPTER padapter = pDM_Odm->Adapter;
if (padapter->net_closed == true)
return;
odm_FastAntTraining(pDM_Odm);
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
void odm_FastAntTrainingCallback(void *FunctionContext)
{
PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext;
odm_FastAntTraining(pDM_Odm);
}
#endif
*/
#else //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#else /* if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
void
ODM_SetTxAntByTxInfo_88E(
@ -797,7 +714,7 @@ ODM_SetTxAntByTxInfo_88E(
)
{
}
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
#else/* (DM_ODM_SUPPORT_TYPE == ODM_AP) */
void
ODM_SetTxAntByTxInfo_88E(
PDM_ODM_T pDM_Odm
@ -805,10 +722,10 @@ ODM_SetTxAntByTxInfo_88E(
{
}
#endif
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
//3============================================================
//3 Dynamic Primary CCA
//3============================================================
#endif /* if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
/* 3============================================================ */
/* 3 Dynamic Primary CCA */
/* 3============================================================ */
void
odm_PrimaryCCA_Init(
@ -837,8 +754,8 @@ odm_DynamicPrimaryCCA(
PDM_ODM_T pDM_Odm
)
{
PADAPTER Adapter = pDM_Odm->Adapter; // for NIC
prtl8192cd_priv priv = pDM_Odm->priv; // for AP
PADAPTER Adapter = pDM_Odm->Adapter; /* for NIC */
prtl8192cd_priv priv = pDM_Odm->priv; /* for AP */
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP))
@ -850,8 +767,8 @@ odm_DynamicPrimaryCCA(
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
bool Is40MHz;
bool Client_40MHz = false, Client_tmp = false; // connected client BW
bool bConnected = false; // connected or not
bool Client_40MHz = false, Client_tmp = false; /* connected client BW */
bool bConnected = false; /* connected or not */
static u1Byte Client_40MHz_pre = 0;
static u8Byte lastTxOkCnt = 0;
static u8Byte lastRxOkCnt = 0;
@ -875,22 +792,22 @@ odm_DynamicPrimaryCCA(
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
if (Is40MHz==1)
SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above
SecCHOffset = SecCHOffset%2+1; /* NIC's definition is reverse to AP 1:secondary below, 2: secondary above */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset));
//3 Check Current WLAN Traffic
/* 3 Check Current WLAN Traffic */
curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
//3 Check Current WLAN Traffic
/* 3 Check Current WLAN Traffic */
curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
#endif
//==================Debug Message====================
/* Debug Message==================== */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC));
@ -899,16 +816,16 @@ odm_DynamicPrimaryCCA(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail));
//================================================
/* */
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode
if (ACTING_AS_AP(Adapter)) /* primary cca process only do at AP mode */
#endif
{
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter)));
//3 To get entry's connection and BW infomation status.
/* 3 To get entry's connection and BW infomation status. */
for (i=0;i<ASSOCIATE_ENTRY_NUM;i++)
{
if (IsAPModeExist(Adapter)&&GetFirstExtAdapter(Adapter)!=NULL)
@ -917,14 +834,14 @@ odm_DynamicPrimaryCCA(
pEntry=AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
if (pEntry!=NULL)
{
Client_tmp = pEntry->HTInfo.bBw40MHz; // client BW
Client_tmp = pEntry->HTInfo.bBw40MHz; /* client BW */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp));
if (Client_tmp>Client_40MHz)
Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High
Client_40MHz = Client_tmp; /* 40M/20M coexist => 40M priority is High */
if (pEntry->bAssociated)
{
bConnected=true; // client is connected or not
bConnected=true; /* client is connected or not */
break;
}
}
@ -934,7 +851,7 @@ odm_DynamicPrimaryCCA(
}
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
//3 To get entry's connection and BW infomation status.
/* 3 To get entry's connection and BW infomation status. */
PSTA_INFO_T pstat;
@ -945,7 +862,7 @@ odm_DynamicPrimaryCCA(
{
Client_tmp = pstat->tx_bw;
if (Client_tmp>Client_40MHz)
Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High
Client_40MHz = Client_tmp; /* 40M/20M coexist => 40M priority is High */
bConnected = true;
}
@ -953,10 +870,10 @@ odm_DynamicPrimaryCCA(
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz));
//1 Monitor whether the interference exists or not
/* 1 Monitor whether the interference exists or not */
if (PrimaryCCA->Monitor_flag == 1)
{
if (SecCHOffset == 1) // secondary channel is below the primary channel
if (SecCHOffset == 1) /* secondary channel is below the primary channel */
{
if ((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500))
{
@ -964,7 +881,7 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_type = 1;
PrimaryCCA->PriCCA_flag = 1;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); /* USC MF */
if (PrimaryCCA->DupRTS_flag == 1)
PrimaryCCA->DupRTS_flag = 0;
}
@ -976,14 +893,14 @@ odm_DynamicPrimaryCCA(
}
}
else // interferecne disappear
else /* interferecne disappear */
{
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
}
}
else if (SecCHOffset == 2) // secondary channel is above the primary channel
else if (SecCHOffset == 2) /* secondary channel is above the primary channel */
{
if ((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500))
{
@ -991,7 +908,7 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_type = 1;
PrimaryCCA->PriCCA_flag = 1;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); /* LSC MF */
if (PrimaryCCA->DupRTS_flag == 1)
PrimaryCCA->DupRTS_flag = 0;
}
@ -1003,7 +920,7 @@ odm_DynamicPrimaryCCA(
}
}
else // interferecne disappear
else /* interferecne disappear */
{
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
@ -1015,33 +932,33 @@ odm_DynamicPrimaryCCA(
PrimaryCCA->Monitor_flag = 0;
}
//1 Dynamic Primary CCA Main Function
/* 1 Dynamic Primary CCA Main Function */
if (PrimaryCCA->Monitor_flag == 0)
{
if (Is40MHz) // if RFBW==40M mode which require to process primary cca
if (Is40MHz) /* if RFBW==40M mode which require to process primary cca */
{
//2 STA is NOT Connected
/* 2 STA is NOT Connected */
if (!bConnected)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n"));
if (PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected
if (PrimaryCCA->PriCCA_flag == 1) /* reset primary cca when STA is disconnected */
{
PrimaryCCA->PriCCA_flag = 0;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0);
}
if (PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected
if (PrimaryCCA->DupRTS_flag == 1) /* reset Duplicate RTS when STA is disconnected */
PrimaryCCA->DupRTS_flag = 0;
if (SecCHOffset == 1) // secondary channel is below the primary channel
if (SecCHOffset == 1) /* secondary channel is below the primary channel */
{
if ((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9))
{
PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
PrimaryCCA->intf_flag = 1; /* secondary channel interference is detected!!! */
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; /* interference is shift */
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; /* interference is in-band */
}
else
{
@ -1049,15 +966,15 @@ odm_DynamicPrimaryCCA(
PrimaryCCA->intf_type = 0;
}
}
else if (SecCHOffset == 2) // secondary channel is above the primary channel
else if (SecCHOffset == 2) /* secondary channel is above the primary channel */
{
if ((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9))
{
PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
PrimaryCCA->intf_flag = 1; /* secondary channel interference is detected!!! */
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; /* interference is shift */
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; /* interference is in-band */
}
else
{
@ -1068,10 +985,10 @@ odm_DynamicPrimaryCCA(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type));
}
//2 STA is Connected
/* 2 STA is Connected */
else
{
if (Client_40MHz == 0) //3 // client BW = 20MHz
if (Client_40MHz == 0) /* 3 client BW = 20MHz */
{
if (PrimaryCCA->PriCCA_flag == 0)
{
@ -1083,9 +1000,9 @@ odm_DynamicPrimaryCCA(
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag));
}
else //3 // client BW = 40MHz
else /* 3 client BW = 40MHz */
{
if (PrimaryCCA->intf_flag == 1) // interference is detected!!
if (PrimaryCCA->intf_flag == 1) /* interference is detected!! */
{
if (PrimaryCCA->intf_type == 1)
{
@ -1104,9 +1021,9 @@ odm_DynamicPrimaryCCA(
PrimaryCCA->DupRTS_flag = 1;
}
}
else // if intf_flag==0
else /* if intf_flag==0 */
{
if ((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low
if ((curTxOkCnt+curRxOkCnt)<10000) /* idle mode or TP traffic is very low */
{
if (SecCHOffset == 1)
{
@ -1114,9 +1031,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; /* interference is shift */
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; /* interference is in-band */
}
}
else if (SecCHOffset == 2)
@ -1125,26 +1042,26 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; /* interference is shift */
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; /* interference is in-band */
}
}
}
else // TP Traffic is High
else /* TP Traffic is High */
{
if (SecCHOffset == 1)
{
if (FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500))
{
if (Delay == 0) // add delay to avoid interference occurring abruptly, jump one time
if (Delay == 0) /* add delay to avoid interference occurring abruptly, jump one time */
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; /* interference is shift */
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; /* interference is in-band */
Delay = 1;
}
else
@ -1155,13 +1072,13 @@ odm_DynamicPrimaryCCA(
{
if (FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500))
{
if (Delay == 0) // add delay to avoid interference occurring abruptly
if (Delay == 0) /* add delay to avoid interference occurring abruptly */
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; /* interference is shift */
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; /* interference is in-band */
Delay = 1;
}
else
@ -1174,22 +1091,22 @@ odm_DynamicPrimaryCCA(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag));
}
}// end of connected
}/* end of connected */
}
}
//1 Dynamic Primary CCA Monitor Counter
/* 1 Dynamic Primary CCA Monitor Counter */
if ((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1))
{
if (Client_40MHz == 0) // client=20M no need to monitor primary cca flag
if (Client_40MHz == 0) /* client=20M no need to monitor primary cca flag */
{
Client_40MHz_pre = Client_40MHz;
return;
}
Counter++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter));
if ((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time
if ((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) /* Every 60 sec to monitor one time */
{
PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!!
PrimaryCCA->Monitor_flag = 1; /* monitor flag is triggered!!!!! */
if (PrimaryCCA->PriCCA_flag == 1)
{
PrimaryCCA->PriCCA_flag = 0;
@ -1202,7 +1119,7 @@ odm_DynamicPrimaryCCA(
Client_40MHz_pre = Client_40MHz;
}
#else //#if (RTL8188E_SUPPORT == 1)
#else /* if (RTL8188E_SUPPORT == 1) */
void
ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant)
{
@ -1225,4 +1142,4 @@ ODM_DynamicPrimaryCCA_DupRTS(
{
return false;
}
#endif //#if (RTL8188E_SUPPORT == 1)
#endif /* if (RTL8188E_SUPPORT == 1) */

10
hal/odm_RegConfig8188E.c
View file

@ -62,7 +62,7 @@ odm_ConfigRFReg_8188E(
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
@ -75,7 +75,7 @@ odm_ConfigRF_RadioA_8188E(
u4Byte Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte content = 0x1000; /* RF_Content: radioa_txt */
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
@ -90,7 +90,7 @@ odm_ConfigRF_RadioB_8188E(
u4Byte Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte content = 0x1001; /* RF_Content: radiob_txt */
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
@ -119,7 +119,7 @@ odm_ConfigBB_AGC_8188E(
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
@ -200,7 +200,7 @@ odm_ConfigBB_PHY_8188E(
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}

6
hal/odm_debug.c
View file

@ -18,9 +18,9 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"

54
hal/odm_interface.c
View file

@ -18,14 +18,14 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
//
// ODM IO Relative API.
//
/* */
/* ODM IO Relative API. */
/* */
u1Byte
ODM_Read1Byte(
@ -253,9 +253,9 @@ ODM_GetRFReg(
//
// ODM Memory relative API.
//
/* */
/* ODM Memory relative API. */
/* */
void
ODM_AllocateMemory(
PDM_ODM_T pDM_Odm,
@ -273,7 +273,7 @@ ODM_AllocateMemory(
#endif
}
// length could be ignored, used to detect memory leakage.
/* length could be ignored, used to detect memory leakage. */
void
ODM_FreeMemory(
PDM_ODM_T pDM_Odm,
@ -286,7 +286,7 @@ ODM_FreeMemory(
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
rtw_vmfree(pPtr, length);
#elif (DM_ODM_SUPPORT_TYPE & ODM_MP)
//PADAPTER Adapter = pDM_Odm->Adapter;
/* PADAPTER Adapter = pDM_Odm->Adapter; */
PlatformFreeMemory(pPtr, length);
#endif
}
@ -308,9 +308,9 @@ s4Byte ODM_CompareMemory(
//
// ODM MISC relative API.
//
/* */
/* ODM MISC relative API. */
/* */
void
ODM_AcquireSpinLock(
PDM_ODM_T pDM_Odm,
@ -342,9 +342,9 @@ ODM_ReleaseSpinLock(
#endif
}
//
// Work item relative API. FOr MP driver only~!
//
/* */
/* Work item relative API. FOr MP driver only~! */
/* */
void
ODM_InitializeWorkItem(
PDM_ODM_T pDM_Odm,
@ -441,9 +441,9 @@ ODM_IsWorkItemScheduled(
//
// ODM Timer relative API.
//
/* */
/* ODM Timer relative API. */
/* */
void
ODM_StallExecution(
u4Byte usDelay
@ -514,7 +514,7 @@ ODM_SetTimer(
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
mod_timer(pTimer, jiffies + (msDelay+9)/10);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
_set_timer(pTimer,msDelay ); //ms
_set_timer(pTimer,msDelay ); /* ms */
#elif (DM_ODM_SUPPORT_TYPE & ODM_MP)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformSetTimer(Adapter, pTimer, msDelay);
@ -576,8 +576,8 @@ ODM_ReleaseTimer(
PADAPTER Adapter = pDM_Odm->Adapter;
// <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm.
// Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail.
/* <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. */
/* Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. */
if (pTimer == 0)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n"));
@ -589,9 +589,9 @@ ODM_ReleaseTimer(
}
//
// ODM FW relative API.
//
/* */
/* ODM FW relative API. */
/* */
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
void
ODM_FillH2CCmd(
@ -652,7 +652,7 @@ ODM_FillH2CCmd(
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif (DM_ODM_SUPPORT_TYPE & ODM_MP)
//FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq);
/* FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq); */
return false;
#endif

307
hal/rtl8188e_cmd.c
View file

@ -45,8 +45,6 @@ static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)
u8 valid;
//DBG_88E(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num);
do{
valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
if (0 == valid ){
@ -115,7 +113,7 @@ _func_enter_;
if (padapter->bSurpriseRemoved == true)
goto exit;
//pay attention to if race condition happened in H2C cmd setting.
/* pay attention to if race condition happened in H2C cmd setting. */
do{
h2c_box_num = pHalData->LastHMEBoxNum;
@ -135,7 +133,7 @@ _func_enter_;
ext_cmd_len = CmdLen-3;
_rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer+3,ext_cmd_len );
//Write Ext command
/* Write Ext command */
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for (cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){
@ -146,7 +144,7 @@ _func_enter_;
rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
#endif
}
// Write command
/* Write command */
msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *RTL88E_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for (cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){
@ -159,9 +157,6 @@ _func_enter_;
bcmd_down = true;
// DBG_88E("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n"
// ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);
pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS;
}while ((!bcmd_down) && (retry_cnts--));
@ -223,21 +218,20 @@ _func_exit_;
}
//bitmap[0:27] = tx_rate_bitmap
//bitmap[28:31]= Rate Adaptive id
//arg[0:4] = macid
//arg[5] = Short GI
/* bitmap[0:27] = tx_rate_bitmap */
/* bitmap[28:31]= Rate Adaptive id */
/* arg[0:4] = macid */
/* arg[5] = Short GI */
void rtl8188e_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 macid, init_rate, raid, shortGIrate=false;
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_buddy_adapter_up(pAdapter) && pAdapter->adapter_type > PRIMARY_ADAPTER)
pHalData = GET_HAL_DATA(pAdapter->pbuddy_adapter);
#endif //CONFIG_CONCURRENT_MODE
#endif /* CONFIG_CONCURRENT_MODE */
macid = arg&0x1f;
@ -249,7 +243,7 @@ void rtl8188e_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level);
bitmap |= ((raid<<28)&0xf0000000);
#endif //CONFIG_ODM_REFRESH_RAMASK
#endif /* CONFIG_ODM_REFRESH_RAMASK */
init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f;
@ -259,9 +253,6 @@ void rtl8188e_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
if (shortGIrate==true)
init_rate |= BIT(6);
//rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
raid = (bitmap>>28) & 0x0f;
bitmap &= 0x0fffffff;
@ -286,7 +277,7 @@ void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode)
{
SETPWRMODE_PARM H2CSetPwrMode;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
u8 RLBM = 0; // 0:Min, 1:Max , 2:User define
u8 RLBM = 0; /* 0:Min, 1:Max , 2:User define */
_func_enter_;
DBG_88E("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __func__,
@ -316,8 +307,6 @@ _func_enter_;
break;
}
//H2CSetPwrMode.Mode = Mode;
H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps<<4)&0xf0) | (RLBM & 0x0f));
H2CSetPwrMode.AwakeInterval = 1;
@ -326,13 +315,13 @@ _func_enter_;
if (Mode > 0)
{
H2CSetPwrMode.PwrState = 0x00;// AllON(0x0C), RFON(0x04), RFOFF(0x00)
H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
#ifdef CONFIG_EXT_CLK
H2CSetPwrMode.Mode |= BIT(7);//supporting 26M XTAL CLK_Request feature.
#endif //CONFIG_EXT_CLK
H2CSetPwrMode.Mode |= BIT(7);/* supporting 26M XTAL CLK_Request feature. */
#endif /* CONFIG_EXT_CLK */
}
else
H2CSetPwrMode.PwrState = 0x0C;// AllON(0x0C), RFON(0x04), RFOFF(0x00)
H2CSetPwrMode.PwrState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
FillH2CCmd_88E(padapter, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);
@ -361,9 +350,6 @@ static void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
//DBG_88E("%s\n", __func__);
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
fctrl = &(pwlanhdr->frame_ctl);
@ -374,23 +360,22 @@ static void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
//pmlmeext->mgnt_seq++;
SetFrameSubType(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
//timestamp will be inserted by hardware
/* timestamp will be inserted by hardware */
pframe += 8;
pktlen += 8;
// beacon interval: 2 bytes
/* beacon interval: 2 bytes */
_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
pframe += 2;
pktlen += 2;
// capability info: 2 bytes
/* capability info: 2 bytes */
_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
pframe += 2;
@ -398,46 +383,44 @@ static void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
if ( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
{
//DBG_88E("ie len=%d\n", cur_network->IELength);
pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
_rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen);
goto _ConstructBeacon;
}
//below for ad-hoc mode
/* below for ad-hoc mode */
// SSID
/* SSID */
pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
// supported rates...
/* supported rates... */
rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen);
// DS parameter set
/* DS parameter set */
pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
if ( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
{
u32 ATIMWindow;
// IBSS Parameter Set...
//ATIMWindow = cur->Configuration.ATIMWindow;
/* IBSS Parameter Set... */
ATIMWindow = 0;
pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
}
//todo: ERP IE
/* todo: ERP IE */
// EXTERNDED SUPPORTED RATE
/* EXTERNDED SUPPORTED RATE */
if (rate_len > 8)
{
pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
}
//todo:HT for adhoc
/* todo:HT for adhoc */
_ConstructBeacon:
@ -448,9 +431,6 @@ _ConstructBeacon:
}
*pLength = pktlen;
//DBG_88E("%s bcn_sz=%d\n", __func__, pktlen);
}
static void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
@ -461,23 +441,21 @@ static void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//DBG_88E("%s\n", __func__);
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
// Frame control.
/* Frame control. */
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
SetPwrMgt(fctrl);
SetFrameSubType(pframe, WIFI_PSPOLL);
// AID.
/* AID. */
SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
// BSSID.
/* BSSID. */
_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
// TA.
/* TA. */
_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
*pLength = 16;
@ -501,20 +479,14 @@ static void ConstructNullFunctionData(
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//DBG_88E("%s:%d\n", __func__, bForcePowerSave);
pwlanhdr = (struct rtw_ieee80211_hdr*)pframe;
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
if (bForcePowerSave)
{
SetPwrMgt(fctrl);
}
switch (cur_network->network.InfrastructureMode)
{
switch (cur_network->network.InfrastructureMode) {
case Ndis802_11Infrastructure:
SetToDs(fctrl);
_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
@ -566,9 +538,6 @@ static void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
//DBG_88E("%s\n", __func__);
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
mac = myid(&(padapter->eeprompriv));
@ -596,36 +565,25 @@ static void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *
*pLength = pktlen;
}
// To check if reserved page content is destroyed by beacon beacuse beacon is too large.
// 2010.06.23. Added by tynli.
/* To check if reserved page content is destroyed by beacon beacuse beacon is too large. */
/* 2010.06.23. Added by tynli. */
void
CheckFwRsvdPageContent(
PADAPTER Adapter
)
{
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
u32 MaxBcnPageNum;
if (pHalData->FwRsvdPageStartOffset != 0)
{
/*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);
RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset),
("CheckFwRsvdPageContent(): The reserved page content has been"\
"destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!",
MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/
}
}
//
// Description: Fill the reserved packets that FW will use to RSVD page.
// Now we just send 4 types packet to rsvd page.
// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
// Input:
// bDLFinished - false: At the first time we will send all the packets as a large packet to Hw,
// so we need to set the packet length to total lengh.
// true: At the second time, we should send the first packet (default:beacon)
// to Hw again and set the lengh in descriptor to the real beacon lengh.
// 2009.10.15 by tynli.
/* */
/* Description: Fill the reserved packets that FW will use to RSVD page. */
/* Now we just send 4 types packet to rsvd page. */
/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */
/* Input: */
/* bDLFinished - false: At the first time we will send all the packets as a large packet to Hw, */
/* so we need to set the packet length to total lengh. */
/* true: At the second time, we should send the first packet (default:beacon) */
/* to Hw again and set the lengh in descriptor to the real beacon lengh. */
/* 2009.10.15 by tynli. */
static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
{
PHAL_DATA_TYPE pHalData;
@ -659,14 +617,14 @@ static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
TxDescLen = TXDESC_SIZE;
PageNum = 0;
//3 (1) beacon * 2 pages
/* 3 (1) beacon * 2 pages */
BufIndex = TXDESC_OFFSET;
ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength);
// When we count the first page size, we need to reserve description size for the RSVD
// packet, it will be filled in front of the packet in TXPKTBUF.
/* When we count the first page size, we need to reserve description size for the RSVD */
/* packet, it will be filled in front of the packet in TXPKTBUF. */
PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);
// To reserved 2 pages for beacon buffer. 2010.06.24.
/* To reserved 2 pages for beacon buffer. 2010.06.24. */
if (PageNeed == 1)
PageNeed += 1;
PageNum += PageNeed;
@ -674,7 +632,7 @@ static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
BufIndex += PageNeed*128;
//3 (2) ps-poll *1 page
/* 3 (2) ps-poll *1 page */
RsvdPageLoc.LocPsPoll = PageNum;
ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength);
rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, true, false);
@ -684,7 +642,7 @@ static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
BufIndex += PageNeed*128;
//3 (3) null data * 1 page
/* 3 (3) null data * 1 page */
RsvdPageLoc.LocNullData = PageNum;
ConstructNullFunctionData(
padapter,
@ -699,7 +657,7 @@ static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
BufIndex += PageNeed*128;
//3 (4) probe response * 1page
/* 3 (4) probe response * 1page */
RsvdPageLoc.LocProbeRsp = PageNum;
ConstructProbeRsp(
padapter,
@ -714,7 +672,7 @@ static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
BufIndex += PageNeed*128;
//3 (5) Qos null data
/* 3 (5) Qos null data */
RsvdPageLoc.LocQosNull = PageNum;
ConstructNullFunctionData(
padapter,
@ -728,27 +686,11 @@ static void SetFwRsvdPagePkt(PADAPTER padapter, bool bDLFinished)
PageNum += PageNeed;
TotalPacketLen = BufIndex + QosNullLength;
/*
BufIndex += PageNeed*128;
//3 (6) BT Qos null data
RsvdPageLoc.LocBTQosNull = PageNum;
ConstructNullFunctionData(
padapter,
&ReservedPagePacket[BufIndex],
&BTQosNullLength,
get_my_bssid(&pmlmeinfo->network),
true, 0, 0, false);
rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, false, true);
TotalPacketLen = BufIndex + BTQosNullLength;
*/
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL)
goto exit;
// update attribute
/* update attribute */
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(padapter, pattrib);
pattrib->qsel = 0x10;
@ -781,24 +723,18 @@ _func_enter_;
if (mstatus == 1)
{
// We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.
// Suggested by filen. Added by tynli.
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
// Do not set TSF again here or vWiFi beacon DMA INT will not work.
//correct_TSF(padapter, pmlmeext);
// Hw sequende enable by dedault. 2010.06.23. by tynli.
//rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF));
//rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
//Set REG_CR bit 8. DMA beacon by SW.
/* Set REG_CR bit 8. DMA beacon by SW. */
pHalData->RegCR_1 |= BIT0;
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
// Disable Hw protection for a time which revserd for Hw sending beacon.
// Fix download reserved page packet fail that access collision with the protection time.
// 2010.05.11. Added by tynli.
//SetBcnCtrlReg(padapter, 0, BIT3);
//SetBcnCtrlReg(padapter, BIT4, 0);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
/* 2010.05.11. Added by tynli. */
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
@ -808,31 +744,30 @@ _func_enter_;
bSendBeacon = true;
}
// Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6)));
pHalData->RegFwHwTxQCtrl &= (~BIT6);
// Clear beacon valid check bit.
/* Clear beacon valid check bit. */
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DLBcnCount = 0;
poll = 0;
do
{
// download rsvd page.
/* download rsvd page. */
SetFwRsvdPagePkt(padapter, false);
DLBcnCount++;
do
{
rtw_yield_os();
//rtw_mdelay_os(10);
// check rsvd page download OK.
/* rtw_mdelay_os(10); */
/* check rsvd page download OK. */
rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));
poll++;
} while (!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
}while (!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n"));
if (padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
@ -840,81 +775,42 @@ _func_enter_;
DBG_88E("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __func__ ,DLBcnCount, poll);
else
DBG_88E("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __func__, DLBcnCount, poll);
//
// We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower)
// becuase we need to free the Tx BCN Desc which is used by the first reserved page packet.
// At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return
// the beacon TCB in the following code. 2011.11.23. by tynli.
//
//if (bcn_valid && padapter->bEnterPnpSleep)
if (0)
{
if (bSendBeacon)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DLBcnCount = 0;
poll = 0;
do
{
SetFwRsvdPagePkt(padapter, true);
DLBcnCount++;
/* */
/* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */
/* becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. */
/* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */
/* the beacon TCB in the following code. 2011.11.23. by tynli. */
/* */
do
{
rtw_yield_os();
//rtw_mdelay_os(10);
// check rsvd page download OK.
rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));
poll++;
} while (!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
}while (!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n"));
if (padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
else if (!bcn_valid)
DBG_88E("%s: 2 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __func__ ,DLBcnCount, poll);
else
DBG_88E("%s: 2 Download RSVD success! DLBcnCount:%u, poll:%u\n", __func__, DLBcnCount, poll);
}
}
// Enable Bcn
//SetBcnCtrlReg(padapter, BIT3, 0);
//SetBcnCtrlReg(padapter, 0, BIT4);
/* Enable Bcn */
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4)));
// To make sure that if there exists an adapter which would like to send beacon.
// If exists, the origianl value of 0x422[6] will be 1, we should check this to
// prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
// the beacon cannot be sent by HW.
// 2010.06.23. Added by tynli.
/* To make sure that if there exists an adapter which would like to send beacon. */
/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bSendBeacon)
{
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));
pHalData->RegFwHwTxQCtrl |= BIT6;
}
//
// Update RSVD page location H2C to Fw.
//
/* */
/* Update RSVD page location H2C to Fw. */
/* */
if (bcn_valid)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DBG_88E("Set RSVD page location to Fw.\n");
//FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc);
}
// Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.
//if (!padapter->bEnterPnpSleep)
{
// Clear CR[8] or beacon packet will not be send to TxBuf anymore.
/* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
pHalData->RegCR_1 &= (~BIT0);
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
}
}
#ifdef CONFIG_WOWLAN
if (padapter->pwrctrlpriv.wowlan_mode){
JoinBssRptParm.OpMode = mstatus;
@ -924,7 +820,7 @@ _func_enter_;
} else {
DBG_88E_LEVEL(_drv_info_, "%s wowlan_mode is off\n", __func__);
}
#endif //CONFIG_WOWLAN
#endif /* CONFIG_WOWLAN */
_func_exit_;
}
@ -948,40 +844,33 @@ _func_enter_;
break;
case P2P_PS_ENABLE:
DBG_88E("P2P_PS_ENABLE\n");
// update CTWindow value.
/* update CTWindow value. */
if ( pwdinfo->ctwindow > 0 )
{
p2p_ps_offload->CTWindow_En = 1;
rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
}
// hw only support 2 set of NoA
/* hw only support 2 set of NoA */
for ( i=0 ; i<pwdinfo->noa_num ; i++)
{
// To control the register setting for which NOA
/* To control the register setting for which NOA */
rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
if (i == 0)
p2p_ps_offload->NoA0_En = 1;
else
p2p_ps_offload->NoA1_En = 1;
// config P2P NoA Descriptor Register
//DBG_88E("%s(): noa_duration = %x\n",__func__,pwdinfo->noa_duration[i]);
/* config P2P NoA Descriptor Register */
rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
//DBG_88E("%s(): noa_interval = %x\n",__func__,pwdinfo->noa_interval[i]);
rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
//DBG_88E("%s(): start_time = %x\n",__func__,pwdinfo->noa_start_time[i]);
rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
//DBG_88E("%s(): noa_count = %x\n",__func__,pwdinfo->noa_count[i]);
rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
}
if ( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )
{
// rst p2p circuit
/* rst p2p circuit */
rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->Offload_En = 1;
@ -1018,7 +907,7 @@ _func_enter_;
_func_exit_;
}
#endif //CONFIG_P2P_PS
#endif /* CONFIG_P2P_PS */
#ifdef CONFIG_TSF_RESET_OFFLOAD
/*
@ -1066,7 +955,7 @@ int reset_tsf(PADAPTER Adapter, u8 reset_port )
}
#endif // CONFIG_TSF_RESET_OFFLOAD
#endif /* CONFIG_TSF_RESET_OFFLOAD */
#ifdef CONFIG_WOWLAN
void rtl8188es_set_wowlan_cmd(_adapter* padapter, u8 enable)
@ -1112,19 +1001,19 @@ _func_enter_;
DBG_88E_LEVEL(_drv_info_, "%s, disconnected, no FwJoinBssReport\n",__func__);
rtw_msleep_os(2);
//WOWLAN_GPIO_ACTIVE means GPIO high active
//pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE;
/* WOWLAN_GPIO_ACTIVE means GPIO high active */
/* pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; */
pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP;
pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP;
//DataPinWakeUp
/* DataPinWakeUp */
#ifdef CONFIG_USB_HCI
pwowlan_parm.gpio_index=0x0;
#endif //CONFIG_USB_HCI
#endif /* CONFIG_USB_HCI */
#ifdef CONFIG_SDIO_HCI
pwowlan_parm.gpio_index=0x80;
#endif //CONFIG_SDIO_HCI
#endif /* CONFIG_SDIO_HCI */
DBG_88E_LEVEL(_drv_info_, "%s 5.pwowlan_parm.mode=0x%x\n",__func__,pwowlan_parm.mode);
DBG_88E_LEVEL(_drv_info_, "%s 6.pwowlan_parm.index=0x%x\n",__func__,pwowlan_parm.gpio_index);
@ -1132,19 +1021,19 @@ _func_enter_;
rtw_msleep_os(2);
//disconnect decision
/* disconnect decision */
pwowlan_parm.mode =1;
pwowlan_parm.gpio_index=0;
pwowlan_parm.gpio_duration=0;
FillH2CCmd_88E(padapter, H2C_COM_DISCNT_DECISION, 3, (u8 *)&pwowlan_parm);
//keep alive period = 10 * 10 BCN interval
/* keep alive period = 10 * 10 BCN interval */
pwowlan_parm.mode =1;
pwowlan_parm.gpio_index=10;
res = FillH2CCmd_88E(padapter, H2C_COM_KEEP_ALIVE, 2, (u8 *)&pwowlan_parm);
rtw_msleep_os(2);
//Configure STA security information for GTK rekey wakeup event.
/* Configure STA security information for GTK rekey wakeup event. */
paoac_global_info_parm.pairwiseEncAlg=
padapter->securitypriv.dot11PrivacyAlgrthm;
paoac_global_info_parm.groupEncAlg=
@ -1152,7 +1041,7 @@ _func_enter_;
res = FillH2CCmd_88E(padapter, H2C_COM_AOAC_GLOBAL_INFO, 2, (u8 *)&paoac_global_info_parm);
rtw_msleep_os(2);
//enable Remote wake ctrl
/* enable Remote wake ctrl */
pwowlan_parm.mode = 1;
pwowlan_parm.gpio_index=0;
pwowlan_parm.gpio_duration=0;
@ -1167,4 +1056,4 @@ _func_exit_;
DBG_88E_LEVEL(_drv_info_, "-%s res:%d-\n", __func__, res);
return ;
}
#endif //CONFIG_WOWLAN
#endif /* CONFIG_WOWLAN */

231
hal/rtl8188e_dm.c
View file

@ -17,27 +17,27 @@
*
*
******************************************************************************/
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
/* */
/* Description: */
/* */
/* This file is for 92CE/92CU dynamic mechanism only */
/* */
/* */
/* */
#define _RTL8188E_DM_C_
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8188e_hal.h>
//============================================================
// Global var
//============================================================
/* */
/* Global var */
/* */
static void
@ -65,14 +65,14 @@ static void dm_CheckPbcGPIO(_adapter *padapter)
#ifdef CONFIG_USB_HCI
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level
rtw_write8(padapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
tmp1byte =rtw_read8(padapter, GPIO_IN);
@ -85,7 +85,6 @@ static void dm_CheckPbcGPIO(_adapter *padapter)
}
#else
tmp1byte = rtw_read8(padapter, GPIO_IN);
//RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte));
if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
return ;
@ -98,8 +97,8 @@ static void dm_CheckPbcGPIO(_adapter *padapter)
if ( true == bPbcPressed)
{
// Here we only set bPbcPressed to true
// After trigger PBC, the variable will be set to false
/* Here we only set bPbcPressed to true */
/* After trigger PBC, the variable will be set to false */
DBG_88E("CheckPbcGPIO - PBC is pressed\n");
#ifdef RTK_DMP_PLATFORM
@ -111,7 +110,7 @@ static void dm_CheckPbcGPIO(_adapter *padapter)
#else
if ( padapter->pid[0] == 0 )
{ // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver.
{ /* 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */
return;
}
@ -123,15 +122,15 @@ static void dm_CheckPbcGPIO(_adapter *padapter)
}
#ifdef CONFIG_PCI_HCI
//
// Description:
// Perform interrupt migration dynamically to reduce CPU utilization.
//
// Assumption:
// 1. Do not enable migration under WIFI test.
//
// Created by Roger, 2010.03.05.
//
/* */
/* Description: */
/* Perform interrupt migration dynamically to reduce CPU utilization. */
/* */
/* Assumption: */
/* 1. Do not enable migration under WIFI test. */
/* */
/* Created by Roger, 2010.03.05. */
/* */
void
dm_InterruptMigration(
PADAPTER Adapter
@ -144,72 +143,50 @@ dm_InterruptMigration(
bool ACIntToSet = false;
// Retrieve current interrupt migration and Tx four ACs IMR settings first.
/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
bCurrentIntMt = pHalData->bInterruptMigration;
bCurrentACIntDisable = pHalData->bDisableTxInt;
//
// <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
// when interrupt migration is set before. 2010.03.05.
//
/* */
/* <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics */
/* when interrupt migration is set before. 2010.03.05. */
/* */
if (!Adapter->registrypriv.wifi_spec &&
(check_fwstate(pmlmepriv, _FW_LINKED)== true) &&
pmlmepriv->LinkDetectInfo.bHigherBusyTraffic)
{
IntMtToSet = true;
// To check whether we should disable Tx interrupt or not.
/* To check whether we should disable Tx interrupt or not. */
if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic )
ACIntToSet = true;
}
//Update current settings.
/* Update current settings. */
if ( bCurrentIntMt != IntMtToSet ){
DBG_88E("%s(): Update interrrupt migration(%d)\n",__func__,IntMtToSet);
if (IntMtToSet)
{
//
// <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.
// timer 25ns*0xfa0=100us for 0xf packets.
// 2010.03.05.
//
rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx
/* */
/* <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter. */
/* timer 25ns*0xfa0=100us for 0xf packets. */
/* 2010.03.05. */
/* */
rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);/* 0x306:Rx, 0x307:Tx */
pHalData->bInterruptMigration = IntMtToSet;
}
else
{
// Reset all interrupt migration settings.
} else {
/* Reset all interrupt migration settings. */
rtw_write32(Adapter, REG_INT_MIG, 0);
pHalData->bInterruptMigration = IntMtToSet;
}
}
/*if ( bCurrentACIntDisable != ACIntToSet ){
DBG_88E("%s(): Update AC interrrupt(%d)\n",__func__,ACIntToSet);
if (ACIntToSet) // Disable four ACs interrupts.
{
//
// <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization.
// When extremely highly Rx OK occurs, we will disable Tx interrupts.
// 2010.03.05.
//
UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );
pHalData->bDisableTxInt = ACIntToSet;
}
else// Enable four ACs interrupts.
{
UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );
pHalData->bDisableTxInt = ACIntToSet;
}
}*/
}
#endif
//
// Initialize GPIO setting registers
//
/* */
/* Initialize GPIO setting registers */
/* */
static void
dm_InitGPIOSetting(
PADAPTER Adapter
@ -223,7 +200,7 @@ dm_InitGPIOSetting(
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
#ifdef CONFIG_BT_COEXIST
// UMB-B cut bug. We need to support the modification.
/* UMB-B cut bug. We need to support the modification. */
if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
pHalData->bt_coexist.BT_Coexist)
{
@ -234,9 +211,9 @@ dm_InitGPIOSetting(
}
//============================================================
// functions
//============================================================
/* */
/* functions */
/* */
static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
{
@ -245,9 +222,9 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
u8 cut_ver,fab_ver;
//
// Init Value
//
/* */
/* Init Value */
/* */
_rtw_memset(pDM_Odm,0,sizeof(pDM_Odm));
pDM_Odm->Adapter = Adapter;
@ -257,7 +234,7 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
if (Adapter->interface_type == RTW_GSPI )
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);
else
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);/* RTL871X_HCI_TYPE */
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8188E);
@ -289,10 +266,8 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
pdmpriv->InitODMFlag = 0;
#else
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |
ODM_RF_TX_PWR_TRACK //|
ODM_RF_TX_PWR_TRACK /* */
;
//if (pHalData->AntDivCfg)
// pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
#endif
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
@ -309,7 +284,7 @@ static void Update_ODM_ComInfo_88E(PADAPTER Adapter)
int i;
#ifdef CONFIG_DISABLE_ODM
pdmpriv->InitODMFlag = 0;
#else //CONFIG_DISABLE_ODM
#else /* CONFIG_DISABLE_ODM */
pdmpriv->InitODMFlag = ODM_BB_DIG |
#ifdef CONFIG_ODM_REFRESH_RAMASK
@ -333,9 +308,9 @@ static void Update_ODM_ComInfo_88E(PADAPTER Adapter)
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |
ODM_RF_TX_PWR_TRACK;
}
#endif//(MP_DRIVER==1)
#endif/* MP_DRIVER==1) */
#endif//CONFIG_DISABLE_ODM
#endif/* CONFIG_DISABLE_ODM */
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes));
@ -347,29 +322,13 @@ static void Update_ODM_ComInfo_88E(PADAPTER Adapter)
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));
//================= only for 8192D =================
/*
//pHalData->CurrentBandType92D
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));
//================= only for 8192D =================
// driver havn't those variable now
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));
*/
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
for (i=0; i< NUM_STA; i++)
{
//pDM_Odm->pODM_StaInfo[i] = NULL;
ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);
}
}
void
rtl8188e_InitHalDm(
@ -409,7 +368,7 @@ rtl8188e_HalDmWatchDog(
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
#ifdef CONFIG_CONCURRENT_MODE
PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
#endif //CONFIG_CONCURRENT_MODE
#endif /* CONFIG_CONCURRENT_MODE */
_func_enter_;
@ -439,18 +398,18 @@ rtl8188e_HalDmWatchDog(
#endif
#ifdef CONFIG_P2P_PS
// Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
// modifed by thomas. 2011.06.11.
/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
/* modifed by thomas. 2011.06.11. */
if (Adapter->wdinfo.p2p_ps_mode)
bFwPSAwake = false;
#endif //CONFIG_P2P_PS
#endif /* CONFIG_P2P_PS */
if ( (hw_init_completed == true)
&& ((!bFwCurrentInPSMode) && bFwPSAwake))
{
//
// Calculate Tx/Rx statistics.
//
/* */
/* Calculate Tx/Rx statistics. */
/* */
dm_CheckStatistics(Adapter);
#ifdef CONFIG_CONCURRENT_MODE
@ -458,25 +417,12 @@ rtl8188e_HalDmWatchDog(
goto _record_initrate;
#endif
//
// Dynamically switch RTS/CTS protection.
//
//dm_CheckProtection(Adapter);
#ifdef CONFIG_PCI_HCI
// 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput.
// Tx Migration settings.
//dm_InterruptMigration(Adapter);
//if (Adapter->HalFunc.TxCheckStuckHandler(Adapter))
// PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem));
#endif
_record_initrate:
_func_exit_;
}
//ODM
/* ODM */
if (hw_init_completed == true)
{
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
@ -491,7 +437,7 @@ rtl8188e_HalDmWatchDog(
if (Adapter->stapriv.asoc_sta_count > 2)
bLinked = true;
}
else{//Station mode
else{/* Station mode */
if (check_fwstate(pmlmepriv, _FW_LINKED)== true)
bLinked = true;
}
@ -499,7 +445,7 @@ rtl8188e_HalDmWatchDog(
#ifdef CONFIG_CONCURRENT_MODE
if (check_buddy_fw_link(Adapter))
bLinked = true;
#endif //CONFIG_CONCURRENT_MODE
#endif /* CONFIG_CONCURRENT_MODE */
ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked);
ODM_DMWatchdog(&pHalData->odmpriv);
@ -508,14 +454,14 @@ rtl8188e_HalDmWatchDog(
skip_dm:
// Check GPIO to determine current RF on/off and Pbc status.
// Check Hardware Radio ON/OFF or not
/* Check GPIO to determine current RF on/off and Pbc status. */
/* Check Hardware Radio ON/OFF or not */
#ifdef CONFIG_PCI_HCI
if (pHalData->bGpioHwWpsPbc)
#endif
{
//temp removed
//dm_CheckPbcGPIO(Adapter);
/* temp removed */
/* dm_CheckPbcGPIO(Adapter); */
}
return;
}
@ -526,10 +472,8 @@ void rtl8188e_init_dm_priv(PADAPTER Adapter)
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
//_rtw_spinlock_init(&(pHalData->odm_stainfo_lock));
Init_ODM_ComInfo_88E(Adapter);
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter);
ODM_InitAllTimers(podmpriv );
#endif
ODM_InitDebugSetting(podmpriv);
@ -540,29 +484,23 @@ void rtl8188e_deinit_dm_priv(PADAPTER Adapter)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);
ODM_CancelAllTimers(podmpriv);
#endif
}
#ifdef CONFIG_ANTENNA_DIVERSITY
// Add new function to reset the state of antenna diversity before link.
//
// Compare RSSI for deciding antenna
/* Add new function to reset the state of antenna diversity before link. */
/* */
/* Compare RSSI for deciding antenna */
void AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
{
//PADAPTER Adapter = pDM_Odm->Adapter ;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if (0 != pHalData->AntDivCfg )
{
//DBG_88E("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
// src->Rssi,query_rx_pwr_percentage(src->Rssi));
//select optimum_antenna for before linked =>For antenna diversity
if (dst->Rssi >= src->Rssi )//keep org parameter
/* select optimum_antenna for before linked =>For antenna diversity */
if (dst->Rssi >= src->Rssi )/* keep org parameter */
{
src->Rssi = dst->Rssi;
src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
@ -570,7 +508,7 @@ void AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src
}
}
// Add new function to reset the state of antenna diversity before link.
/* Add new function to reset the state of antenna diversity before link. */
u8 AntDivBeforeLink8188E(PADAPTER Adapter )
{
@ -579,12 +517,9 @@ u8 AntDivBeforeLink8188E(PADAPTER Adapter )
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
// Condition that does not need to use antenna diversity.
/* Condition that does not need to use antenna diversity. */
if (pHalData->AntDivCfg==0)
{
//DBG_88E("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
return false;
}
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
{
@ -593,17 +528,13 @@ u8 AntDivBeforeLink8188E(PADAPTER Adapter )
if (pDM_SWAT_Table->SWAS_NoLink_State == 0){
//switch channel
/* switch channel */
pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, false);
//DBG_88E("%s change antenna to ANT_( %s ).....\n",__func__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B");
return true;
}
else
{
} else {
pDM_SWAT_Table->SWAS_NoLink_State = 0;
return false;
}

543
hal/rtl8188e_hal_init.c
View file

File diff suppressed because it is too large Load diff

299
hal/rtl8188e_mp.c
View file

@ -75,19 +75,19 @@ static void Hal_disable_dm(PADAPTER padapter)
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
//3 1. disable firmware dynamic mechanism
// disable Power Training, Rate Adaptive
/* 3 1. disable firmware dynamic mechanism */
/* disable Power Training, Rate Adaptive */
v8 = rtw_read8(padapter, REG_BCN_CTRL);
v8 &= ~EN_BCN_FUNCTION;
rtw_write8(padapter, REG_BCN_CTRL, v8);
//3 2. disable driver dynamic mechanism
// disable Dynamic Initial Gain
// disable High Power
// disable Power Tracking
/* 3 2. disable driver dynamic mechanism */
/* disable Dynamic Initial Gain */
/* disable High Power */
/* disable Power Tracking */
Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, false);
// enable APK, LCK and IQK but disable power tracking
/* enable APK, LCK and IQK but disable power tracking */
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = false;
Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, true);
}
@ -111,14 +111,14 @@ static void Hal_disable_dm(PADAPTER padapter)
*---------------------------------------------------------------------------*/
void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
{
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
/* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); */
struct mp_priv *pmp = &pAdapter->mppriv;
u1Byte ChannelToSw = pmp->channel;
ULONG ulRateIdx = pmp->rateidx;
ULONG ulbandwidth = pmp->bandwidth;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
// <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.
/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. */
pmp->MptCtx.backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pmp->MptCtx.backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
@ -137,38 +137,36 @@ void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, bool bInCH14)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
// get current cck swing value and check 0xa22 & 0xa23 later to match the table.
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
if (!bInCH14)
{
// Readback the current bb cck swing value and compare with the table to
// get the current swing index
/* Readback the current bb cck swing value and compare with the table to */
/* get the current swing index */
for (i = 0; i < CCK_TABLE_SIZE; i++)
{
if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
{
CCKSwingIndex = i;
// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
break;
}
}
//Write 0xa22 0xa23
/* Write 0xa22 0xa23 */
TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
//Write 0xa24 ~ 0xa27
/* Write 0xa24 ~ 0xa27 */
TempVal2 = 0;
TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
//Write 0xa28 0xa29
/* Write 0xa28 0xa29 */
TempVal3 = 0;
TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
@ -181,24 +179,22 @@ void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, bool bInCH14)
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
{
CCKSwingIndex = i;
// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
break;
}
}
//Write 0xa22 0xa23
/* Write 0xa22 0xa23 */
TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
(CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
//Write 0xa24 ~ 0xa27
/* Write 0xa24 ~ 0xa27 */
TempVal2 = 0;
TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
(CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
(CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
(CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
//Write 0xa28 0xa29
/* Write 0xa28 0xa29 */
TempVal3 = 0;
TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
(CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
@ -213,7 +209,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
{
s32 TempCCk;
u8 CCK_index, CCK_index_old;
u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even
u8 Action = 0; /* 0: no action, 1: even->odd, 2:odd->even */
u8 TimeOut = 100;
s32 i = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@ -225,12 +221,12 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
if (!IS_92C_SERIAL(pHalData->VersionID))
return;
if (beven && !pMptCtx->bMptIndexEven) //odd->even
if (beven && !pMptCtx->bMptIndexEven) /* odd->even */
{
Action = 2;
pMptCtx->bMptIndexEven = true;
}
else if (!beven && pMptCtx->bMptIndexEven) //even->odd
else if (!beven && pMptCtx->bMptIndexEven) /* even->odd */
{
Action = 1;
pMptCtx->bMptIndexEven = false;
@ -238,7 +234,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
if (Action != 0)
{
//Query CCK default setting From 0xa24
/* Query CCK default setting From 0xa24 */
TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
for (i = 0; i < CCK_TABLE_SIZE; i++)
{
@ -247,8 +243,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == true)
{
CCK_index_old = (u8) i;
// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",
// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
break;
}
}
@ -257,8 +251,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == true)
{
CCK_index_old = (u8) i;
// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",
// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
break;
}
}
@ -269,10 +261,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
else
CCK_index = CCK_index_old + 1;
// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",
// CCK_index));
//Adjust CCK according to gain index
/* Adjust CCK according to gain index */
if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
@ -316,7 +305,7 @@ void Hal_SetChannel(PADAPTER pAdapter)
u8 rate = pmp->rateidx;
// set RF channel register
/* set RF channel register */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
{
if (IS_HARDWARE_TYPE_8192D(pAdapter))
@ -356,12 +345,12 @@ void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
u32 tmpval = 0;
// rf-A cck tx power
/* rf-A cck tx power */
write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
// rf-B cck tx power
/* rf-B cck tx power */
write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
@ -379,7 +368,7 @@ void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
// HT Tx-rf(A)
/* HT Tx-rf(A) */
tmpval = TxPower[RF_PATH_A];
TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
@ -390,7 +379,7 @@ void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
// HT Tx-rf(B)
/* HT Tx-rf(B) */
tmpval = TxPower[RF_PATH_B];
TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
@ -432,7 +421,7 @@ void Hal_SetAntennaPathPower(PADAPTER pAdapter)
case RF_8256:
case RF_6052:
Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
break;
@ -469,13 +458,13 @@ void Hal_SetTxPower(PADAPTER pAdapter)
switch (pHalData->rf_chip)
{
// 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!
// We should call normal driver API later!!
/* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
/* We should call normal driver API later!! */
case RF_8225:
case RF_8256:
case RF_6052:
Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
break;
@ -483,9 +472,6 @@ void Hal_SetTxPower(PADAPTER pAdapter)
default:
break;
}
// SetCCKTxPower(pAdapter, TxPower);
// SetOFDMTxPower(pAdapter, TxPower);
}
void Hal_SetDataRate(PADAPTER pAdapter)
@ -509,8 +495,8 @@ void Hal_SetAntenna(PADAPTER pAdapter)
p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
p_ofdm_tx->r_ant_ht1 = 0x1;
p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A
p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3
p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */
p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */
switch (pAdapter->mppriv.antenna_tx)
{
@ -523,17 +509,15 @@ void Hal_SetAntenna(PADAPTER pAdapter)
p_cck_txrx->r_ccktx_enable = 0x8;
chgTx = 1;
// From SD3 Willis suggestion !!! Set RF A=TX and B as standby
// if (IS_HARDWARE_TYPE_8192S(pAdapter))
{
/* From SD3 Willis suggestion !!! Set RF A=TX and B as standby */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
r_ofdm_tx_en_val = 0x3;
// Power save
//cosa r_ant_select_ofdm_val = 0x11111111;
/* Power save */
/* cosa r_ant_select_ofdm_val = 0x11111111; */
// We need to close RFB by SW control
/* We need to close RFB by SW control */
if (pHalData->rf_type == RF_2T2R)
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
@ -542,7 +526,6 @@ void Hal_SetAntenna(PADAPTER pAdapter)
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
}
}
break;
case ANTENNA_B:
@ -554,31 +537,26 @@ void Hal_SetAntenna(PADAPTER pAdapter)
p_cck_txrx->r_ccktx_enable = 0x4;
chgTx = 1;
// From SD3 Willis suggestion !!! Set RF A as standby
//if (IS_HARDWARE_TYPE_8192S(pAdapter))
{
/* From SD3 Willis suggestion !!! Set RF A as standby */
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
// r_ofdm_tx_en_val = 0x3;
// Power save
//cosa r_ant_select_ofdm_val = 0x22222222;
/* Power save */
/* cosa r_ant_select_ofdm_val = 0x22222222; */
// 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.
// 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control
/* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
/* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
}
break;
case ANTENNA_AB: // For 8192S
case ANTENNA_AB: /* For 8192S */
p_ofdm_tx->r_tx_antenna = 0x3;
r_ofdm_tx_en_val = 0x3;
p_ofdm_tx->r_ant_l = 0x3;
@ -587,15 +565,13 @@ void Hal_SetAntenna(PADAPTER pAdapter)
p_cck_txrx->r_ccktx_enable = 0xC;
chgTx = 1;
// From SD3 Willis suggestion !!! Set RF B as standby
//if (IS_HARDWARE_TYPE_8192S(pAdapter))
{
/* From SD3 Willis suggestion !!! Set RF B as standby */
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
// Disable Power save
//cosa r_ant_select_ofdm_val = 0x3321333;
// 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
/* Disable Power save */
/* cosa r_ant_select_ofdm_val = 0x3321333; */
/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
if (pHalData->rf_type == RF_2T2R)
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
@ -603,38 +579,36 @@ void Hal_SetAntenna(PADAPTER pAdapter)
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
}
break;
default:
break;
}
//
// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
// r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
// r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D
//
/* */
/* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
/* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
/* */
switch (pAdapter->mppriv.antenna_rx)
{
case ANTENNA_A:
r_rx_antenna_ofdm = 0x1; // A
p_cck_txrx->r_cckrx_enable = 0x0; // default: A
p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A
r_rx_antenna_ofdm = 0x1; /* A */
p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
chgRx = 1;
break;
case ANTENNA_B:
r_rx_antenna_ofdm = 0x2; // B
p_cck_txrx->r_cckrx_enable = 0x1; // default: B
p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B
r_rx_antenna_ofdm = 0x2; /* B */
p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
chgRx = 1;
break;
case ANTENNA_AB:
r_rx_antenna_ofdm = 0x3; // AB
p_cck_txrx->r_cckrx_enable = 0x0; // default:A
p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B
r_rx_antenna_ofdm = 0x3; /* AB */
p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
chgRx = 1;
break;
@ -649,12 +623,12 @@ void Hal_SetAntenna(PADAPTER pAdapter)
case RF_8225:
case RF_8256:
case RF_6052:
//r_ant_sel_cck_val = r_ant_select_cck_val;
PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx
PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx
PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx
/* r_ant_sel_cck_val = r_ant_select_cck_val; */
PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /* OFDM Tx */
PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /* OFDM Tx */
PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */
break;
@ -696,19 +670,13 @@ void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
{
_write_rfreg( pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 |BIT16 , 0x03 );
// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
}
u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
{
u32 ThermalValue = 0;
//ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0]
ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);
// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));
return (u8)ThermalValue;
}
@ -723,52 +691,51 @@ void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
if (bStart)// Start Single Carrier.
if (bStart)/* Start Single Carrier. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
// 1. if OFDM block on?
/* 1. if OFDM block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
{
// 2. set CCK test mode off, set to CCK normal mode
/* 2. set CCK test mode off, set to CCK normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
// 3. turn on scramble setting
/* 3. turn on scramble setting */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
}
// 4. Turn On Single Carrier Tx and turn off the other test modes.
/* 4. Turn On Single Carrier Tx and turn off the other test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
#ifdef CONFIG_RTL8192C
// 5. Disable TX power saving at STF & LLTF
/* 5. Disable TX power saving at STF & LLTF */
write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);
#endif
//for dynamic set Power index.
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else// Stop Single Carrier.
else/* Stop Single Carrier. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));
// Turn off all test modes.
/* Turn off all test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
#ifdef CONFIG_RTL8192C
// Cancel disable TX power saving at STF&LLTF
/* Cancel disable TX power saving at STF&LLTF */
write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);
#endif
//Delay 10 ms //delay_ms(10);
rtw_msleep_os(10);
//BB Reset
/* BB Reset */
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
//Stop for dynamic set Power index.
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
@ -798,10 +765,10 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
}
pAdapter->mppriv.MptCtx.bSingleTone = bStart;
if (bStart)// Start Single Tone.
if (bStart)/* Start Single Tone. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));
{ // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter))
{
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
@ -818,31 +785,31 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
rtw_usleep_os(100);
if (rfPath == RF_PATH_A)
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); /* PAD all on. */
else if (rfPath == RF_PATH_B)
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
rtw_usleep_os(100);
}
else
{
write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
rtw_usleep_os(100);
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
rtw_usleep_os(100);
}
//for dynamic set Power index.
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else// Stop Single Tone.
else/* Stop Single Tone. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
{ // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
// <20120326, Kordan> Only in single tone mode. (asked by Edlu)
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
/* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter))
{
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
@ -856,17 +823,17 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
if (is92C) {
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
rtw_usleep_os(100);
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); /* PAD all on. */
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); /* PAD all on. */
rtw_usleep_os(100);
} else {
write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
rtw_usleep_os(100);
write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.
write_rfreg(pAdapter, rfPath, 0x00, 0x30000); /* PAD all on. */
rtw_usleep_os(100);
}
//Stop for dynamic set Power index.
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
@ -879,53 +846,49 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
{
pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
if (bStart) // Start Carrier Suppression.
if (bStart) /* Start Carrier Suppression. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
//if (pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
{
// 1. if CCK block on?
/* 1. if CCK block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
//Turn Off All Test Mode
/* Turn Off All Test Mode */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /* turn off scramble setting */
//Set CCK Tx Test Rate
//PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps
/* Set CCK Tx Test Rate */
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /* Set FTxRate to 1Mbps */
}
//for dynamic set Power index.
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else// Stop Carrier Suppression.
else/* Stop Carrier Suppression. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
//if (pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /* turn on scramble setting */
//BB Reset
/* BB Reset */
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
}
//Stop for dynamic set Power index.
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
//DbgPrint("\n MPT_ProSetCarrierSupp() is finished.\n");
}
void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
@ -937,28 +900,28 @@ void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
RT_TRACE(_module_mp_, _drv_alert_,
("SetCCKContinuousTx: test start\n"));
// 1. if CCK block on?
/* 1. if CCK block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
//Turn Off All Test Mode
/* Turn Off All Test Mode */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
//Set CCK Tx Test Rate
/* Set CCK Tx Test Rate */
cckrate = pAdapter->mppriv.rateidx;
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
#ifdef CONFIG_RTL8192C
// Patch for CCK 11M waveform
/* Patch for CCK 11M waveform */
if (cckrate == MPT_RATE_1M)
write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);
else
write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);
#endif
//for dynamic set Power index.
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
@ -967,14 +930,14 @@ void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
RT_TRACE(_module_mp_, _drv_info_,
("SetCCKContinuousTx: test stop\n"));
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
//BB Reset
/* BB Reset */
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
//Stop for dynamic set Power index.
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
@ -989,23 +952,23 @@ void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
if (bStart) {
RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
// 1. if OFDM block on?
/* 1. if OFDM block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
{
// 2. set CCK test mode off, set to CCK normal mode
/* 2. set CCK test mode off, set to CCK normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
// 3. turn on scramble setting
/* 3. turn on scramble setting */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
}
// 4. Turn On Continue Tx and turn off the other test modes.
/* 4. Turn On Continue Tx and turn off the other test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
//for dynamic set Power index.
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
@ -1014,13 +977,13 @@ void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
//Delay 10 ms
/* Delay 10 ms */
rtw_msleep_os(10);
//BB Reset
/* BB Reset */
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
//Stop for dynamic set Power index.
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
@ -1046,4 +1009,4 @@ void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
}
}
#endif // CONFIG_MP_INCLUDE
#endif /* CONFIG_MP_INCLUDE */

1059
hal/rtl8188e_phycfg.c
View file

File diff suppressed because it is too large Load diff

235
hal/rtl8188e_rf6052.c
View file

@ -48,17 +48,17 @@
#include <rtl8188e_hal.h>
/*---------------------------Define Local Constant---------------------------*/
// Define local structure for debug!!!!!
/* Define local structure for debug!!!!! */
typedef struct RF_Shadow_Compare_Map {
// Shadow register value
/* Shadow register value */
u32 Value;
// Compare or not flag
/* Compare or not flag */
u8 Compare;
// Record If it had ever modified unpredicted
/* Record If it had ever modified unpredicted */
u8 ErrorOrNot;
// Recorver Flag
/* Recorver Flag */
u8 Recorver;
//
/* */
u8 Driver_Write;
}RF_SHADOW_T;
/*---------------------------Define Local Constant---------------------------*/
@ -69,8 +69,8 @@ typedef struct RF_Shadow_Compare_Map {
/*------------------------Define local variable------------------------------*/
// 2008/11/20 MH For Debug only, RF
//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
/* 2008/11/20 MH For Debug only, RF */
/* static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */
static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
/*------------------------Define local variable------------------------------*/
@ -80,7 +80,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
*
* Overview: For RL6052, we must change some RF settign for 1T or 2T.
*
* Input: u2Byte DataRate // 0x80-8f, 0x90-9f
* Input: u2Byte DataRate 0x80-8f, 0x90-9f
*
* Output: NONE
*
@ -95,7 +95,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
/* We do not support gain table change inACUT now !!!! Delete later !!! */
} /* RF_ChangeTxPath */
@ -105,7 +105,7 @@ void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
@ -116,7 +116,7 @@ void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
void
rtl8188e_PHY_RF6052SetBandwidth(
PADAPTER Adapter,
HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
HT_CHANNEL_WIDTH Bandwidth) /* 20M or 40M */
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -133,7 +133,7 @@ rtl8188e_PHY_RF6052SetBandwidth(
break;
default:
//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
break;
}
@ -166,13 +166,13 @@ rtl8188e_PHY_RF6052SetCckTxPower(
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
//PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
bool TurboScanOff = false;
u8 idx1, idx2;
u8* ptr;
u8 direction;
//FOR CE ,must disable turbo scan
/* FOR CE ,must disable turbo scan */
TurboScanOff = true;
@ -181,7 +181,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;//disable turbo scan
TurboScanOff = true;/* disable turbo scan */
if (TurboScanOff)
{
@ -191,7 +191,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
#ifdef CONFIG_USB_HCI
// 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
TxAGC[idx1] = 0x20;
#endif
@ -200,9 +200,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
}
else
{
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
{
TxAGC[RF_PATH_A] = 0x10101010;
@ -247,41 +247,35 @@ rtl8188e_PHY_RF6052SetCckTxPower(
}
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
if (direction == 1) // Increase TX pwoer
if (direction == 1) /* Increase TX pwoer */
{
TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value;
}
else if (direction == 2) // Decrease TX pwoer
else if (direction == 2) /* Decrease TX pwoer */
{
TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value;
}
// rf-A cck tx power
/* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A]&0xff;
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
tmpval = TxAGC[RF_PATH_A]>>8;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
// rf-B cck tx power
/* rf-B cck tx power */
tmpval = TxAGC[RF_PATH_B]>>24;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
// tmpval, rTxAGC_B_CCK1_55_Mcs32));
} /* PHY_RF6052SetCckTxPower */
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
//
/* */
/* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */
/* */
static void getPowerBase88E(
PADAPTER Adapter,
u8* pPowerLevelOFDM,
@ -304,12 +298,11 @@ static void getPowerBase88E(
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
*(OfdmBase+i) = powerBase0;
//DBG_88E(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i));
}
for (i=0; i<pHalData->NumTotalRFPath; i++)
{
//Check HT20 to HT40 diff
/* Check HT20 to HT40 diff */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
powerlevel[i] = pPowerLevelBW20[i];
@ -321,7 +314,6 @@ static void getPowerBase88E(
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
*(MCSBase+i) = powerBase1;
//DBG_88E(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
}
}
@ -342,101 +334,61 @@ static void getTxPowerWriteValByRegulatory88E(
u4Byte writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory;
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
/* */
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
/* */
for (rf=0; rf<2; rf++) {
switch (Regulatory)
{
case 0: // Realtek better performance
// increase power diff defined by Realtek for large power
case 0: /* Realtek better performance */
/* increase power diff defined by Realtek for large power */
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 1: // Realtek regulatory
// increase power diff defined by Realtek for regulatory
case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */
{
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
{
if (Channel < 3) // Chanel 1-2
if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0;
else if (Channel < 6) // Channel 3-5
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if (Channel <9) // Channel 6-8
else if (Channel <9) /* Channel 6-8 */
chnlGroup = 2;
else if (Channel <12) // Channel 9-11
else if (Channel <12) /* Channel 9-11 */
chnlGroup = 3;
else if (Channel <14) // Channel 12-13
else if (Channel <14) /* Channel 12-13 */
chnlGroup = 4;
else if (Channel ==14) // Channel 14
else if (Channel ==14) /* Channel 14 */
chnlGroup = 5;
/*
if (Channel <= 3)
chnlGroup = 0;
else if (Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if (Channel > 9)
chnlGroup = 2;
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=4;
*/
}
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
}
break;
case 2: // Better regulatory
// don't increase any power diff
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 3: // Customer defined power diff.
// increase power diff defined by customer.
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
/*
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
{
RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
}
else
{
RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
}*/
if (index < 2)
pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
//RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
else
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
//RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit));
if (pwr_diff >= customer_pwr_limit)
pwr_diff = 0;
else
@ -451,46 +403,34 @@ static void getTxPowerWriteValByRegulatory88E(
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
}
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
//92d do not need this
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
/* 92d do not need this */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
// 20100628 Joseph: High power mode for BT-Coexist mechanism.
// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
writeVal = writeVal - 0x06060606;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
writeVal = writeVal ;
}
/*
if (pMgntInfo->bDisableTXPowerByRate)
{
// add for OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate
writeVal = 0x2c2c2c2c;
}
*/
*(pOutWriteVal+rf) = writeVal;
}
}
@ -529,9 +469,8 @@ static void writeOFDMPowerReg88E(
RegOffset = RegOffset_B[index];
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
//RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
// 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if (((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
((pHalData->rf_type != RF_2T2R) &&
@ -591,15 +530,12 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
u8 direction;
u8 index = 0;
//DBG_88E("PHY_RF6052SetOFDMTxPower, channel(%d)\n", Channel);
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
//
// 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power.
// This is ued to fix unstable power tracking mode.
//
/* */
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
/* This is ued to fix unstable power tracking mode. */
/* */
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
for (index=0; index<6; index++)
@ -622,18 +558,11 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
}
}
static void
phy_RF6052_Config_HardCode(
PADAPTER Adapter
)
{
// Set Default Bandwidth to 20M
//Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
// TODO: Set Default Channel to channel one for RTL8225
}
static int
@ -657,18 +586,16 @@ phy_RF6052_Config_ParaFile(
pszRadioBFile = sz88eRadioBFile;
#endif
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch (eRFPath)
{
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
@ -681,22 +608,21 @@ phy_RF6052_Config_ParaFile(
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath)
{
switch (eRFPath) {
case RF_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
#ifdef CONFIG_PHY_SETTING_WITH_ODM
@ -704,10 +630,10 @@ phy_RF6052_Config_ParaFile(
rtStatus= _FAIL;
#else
rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
#endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */
#else
rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
#endif//#ifdef CONFIG_EMBEDDED_FWIMG
#endif/* ifdef CONFIG_EMBEDDED_FWIMG */
break;
case RF_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
@ -716,7 +642,7 @@ phy_RF6052_Config_ParaFile(
rtStatus= _FAIL;
#else
rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
#endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM
#endif /* ifdef CONFIG_PHY_SETTING_WITH_ODM */
#else
rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
#endif
@ -740,14 +666,11 @@ phy_RF6052_Config_ParaFile(
break;
}
if (rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
if (rtStatus != _SUCCESS)
goto phy_RF6052_Config_ParaFile_Fail;
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
@ -762,18 +685,18 @@ PHY_RF6052_Config8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
//
// Initialize general global value
//
// TODO: Extend RF_PATH_C and RF_PATH_D in the future
/* */
/* Initialize general global value */
/* */
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
if (pHalData->rf_type == RF_1T1R)
pHalData->NumTotalRFPath = 1;
else
pHalData->NumTotalRFPath = 2;
//
// Config BB and RF
//
/* */
/* Config BB and RF */
/* */
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
return rtStatus;
}

117
hal/rtl8188e_rxdesc.c
View file

@ -26,10 +26,10 @@
static s32 translate2dbm(u8 signal_strength_idx)
{
s32 signal_power; // in dBm.
s32 signal_power; /* in dBm. */
// Translate to dBm (x=0.5y-95).
/* Translate to dBm (x=0.5y-95). */
signal_power = (s32)((signal_strength_idx + 1) >> 1);
signal_power -= 95;
@ -43,10 +43,8 @@ static void process_rssi(_adapter *padapter,union recv_frame *prframe)
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
//DBG_88E("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength);
//if (pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
{
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
@ -59,9 +57,8 @@ static void process_rssi(_adapter *padapter,union recv_frame *prframe)
signal_stat->total_num++;
signal_stat->total_val += pattrib->phy_info.SignalStrength;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
//Adapter->RxStats.RssiCalculateCnt++; //For antenna Test
if (padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX)
{
padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
@ -86,10 +83,10 @@ static void process_rssi(_adapter *padapter,union recv_frame *prframe)
}
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
}
}// Process_UI_RSSI_8192C
}/* Process_UI_RSSI_8192C */
@ -99,7 +96,7 @@ static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
struct rx_pkt_attrib *pattrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
if (prframe == NULL || padapter==NULL){
return;
@ -108,9 +105,7 @@ static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
pattrib = &prframe->u.hdr.attrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
signal_stat = &padapter->recvpriv.signal_qual_data;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
//DBG_88E("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual);
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
if (signal_stat->update_req) {
@ -123,12 +118,12 @@ static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
signal_stat->total_val += pattrib->phy_info.SignalQuality;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
if (pattrib->phy_info.SignalQuality != 0)
{
//
// 1. Record the general EVM to the sliding window.
//
/* */
/* 1. Record the general EVM to the sliding window. */
/* */
if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
{
padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
@ -143,7 +138,7 @@ static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality));
// <1> Showed on UI for user, in percentage.
/* <1> Showed on UI for user, in percentage. */
tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
padapter->recvpriv.signal_qual=(u8)tmpVal;
@ -152,28 +147,23 @@ static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality));
}
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
}
//void rtl8188e_process_phy_info(_adapter *padapter, union recv_frame *prframe)
void rtl8188e_process_phy_info(_adapter *padapter, void *prframe)
{
union recv_frame *precvframe = (union recv_frame *)prframe;
//
// Check RSSI
//
/* */
/* Check RSSI */
/* */
process_rssi(padapter, precvframe);
//
// Check PWDB.
//
//process_PWDB(padapter, precvframe);
/* */
/* Check PWDB. */
/* */
//UpdateRxSignalStatistics8192C(Adapter, pRfd);
//
// Check EVM
//
/* Check EVM */
process_link_qual(padapter, precvframe);
}
@ -196,51 +186,51 @@ void update_recvframe_attrib_88e(
pattrib = &precvframe->u.hdr.attrib;
_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
pattrib->crc_err = (u8)((le32_to_cpu(report.rxdw0) >> 14) & 0x1);;//(u8)prxreport->crc32;
pattrib->crc_err = (u8)((le32_to_cpu(report.rxdw0) >> 14) & 0x1);;/* u8)prxreport->crc32; */
// update rx report to recv_frame attribute
pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);//prxreport->rpt_sel;
/* update rx report to recv_frame attribute */
pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);/* prxreport->rpt_sel; */
if (pattrib->pkt_rpt_type == NORMAL_RX) { //Normal rx packet
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) & 0x00003fff);//(u16)prxreport->pktlen;
pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;//(u8)(prxreport->drvinfosize << 3);
if (pattrib->pkt_rpt_type == NORMAL_RX) { /* Normal rx packet */
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) & 0x00003fff);/* u16)prxreport->pktlen; */
pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;/* u8)(prxreport->drvinfosize << 3); */
pattrib->physt = (u8)((le32_to_cpu(report.rxdw0) >> 26) & 0x1);//(u8)prxreport->physt;
pattrib->physt = (u8)((le32_to_cpu(report.rxdw0) >> 26) & 0x1);/* u8)prxreport->physt; */
pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27))? 0:1;//(u8)(prxreport->swdec ? 0 : 1);
pattrib->encrypt = (u8)((le32_to_cpu(report.rxdw0) >> 20) & 0x7);//(u8)prxreport->security;
pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27))? 0:1;/* u8)(prxreport->swdec ? 0 : 1); */
pattrib->encrypt = (u8)((le32_to_cpu(report.rxdw0) >> 20) & 0x7);/* u8)prxreport->security; */
pattrib->qos = (u8)((le32_to_cpu(report.rxdw0) >> 23) & 0x1);//(u8)prxreport->qos;
pattrib->priority = (u8)((le32_to_cpu(report.rxdw1) >> 8) & 0xf);//(u8)prxreport->tid;
pattrib->qos = (u8)((le32_to_cpu(report.rxdw0) >> 23) & 0x1);/* u8)prxreport->qos; */
pattrib->priority = (u8)((le32_to_cpu(report.rxdw1) >> 8) & 0xf);/* u8)prxreport->tid; */
pattrib->amsdu = (u8)((le32_to_cpu(report.rxdw1) >> 13) & 0x1);//(u8)prxreport->amsdu;
pattrib->amsdu = (u8)((le32_to_cpu(report.rxdw1) >> 13) & 0x1);/* u8)prxreport->amsdu; */
pattrib->seq_num = (u16)(le32_to_cpu(report.rxdw2) & 0x00000fff);//(u16)prxreport->seq;
pattrib->frag_num = (u8)((le32_to_cpu(report.rxdw2) >> 12) & 0xf);//(u8)prxreport->frag;
pattrib->mfrag = (u8)((le32_to_cpu(report.rxdw1) >> 27) & 0x1);//(u8)prxreport->mf;
pattrib->mdata = (u8)((le32_to_cpu(report.rxdw1) >> 26) & 0x1);//(u8)prxreport->md;
pattrib->seq_num = (u16)(le32_to_cpu(report.rxdw2) & 0x00000fff);/* u16)prxreport->seq; */
pattrib->frag_num = (u8)((le32_to_cpu(report.rxdw2) >> 12) & 0xf);/* u8)prxreport->frag; */
pattrib->mfrag = (u8)((le32_to_cpu(report.rxdw1) >> 27) & 0x1);/* u8)prxreport->mf; */
pattrib->mdata = (u8)((le32_to_cpu(report.rxdw1) >> 26) & 0x1);/* u8)prxreport->md; */
pattrib->mcs_rate = (u8)(le32_to_cpu(report.rxdw3) & 0x3f);//(u8)prxreport->rxmcs;
pattrib->rxht = (u8)((le32_to_cpu(report.rxdw3) >> 6) & 0x1);//(u8)prxreport->rxht;
pattrib->mcs_rate = (u8)(le32_to_cpu(report.rxdw3) & 0x3f);/* u8)prxreport->rxmcs; */
pattrib->rxht = (u8)((le32_to_cpu(report.rxdw3) >> 6) & 0x1);/* u8)prxreport->rxht; */
pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);//(u8)prxreport->icverr;
pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);/* u8)prxreport->icverr; */
pattrib->shift_sz = (u8)((le32_to_cpu(report.rxdw0) >> 24) & 0x3);
} else if (pattrib->pkt_rpt_type == TX_REPORT1) { //CCX
} else if (pattrib->pkt_rpt_type == TX_REPORT1) { /* CCX */
pattrib->pkt_len = TX_RPT1_PKT_LEN;
pattrib->drvinfo_sz = 0;
} else if (pattrib->pkt_rpt_type == TX_REPORT2) { // TX RPT
pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);//Rx length[9:0]
} else if (pattrib->pkt_rpt_type == TX_REPORT2) { /* TX RPT */
pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);/* Rx length[9:0] */
pattrib->drvinfo_sz = 0;
//
// Get TX report MAC ID valid.
//
/* */
/* Get TX report MAC ID valid. */
/* */
pattrib->MacIDValidEntry[0] = le32_to_cpu(report.rxdw4);
pattrib->MacIDValidEntry[1] = le32_to_cpu(report.rxdw5);
} else if (pattrib->pkt_rpt_type == HIS_REPORT) { // USB HISR RPT
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);//(u16)prxreport->pktlen;
} else if (pattrib->pkt_rpt_type == HIS_REPORT) { /* USB HISR RPT */
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */
}
}
@ -263,7 +253,6 @@ void update_recvframe_phyinfo_88e(
u8 *sa;
struct sta_priv *pstapriv;
struct sta_info *psta;
//_irqL irqL;
pkt_info.bPacketMatchBSSID =false;
pkt_info.bPacketToSelf = false;
@ -283,7 +272,7 @@ void update_recvframe_phyinfo_88e(
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == true){
sa = padapter->mlmepriv.cur_network.network.MacAddress;
}
//to do Ad-hoc
/* to do Ad-hoc */
}
else{
sa = get_sa(wlanhdr);
@ -293,22 +282,16 @@ void update_recvframe_phyinfo_88e(
pkt_info.StationID = 0xFF;
psta = rtw_get_stainfo(pstapriv, sa);
if (psta)
{
pkt_info.StationID = psta->mac_id;
//DBG_88E("%s ==> StationID(%d)\n",__func__,pkt_info.StationID);
}
pkt_info.Rate = pattrib->mcs_rate;
//rtl8188e_query_rx_phy_status(precvframe, pphy_status);
#ifdef CONFIG_CONCURRENT_MODE
//get Primary adapter's odmpriv
/* get Primary adapter's odmpriv */
if (padapter->adapter_type > PRIMARY_ADAPTER){
pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
}
#endif
//_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info));
//_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
precvframe->u.hdr.psta = NULL;
if (pkt_info.bPacketMatchBSSID &&

45
hal/rtl8188e_sreset.c
View file

@ -54,14 +54,10 @@ static void _restore_security_setting(_adapter *padapter)
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
{
psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
if (psta == NULL) {
//DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n"));
}
else
{
//pairwise key
if (psta) {
/* pairwise key */
rtw_setstakey_cmd(padapter, (unsigned char *)psta, true);
//group key
/* group key */
rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0);
}
}
@ -76,36 +72,34 @@ static void _restore_network_status(_adapter *padapter)
WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
unsigned short caps;
u8 join_type;
#if 1
//=======================================================
// reset related register of Beacon control
/* */
/* reset related register of Beacon control */
//set MSR to nolink
/* set MSR to nolink */
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
/* reject all data frame */
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
/* reset TSF */
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
/* disable update TSF */
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
/* */
rtw_joinbss_reset(padapter);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//pmlmeinfo->assoc_AP_vendor = maxAP;
if (padapter->registrypriv.wifi_spec) {
// for WiFi test, follow WMM test plan spec
/* for WiFi test, follow WMM test plan spec */
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F431C);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E541C);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x0000A525);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A549);
#ifdef CONFIG_80211N_HT
// for WiFi test, mixed mode with intel STA under bg mode throughput issue
/* for WiFi test, mixed mode with intel STA under bg mode throughput issue */
if (padapter->mlmepriv.htpriv.ht_option == 0)
#endif //CONFIG_80211N_HT
#endif /* CONFIG_80211N_HT */
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00004320);
} else {
@ -115,10 +109,6 @@ static void _restore_network_status(_adapter *padapter)
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A444);
}
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, false);
#endif
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
@ -126,7 +116,7 @@ static void _restore_network_status(_adapter *padapter)
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
/* restore Sequence No. */
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
}
@ -194,9 +184,7 @@ void rtl8188e_sreset_xmit_status_check(_adapter *padapter)
rtl8188e_silentreset_for_specific_platform(padapter);
}
#ifdef CONFIG_USB_HCI
//total xmit irp = 4
//DBG_88E("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__func__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
//if (pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
/* total xmit irp = 4 */
current_time = rtw_get_current_time();
if (0==pxmitpriv->free_xmitbuf_cnt)
{
@ -209,14 +197,13 @@ void rtl8188e_sreset_xmit_status_check(_adapter *padapter)
else{
diff_time = jiffies_to_msecs(current_time - psrtpriv->last_tx_complete_time);
if (diff_time > 4000){
//padapter->Wifi_Error_Status = WIFI_TX_HANG;
DBG_88E("%s tx hang\n", __func__);
rtl8188e_silentreset_for_specific_platform(padapter);
}
}
}
}
#endif //CONFIG_USB_HCI
#endif /* CONFIG_USB_HCI */
}
void rtl8188e_sreset_linked_status_check(_adapter *padapter)

19
hal/rtl8188e_xmit.c
View file

@ -61,7 +61,7 @@ void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf)
rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
}
}
#endif //CONFIG_XMIT_ACK
#endif /* CONFIG_XMIT_ACK */
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc)
{
@ -69,24 +69,22 @@ void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc)
u8 bDumpTxDesc = false;
rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
if (bDumpTxPkt ==1){//dump txdesc for data frame
if (bDumpTxPkt ==1){/* dump txdesc for data frame */
DBG_88E("dump tx_desc for data frame\n");
if ((frame_tag&0x0f) == DATA_FRAMETAG){
bDumpTxDesc = true;
}
}
else if (bDumpTxPkt ==2){//dump txdesc for mgnt frame
else if (bDumpTxPkt ==2){/* dump txdesc for mgnt frame */
DBG_88E("dump tx_desc for mgnt frame\n");
if ((frame_tag&0x0f) == MGNT_FRAMETAG){
bDumpTxDesc = true;
}
}
else if (bDumpTxPkt ==3){//dump early info
else if (bDumpTxPkt ==3){/* dump early info */
}
if (bDumpTxDesc){
// ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M
// ptxdesc->txdw6 = 0x6666f800;
DBG_88E("=====================================\n");
DBG_88E("txdw0(0x%08x)\n",ptxdesc->txdw0);
DBG_88E("txdw1(0x%08x)\n",ptxdesc->txdw1);
@ -112,7 +110,7 @@ void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc)
*/
#ifdef CONFIG_TX_EARLY_MODE
//#define DBG_EMINFO
/* define DBG_EMINFO */
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
#define EARLY_MODE_MAX_PKT_NUM 10
@ -206,15 +204,10 @@ InsertEMContent_8188E(
SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
#endif
//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
}
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
{
//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq
int index,j;
u16 offset,pktlen;
PTXDESC ptxdesc;
@ -262,7 +255,7 @@ void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmit
eminfo.EMPktNum = pframe->agg_num-(index+1);
}
for (j=0;j< eminfo.EMPktNum ;j++){
eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;/* 4 bytes CRC */
}
if (pmem){

73
hal/rtl8188eu_led.c
View file

@ -24,27 +24,26 @@
#include <rtl8188e_hal.h>
#include <rtl8188e_led.h>
// LED object.
//================================================================================
/* LED object. */
/* */
//================================================================================
// Prototype of protected function.
//================================================================================
/* */
/* Prototype of protected function. */
/* */
//================================================================================
// LED_819xUsb routines.
//================================================================================
/* */
/* LED_819xUsb routines. */
/* */
//
// Description:
// Turn on LED according to LedPin specified.
//
/* */
/* Description: */
/* Turn on LED according to LedPin specified. */
/* */
void SwLedOn(_adapter *padapter, PLED_871x pLed)
{
u8 LedCfg;
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if ( (padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true))
{
@ -55,11 +54,11 @@ void SwLedOn(_adapter *padapter, PLED_871x pLed)
switch (pLed->LedPin)
{
case LED_PIN_LED0:
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on.
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
break;
case LED_PIN_LED1:
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on.
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); /* SW control led1 on. */
break;
default:
@ -70,10 +69,10 @@ void SwLedOn(_adapter *padapter, PLED_871x pLed)
}
//
// Description:
// Turn off LED according to LedPin specified.
//
/* */
/* Description: */
/* Turn off LED according to LedPin specified. */
/* */
void SwLedOff(_adapter *padapter, PLED_871x pLed)
{
u8 LedCfg;
@ -85,14 +84,14 @@ void SwLedOff(_adapter *padapter, PLED_871x pLed)
}
LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E
LedCfg = rtw_read8(padapter, REG_LEDCFG2);/* 0x4E */
switch (pLed->LedPin)
{
case LED_PIN_LED0:
if (pHalData->bLedOpenDrain == true) // Open-drain arrangement for controlling the LED)
if (pHalData->bLedOpenDrain == true) /* Open-drain arrangement for controlling the LED) */
{
LedCfg &= 0x90; // Set to software control.
LedCfg &= 0x90; /* Set to software control. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG);
LedCfg &= 0xFE;
@ -105,7 +104,7 @@ void SwLedOff(_adapter *padapter, PLED_871x pLed)
break;
case LED_PIN_LED1:
LedCfg &= 0x0f; // Set to software control.
LedCfg &= 0x0f; /* Set to software control. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
break;
@ -117,19 +116,19 @@ exit:
}
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
/* */
/* Interface to manipulate LED objects. */
/* */
//================================================================================
// Default LED behavior.
//================================================================================
/* */
/* Default LED behavior. */
/* */
//
// Description:
// Initialize all LED_871x objects.
//
/* */
/* Description: */
/* Initialize all LED_871x objects. */
/* */
void
rtl8188eu_InitSwLeds(
_adapter *padapter
@ -145,10 +144,10 @@ rtl8188eu_InitSwLeds(
}
//
// Description:
// DeInitialize all LED_819xUsb objects.
//
/* */
/* Description: */
/* DeInitialize all LED_819xUsb objects. */
/* */
void
rtl8188eu_DeInitSwLeds(
_adapter *padapter

17
hal/rtl8188eu_recv.c
View file

@ -65,8 +65,8 @@ int rtl8188eu_init_recv_priv(_adapter *padapter)
struct recv_buf *precvbuf;
#ifdef CONFIG_RECV_THREAD_MODE
_rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed
_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed
_rtw_init_sema(&precvpriv->recv_sema, 0);/* will be removed */
_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);/* will be removed */
#endif
#ifdef PLATFORM_LINUX
@ -92,12 +92,12 @@ int rtl8188eu_init_recv_priv(_adapter *padapter)
}
#endif
//init recv_buf
/* init recv_buf */
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
if (precvpriv->pallocated_recv_buf==NULL){
@ -108,8 +108,6 @@ int rtl8188eu_init_recv_priv(_adapter *padapter)
_rtw_memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
//precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 -
// ((uint) (precvpriv->pallocated_recv_buf) &(4-1));
precvbuf = (struct recv_buf*)precvpriv->precv_buf;
@ -130,7 +128,6 @@ int rtl8188eu_init_recv_priv(_adapter *padapter)
precvbuf->adapter =padapter;
//rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue));
precvbuf++;
@ -154,7 +151,7 @@ int rtl8188eu_init_recv_priv(_adapter *padapter)
for (i=0; i<NR_PREALLOC_RECV_SKB; i++)
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) /* www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
#else
pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
@ -208,11 +205,11 @@ void rtl8188eu_free_recv_priv (_adapter *padapter)
{
usb_free_urb(precvpriv->int_in_urb);
}
#endif//PLATFORM_LINUX
#endif/* PLATFORM_LINUX */
if (precvpriv->int_in_buf)
rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN);
#endif//CONFIG_USB_INTERRUPT_IN_PIPE
#endif/* CONFIG_USB_INTERRUPT_IN_PIPE */
#ifdef PLATFORM_LINUX

349
hal/rtl8188eu_xmit.c
View file

@ -64,22 +64,22 @@ static u8 urb_zero_packet_chk(_adapter *padapter, int sz)
static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
{
u16 *usPtr = (u16*)ptxdesc;
u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times
u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
u32 index;
u16 checksum = 0;
//Clear first
/* Clear first */
ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
for (index = 0; index < count; index++)
checksum = checksum ^ le16_to_cpu(*(__le16 *)(usPtr + index));
ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum);
}
//
// Description: In normal chip, we should send some packet to Hw which will be used by Fw
// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
// Fw can tell Hw to send these packet derectly.
//
/* */
/* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
/* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
/* Fw can tell Hw to send these packet derectly. */
/* */
void rtl8188e_fill_fake_txdesc(
PADAPTER padapter,
u8* pDesc,
@ -90,42 +90,42 @@ void rtl8188e_fill_fake_txdesc(
struct tx_desc *ptxdesc;
// Clear all status
/* Clear all status */
ptxdesc = (struct tx_desc*)pDesc;
_rtw_memset(pDesc, 0, TXDESC_SIZE);
//offset 0
ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg;
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); //32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); /* 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header
ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); /* Buffer size + command header */
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); // Fixed queue of Mgnt queue
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); /* Fixed queue of Mgnt queue */
//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
if (IsPsPoll)
{
ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
}
else
{
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
}
if (true == IsBTQosNull)
{
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
}
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
// USB interface drop packet if the checksum of descriptor isn't correct.
// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
/* USB interface drop packet if the checksum of descriptor isn't correct. */
/* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
rtl8188eu_cal_txdesc_chksum(ptxdesc);
#endif
}
@ -134,7 +134,7 @@ static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxd
{
if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
switch (pattrib->encrypt) {
//SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES
/* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
case _WEP40_:
case _WEP104_:
ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
@ -177,7 +177,7 @@ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
}
if (pattrib->vcs_mode) {
*pdw |= cpu_to_le32(HW_RTS_EN);
// Set RTS BW
/* Set RTS BW */
if (pattrib->ht_en) {
*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(27)):0;
@ -219,7 +219,6 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
//struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -227,42 +226,38 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
#ifdef CONFIG_P2P
struct wifidirect_info* pwdinfo = &padapter->wdinfo;
#endif //CONFIG_P2P
#endif /* CONFIG_P2P */
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
#endif //CONFIG_CONCURRENT_MODE
#endif /* CONFIG_CONCURRENT_MODE */
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
if (padapter->registrypriv.mp_mode == 0)
{
if ((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))//(sz %512) != 0
//if ((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==false))
if ((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))/* sz %512) != 0 */
{
ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
//DBG_88E("==> non-agg-pkt,shift pointer...\n");
pull = 1;
}
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
_rtw_memset(ptxdesc, 0, sizeof(struct tx_desc));
//4 offset 0
/* 4 offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
//DBG_88E("%s==> pkt_len=%d,bagg_pkt=%02x\n",__func__,sz,bagg_pkt);
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);//update TXPKTSIZE
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */
offset = TXDESC_SIZE + OFFSET_SZ;
#ifdef CONFIG_TX_EARLY_MODE
if (bagg_pkt){
offset += EARLY_MODE_INFO_SIZE ;//0x28
offset += EARLY_MODE_INFO_SIZE ;/* 0x28 */
}
#endif
//DBG_88E("%s==>offset(0x%02x)\n",__func__,offset);
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */
if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC);
@ -276,24 +271,21 @@ if (padapter->registrypriv.mp_mode == 0)
}
}
#endif
//DBG_88E("%s, pkt_offset=0x%02x\n",__func__,pxmitframe->pkt_offset);
// pkt_offset, unit:8 bytes padding
/* pkt_offset, unit:8 bytes padding */
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
//driver uses rate
ptxdesc->txdw4 |= cpu_to_le32(USERATE);//rate control always by driver
/* driver uses rate */
ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
//DBG_88E("pxmitframe->frame_tag == DATA_FRAMETAG\n");
//offset 4
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3F);
qsel = (uint)(pattrib->qsel & 0x0000001f);
//DBG_88E("==> macid(%d) qsel:0x%02x\n",pattrib->mac_id,qsel);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000F0000);
@ -301,34 +293,28 @@ if (padapter->registrypriv.mp_mode == 0)
fill_txdesc_sectype(pattrib, ptxdesc);
if (pattrib->ampdu_en==true){
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);//AGG EN
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
//SET_TX_DESC_MAX_AGG_NUM_88E(pDesc, 0x1F);
//SET_TX_DESC_MCSG1_MAX_LEN_88E(pDesc, 0x6);
//SET_TX_DESC_MCSG2_MAX_LEN_88E(pDesc, 0x6);
//SET_TX_DESC_MCSG3_MAX_LEN_88E(pDesc, 0x6);
//SET_TX_DESC_MCS7_SGI_MAX_LEN_88E(pDesc, 0x6);
ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
}
else{
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
}
//offset 8
/* offset 8 */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<< SEQ_SHT)&0x0FFF0000);
//offset 16 , offset 20
/* offset 16 , offset 20 */
if (pattrib->qos_en)
ptxdesc->txdw4 |= cpu_to_le32(QOS);//QoS
ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
//offset 20
/* offset 20 */
#ifdef CONFIG_USB_TX_AGGREGATION
if (pxmitframe->agg_num > 1){
//DBG_88E("%s agg_num:%d\n",__func__,pxmitframe->agg_num );
ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
}
#endif
@ -338,18 +324,18 @@ if (padapter->registrypriv.mp_mode == 0)
(pattrib->ether_type != 0x88b4) &&
(pattrib->dhcp_pkt != 1))
{
//Non EAP & ARP & DHCP type data packet
/* Non EAP & ARP & DHCP type data packet */
fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//DATA/RTS Rate FB LMT
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
#if (RATE_ADAPTIVE_SUPPORT == 1)
if (pattrib->ht_en){
if ( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
}
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
@ -358,39 +344,38 @@ if (padapter->registrypriv.mp_mode == 0)
#if (POWER_TRAINING_ACTIVE==1)
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT);
#endif //(POWER_TRAINING_ACTIVE==1)
#else//if (RATE_ADAPTIVE_SUPPORT == 1)
#endif /* POWER_TRAINING_ACTIVE==1) */
#else/* if (RATE_ADAPTIVE_SUPPORT == 1) */
if (pattrib->ht_en)
ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
data_rate = 0x13; //default rate: MCS7
if (padapter->fix_rate!= 0xFF){//rate control by iwpriv
data_rate = 0x13; /* default rate: MCS7 */
if (padapter->fix_rate!= 0xFF){/* rate control by iwpriv */
data_rate = padapter->fix_rate;
}
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
#endif//if (RATE_ADAPTIVE_SUPPORT == 1)
#endif/* if (RATE_ADAPTIVE_SUPPORT == 1) */
}
else
{
// EAP data packet and ARP packet and DHCP.
// Use the 1M data rate to send the EAP/ARP packet.
// This will maybe make the handshake smooth.
/* EAP data packet and ARP packet and DHCP. */
/* Use the 1M data rate to send the EAP/ARP packet. */
/* This will maybe make the handshake smooth. */
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
//offset 24
/* offset 24 */
if ( pattrib->hw_tcp_csum == 1 ) {
// ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!!
u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8;
ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16);
DBG_88E("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7);
@ -399,9 +384,8 @@ if (padapter->registrypriv.mp_mode == 0)
}
else if ((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG)
{
//DBG_88E("pxmitframe->frame_tag == MGNT_FRAMETAG\n");
//offset 4
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f);
qsel = (uint)(pattrib->qsel&0x0000001f);
@ -409,11 +393,10 @@ if (padapter->registrypriv.mp_mode == 0)
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000f0000);
//fill_txdesc_sectype(pattrib, ptxdesc);
//offset 8
/* offset 8 */
#ifdef CONFIG_XMIT_ACK
//CCX-TXRPT ack for xmit mgmt frames.
/* CCX-TXRPT ack for xmit mgmt frames. */
if (pxmitframe->ack_report) {
#ifdef DBG_CCX
static u16 ccx_sw = 0x123;
@ -423,17 +406,17 @@ if (padapter->registrypriv.mp_mode == 0)
#endif
ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
}
#endif //CONFIG_XMIT_ACK
#endif /* CONFIG_XMIT_ACK */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
//offset 20
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);//retry limit enable
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
if (pattrib->retry_ctrl == true)
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
else
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
#ifdef CONFIG_INTEL_PROXIM
if ((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)){
@ -461,39 +444,36 @@ if (padapter->registrypriv.mp_mode == 0)
{
DBG_88E("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);//CAM_ID(MAC_ID)
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);/* CAM_ID(MAC_ID) */
ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);//raid
ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);/* raid */
//offset 8
/* offset 8 */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
//offset 20
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
// 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
// (1) The sequence number of each non-Qos frame / broadcast / multicast /
// mgnt frame should be controled by Hw because Fw will also send null data
// which we cannot control when Fw LPS enable.
// --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
// (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
// (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
// 2010.06.23. Added by tynli.
/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
/* mgnt frame should be controled by Hw because Fw will also send null data */
/* which we cannot control when Fw LPS enable. */
/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
/* 2010.06.23. Added by tynli. */
if (!pattrib->qos_en)
{
//ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
//ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
}
#ifdef CONFIG_HW_ANTENNA_DIVERSITY //CONFIG_ANTENNA_DIVERSITY
#ifdef CONFIG_HW_ANTENNA_DIVERSITY /* CONFIG_ANTENNA_DIVERSITY */
ODM_SetTxAntByTxInfo_88E(&pHalData->odmpriv, pmem, pattrib->mac_id);
#endif
@ -515,15 +495,12 @@ if (padapter->registrypriv.mp_mode == 0)
*/
s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter)
{
//PHAL_DATA_TYPE phal;
struct xmit_priv *pxmitpriv;
struct xmit_buf *pxmitbuf;
s32 ret;
//phal = GET_HAL_DATA(padapter);
pxmitpriv = &padapter->xmitpriv;
ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
if (_FAIL == ret) {
RT_TRACE(_module_hal_xmit_c_, _drv_emerg_,
@ -570,7 +547,7 @@ s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter)
#ifdef CONFIG_IOL_IOREG_CFG_DBG
#include <rtw_iol.h>
#endif
//for non-agg data frame or management frame
/* for non-agg data frame or management frame */
static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 ret = _SUCCESS;
@ -591,7 +568,7 @@ static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
{
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
#endif //CONFIG_80211N_HT
#endif /* CONFIG_80211N_HT */
mem_addr = pxmitframe->buf_addr;
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
@ -608,7 +585,7 @@ static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
sz = pxmitpriv->frag_len;
sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
}
else //no frag
else /* no frag */
{
sz = pattrib->last_txcmdsz;
}
@ -617,9 +594,8 @@ static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
if (pull)
{
mem_addr += PACKET_OFFSET_SZ; //pull txdesc head
mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
//pxmitbuf ->pbuf = mem_addr;
pxmitframe->buf_addr = mem_addr;
w_sz = sz + TXDESC_SIZE;
@ -644,7 +620,6 @@ static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
rtw_count_tx_stats(padapter, pxmitframe, sz);
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz));
//DBG_88E("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority);
mem_addr += w_sz;
@ -667,7 +642,7 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
u32 len = 0;
// no consider fragement
/* no consider fragement */
len = pattrib->hdrlen + pattrib->iv_len +
SNAP_SIZE + sizeof(u16) +
pattrib->pktlen +
@ -679,14 +654,14 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
return len;
}
#define IDEA_CONDITION 1 // check all packets before enqueue
#define IDEA_CONDITION 1 /* check all packets before enqueue */
s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct xmit_frame *pxmitframe = NULL;
struct xmit_frame *pfirstframe = NULL;
// aggregate variable
/* aggregate variable */
struct hw_xmit *phwxmit;
struct sta_info *psta = NULL;
struct tx_servq *ptxservq = NULL;
@ -694,15 +669,15 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
_irqL irqL;
_list *xmitframe_plist = NULL, *xmitframe_phead = NULL;
u32 pbuf; // next pkt address
u32 pbuf_tail; // last pkt tail
u32 len; // packet length, except TXDESC_SIZE and PKT_OFFSET
u32 pbuf; /* next pkt address */
u32 pbuf_tail; /* last pkt tail */
u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */
u32 bulkSize = pHalData->UsbBulkOutSize;
u8 descCount;
u32 bulkPtr;
// dump frame variable
/* dump frame variable */
u32 ff_hwaddr;
#ifndef IDEA_CONDITION
@ -712,24 +687,21 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n"));
// check xmitbuffer is ok
/* check xmitbuffer is ok */
if (pxmitbuf == NULL) {
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (pxmitbuf == NULL){
//DBG_88E("%s #1, connot alloc xmitbuf!!!!\n",__func__);
return false;
}
}
//DBG_88E("%s =====================================\n",__func__);
//3 1. pick up first frame
/* 3 1. pick up first frame */
do {
rtw_free_xmitframe(pxmitpriv, pxmitframe);
pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
if (pxmitframe == NULL) {
// no more xmit frame, release xmit buffer
//DBG_88E("no more xmit frame ,return\n");
/* no more xmit frame, release xmit buffer */
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
return false;
}
@ -739,30 +711,27 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
pxmitframe->frame_tag, DATA_FRAMETAG));
// rtw_free_xmitframe(pxmitpriv, pxmitframe);
continue;
}
// TID 0~15
/* TID 0~15 */
if ((pxmitframe->attrib.priority < 0) ||
(pxmitframe->attrib.priority > 15)) {
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
("xmitframe_complete: TID(%d) should be 0~15!\n",
pxmitframe->attrib.priority));
// rtw_free_xmitframe(pxmitpriv, pxmitframe);
continue;
}
#endif
//DBG_88E("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf;
pxmitbuf->priv_data = pxmitframe;
pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1.
pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */
#ifdef CONFIG_TX_EARLY_MODE
pxmitframe->pkt_offset = 2; // first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check
pxmitframe->pkt_offset = 2; /* first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check */
#else
pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset
pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */
#endif
#ifdef IDEA_CONDITION
@ -770,34 +739,33 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
#else
res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
if (res == false) {
// rtw_free_xmitframe(pxmitpriv, pxmitframe);
continue;
}
#endif
// always return ndis_packet after rtw_xmitframe_coalesce
/* always return ndis_packet after rtw_xmitframe_coalesce */
rtw_os_xmit_complete(padapter, pxmitframe);
break;
} while (1);
//3 2. aggregate same priority and same DA(AP or STA) frames
/* 3 2. aggregate same priority and same DA(AP or STA) frames */
pfirstframe = pxmitframe;
len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE+(pfirstframe->pkt_offset*PACKET_OFFSET_SZ);
pbuf_tail = len;
pbuf = _RND8(pbuf_tail);
// check pkt amount in one bulk
/* check pkt amount in one bulk */
descCount = 0;
bulkPtr = bulkSize;
if (pbuf < bulkPtr)
descCount++;
else {
descCount = 0;
bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize
bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; /* round to next bulkSize */
}
// dequeue same priority packet from station tx queue
/* dequeue same priority packet from station tx queue */
psta = pfirstframe->attrib.psta;
switch (pfirstframe->attrib.priority) {
case 1:
@ -825,10 +793,6 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
phwxmit = pxmitpriv->hwxmits + 2;
break;
}
//DBG_88E("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n",
//pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset );
_enter_critical_bh(&pxmitpriv->lock, &irqL);
xmitframe_phead = get_list_head(&ptxservq->sta_pending);
@ -839,19 +803,17 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
xmitframe_plist = get_next(xmitframe_plist);
pxmitframe->agg_num = 0; // not first frame of aggregation
pxmitframe->agg_num = 0; /* not first frame of aggregation */
#ifdef CONFIG_TX_EARLY_MODE
pxmitframe->pkt_offset = 1;// not first frame of aggregation,reserve offset for EM Info
pxmitframe->pkt_offset = 1;/* not first frame of aggregation,reserve offset for EM Info */
#else
pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset
pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */
#endif
len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE +(pxmitframe->pkt_offset*PACKET_OFFSET_SZ);
if (_RND8(pbuf + len) > MAX_XMITBUF_SZ)
//if (_RND8(pbuf + len) > (MAX_XMITBUF_SZ/2))//to do : for TX TP finial tune , Georgia 2012-0323
{
//DBG_88E("%s....len> MAX_XMITBUF_SZ\n",__func__);
pxmitframe->agg_num = 1;
pxmitframe->pkt_offset = 1;
break;
@ -861,7 +823,7 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
phwxmit->accnt--;
#ifndef IDEA_CONDITION
// suppose only data frames would be in queue
/* suppose only data frames would be in queue */
if (pxmitframe->frame_tag != DATA_FRAMETAG) {
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
@ -870,7 +832,7 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
continue;
}
// TID 0~15
/* TID 0~15 */
if ((pxmitframe->attrib.priority < 0) ||
(pxmitframe->attrib.priority > 15)) {
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
@ -881,7 +843,6 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
}
#endif
// pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
#ifdef IDEA_CONDITION
@ -894,17 +855,16 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
continue;
}
#endif
//DBG_88E("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
// always return ndis_packet after rtw_xmitframe_coalesce
/* always return ndis_packet after rtw_xmitframe_coalesce */
rtw_os_xmit_complete(padapter, pxmitframe);
// (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz
/* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */
update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz,true);
// don't need xmitframe any more
/* don't need xmitframe any more */
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// handle pointer and stop condition
/* handle pointer and stop condition */
pbuf_tail = pbuf + len;
pbuf = _RND8(pbuf_tail);
@ -925,7 +885,7 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
descCount = 0;
bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize;
}
}//end while ( aggregate same priority and same DA(AP or STA) frames)
}/* end while ( aggregate same priority and same DA(AP or STA) frames) */
if (_rtw_queue_empty(&ptxservq->sta_pending) == true)
@ -940,36 +900,33 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
{
rtw_issue_addbareq_cmd(padapter, pfirstframe);
}
#endif //CONFIG_80211N_HT
#endif /* CONFIG_80211N_HT */
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
//3 3. update first frame txdesc
/* 3 3. update first frame txdesc */
if ((pbuf_tail % bulkSize) == 0) {
// remove pkt_offset
/* remove pkt_offset */
pbuf_tail -= PACKET_OFFSET_SZ;
pfirstframe->buf_addr += PACKET_OFFSET_SZ;
pfirstframe->pkt_offset--;
//DBG_88E("$$$$$ buf size equal to USB block size $$$$$$\n");
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz,true);
#ifdef CONFIG_TX_EARLY_MODE
//prepare EM info for first frame, agg_num value start from 1
/* prepare EM info for first frame, agg_num value start from 1 */
pxmitpriv->agg_pkt[0].offset = _RND8(pfirstframe->attrib.last_txcmdsz +TXDESC_SIZE +(pfirstframe->pkt_offset*PACKET_OFFSET_SZ));
pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;//get from rtw_xmitframe_coalesce
pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;/* get from rtw_xmitframe_coalesce */
UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf );
#endif
//3 4. write xmit buffer to USB FIFO
/* 3 4. write xmit buffer to USB FIFO */
ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
//DBG_88E("%s ===================================== write port,buf_size(%d)\n",__func__,pbuf_tail);
// xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr
rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf);
//3 5. update statisitc
/* 3 5. update statisitc */
pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
@ -1020,12 +977,11 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
if (pxmitframe->attrib.priority<=15)//TID0~15
if (pxmitframe->attrib.priority<=15)/* TID0~15 */
{
res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
}
//DBG_88E("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce
rtw_os_xmit_complete(padapter, pxmitframe);/* always return ndis_packet after rtw_xmitframe_coalesce */
}
@ -1065,7 +1021,6 @@ s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 res = _SUCCESS;
//DBG_88E("==> %s\n",__func__);
res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
if (res == _SUCCESS) {
@ -1098,11 +1053,8 @@ static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe)
_enter_critical_bh(&pxmitpriv->lock, &irqL);
//DBG_88E("==> %s\n",__func__);
if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0)
{
//DBG_88E("enqueue AC(%d)\n",pattrib->priority);
goto enqueue;
}
@ -1140,7 +1092,7 @@ enqueue:
RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n"));
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// Trick, make the statistics correct
/* Trick, make the statistics correct */
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
return true;
@ -1171,7 +1123,6 @@ static void rtl8188eu_hostap_mgnt_xmit_cb(struct urb *urb)
#ifdef PLATFORM_LINUX
struct sk_buff *skb = (struct sk_buff *)urb->context;
//DBG_88E("%s\n", __func__);
dev_kfree_skb_any(skb);
#endif
@ -1194,8 +1145,6 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
//DBG_88E("%s\n", __func__);
skb = pkt;
len = skb->len;
@ -1206,7 +1155,7 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT)
goto _exit;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) /* www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
pxmit_skb = dev_alloc_skb(len + TXDESC_SIZE);
#else
pxmit_skb = netdev_alloc_skb(pnetdev, len + TXDESC_SIZE);
@ -1222,13 +1171,13 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
goto _exit;
}
// ----- fill tx desc -----
/* ----- fill tx desc ----- */
ptxdesc = (struct tx_desc *)pxmitbuf;
_rtw_memset(ptxdesc, 0, sizeof(*ptxdesc));
//offset 0
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff);
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);//default = 32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);/* default = 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
if (bmcst)
@ -1236,44 +1185,42 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
}
//offset 4
ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(0x00);/* MAC_ID */
ptxdesc->txdw1 |= cpu_to_le32((0x12<<QSEL_SHT)&0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode
ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);/* b mode */
//offset 8
/* offset 8 */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000);
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
//offset 20
/* offset 20 */
//HW append seq
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
/* HW append seq */
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
rtl8188eu_cal_txdesc_chksum(ptxdesc);
// ----- end of fill tx desc -----
/* ----- end of fill tx desc ----- */
//
/* */
skb_put(pxmit_skb, len + TXDESC_SIZE);
pxmitbuf = pxmitbuf + TXDESC_SIZE;
_rtw_memcpy(pxmitbuf, skb->data, len);
//DBG_88E("mgnt_xmit, len=%x\n", pxmit_skb->len);
// ----- prepare urb for submit -----
/* ----- prepare urb for submit ----- */
//translate DMA FIFO addr to pipehandle
//pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);
/* translate DMA FIFO addr to pipehandle */
pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f);
usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe,

1079
hal/usb_halinit.c
View file

File diff suppressed because it is too large Load diff

239
hal/usb_ops_linux.c
View file

@ -49,7 +49,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
u8 *tmp_buf;
#else // use stack memory
#else /* use stack memory */
u8 tmp_buf[MAX_USB_IO_CTL_SIZE];
#endif
@ -62,8 +62,6 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
}
#endif
//DBG_88E("%s %s:%d\n",__func__, current->comm, current->pid);
if ((padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)){
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
status = -EPERM;
@ -81,20 +79,20 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
#endif
// Acquire IO memory for vendorreq
/* Acquire IO memory for vendorreq */
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
pIo_buf = pdvobjpriv->usb_vendor_req_buf;
#else
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT);
tmp_buflen = (u32)len + ALIGNMENT_UNIT;
#else // use stack memory
#else /* use stack memory */
tmp_buflen = MAX_USB_IO_CTL_SIZE;
#endif
// Added by Albert 2010/02/09
// For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment.
// Trying to fix it here.
/* Added by Albert 2010/02/09 */
/* For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. */
/* Trying to fix it here. */
pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f );
#endif
@ -110,27 +108,27 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
if (requesttype == 0x01)
{
pipe = usb_rcvctrlpipe(udev, 0);//read_in
pipe = usb_rcvctrlpipe(udev, 0);/* read_in */
reqtype = REALTEK_USB_VENQT_READ;
}
else
{
pipe = usb_sndctrlpipe(udev, 0);//write_out
pipe = usb_sndctrlpipe(udev, 0);/* write_out */
reqtype = REALTEK_USB_VENQT_WRITE;
_rtw_memcpy( pIo_buf, pdata, len);
}
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
if ( status == len) // Success this control transfer.
if ( status == len) /* Success this control transfer. */
{
rtw_reset_continual_urb_error(pdvobjpriv);
if ( requesttype == 0x01 )
{ // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
{ /* For Control read transfer, we have to copy the read data from pIo_buf to pdata. */
_rtw_memcpy( pdata, pIo_buf, len );
}
}
else { // error cases
else { /* error cases */
DBG_88E("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n"
, value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times);
@ -147,11 +145,11 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
#endif
}
}
else // status != len && status >= 0
else /* status != len && status >= 0 */
{
if (status > 0) {
if ( requesttype == 0x01 )
{ // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
{ /* For Control read transfer, we have to copy the read data from pIo_buf to pdata. */
_rtw_memcpy( pdata, pIo_buf, len );
}
}
@ -164,13 +162,13 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
}
// firmware download is checksumed, don't retry
/* firmware download is checksumed, don't retry */
if ( (value >= FW_8188E_START_ADDRESS && value <= FW_8188E_END_ADDRESS) || status == len )
break;
}
// release IO memory used by vendorreq
/* release IO memory used by vendorreq */
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
rtw_mfree(tmp_buf, tmp_buflen);
#endif
@ -196,8 +194,8 @@ static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
_func_enter_;
request = 0x05;
requesttype = 0x01;//read_in
index = 0;//n/a
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 1;
@ -221,8 +219,8 @@ static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
_func_enter_;
request = 0x05;
requesttype = 0x01;//read_in
index = 0;//n/a
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 2;
usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
@ -243,8 +241,8 @@ static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
_func_enter_;
request = 0x05;
requesttype = 0x01;//read_in
index = 0;//n/a
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 4;
@ -269,8 +267,8 @@ static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
_func_enter_;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 1;
@ -298,8 +296,8 @@ static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
_func_enter_;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 2;
@ -326,8 +324,8 @@ static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
_func_enter_;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 4;
@ -353,8 +351,8 @@ static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata
_func_enter_;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = length;
@ -380,7 +378,7 @@ static void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
return ;
}
// HISR
/* HISR */
_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
@ -388,13 +386,12 @@ static void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
if ( pHalData->IntArray[0] & IMR_CPWM_88E )
{
_rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1);
//_rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1);
//88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow.
/* 88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */
pwr_rpt.state |= PS_STATE_S2;
_set_workitem(&padapter->pwrctrlpriv.cpwm_event);
}
#endif//CONFIG_LPS_LCLK
#endif/* CONFIG_LPS_LCLK */
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
@ -419,7 +416,7 @@ static void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
#endif
}
#endif //CONFIG_INTERRUPT_BASED_TXBCN
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
@ -433,13 +430,13 @@ static void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
DBG_88E("===> %s Transmit FIFO Overflow\n",__func__);
if ( pHalData->IntArray[1] & IMR_RXFOVW_88E )
DBG_88E("===> %s Receive FIFO Overflow\n",__func__);
#endif//DBG_CONFIG_ERROR_DETECT_INT
#endif/* DBG_CONFIG_ERROR_DETECT_INT */
// C2H Event
/* C2H Event */
if (pbuf[0]!= 0){
_rtw_memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16);
//rtw_c2h_wk_cmd(padapter); to do..
/* rtw_c2h_wk_cmd(padapter); to do.. */
}
}
@ -459,7 +456,7 @@ static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
return;
}
if (purb->status==0)//SUCCESS
if (purb->status==0)/* SUCCESS */
{
if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN)
{
@ -483,8 +480,8 @@ static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
//padapter->bSurpriseRemoved=true;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=true\n"));
/* fall through here */
case -ENOENT:
padapter->bDriverStopped=true;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=true\n"));
@ -513,7 +510,7 @@ static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr)
_func_enter_;
//translate DMA FIFO addr to pipehandle
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe,
@ -553,27 +550,23 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);
if (IS_MCAST(paddr1) == false)//unicast packets
if (IS_MCAST(paddr1) == false)/* unicast packets */
{
//primary_myid = myid(&primary_padapter->eeprompriv);
secondary_myid = myid(&secondary_padapter->eeprompriv);
if (_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
{
//change to secondary interface
/* change to secondary interface */
precvframe->u.hdr.adapter = secondary_padapter;
}
//ret = recv_entry(precvframe);
}
else // Handle BC/MC Packets
else /* Handle BC/MC Packets */
{
u8 clone = true;
if (true == clone)
{
//clone/copy to if2
/* clone/copy to if2 */
u8 shift_sz = 0;
u32 alloc_sz, skb_len;
_pkt *pkt_copy = NULL;
@ -585,16 +578,16 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
precvframe_if2->u.hdr.adapter = secondary_padapter;
_rtw_init_listhead(&precvframe_if2->u.hdr.list);
precvframe_if2->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
precvframe_if2->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe_if2->u.hdr.len=0;
_rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
pattrib = &precvframe_if2->u.hdr.attrib;
// Modified by Albert 20101213
// For 8 bytes IP header alignment.
if (pattrib->qos) // Qos data, wireless lan header length is 26
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
{
shift_sz = 6;
}
@ -605,10 +598,9 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
skb_len = pattrib->pkt_len;
// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
//alloc_sz = 1664; //1664 is 128 alignment.
if (skb_len <= 1650)
alloc_sz = 1664;
else
@ -616,12 +608,12 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
}
else {
alloc_sz = skb_len;
// 6 is for IP header 8 bytes alignment in QoS packet case.
// 8 is for skb->data 4 bytes alignment.
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) /* www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
pkt_copy = dev_alloc_skb(alloc_sz);
#else
pkt_copy = netdev_alloc_skb(secondary_padapter->pnetdev, alloc_sz);
@ -632,8 +624,8 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
precvframe_if2->u.hdr.pkt = pkt_copy;
precvframe_if2->u.hdr.rx_head = pkt_copy->data;
precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz;
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */
skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */
_rtw_memcpy(pkt_copy->data, pbuf, skb_len);
precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data;
@ -704,19 +696,13 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
}
_rtw_init_listhead(&precvframe->u.hdr.list);
precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->u.hdr.len=0;
//rtl8192c_query_rx_desc_status(precvframe, prxstat);
update_recvframe_attrib_88e(precvframe, prxstat);
pattrib = &precvframe->u.hdr.attrib;
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
//if (pattrib->pkt_len>2000){
// printk("%s: RX Warning!pkt_len= %d, data rate=0x%02x\n", __func__,pattrib->pkt_len,pattrib->mcs_rate);
//}
#endif
if ((pattrib->crc_err) || (pattrib->icv_err))
{
if (pattrib->pkt_len>2000){
@ -745,9 +731,9 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
goto _exit_recvbuf2recvframe;
}
// Modified by Albert 20101213
// For 8 bytes IP header alignment.
if (pattrib->qos) // Qos data, wireless lan header length is 26
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
{
shift_sz = 6;
}
@ -758,10 +744,9 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
skb_len = pattrib->pkt_len;
// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
//alloc_sz = 1664; //1664 is 128 alignment.
if (skb_len <= 1650)
alloc_sz = 1664;
else
@ -769,12 +754,12 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
}
else {
alloc_sz = skb_len;
// 6 is for IP header 8 bytes alignment in QoS packet case.
// 8 is for skb->data 4 bytes alignment.
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) /* www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
pkt_copy = dev_alloc_skb(alloc_sz);
#else
pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
@ -785,17 +770,14 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
precvframe->u.hdr.pkt = pkt_copy;
precvframe->u.hdr.rx_head = pkt_copy->data;
precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */
skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */
_rtw_memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
}
else
{
DBG_88E("recvbuf2recvframe:can not allocate memory for skb copy\n");
//precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC);
//precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf;
//precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612);
precvframe->u.hdr.pkt = NULL;
rtw_free_recvframe(precvframe, pfree_recv_queue);
@ -804,7 +786,6 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
}
recvframe_put(precvframe, skb_len);
//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
#ifdef CONFIG_USB_RX_AGGREGATION
switch (pHalData->UsbRxAggMode)
@ -822,7 +803,7 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
}
#endif
if (pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
{
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_buddy_adapter_up(padapter))
@ -846,17 +827,15 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
}
}
else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */
//enqueue recvframe to txrtp queue
/* enqueue recvframe to txrtp queue */
if (pattrib->pkt_rpt_type == TX_REPORT1){
//DBG_88E("rx CCX\n");
//CCX-TXRPT ack for xmit mgmt frames.
/* CCX-TXRPT ack for xmit mgmt frames. */
handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
}
else if (pattrib->pkt_rpt_type == TX_REPORT2){
//DBG_88E("rx TX RPT\n");
ODM_RA_TxRPT2Handle_8188E(
&pHalData->odmpriv,
precvframe->u.hdr.rx_data,
@ -868,7 +847,6 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
}
else if (pattrib->pkt_rpt_type == HIS_REPORT)
{
//DBG_88E("%s , rx USB HISR\n",__func__);
#ifdef CONFIG_SUPPORT_USB_INT
interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data);
#endif
@ -934,7 +912,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
goto exit;
}
if (purb->status==0)//SUCCESS
if (purb->status==0)/* SUCCESS */
{
if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
{
@ -948,7 +926,6 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
precvbuf->transfer_len = purb->actual_length;
//rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf);
rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue);
tasklet_schedule(&precvpriv->recv_tasklet);
@ -969,8 +946,8 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
//padapter->bSurpriseRemoved=true;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=true\n"));
/* fall through here */
case -ENOENT:
padapter->bDriverStopped=true;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=true\n"));
@ -1030,14 +1007,14 @@ _func_enter_;
purb = precvbuf->purb;
//translate DMA FIFO addr to pipehandle
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_bulk_urb(purb, pusbd, pipe,
precvbuf->pbuf,
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
precvbuf);/* context is precvbuf */
purb->transfer_dma = precvbuf->dma_transfer_addr;
purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
@ -1063,7 +1040,7 @@ _func_exit_;
return ret;
}
#else // CONFIG_USE_USB_BUFFER_ALLOC_RX
#else /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
{
u8 *pbuf;
@ -1103,10 +1080,9 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
}
_rtw_init_listhead(&precvframe->u.hdr.list);
precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->u.hdr.len=0;
//rtl8192c_query_rx_desc_status(precvframe, prxstat);
update_recvframe_attrib_88e(precvframe, prxstat);
pattrib = &precvframe->u.hdr.attrib;
@ -1134,9 +1110,9 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
goto _exit_recvbuf2recvframe;
}
// Modified by Albert 20101213
// For 8 bytes IP header alignment.
if (pattrib->qos) // Qos data, wireless lan header length is 26
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
{
shift_sz = 6;
}
@ -1147,10 +1123,9 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
skb_len = pattrib->pkt_len;
// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
//alloc_sz = 1664; //1664 is 128 alignment.
if (skb_len <= 1650)
alloc_sz = 1664;
else
@ -1158,12 +1133,12 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
}
else {
alloc_sz = skb_len;
// 6 is for IP header 8 bytes alignment in QoS packet case.
// 8 is for skb->data 4 bytes alignment.
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) /* www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
pkt_copy = dev_alloc_skb(alloc_sz);
#else
pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
@ -1174,8 +1149,8 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
precvframe->u.hdr.pkt = pkt_copy;
precvframe->u.hdr.rx_head = pkt_copy->data;
precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */
skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */
_rtw_memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
}
@ -1205,7 +1180,6 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
}
recvframe_put(precvframe, skb_len);
//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
#ifdef CONFIG_USB_RX_AGGREGATION
switch (pHalData->UsbRxAggMode)
@ -1223,7 +1197,7 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
}
#endif
if (pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
{
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_buddy_adapter_up(padapter))
@ -1246,16 +1220,14 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
}
}
}
else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */
//enqueue recvframe to txrtp queue
/* enqueue recvframe to txrtp queue */
if (pattrib->pkt_rpt_type == TX_REPORT1){
//DBG_88E("rx CCX\n");
//CCX-TXRPT ack for xmit mgmt frames.
/* CCX-TXRPT ack for xmit mgmt frames. */
handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
}
else if (pattrib->pkt_rpt_type == TX_REPORT2){
//DBG_88E("rx TX RPT\n");
ODM_RA_TxRPT2Handle_8188E(
&pHalData->odmpriv,
precvframe->u.hdr.rx_data,
@ -1267,7 +1239,6 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
}
else if (pattrib->pkt_rpt_type == HIS_REPORT)
{
//DBG_88E("%s , rx USB HISR\n",__func__);
#ifdef CONFIG_SUPPORT_USB_INT
interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data);
#endif
@ -1336,19 +1307,8 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
//_enter_critical(&precvpriv->lock, &irqL);
//precvbuf->irp_pending=false;
//precvpriv->rx_pending_cnt --;
//_exit_critical(&precvpriv->lock, &irqL);
precvpriv->rx_pending_cnt --;
//if (precvpriv->rx_pending_cnt== 0)
//{
// RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n"));
// _rtw_up_sema(&precvpriv->allrxreturnevt);
//}
if (padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
{
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved));
@ -1366,7 +1326,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
goto exit;
}
if (purb->status==0)//SUCCESS
if (purb->status==0)/* SUCCESS */
{
if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
{
@ -1406,7 +1366,6 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
//padapter->bSurpriseRemoved=true;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=true\n"));
case -ENOENT:
padapter->bDriverStopped=true;
@ -1477,11 +1436,10 @@ _func_enter_;
{
rtl8188eu_init_recvbuf(adapter, precvbuf);
//re-assign for linux based on skb
/* re-assign for linux based on skb */
if ((precvbuf->reuse == false) || (precvbuf->pskb == NULL))
{
//precvbuf->pskb = alloc_skb(MAX_RECVBUF_SZ, GFP_ATOMIC);//don't use this after v2.6.25
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) /* www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
precvbuf->pskb = dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
#else
precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
@ -1503,7 +1461,7 @@ _func_enter_;
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
}
else//reuse skb
else/* reuse skb */
{
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
@ -1514,23 +1472,18 @@ _func_enter_;
precvbuf->reuse = false;
}
//_enter_critical(&precvpriv->lock, &irqL);
//precvpriv->rx_pending_cnt++;
//precvbuf->irp_pending = true;
//_exit_critical(&precvpriv->lock, &irqL);
precvpriv->rx_pending_cnt++;
purb = precvbuf->purb;
//translate DMA FIFO addr to pipehandle
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_bulk_urb(purb, pusbd, pipe,
precvbuf->pbuf,
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
precvbuf);/* context is precvbuf */
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != (-EPERM)))
@ -1550,7 +1503,7 @@ _func_exit_;
return ret;
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
void rtl8188eu_xmit_tasklet(void *priv)
{