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https://github.com/lwfinger/rtl8188eu.git
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48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. */
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/* ************************************************************
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* File Name: hal8188ereg.h
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*
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* Description:
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*
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* This file is for RTL8188E register definition.
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*
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*
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* ************************************************************ */
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#ifndef __HAL_8188E_REG_H__
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#define __HAL_8188E_REG_H__
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/*
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* Register Definition
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* */
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#define TRX_ANTDIV_PATH 0x860
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#define RX_ANTDIV_PATH 0xb2c
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#define ODM_R_A_AGC_CORE1_8188E 0xc50
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#define REG_GPIO_EXT_CTRL 0x0060
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#define REG_MCUFWDL_8188E 0x0080
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#define REG_FW_DBG_STATUS_8188E 0x0088
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#define REG_FW_DBG_CTRL_8188E 0x008F
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#define REG_CR_8188E 0x0100
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/*
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* Bitmap Definition
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* */
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#define BIT_FA_RESET_8188E BIT(0)
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#define REG_ADAPTIVE_DATA_RATE_0 0x2B0
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#define REG_DBI_WDATA_8188 0x0348 /* DBI Write data */
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#define REG_DBI_RDATA_8188 0x034C /* DBI Read data */
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#define REG_DBI_ADDR_8188 0x0350 /* DBI Address */
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#define REG_DBI_FLAG_8188 0x0352 /* DBI Read/Write Flag */
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#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
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#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
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#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
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/* [0-63] */
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#define REG_MACID_NO_LINK 0x484 /* No Link register (bit[x] enabled means dropping packets for MACID in HW queue) */
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#endif
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