mirror of
https://github.com/lwfinger/rtl8188eu.git
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294 lines
7.7 KiB
C
294 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. */
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#ifndef __ODM_DBG_H__
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#define __ODM_DBG_H__
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/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
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/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
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#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
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/* -----------------------------------------------------------------------------
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* Define the debug levels
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*
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* 1. DBG_TRACE and DBG_LOUD are used for normal cases.
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* So that, they can help SW engineer to develope or trace states changed
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* and also help HW enginner to trace every operation to and from HW,
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* e.g IO, Tx, Rx.
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*
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* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
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* which help us to debug SW or HW.
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*
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* -----------------------------------------------------------------------------
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*
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* Never used in a call to ODM_RT_TRACE()!
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* */
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#define ODM_DBG_OFF 1
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/*
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* Fatal bug.
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* For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
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* resource allocation failed, unexpected HW behavior, HW BUG and so on.
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* */
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#define ODM_DBG_SERIOUS 2
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/*
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* Abnormal, rare, or unexpeted cases.
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* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
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* */
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#define ODM_DBG_WARNING 3
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/*
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* Normal case with useful information about current SW or HW state.
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* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
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* SW protocol state change, dynamic mechanism state change and so on.
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* */
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#define ODM_DBG_LOUD 4
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/*
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* Normal case with detail execution flow or information.
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* */
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#define ODM_DBG_TRACE 5
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/*FW DBG MSG*/
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#define RATE_DECISION BIT(0)
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#define INIT_RA_TABLE BIT(1)
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#define RATE_UP BIT(2)
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#define RATE_DOWN BIT(3)
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#define TRY_DONE BIT(4)
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#define RA_H2C BIT(5)
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#define F_RATE_AP_RPT BIT(7)
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/* -----------------------------------------------------------------------------
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* Define the tracing components
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*
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* -----------------------------------------------------------------------------
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*BB FW Functions*/
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#define PHYDM_FW_COMP_RA BIT(0)
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#define PHYDM_FW_COMP_MU BIT(1)
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#define PHYDM_FW_COMP_PATH_DIV BIT(2)
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#define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
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/*BB Driver Functions*/
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#define ODM_COMP_DIG BIT(0)
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#define ODM_COMP_RA_MASK BIT(1)
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#define ODM_COMP_DYNAMIC_TXPWR BIT(2)
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#define ODM_COMP_FA_CNT BIT(3)
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#define ODM_COMP_RSSI_MONITOR BIT(4)
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#define ODM_COMP_SNIFFER BIT(5)
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#define ODM_COMP_ANT_DIV BIT(6)
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#define ODM_COMP_DFS BIT(7)
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#define ODM_COMP_NOISY_DETECT BIT(8)
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#define ODM_COMP_RATE_ADAPTIVE BIT(9)
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#define ODM_COMP_PATH_DIV BIT(10)
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#define ODM_COMP_CCX BIT(11)
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#define ODM_COMP_DYNAMIC_PRICCA BIT(12)
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/*BIT13 TBD*/
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#define ODM_COMP_MP BIT(14)
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#define ODM_COMP_CFO_TRACKING BIT(15)
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#define ODM_COMP_ACS BIT(16)
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#define PHYDM_COMP_ADAPTIVITY BIT(17)
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#define PHYDM_COMP_RA_DBG BIT(18)
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#define PHYDM_COMP_TXBF BIT(19)
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/* MAC Functions */
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#define ODM_COMP_EDCA_TURBO BIT(20)
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#define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
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#define ODM_FW_DEBUG_TRACE BIT(22)
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/* RF Functions */
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/*BIT23 TBD*/
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#define ODM_COMP_TX_PWR_TRACK BIT(24)
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/*BIT25 TBD*/
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#define ODM_COMP_CALIBRATION BIT(26)
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/* Common Functions */
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/*BIT27 TBD*/
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#define ODM_PHY_CONFIG BIT(28)
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#define ODM_COMP_INIT BIT(29)
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#define ODM_COMP_COMMON BIT(30)
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#define ODM_COMP_API BIT(31)
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/*------------------------Export Marco Definition---------------------------*/
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#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
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#define dbg_print printk
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#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __func__, ## args);
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#define RT_DISP(dbgtype, dbgflag, printstr)
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#ifndef ASSERT
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#define ASSERT(expr)
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#endif
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#if DBG
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#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \
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do { \
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if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \
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\
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if (p_dm_odm->support_ic_type == ODM_RTL8188E) \
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dbg_print("[PhyDM-8188E] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8192E) \
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dbg_print("[PhyDM-8192E] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8812) \
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dbg_print("[PhyDM-8812A] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8821) \
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dbg_print("[PhyDM-8821A] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8814A) \
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dbg_print("[PhyDM-8814A] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8703B) \
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dbg_print("[PhyDM-8703B] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8822B) \
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dbg_print("[PhyDM-8822B] "); \
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else if (p_dm_odm->support_ic_type == ODM_RTL8188F) \
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dbg_print("[PhyDM-8188F] "); \
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RT_PRINTK fmt; \
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} \
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} while (0)
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#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) do {\
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if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \
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\
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RT_PRINTK fmt; \
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} \
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} while (0)
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#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) do {\
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if (!(expr)) { \
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dbg_print("Assertion failed! %s at ......\n", #expr); \
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dbg_print(" ......%s,%s, line=%d\n", __FILE__, __func__, __LINE__); \
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RT_PRINTK fmt; \
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ASSERT(false); \
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} \
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} while (0)
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#define ODM_dbg_enter() { dbg_print(" == > %s\n", __func__); }
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#define ODM_dbg_exit() { dbg_print("< == %s\n", __func__); }
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#define ODM_dbg_trace(str) { dbg_print("%s:%s\n", __func__, str); }
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#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) do {\
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if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \
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\
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int __i; \
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u8 *__ptr = (u8 *)ptr; \
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dbg_print("[ODM] "); \
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dbg_print(title_str); \
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dbg_print(" "); \
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for (__i = 0; __i < 6; __i++) \
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dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
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dbg_print("\n"); \
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} \
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} while (0)
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#else
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#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt)
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#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt)
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#define ODM_RT_ASSERT(p_dm_odm, expr, fmt)
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#define ODM_dbg_enter()
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#define ODM_dbg_exit()
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#define ODM_dbg_trace(str)
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#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr)
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#endif
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void
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phydm_init_debug_setting(struct PHY_DM_STRUCT *p_dm_odm);
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void phydm_basic_dbg_message(void *p_dm_void);
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#define PHYDM_DBGPRINT 0
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#define MAX_ARGC 20
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#define MAX_ARGV 16
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#define DCMD_DECIMAL "%d"
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#define DCMD_CHAR "%c"
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#define DCMD_HEX "%x"
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#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
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#define PHYDM_VAST_INFO_SNPRINTF(msg)\
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do {\
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snprintf msg;\
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dbg_print(output);\
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} while (0)
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#if (PHYDM_DBGPRINT == 1)
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#define PHYDM_SNPRINTF(msg)\
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do {\
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snprintf msg;\
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dbg_print(output);\
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} while (0)
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#else
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#define PHYDM_SNPRINTF(msg)\
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do {\
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if (out_len > used)\
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used += snprintf msg;\
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} while (0)
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#endif
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void phydm_basic_profile(
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void *p_dm_void,
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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s32
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phydm_cmd(
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struct PHY_DM_STRUCT *p_dm_odm,
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char *input,
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u32 in_len,
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u8 flag,
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char *output,
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u32 out_len
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);
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void
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phydm_cmd_parser(
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struct PHY_DM_STRUCT *p_dm_odm,
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char input[][16],
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u32 input_num,
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u8 flag,
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char *output,
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u32 out_len
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);
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bool
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phydm_api_trx_mode(
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struct PHY_DM_STRUCT *p_dm_odm,
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enum odm_rf_path_e tx_path,
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enum odm_rf_path_e rx_path,
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bool is_tx2_path
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);
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void
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phydm_fw_trace_en_h2c(
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void *p_dm_void,
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bool enable,
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u32 fw_debug_component,
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u32 monitor_mode,
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u32 macid
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);
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void
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phydm_fw_trace_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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void
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phydm_fw_trace_handler_code(
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void *p_dm_void,
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u8 *buffer,
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u8 cmd_len
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);
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void
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phydm_fw_trace_handler_8051(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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#endif /* __ODM_DBG_H__ */
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