mirror of
https://github.com/lwfinger/rtl8188eu.git
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308 lines
6.7 KiB
C
308 lines
6.7 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __PHYDMDIG_H__
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#define __PHYDMDIG_H__
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#define DIG_VERSION "1.3" /* 2016.08.16 YuChen. Modify IGI lower bound to 0x1e for 8197F asked by RF Arthur*/
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/* Pause DIG & CCKPD */
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#define DM_DIG_MAX_PAUSE_TYPE 0x7
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enum dig_goupcheck_level {
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DIG_GOUPCHECK_LEVEL_0,
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DIG_GOUPCHECK_LEVEL_1,
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DIG_GOUPCHECK_LEVEL_2
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};
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struct _dynamic_initial_gain_threshold_ {
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bool is_stop_dig; /* for debug */
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bool is_ignore_dig;
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bool is_psd_in_progress;
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u8 dig_enable_flag;
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u8 dig_ext_port_stage;
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int rssi_low_thresh;
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int rssi_high_thresh;
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u32 fa_low_thresh;
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u32 fa_high_thresh;
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u8 cur_sta_connect_state;
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u8 pre_sta_connect_state;
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u8 cur_multi_sta_connect_state;
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u8 pre_ig_value;
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u8 cur_ig_value;
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u8 backup_ig_value; /* MP DIG */
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u8 bt30_cur_igi;
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u8 igi_backup;
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s8 backoff_val;
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s8 backoff_val_range_max;
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s8 backoff_val_range_min;
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u8 rx_gain_range_max;
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u8 rx_gain_range_min;
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u8 rssi_val_min;
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u8 pre_cck_cca_thres;
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u8 cur_cck_cca_thres;
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u8 pre_cck_pd_state;
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u8 cur_cck_pd_state;
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u8 cck_pd_backup;
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u8 pause_cckpd_level;
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u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
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u8 large_fa_hit;
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u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/
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u8 forbidden_igi;
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u32 recover_cnt;
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u8 dig_dynamic_min_0;
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u8 dig_dynamic_min_1;
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bool is_media_connect_0;
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bool is_media_connect_1;
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u32 ant_div_rssi_max;
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u32 RSSI_max;
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u8 *is_p2p_in_process;
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u8 pause_dig_level;
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u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
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u32 cck_fa_ma;
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enum dig_goupcheck_level dig_go_up_check_level;
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};
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struct _FALSE_ALARM_STATISTICS {
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_crc8_fail;
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u32 cnt_mcs_fail;
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u32 cnt_ofdm_fail;
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u32 cnt_ofdm_fail_pre; /* For RTL8881A */
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u32 cnt_cck_fail;
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u32 cnt_all;
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u32 cnt_all_pre;
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u32 cnt_fast_fsync;
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u32 cnt_sb_search_fail;
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cca_all;
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u32 cnt_bw_usc; /* Gary */
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u32 cnt_bw_lsc; /* Gary */
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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bool cck_block_enable;
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bool ofdm_block_enable;
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u32 dbg_port0;
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bool edcca_flag;
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};
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enum dm_dig_op_e {
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DIG_TYPE_THRESH_HIGH = 0,
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DIG_TYPE_THRESH_LOW = 1,
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DIG_TYPE_BACKOFF = 2,
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DIG_TYPE_RX_GAIN_MIN = 3,
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DIG_TYPE_RX_GAIN_MAX = 4,
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DIG_TYPE_ENABLE = 5,
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DIG_TYPE_DISABLE = 6,
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DIG_OP_TYPE_MAX
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};
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/*
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enum dm_cck_pdth_e
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{
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CCK_PD_STAGE_LowRssi = 0,
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CCK_PD_STAGE_HighRssi = 1,
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CCK_PD_STAGE_MAX = 3,
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};
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enum dm_dig_ext_port_alg_e
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{
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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};
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enum dm_dig_connect_e
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{
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DIG_STA_DISCONNECT = 0,
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DIG_STA_CONNECT = 1,
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DIG_STA_BEFORE_CONNECT = 2,
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dig_multi_sta_disconnect = 3,
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dig_multi_sta_connect = 4,
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DIG_CONNECT_MAX
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};
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#define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;}
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#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
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DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect)
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#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
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DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect)
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*/
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enum phydm_pause_type {
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PHYDM_PAUSE = BIT(0),
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PHYDM_RESUME = BIT(1)
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};
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enum phydm_pause_level {
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/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
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PHYDM_PAUSE_LEVEL_0 = 0,
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PHYDM_PAUSE_LEVEL_1 = 1,
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PHYDM_PAUSE_LEVEL_2 = 2,
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PHYDM_PAUSE_LEVEL_3 = 3,
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PHYDM_PAUSE_LEVEL_4 = 4,
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PHYDM_PAUSE_LEVEL_5 = 5,
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PHYDM_PAUSE_LEVEL_6 = 6,
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PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
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};
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#define DM_DIG_THRESH_HIGH 40
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#define DM_DIG_THRESH_LOW 35
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#define DM_FALSEALARM_THRESH_LOW 400
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#define DM_FALSEALARM_THRESH_HIGH 1000
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#define DM_DIG_MAX_NIC 0x3e
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#define DM_DIG_MIN_NIC 0x20
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#define DM_DIG_MAX_OF_MIN_NIC 0x3e
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#define DM_DIG_MAX_AP 0x3e
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#define DM_DIG_MIN_AP 0x20
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#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */
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#define DM_DIG_MIN_AP_DFS 0x20
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#define DM_DIG_MAX_NIC_HP 0x46
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#define DM_DIG_MIN_NIC_HP 0x2e
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#define DM_DIG_MAX_AP_HP 0x42
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#define DM_DIG_MIN_AP_HP 0x30
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/* vivi 92c&92d has different definition, 20110504
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* this is for 92c */
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#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
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#define DM_DIG_FA_TH0 0x80/* 0x20 */
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#else
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#define DM_DIG_FA_TH0 0x200/* 0x20 */
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#endif
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#define DM_DIG_FA_TH1 0x300
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#define DM_DIG_FA_TH2 0x400
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/* this is for 92d */
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#define DM_DIG_FA_TH0_92D 0x100
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#define DM_DIG_FA_TH1_92D 0x400
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#define DM_DIG_FA_TH2_92D 0x600
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#define DM_DIG_BACKOFF_MAX 12
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#define DM_DIG_BACKOFF_MIN -4
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#define DM_DIG_BACKOFF_DEFAULT 10
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#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */
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#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
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#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
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#define RSSI_OFFSET_DIG 0x05
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#define LARGE_FA_TIMEOUT 60
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void
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odm_change_dynamic_init_gain_thresh(
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void *p_dm_void,
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u32 dm_type,
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u32 dm_value
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);
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void
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odm_write_dig(
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void *p_dm_void,
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u8 current_igi
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);
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void
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odm_pause_dig(
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void *p_dm_void,
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enum phydm_pause_type pause_type,
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enum phydm_pause_level pause_level,
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u8 igi_value
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);
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void
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odm_dig_init(
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void *p_dm_void
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);
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void
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odm_DIG(
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void *p_dm_void
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);
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void
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odm_dig_by_rssi_lps(
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void *p_dm_void
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);
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void
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odm_false_alarm_counter_statistics(
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void *p_dm_void
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);
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void
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odm_pause_cck_packet_detection(
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void *p_dm_void,
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enum phydm_pause_type pause_type,
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enum phydm_pause_level pause_level,
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u8 cck_pd_threshold
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);
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void
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odm_cck_packet_detection_thresh(
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void *p_dm_void
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);
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void
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odm_write_cck_cca_thres(
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void *p_dm_void,
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u8 cur_cck_cca_thres
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);
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bool
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phydm_dig_go_up_check(
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void *p_dm_void
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);
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#endif
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