mirror of
https://github.com/lwfinger/rtl8188eu.git
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192 lines
6.4 KiB
C
192 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. */
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/* ************************************************************
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* include files
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* ************************************************************ */
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#if PHYDM_SUPPORT_EDCA
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void
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odm_edca_turbo_init(
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void *p_dm_void)
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{
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struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
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struct _ADAPTER *adapter = p_dm_odm->adapter;
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p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
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p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
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adapter->recvpriv.is_any_non_be_pkts = false;
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VO_PARAM)));
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VI_PARAM)));
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BK_PARAM)));
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} /* ODM_InitEdcaTurbo */
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void
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odm_edca_turbo_check(
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void *p_dm_void
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)
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{
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/* */
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/* For AP/ADSL use struct rtl8192cd_priv* */
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/* For CE/NIC use struct _ADAPTER* */
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/* */
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/* */
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/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
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/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
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/* HW dynamic mechanism. */
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/* */
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struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check========================>\n"));
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if (!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO))
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return;
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switch (p_dm_odm->support_platform) {
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case ODM_WIN:
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break;
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case ODM_CE:
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odm_edca_turbo_check_ce(p_dm_odm);
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break;
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}
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_edca_turbo_check\n"));
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} /* odm_CheckEdcaTurbo */
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void
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odm_edca_turbo_check_ce(
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void *p_dm_void
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)
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{
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struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
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struct _ADAPTER *adapter = p_dm_odm->adapter;
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u32 EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
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u32 EDCA_BE_DL = 0x00a42b;/* Parameter suggested by Scott */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
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u32 ic_type = p_dm_odm->support_ic_type;
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u32 iot_peer = 0;
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u8 wireless_mode = 0xFF; /* invalid value */
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u32 traffic_index;
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u32 edca_param;
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u64 cur_tx_bytes = 0;
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u64 cur_rx_bytes = 0;
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u8 bbtchange = true;
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u8 is_bias_on_rx = false;
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
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struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
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struct recv_priv *precvpriv = &(adapter->recvpriv);
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struct registry_priv *pregpriv = &adapter->registrypriv;
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struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
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struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
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if (p_dm_odm->is_linked != true) {
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precvpriv->is_any_non_be_pkts = false;
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return;
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}
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if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
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precvpriv->is_any_non_be_pkts = false;
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return;
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}
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if (p_dm_odm->p_wireless_mode != NULL)
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wireless_mode = *(p_dm_odm->p_wireless_mode);
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iot_peer = pmlmeinfo->assoc_AP_vendor;
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if (iot_peer >= HT_IOT_PEER_MAX) {
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precvpriv->is_any_non_be_pkts = false;
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return;
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}
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if (p_dm_odm->support_ic_type & ODM_RTL8188E) {
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if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
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is_bias_on_rx = true;
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}
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/* Check if the status needs to be changed. */
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if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
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cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
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cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
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/* traffic, TX or RX */
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if (is_bias_on_rx) {
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if (cur_tx_bytes > (cur_rx_bytes << 2)) {
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/* Uplink TP is present. */
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traffic_index = UP_LINK;
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} else {
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/* Balance TP is present. */
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traffic_index = DOWN_LINK;
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}
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} else {
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if (cur_rx_bytes > (cur_tx_bytes << 2)) {
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/* Downlink TP is present. */
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traffic_index = DOWN_LINK;
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} else {
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/* Balance TP is present. */
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traffic_index = UP_LINK;
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}
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}
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/* if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index) || (!p_dm_odm->dm_edca_table.is_current_turbo_edca)) */
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{
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if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
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EDCA_BE_UL = 0x6ea42b;
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EDCA_BE_DL = 0x6ea42b;
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}
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/* 92D txop can't be set to 0x3e for cisco1250 */
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if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
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EDCA_BE_DL = edca_setting_DL[iot_peer];
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EDCA_BE_UL = edca_setting_UL[iot_peer];
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}
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/* merge from 92s_92c_merge temp brunch v2445 20120215 */
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else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
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EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
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else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
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EDCA_BE_DL = 0xa630;
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else if (iot_peer == HT_IOT_PEER_MARVELL) {
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EDCA_BE_DL = edca_setting_DL[iot_peer];
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EDCA_BE_UL = edca_setting_UL[iot_peer];
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} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
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/* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
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EDCA_BE_DL = edca_setting_DL[iot_peer];
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}
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if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8821) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
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EDCA_BE_UL = 0x5ea42b;
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EDCA_BE_DL = 0x5ea42b;
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x", EDCA_BE_UL, EDCA_BE_DL));
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}
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if (traffic_index == DOWN_LINK)
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edca_param = EDCA_BE_DL;
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else
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edca_param = EDCA_BE_UL;
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rtw_write32(adapter, REG_EDCA_BE_PARAM, edca_param);
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p_dm_odm->dm_edca_table.prv_traffic_idx = traffic_index;
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}
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p_dm_odm->dm_edca_table.is_current_turbo_edca = true;
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} else {
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/* */
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/* Turn Off EDCA turbo here. */
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/* Restore original EDCA according to the declaration of AP. */
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/* */
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if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
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rtw_write32(adapter, REG_EDCA_BE_PARAM, p_hal_data->ac_param_be);
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p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
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}
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}
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}
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#endif /*PHYDM_SUPPORT_EDCA*/
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