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https://github.com/lwfinger/rtl8188eu.git
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119 lines
3.4 KiB
C
119 lines
3.4 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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//============================================================
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// File Name: odm_reg.h
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//
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// Description:
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//
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// This file is for general register definition.
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//
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//
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//============================================================
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#ifndef __HAL_ODM_REG_H__
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#define __HAL_ODM_REG_H__
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//
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// Register Definition
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//
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//MAC REG
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#define ODM_BB_RESET 0x002
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#define ODM_DUMMY 0x4fe
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#define ODM_EDCA_VO_PARAM 0x500
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#define ODM_EDCA_VI_PARAM 0x504
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#define ODM_EDCA_BE_PARAM 0x508
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#define ODM_EDCA_BK_PARAM 0x50C
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#define ODM_TXPAUSE 0x522
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//BB REG
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#define ODM_FPGA_PHY0_PAGE8 0x800
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#define ODM_PSD_SETTING 0x808
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#define ODM_AFE_SETTING 0x818
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#define ODM_TXAGC_B_6_18 0x830
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#define ODM_TXAGC_B_24_54 0x834
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#define ODM_TXAGC_B_MCS32_5 0x838
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#define ODM_TXAGC_B_MCS0_MCS3 0x83c
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#define ODM_TXAGC_B_MCS4_MCS7 0x848
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#define ODM_TXAGC_B_MCS8_MCS11 0x84c
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#define ODM_ANALOG_REGISTER 0x85c
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#define ODM_RF_INTERFACE_OUTPUT 0x860
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#define ODM_TXAGC_B_MCS12_MCS15 0x868
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#define ODM_TXAGC_B_11_A_2_11 0x86c
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#define ODM_AD_DA_LSB_MASK 0x874
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#define ODM_ENABLE_3_WIRE 0x88c
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#define ODM_PSD_REPORT 0x8b4
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#define ODM_R_ANT_SELECT 0x90c
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#define ODM_CCK_ANT_SELECT 0xa07
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#define ODM_CCK_PD_THRESH 0xa0a
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#define ODM_CCK_RF_REG1 0xa11
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#define ODM_CCK_MATCH_FILTER 0xa20
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#define ODM_CCK_RAKE_MAC 0xa2e
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#define ODM_CCK_CNT_RESET 0xa2d
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#define ODM_CCK_TX_DIVERSITY 0xa2f
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#define ODM_CCK_FA_CNT_MSB 0xa5b
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#define ODM_CCK_FA_CNT_LSB 0xa5c
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#define ODM_CCK_NEW_FUNCTION 0xa75
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#define ODM_OFDM_PHY0_PAGE_C 0xc00
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#define ODM_OFDM_RX_ANT 0xc04
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#define ODM_R_A_RXIQI 0xc14
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#define ODM_R_A_AGC_CORE1 0xc50
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#define ODM_R_A_AGC_CORE2 0xc54
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#define ODM_R_B_AGC_CORE1 0xc58
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#define ODM_R_AGC_PAR 0xc70
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#define ODM_R_HTSTF_AGC_PAR 0xc7c
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#define ODM_TX_PWR_TRAINING_A 0xc90
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#define ODM_TX_PWR_TRAINING_B 0xc98
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#define ODM_OFDM_FA_CNT1 0xcf0
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#define ODM_OFDM_PHY0_PAGE_D 0xd00
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#define ODM_OFDM_FA_CNT2 0xda0
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#define ODM_OFDM_FA_CNT3 0xda4
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#define ODM_OFDM_FA_CNT4 0xda8
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#define ODM_TXAGC_A_6_18 0xe00
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#define ODM_TXAGC_A_24_54 0xe04
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#define ODM_TXAGC_A_1_MCS32 0xe08
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#define ODM_TXAGC_A_MCS0_MCS3 0xe10
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#define ODM_TXAGC_A_MCS4_MCS7 0xe14
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#define ODM_TXAGC_A_MCS8_MCS11 0xe18
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#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
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//RF REG
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#define ODM_GAIN_SETTING 0x00
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#define ODM_CHANNEL 0x18
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//Ant Detect Reg
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#define ODM_DPDT 0x300
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//PSD Init
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#define ODM_PSDREG 0x808
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//92D Path Div
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#define PATHDIV_REG 0xB30
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#define PATHDIV_TRI 0xBA0
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//
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// Bitmap Definition
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//
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#define BIT_FA_RESET BIT0
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#endif
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