mirror of
https://github.com/lwfinger/rtl8188eu.git
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440 lines
13 KiB
C
440 lines
13 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef _RTW_IO_H_
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#define _RTW_IO_H_
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#include <osdep_service.h>
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#include <osdep_intf.h>
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#include <asm/byteorder.h>
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
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#include <asm/semaphore.h>
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#else
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#include <linux/semaphore.h>
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#endif
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <asm/atomic.h>
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#include <linux/usb.h>
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#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
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#include <linux/usb_ch9.h>
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#else
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#include <linux/usb/ch9.h>
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#endif
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
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#define rtw_usb_buffer_alloc(dev, size, dma) usb_alloc_coherent((dev), (size), (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), (dma))
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#define rtw_usb_buffer_free(dev, size, addr, dma) usb_free_coherent((dev), (size), (addr), (dma))
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#else
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#define rtw_usb_buffer_alloc(dev, size, dma) usb_buffer_alloc((dev), (size), (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), (dma))
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#define rtw_usb_buffer_free(dev, size, addr, dma) usb_buffer_free((dev), (size), (addr), (dma))
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#endif
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#define NUM_IOREQ 8
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#define MAX_PROT_SZ (64-16)
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#define _IOREADY 0
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#define _IO_WAIT_COMPLETE 1
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#define _IO_WAIT_RSP 2
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// IO COMMAND TYPE
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#define _IOSZ_MASK_ (0x7F)
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#define _IO_WRITE_ BIT(7)
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#define _IO_FIXED_ BIT(8)
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#define _IO_BURST_ BIT(9)
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#define _IO_BYTE_ BIT(10)
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#define _IO_HW_ BIT(11)
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#define _IO_WORD_ BIT(12)
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#define _IO_SYNC_ BIT(13)
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#define _IO_CMDMASK_ (0x1F80)
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/*
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For prompt mode accessing, caller shall free io_req
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Otherwise, io_handler will free io_req
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*/
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// IO STATUS TYPE
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#define _IO_ERR_ BIT(2)
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#define _IO_SUCCESS_ BIT(1)
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#define _IO_DONE_ BIT(0)
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#define IO_RD32 (_IO_SYNC_ | _IO_WORD_)
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#define IO_RD16 (_IO_SYNC_ | _IO_HW_)
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#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_)
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#define IO_RD32_ASYNC (_IO_WORD_)
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#define IO_RD16_ASYNC (_IO_HW_)
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#define IO_RD8_ASYNC (_IO_BYTE_)
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#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
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#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
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#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
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#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_)
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#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_)
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#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_)
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/*
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Only Sync. burst accessing is provided.
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*/
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#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
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#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
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//below is for the intf_option bit defition...
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#define _INTF_ASYNC_ BIT(0) //support async io
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struct intf_priv;
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struct intf_hdl;
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struct io_queue;
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struct _io_ops {
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u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
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u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
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u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
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int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
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int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
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int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
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int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
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int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
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int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
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int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
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void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
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u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
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u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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u32 (*_write_scsi)(struct intf_hdl *pintfhdl,u32 cnt, u8 *pmem);
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void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
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void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
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};
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struct io_req {
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struct list_head list;
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u32 addr;
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volatile u32 val;
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u32 command;
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u32 status;
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u8 *pbuf;
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struct semaphore sema;
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
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u8 *cnxt;
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};
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struct intf_hdl {
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_adapter *padapter;
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struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv);
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struct _io_ops io_ops;
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};
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struct reg_protocol_rd {
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#ifdef __LITTLE_ENDIAN
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//DW1
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u32 NumOfTrans:4;
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u32 Reserved1:4;
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u32 Reserved2:24;
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//DW2
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u32 ByteCount:7;
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u32 WriteEnable:1; //0:read, 1:write
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u32 FixOrContinuous:1; //0:continuous, 1: Fix
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u32 BurstMode:1;
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u32 Byte1Access:1;
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u32 Byte2Access:1;
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u32 Byte4Access:1;
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u32 Reserved3:3;
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u32 Reserved4:16;
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//DW3
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u32 BusAddress;
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//DW4
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//u32 Value;
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#else
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//DW1
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u32 Reserved1 :4;
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u32 NumOfTrans :4;
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u32 Reserved2 :24;
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//DW2
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u32 WriteEnable : 1;
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u32 ByteCount :7;
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u32 Reserved3 : 3;
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u32 Byte4Access : 1;
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u32 Byte2Access : 1;
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u32 Byte1Access : 1;
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u32 BurstMode :1 ;
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u32 FixOrContinuous : 1;
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u32 Reserved4 : 16;
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//DW3
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u32 BusAddress;
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//DW4
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//u32 Value;
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#endif
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};
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struct reg_protocol_wt {
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#ifdef __LITTLE_ENDIAN
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//DW1
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u32 NumOfTrans:4;
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u32 Reserved1:4;
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u32 Reserved2:24;
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//DW2
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u32 ByteCount:7;
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u32 WriteEnable:1; //0:read, 1:write
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u32 FixOrContinuous:1; //0:continuous, 1: Fix
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u32 BurstMode:1;
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u32 Byte1Access:1;
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u32 Byte2Access:1;
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u32 Byte4Access:1;
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u32 Reserved3:3;
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u32 Reserved4:16;
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//DW3
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u32 BusAddress;
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//DW4
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u32 Value;
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#else
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//DW1
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u32 Reserved1 :4;
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u32 NumOfTrans :4;
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u32 Reserved2 :24;
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//DW2
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u32 WriteEnable : 1;
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u32 ByteCount :7;
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u32 Reserved3 : 3;
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u32 Byte4Access : 1;
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u32 Byte2Access : 1;
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u32 Byte1Access : 1;
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u32 BurstMode :1 ;
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u32 FixOrContinuous : 1;
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u32 Reserved4 : 16;
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//DW3
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u32 BusAddress;
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//DW4
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u32 Value;
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#endif
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};
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/*
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Below is the data structure used by _io_handler
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*/
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struct io_queue {
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spinlock_t lock;
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struct list_head free_ioreqs;
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struct list_head pending; //The io_req list that will be served in the single protocol read/write.
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struct list_head processing;
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u8 *free_ioreqs_buf; // 4-byte aligned
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u8 *pallocated_free_ioreqs_buf;
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struct intf_hdl intf;
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};
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struct io_priv{
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_adapter *padapter;
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struct intf_hdl intf;
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};
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extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
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extern void sync_ioreq_enqueue(struct io_req *preq,struct io_queue *ioqueue);
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extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
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extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
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extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
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extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
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extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
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extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern u8 _rtw_read8(_adapter *adapter, u32 addr);
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extern u16 _rtw_read16(_adapter *adapter, u32 addr);
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extern u32 _rtw_read32(_adapter *adapter, u32 addr);
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extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void _rtw_read_port_cancel(_adapter *adapter);
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extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
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extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
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extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
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extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
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extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
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extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
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extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
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extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
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extern void _rtw_write_port_cancel(_adapter *adapter);
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#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
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#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
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#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
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#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
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#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
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#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
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#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
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#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
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#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
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#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
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#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
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#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
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#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
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#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
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#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
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#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
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#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
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extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
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//ioreq
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extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
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extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
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extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
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extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
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extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
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extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
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extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void async_write8(_adapter *adapter, u32 addr, u8 val,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern void async_write16(_adapter *adapter, u32 addr, u16 val,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern void async_write32(_adapter *adapter, u32 addr, u32 val,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops));
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extern uint alloc_io_queue(_adapter *adapter);
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extern void free_io_queue(_adapter *adapter);
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extern void async_bus_io(struct io_queue *pio_q);
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extern void bus_sync_io(struct io_queue *pio_q);
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extern u32 _ioreq2rwmem(struct io_queue *pio_q);
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extern void dev_power_down(_adapter * Adapter, u8 bpwrup);
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/*
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#define RTL_R8(reg) rtw_read8(padapter, reg)
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#define RTL_R16(reg) rtw_read16(padapter, reg)
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#define RTL_R32(reg) rtw_read32(padapter, reg)
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#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8)
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#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16)
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#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32)
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*/
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/*
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#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
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#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
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#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
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#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32)
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#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg)
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*/
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#define PlatformEFIOWrite1Byte(_a,_b,_c) \
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rtw_write8(_a,_b,_c)
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#define PlatformEFIOWrite2Byte(_a,_b,_c) \
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rtw_write16(_a,_b,_c)
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#define PlatformEFIOWrite4Byte(_a,_b,_c) \
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rtw_write32(_a,_b,_c)
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#define PlatformEFIORead1Byte(_a,_b) \
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rtw_read8(_a,_b)
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#define PlatformEFIORead2Byte(_a,_b) \
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rtw_read16(_a,_b)
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#define PlatformEFIORead4Byte(_a,_b) \
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rtw_read32(_a,_b)
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#endif //_RTL8711_IO_H_
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