mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-15 01:19:36 +00:00
77d786b6e8
This version takes advantage of all the cleanups to the code. It has been modified to build on older kernels. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2007 - 2011 Realtek Corporation. */
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#ifndef __INC_HAL8188EPHYCFG_H__
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#define __INC_HAL8188EPHYCFG_H__
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#define MAX_AGGR_NUM 0x07
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enum rf_radio_path {
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RF_PATH_A = 0, /* Radio Path A */
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RF_PATH_B = 1, /* Radio Path B */
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};
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#define MAX_PG_GROUP 13
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#define RF_PATH_MAX 3
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#define MAX_TX_COUNT 4 /* path numbers */
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#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
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#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
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*ch9~11, ch12~13, CH 14
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* total three groups */
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struct bb_reg_def {
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u32 rfintfs; /* set software control: */
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/* 0x870~0x877[8 bytes] */
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u32 rfintfi; /* readback data: */
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/* 0x8e0~0x8e7[8 bytes] */
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u32 rfintfo; /* output data: */
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/* 0x860~0x86f [16 bytes] */
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u32 rfintfe; /* output enable: */
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/* 0x860~0x86f [16 bytes] */
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u32 rf3wireOffset; /* LSSI data: */
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/* 0x840~0x84f [16 bytes] */
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u32 rfLSSI_Select; /* BB Band Select: */
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/* 0x878~0x87f [8 bytes] */
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u32 rfTxGainStage; /* Tx gain stage: */
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/* 0x80c~0x80f [4 bytes] */
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u32 rfHSSIPara1; /* wire parameter control1 : */
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/* 0x820~0x823,0x828~0x82b,
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* 0x830~0x833, 0x838~0x83b [16 bytes] */
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u32 rfHSSIPara2; /* wire parameter control2 : */
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/* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
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* 0x83c~0x83f [16 bytes] */
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u32 rfSwitchControl; /* Tx Rx antenna control : */
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/* 0x858~0x85f [16 bytes] */
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u32 rfAGCControl1; /* AGC parameter control1 : */
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/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
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* 0xc68~0xc6b [16 bytes] */
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u32 rfAGCControl2; /* AGC parameter control2 : */
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/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
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* 0xc6c~0xc6f [16 bytes] */
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u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
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/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
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* 0xc2c~0xc2f [16 bytes] */
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u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
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* Rx DC notch filter : */
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/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
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* 0xc28~0xc2b [16 bytes] */
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u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
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/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
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* 0xc98~0xc9b [16 bytes] */
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u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
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/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
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* 0xc9c~0xc9f [16 bytes] */
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u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
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/* 0x8a0~0x8af [16 bytes] */
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u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
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* Path A and B */
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};
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/* BB and RF register read/write */
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u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
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void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
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u32 mask, u32 data);
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u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, u32 regaddr, u32 mask);
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void rtl8188e_PHY_SetRFReg(struct adapter *adapter, u32 regaddr, u32 mask, u32 data);
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/* Initialization related function */
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8188E(struct adapter *adapter);
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int PHY_BBConfig8188E(struct adapter *adapter);
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int PHY_RFConfig8188E(struct adapter *adapter);
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/* BB TX Power R/W */
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void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
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/* Switch bandwidth for 8192S */
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void PHY_SetBWMode8188E(struct adapter *adapter,
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enum ht_channel_width chnlwidth, unsigned char offset);
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/* channel switch related funciton */
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void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
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void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
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u32 mask, u32 data);
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#endif
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