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https://github.com/lwfinger/rtl8188eu.git
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77d786b6e8
This version takes advantage of all the cleanups to the code. It has been modified to build on older kernels. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2007 - 2011 Realtek Corporation. */
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#ifndef __HALPWRSEQCMD_H__
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#define __HALPWRSEQCMD_H__
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#include "drv_types.h"
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/*---------------------------------------------*/
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/* 3 The value of cmd: 4 bits */
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/*---------------------------------------------*/
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#define PWR_CMD_WRITE 0x01
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/* offset: the read register offset */
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/* msk: the mask of the write bits */
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/* value: write value */
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/* note: driver shall implement this cmd by read & msk after write */
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#define PWR_CMD_POLLING 0x02
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/* offset: the read register offset */
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/* msk: the mask of the polled value */
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/* value: the value to be polled, masked by the msd field. */
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/* note: driver shall implement this cmd by */
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/* do{ */
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/* if ( (Read(offset) & msk) == (value & msk) ) */
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/* break; */
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/* } while (not timeout); */
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#define PWR_CMD_DELAY 0x03
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/* offset: the value to delay */
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/* msk: N/A */
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/* value: the unit of delay, 0: us, 1: ms */
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#define PWR_CMD_END 0x04
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/* offset: N/A */
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/* msk: N/A */
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/* value: N/A */
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enum pwrseq_cmd_delat_unit {
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PWRSEQ_DELAY_US,
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PWRSEQ_DELAY_MS,
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};
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struct wl_pwr_cfg {
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u16 offset;
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u8 cmd:4;
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u8 msk;
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u8 value;
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};
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#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
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#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
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#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
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#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
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/* Prototype of protected function. */
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u8 HalPwrSeqCmdParsing(struct adapter *padapter, struct wl_pwr_cfg PwrCfgCmd[]);
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#endif
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