mirror of
https://github.com/lwfinger/rtl8188eu.git
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77d786b6e8
This version takes advantage of all the cleanups to the code. It has been modified to build on older kernels. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
199 lines
5.8 KiB
C
199 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2007 - 2011 Realtek Corporation. */
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#ifndef __RTL8188E_HAL_H__
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#define __RTL8188E_HAL_H__
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/* include HAL Related header after HAL Related compiling flags */
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#include "rtl8188e_spec.h"
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#include "Hal8188EPhyReg.h"
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#include "Hal8188EPhyCfg.h"
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#include "rtl8188e_rf.h"
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#include "rtl8188e_dm.h"
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#include "rtl8188e_recv.h"
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#include "rtl8188e_xmit.h"
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#include "rtl8188e_cmd.h"
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#include "rtw_efuse.h"
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#include "odm_types.h"
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#include "odm.h"
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#include "odm_HWConfig.h"
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#include "odm_RegDefine11N.h"
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#include "HalPhyRf_8188e.h"
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#include "Hal8188ERateAdaptive.h"
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#include "HalHWImg8188E_MAC.h"
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#include "HalHWImg8188E_RF.h"
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#include "HalHWImg8188E_BB.h"
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#include "odm_RegConfig8188E.h"
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#include "odm_RTL8188E.h"
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/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
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#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
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#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
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#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
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#define DRVINFO_SZ 4 /* unit is 8bytes */
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#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
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#define DRIVER_EARLY_INT_TIME 0x05
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#define BCN_DMA_ATIME_INT_TIME 0x02
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#define MAX_RX_DMA_BUFFER_SIZE_88E \
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0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
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* WOLPattern(16*24)) */
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#define TX_SELE_HQ BIT(0) /* High Queue */
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#define TX_SELE_LQ BIT(1) /* Low Queue */
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#define TX_SELE_NQ BIT(2) /* Normal Queue */
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/* Note: We will divide number of page equally for each queue other
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* than public queue! */
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/* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */
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/* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */
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/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
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* null-data */
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#define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */
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#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
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/* Note: For Normal Chip Setting ,modify later */
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#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \
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TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */
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#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \
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(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
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#include "HalVerDef.h"
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#include "hal_com.h"
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/* Channel Plan */
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enum ChannelPlan {
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CHPL_FCC = 0,
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CHPL_IC = 1,
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CHPL_ETSI = 2,
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CHPL_SPA = 3,
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CHPL_FRANCE = 4,
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CHPL_MKK = 5,
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CHPL_MKK1 = 6,
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CHPL_ISRAEL = 7,
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CHPL_TELEC = 8,
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CHPL_GLOBAL = 9,
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CHPL_WORLD = 10,
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};
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struct txpowerinfo24g {
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u8 IndexCCK_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
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u8 IndexBW40_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
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/* If only one tx, only BW20 and OFDM are used. */
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s8 CCK_Diff[RF_PATH_MAX][MAX_TX_COUNT];
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s8 OFDM_Diff[RF_PATH_MAX][MAX_TX_COUNT];
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s8 BW20_Diff[RF_PATH_MAX][MAX_TX_COUNT];
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s8 BW40_Diff[RF_PATH_MAX][MAX_TX_COUNT];
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};
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#define EFUSE_REAL_CONTENT_LEN 512
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#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
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#define EFUSE_REAL_CONTENT_LEN_88E 256
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#define EFUSE_MAP_LEN_88E 512
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#define EFUSE_MAX_SECTION_88E 64
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/* To prevent out of boundary programming case, leave 1byte and program
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* full section */
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/* 9bytes + 1byt + 5bytes and pre 1byte. */
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/* For worst case: */
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/* | 2byte|----8bytes----|1byte|--7bytes--| 92D */
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/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
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#define EFUSE_OOB_PROTECT_BYTES_88E 18
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#define EFUSE_PROTECT_BYTES_BANK 16
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#define USB_RXAGG_PAGE_COUNT 48
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#define USB_RXAGG_PAGE_TIMEOUT 0x4
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struct hal_data_8188e {
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struct HAL_VERSION VersionID;
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/* current WIFI_PHY values */
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enum ht_channel_width CurrentChannelBW;
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u8 CurrentChannel;
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u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
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u8 EEPROMRegulatory;
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u8 EEPROMThermalMeter;
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u8 Index24G_CCK_Base[CHANNEL_MAX_NUMBER];
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u8 Index24G_BW40_Base[CHANNEL_MAX_NUMBER];
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/* If only one tx, only BW20 and OFDM are used. */
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s8 OFDM_24G_Diff[MAX_TX_COUNT];
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s8 BW20_24G_Diff[MAX_TX_COUNT];
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/* HT 20<->40 Pwr diff */
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u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* For HT<->legacy pwr diff */
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u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* For power group */
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u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* Read/write are allow for following hardware information variables */
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u8 pwrGroupCnt;
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u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
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u8 CrystalCap;
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u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
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struct bb_reg_def PHYRegDef;
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u32 RfRegChnlVal;
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/* for host message to fw */
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u8 LastHMEBoxNum;
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u8 fw_ractrl;
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u8 RegFwHwTxQCtrl;
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u8 RegReg542;
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u8 RegCR_1;
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struct dm_priv dmpriv;
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struct odm_dm_struct odmpriv;
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u8 CurAntenna;
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u8 AntDivCfg;
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u8 TRxAntDivType;
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u8 bDumpRxPkt;/* for debug */
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u8 bDumpTxPkt;/* for debug */
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u8 OutEpQueueSel;
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u8 OutEpNumber;
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struct P2P_PS_Offload_t p2p_ps_offload;
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/* Auto FSM to Turn On, include clock, isolation, power control
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* for MAC only */
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u8 bMacPwrCtrlOn;
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};
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s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
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/* EFuse */
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void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
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void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
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bool AutoLoadFail);
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void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent,
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bool AutoLoadFail);
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void Hal_ReadThermalMeter_88E(struct adapter * dapter, u8 *PROMContent,
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bool AutoloadFail);
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void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
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bool AutoLoadFail);
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void rtl8188e_read_chip_version(struct adapter *padapter);
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s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
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void rtw_cancel_all_timer(struct adapter *padapter);
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#endif /* __RTL8188E_HAL_H__ */
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