mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-25 22:13:41 +00:00
77d786b6e8
This version takes advantage of all the cleanups to the code. It has been modified to build on older kernels. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
264 lines
12 KiB
C
264 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2007 - 2011 Realtek Corporation. */
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#include "../include/drv_types.h"
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static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
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{
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struct adapter *adapter = dm_odm->Adapter;
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u32 value32;
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/* MAC Setting */
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value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
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/* Pin Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
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/* OFDM Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
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/* CCK Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
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ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
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}
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static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
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{
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struct adapter *adapter = dm_odm->Adapter;
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u32 value32;
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/* MAC Setting */
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value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
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/* Pin Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
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/* OFDM Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
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/* CCK Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
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/* Tx Settings */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
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ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
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/* antenna mapping table */
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if (!dm_odm->bIsMPChip) { /* testchip */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
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} else { /* MPchip */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
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}
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}
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static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
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{
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struct adapter *adapter = dm_odm->Adapter;
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u32 value32;
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/* MAC Setting */
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value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x4c, bMaskDWord);
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rtl8188e_PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
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value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord);
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rtl8188e_PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
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/* Match MAC ADDR */
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rtl8188e_PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
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rtl8188e_PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
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rtl8188e_PHY_SetBBReg(adapter, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
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rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
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rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
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rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
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rtl8188e_PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
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if (!dm_odm->bIsMPChip) { /* testchip */
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rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
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rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
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} else { /* MPchip */
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rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
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rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
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}
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/* Default Ant Setting when no fast training */
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rtl8188e_PHY_SetBBReg(adapter, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
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rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
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rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
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/* Enter Training state */
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rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
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rtl8188e_PHY_SetBBReg(adapter, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
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}
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void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
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{
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if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
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odm_RX_HWAntDivInit(dm_odm);
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else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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odm_TRX_HWAntDivInit(dm_odm);
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else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
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odm_FastAntTrainingInit(dm_odm);
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}
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void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct adapter *adapter = dm_odm->Adapter;
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u32 DefaultAnt, OptionalAnt;
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if (dm_fat_tbl->RxIdleAnt != Ant) {
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if (Ant == MAIN_ANT) {
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DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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} else {
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DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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}
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT(6) | BIT(7), DefaultAnt); /* Resp Tx */
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} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
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}
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}
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dm_fat_tbl->RxIdleAnt = Ant;
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if (Ant != MAIN_ANT)
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pr_info("RxIdleAnt=AUX_ANT\n");
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}
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static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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u8 TargetAnt;
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if (Ant == MAIN_ANT)
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TargetAnt = MAIN_ANT_CG_TRX;
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else
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TargetAnt = AUX_ANT_CG_TRX;
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dm_fat_tbl->antsel_a[MacId] = TargetAnt & BIT(0);
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dm_fat_tbl->antsel_b[MacId] = (TargetAnt & BIT(1)) >> 1;
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dm_fat_tbl->antsel_c[MacId] = (TargetAnt & BIT(2)) >> 2;
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}
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void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
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SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]);
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SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]);
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SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]);
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}
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}
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void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
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if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
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dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
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dm_fat_tbl->MainAnt_Cnt[MacId]++;
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} else {
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dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
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dm_fat_tbl->AuxAnt_Cnt[MacId]++;
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}
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} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
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if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
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dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
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dm_fat_tbl->MainAnt_Cnt[MacId]++;
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} else {
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dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
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dm_fat_tbl->AuxAnt_Cnt[MacId]++;
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}
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}
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}
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static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
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{
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u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI;
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u32 Main_RSSI, Aux_RSSI;
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u8 RxIdleAnt = 0, TargetAnt = 7;
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
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struct sta_info *pEntry;
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for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
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pEntry = dm_odm->pODM_StaInfo[i];
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if (IS_STA_VALID(pEntry)) {
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/* 2 Caculate RSSI per Antenna */
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Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i] / dm_fat_tbl->MainAnt_Cnt[i]) : 0;
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Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i] / dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
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TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT;
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/* 2 Select MaxRSSI for DIG */
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LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI;
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if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
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AntDivMaxRSSI = LocalMaxRSSI;
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if (LocalMaxRSSI > MaxRSSI)
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MaxRSSI = LocalMaxRSSI;
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/* 2 Select RX Idle Antenna */
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if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
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Main_RSSI = Aux_RSSI;
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else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
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Aux_RSSI = Main_RSSI;
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LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI;
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if (LocalMinRSSI < MinRSSI) {
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MinRSSI = LocalMinRSSI;
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RxIdleAnt = TargetAnt;
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}
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/* 2 Select TRX Antenna */
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i);
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}
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dm_fat_tbl->MainAnt_Sum[i] = 0;
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dm_fat_tbl->AuxAnt_Sum[i] = 0;
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dm_fat_tbl->MainAnt_Cnt[i] = 0;
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dm_fat_tbl->AuxAnt_Cnt[i] = 0;
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}
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/* 2 Set RX Idle Antenna */
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ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
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pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
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pDM_DigTable->RSSI_max = MaxRSSI;
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}
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void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct adapter *adapter = dm_odm->Adapter;
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if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
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return;
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if (!dm_odm->bLinked) {
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if (dm_fat_tbl->bBecomeLinked) {
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
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dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
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}
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return;
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} else {
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if (!dm_fat_tbl->bBecomeLinked) {
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/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
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rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
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dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
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}
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}
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if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
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odm_HWAntDiv(dm_odm);
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}
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