mirror of
https://github.com/lwfinger/rtl8188eu.git
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319 lines
6 KiB
C
319 lines
6 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __PHYDMPATHDIV_H__
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#define __PHYDMPATHDIV_H__
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/*#define PATHDIV_VERSION "2.0" //2014.11.04*/
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#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/
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#if (defined(CONFIG_PATH_DIVERSITY))
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#define USE_PATH_A_AS_DEFAULT_ANT /* for 8814 dynamic TX path selection */
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#define NUM_RESET_DTP_PERIOD 5
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#define ANT_DECT_RSSI_TH 3
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#define PATH_A 1
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#define PATH_B 2
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#define PATH_C 3
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#define PATH_D 4
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#define PHYDM_AUTO_PATH 0
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#define PHYDM_FIX_PATH 1
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#define NUM_CHOOSE2_FROM4 6
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#define NUM_CHOOSE3_FROM4 4
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#define PHYDM_A BIT(0)
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#define PHYDM_B BIT(1)
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#define PHYDM_C BIT(2)
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#define PHYDM_D BIT(3)
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#define PHYDM_AB (BIT(0) | BIT1) /* 0 */
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#define PHYDM_AC (BIT(0) | BIT2) /* 1 */
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#define PHYDM_AD (BIT(0) | BIT3) /* 2 */
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#define PHYDM_BC (BIT(1) | BIT2) /* 3 */
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#define PHYDM_BD (BIT(1) | BIT3) /* 4 */
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#define PHYDM_CD (BIT(2) | BIT3) /* 5 */
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#define PHYDM_ABC (BIT(0) | BIT1 | BIT2) /* 0*/
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#define PHYDM_ABD (BIT(0) | BIT1 | BIT3) /* 1*/
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#define PHYDM_ACD (BIT(0) | BIT2 | BIT3) /* 2*/
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#define PHYDM_BCD (BIT(1) | BIT2 | BIT3) /* 3*/
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#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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enum phydm_dtp_state {
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PHYDM_DTP_INIT = 1,
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PHYDM_DTP_RUNNING_1
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};
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enum phydm_path_div_type {
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PHYDM_2R_PATH_DIV = 1,
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PHYDM_4R_PATH_DIV = 2
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};
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void
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phydm_process_rssi_for_path_div(
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void *p_dm_void,
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void *p_phy_info_void,
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void *p_pkt_info_void
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);
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struct _ODM_PATH_DIVERSITY_ {
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u8 resp_tx_path;
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u8 path_sel[ODM_ASSOCIATE_ENTRY_NUM];
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u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
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u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u8 phydm_path_div_type;
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#if RTL8814A_SUPPORT
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u32 path_a_sum_all;
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u32 path_b_sum_all;
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u32 path_c_sum_all;
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u32 path_d_sum_all;
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u32 path_a_cnt_all;
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u32 path_b_cnt_all;
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u32 path_c_cnt_all;
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u32 path_d_cnt_all;
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u8 dtp_period;
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bool is_become_linked;
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bool is_u3_mode;
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u8 num_tx_path;
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u8 default_path;
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u8 num_candidate;
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u8 ant_candidate_1;
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u8 ant_candidate_2;
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u8 ant_candidate_3;
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u8 phydm_dtp_state;
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u8 dtp_check_patha_counter;
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bool fix_path_bfer;
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u8 search_space_2[NUM_CHOOSE2_FROM4];
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u8 search_space_3[NUM_CHOOSE3_FROM4];
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u8 pre_tx_path;
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u8 use_path_a_as_default_ant;
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bool is_path_a_exist;
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#endif
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};
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#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */
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void
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phydm_c2h_dtp_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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void
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odm_path_diversity_init(
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void *p_dm_void
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);
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void
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odm_path_diversity(
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void *p_dm_void
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);
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void
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odm_pathdiv_debug(
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void *p_dm_void,
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u32 *const dm_value,
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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/* 1 [OLD IC]-------------------------------------------------------------------------------- */
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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/* #define PATHDIV_ENABLE 1 */
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#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi
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#define path_div_check_before_link8192c odm_path_diversity_before_link92c
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struct _path_div_parameter_define_ {
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u32 org_5g_rege30;
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u32 org_5g_regc14;
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u32 org_5g_regca0;
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u32 swt_5g_rege30;
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u32 swt_5g_regc14;
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u32 swt_5g_regca0;
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/* for 2G IQK information */
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u32 org_2g_regc80;
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u32 org_2g_regc4c;
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u32 org_2g_regc94;
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u32 org_2g_regc14;
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u32 org_2g_regca0;
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u32 swt_2g_regc80;
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u32 swt_2g_regc4c;
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u32 swt_2g_regc94;
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u32 swt_2g_regc14;
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u32 swt_2g_regca0;
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};
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void
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odm_path_diversity_init_92c(
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struct _ADAPTER *adapter
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);
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void
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odm_2t_path_diversity_init_92c(
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struct _ADAPTER *adapter
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);
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void
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odm_1t_path_diversity_init_92c(
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struct _ADAPTER *adapter
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);
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bool
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odm_is_connected_92c(
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struct _ADAPTER *adapter
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);
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bool
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odm_path_diversity_before_link92c(
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/* struct _ADAPTER* adapter */
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struct PHY_DM_STRUCT *p_dm_odm
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);
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void
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odm_path_diversity_after_link_92c(
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struct _ADAPTER *adapter
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);
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void
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odm_set_resp_path_92c(
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struct _ADAPTER *adapter,
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u8 default_resp_path
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);
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void
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odm_ofdm_tx_path_diversity_92c(
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struct _ADAPTER *adapter
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);
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void
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odm_cck_tx_path_diversity_92c(
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struct _ADAPTER *adapter
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);
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void
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odm_reset_path_diversity_92c(
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struct _ADAPTER *adapter
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);
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void
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odm_cck_tx_path_diversity_callback(
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struct timer_list *p_timer
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);
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void
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odm_cck_tx_path_diversity_work_item_callback(
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void *p_context
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);
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void
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odm_path_div_chk_ant_switch_callback(
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struct timer_list *p_timer
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);
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void
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odm_path_div_chk_ant_switch_workitem_callback(
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void *p_context
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);
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void
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odm_path_div_chk_ant_switch(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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void
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odm_cck_path_diversity_chk_per_pkt_rssi(
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struct _ADAPTER *adapter,
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bool is_def_port,
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bool is_match_bssid,
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struct _WLAN_STA *p_entry,
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PRT_RFD p_rfd,
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u8 *p_desc
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);
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void
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odm_path_div_chk_per_pkt_rssi(
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struct _ADAPTER *adapter,
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bool is_def_port,
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bool is_match_bssid,
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struct _WLAN_STA *p_entry,
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PRT_RFD p_rfd
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);
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void
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odm_path_div_rest_after_link(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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void
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odm_fill_tx_path_in_txdesc(
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struct _ADAPTER *adapter,
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PRT_TCB p_tcb,
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u8 *p_desc
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);
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void
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odm_path_div_init_92d(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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u8
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odm_sw_ant_div_select_scan_chnl(
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struct _ADAPTER *adapter
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);
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void
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odm_sw_ant_div_construct_scan_chnl(
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struct _ADAPTER *adapter,
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u8 scan_chnl
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);
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#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */
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#endif /* #ifndef __ODMPATHDIV_H__ */
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