mirror of
https://github.com/lwfinger/rtl8188eu.git
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849 lines
25 KiB
C
Executable file
849 lines
25 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __RTL8723A_HAL_H__
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#define __RTL8723A_HAL_H__
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#include "rtl8723a_spec.h"
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#include "rtl8723a_pg.h"
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#include "Hal8723APhyReg.h"
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#include "Hal8723APhyCfg.h"
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#include "rtl8723a_rf.h"
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#ifdef CONFIG_BT_COEXIST
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#include "rtl8723a_bt-coexist.h"
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#endif
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#include "rtl8723a_dm.h"
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#include "rtl8723a_recv.h"
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#include "rtl8723a_xmit.h"
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#include "rtl8723a_cmd.h"
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#ifdef DBG_CONFIG_ERROR_DETECT
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#include "rtl8723a_sreset.h"
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#endif
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#include "rtw_efuse.h"
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#include "../hal/OUTSRC/odm_precomp.h"
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#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
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//2TODO: We should define 8192S firmware related macro settings here!!
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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#define RTL819X_TOTAL_RF_PATH 2
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//---------------------------------------------------------------------
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// RTL8723S From file
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//---------------------------------------------------------------------
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#define RTL8723_FW_UMC_IMG "rtl8723S\\rtl8723fw.bin"
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#define RTL8723_FW_UMC_B_IMG "rtl8723S\\rtl8723fw_B.bin"
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#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
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#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
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#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
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#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
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#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
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#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
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#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
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//---------------------------------------------------------------------
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// RTL8723S From header
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//---------------------------------------------------------------------
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// Fw Array
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#define Rtl8723_FwImageArray Rtl8723SFwImgArray
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#define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723SFwUMCBCutImgArrayWithBT
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#define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723SFwUMCBCutImgArrayWithoutBT
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#define Rtl8723_ImgArrayLength Rtl8723SImgArrayLength
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#define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723SUMCBCutImgArrayWithBTLength
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#define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723SUMCBCutImgArrayWithoutBTLength
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#define Rtl8723_PHY_REG_Array_PG Rtl8723SPHY_REG_Array_PG
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#define Rtl8723_PHY_REG_Array_PGLength Rtl8723SPHY_REG_Array_PGLength
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#if MP_DRIVER == 1
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#define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray
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#define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength
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#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray
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#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
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#define Rtl8723_PHY_REG_Array_MP Rtl8723SPHY_REG_Array_MP
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#define Rtl8723_PHY_REG_Array_MPLength Rtl8723SPHY_REG_Array_MPLength
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#endif
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#ifndef CONFIG_PHY_SETTING_WITH_ODM
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// MAC/BB/PHY Array
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#define Rtl8723_MAC_Array Rtl8723SMAC_2T_Array
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//#define Rtl8723_AGCTAB_2TArray Rtl8723SAGCTAB_2TArray
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#define Rtl8723_AGCTAB_1TArray Rtl8723SAGCTAB_1TArray
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//#define Rtl8723_PHY_REG_2TArray Rtl8723SPHY_REG_2TArray
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#define Rtl8723_PHY_REG_1TArray Rtl8723SPHY_REG_1TArray
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//#define Rtl8723_RadioA_2TArray Rtl8723SRadioA_2TArray
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#define Rtl8723_RadioA_1TArray Rtl8723SRadioA_1TArray
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//#define Rtl8723_RadioB_2TArray Rtl8723SRadioB_2TArray
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#define Rtl8723_RadioB_1TArray Rtl8723SRadioB_1TArray
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// Array length
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#define Rtl8723_MAC_ArrayLength Rtl8723SMAC_2T_ArrayLength
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#define Rtl8723_AGCTAB_1TArrayLength Rtl8723SAGCTAB_1TArrayLength
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#define Rtl8723_PHY_REG_1TArrayLength Rtl8723SPHY_REG_1TArrayLength
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#define Rtl8723_RadioA_1TArrayLength Rtl8723SRadioA_1TArrayLength
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#define Rtl8723_RadioB_1TArrayLength Rtl8723SRadioB_1TArrayLength
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#endif // CONFIG_PHY_SETTING_WITH_ODM
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#endif // CONFIG_SDIO_HCI
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#ifdef CONFIG_USB_HCI
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//2TODO: We should define 8192S firmware related macro settings here!!
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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#define RTL819X_TOTAL_RF_PATH 2
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//TODO: The following need to check!!
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#define RTL8723_FW_UMC_IMG "rtl8192CU\\rtl8723fw.bin"
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#define RTL8723_FW_UMC_B_IMG "rtl8192CU\\rtl8723fw_B.bin"
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#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
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#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
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#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
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#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
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#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
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#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
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#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
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//---------------------------------------------------------------------
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// RTL8723S From header
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//---------------------------------------------------------------------
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// Fw Array
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#define Rtl8723_FwImageArray Rtl8723UFwImgArray
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#define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723UFwUMCBCutImgArrayWithBT
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#define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723UFwUMCBCutImgArrayWithoutBT
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#define Rtl8723_ImgArrayLength Rtl8723UImgArrayLength
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#define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723UUMCBCutImgArrayWithBTLength
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#define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723UUMCBCutImgArrayWithoutBTLength
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#define Rtl8723_PHY_REG_Array_PG Rtl8723UPHY_REG_Array_PG
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#define Rtl8723_PHY_REG_Array_PGLength Rtl8723UPHY_REG_Array_PGLength
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#if MP_DRIVER == 1
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#define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray
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#define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength
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#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray
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#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
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#define Rtl8723_PHY_REG_Array_MP Rtl8723UPHY_REG_Array_MP
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#define Rtl8723_PHY_REG_Array_MPLength Rtl8723UPHY_REG_Array_MPLength
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#endif
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#ifndef CONFIG_PHY_SETTING_WITH_ODM
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// MAC/BB/PHY Array
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#define Rtl8723_MAC_Array Rtl8723UMAC_2T_Array
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//#define Rtl8723_AGCTAB_2TArray Rtl8723UAGCTAB_2TArray
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#define Rtl8723_AGCTAB_1TArray Rtl8723UAGCTAB_1TArray
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//#define Rtl8723_PHY_REG_2TArray Rtl8723UPHY_REG_2TArray
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#define Rtl8723_PHY_REG_1TArray Rtl8723UPHY_REG_1TArray
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//#define Rtl8723_RadioA_2TArray Rtl8723URadioA_2TArray
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#define Rtl8723_RadioA_1TArray Rtl8723URadioA_1TArray
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//#define Rtl8723_RadioB_2TArray Rtl8723URadioB_2TArray
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#define Rtl8723_RadioB_1TArray Rtl8723URadioB_1TArray
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// Array length
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#define Rtl8723_MAC_ArrayLength Rtl8723UMAC_2T_ArrayLength
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#define Rtl8723_AGCTAB_1TArrayLength Rtl8723UAGCTAB_1TArrayLength
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#define Rtl8723_PHY_REG_1TArrayLength Rtl8723UPHY_REG_1TArrayLength
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#define Rtl8723_RadioA_1TArrayLength Rtl8723URadioA_1TArrayLength
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#define Rtl8723_RadioB_1TArrayLength Rtl8723URadioB_1TArrayLength
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#endif
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#endif
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#define DRVINFO_SZ 4 // unit is 8bytes
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#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
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#define FW_8723A_SIZE 0x8000
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#define FW_8723A_START_ADDRESS 0x1000
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#define FW_8723A_END_ADDRESS 0x1FFF //0x5FFF
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#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
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#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
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typedef enum _FIRMWARE_SOURCE {
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FW_SOURCE_IMG_FILE = 0,
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FW_SOURCE_HEADER_FILE = 1, //from header file
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} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
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typedef struct _RT_FIRMWARE {
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FIRMWARE_SOURCE eFWSource;
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#ifdef CONFIG_EMBEDDED_FWIMG
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u8* szFwBuffer;
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#else
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u8 szFwBuffer[FW_8723A_SIZE];
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#endif
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u32 ulFwLength;
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#ifdef CONFIG_EMBEDDED_FWIMG
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u8* szBTFwBuffer;
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#else
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u8 szBTFwBuffer[FW_8723A_SIZE];
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#endif
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u32 ulBTFwLength;
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} RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_8723A, *PRT_FIRMWARE_8723A;
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//
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// This structure must be cared byte-ordering
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//
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// Added by tynli. 2009.12.04.
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typedef struct _RT_8723A_FIRMWARE_HDR
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{
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// 8-byte alinment required
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//--- LONG WORD 0 ----
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u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
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u8 Category; // AP/NIC and USB/PCI
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u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
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u16 Version; // FW Version
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u8 Subversion; // FW Subversion, default 0x00
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u16 Rsvd1;
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//--- LONG WORD 1 ----
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u8 Month; // Release time Month field
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u8 Date; // Release time Date field
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u8 Hour; // Release time Hour field
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u8 Minute; // Release time Minute field
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u16 RamCodeSize; // The size of RAM code
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u16 Rsvd2;
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//--- LONG WORD 2 ----
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u32 SvnIdx; // The SVN entry index
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u32 Rsvd3;
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//--- LONG WORD 3 ----
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u32 Rsvd4;
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u32 Rsvd5;
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}RT_8723A_FIRMWARE_HDR, *PRT_8723A_FIRMWARE_HDR;
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#define DRIVER_EARLY_INT_TIME 0x05
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#define BCN_DMA_ATIME_INT_TIME 0x02
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#ifdef CONFIG_USB_RX_AGGREGATION
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typedef enum _USB_RX_AGG_MODE{
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USB_RX_AGG_DISABLE,
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USB_RX_AGG_DMA,
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USB_RX_AGG_USB,
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USB_RX_AGG_MIX
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}USB_RX_AGG_MODE;
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#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
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#endif
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// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
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#define MAX_TX_QUEUE 9
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#define TX_SELE_HQ BIT(0) // High Queue
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#define TX_SELE_LQ BIT(1) // Low Queue
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#define TX_SELE_NQ BIT(2) // Normal Queue
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// Note: We will divide number of page equally for each queue other than public queue!
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#define TX_TOTAL_PAGE_NUMBER 0xF8
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#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
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// For Normal Chip Setting
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// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
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#define NORMAL_PAGE_NUM_PUBQ 0xE7
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#define NORMAL_PAGE_NUM_HPQ 0x0C
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#define NORMAL_PAGE_NUM_LPQ 0x02
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#define NORMAL_PAGE_NUM_NPQ 0x02
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// For Test Chip Setting
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// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
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#define TEST_PAGE_NUM_PUBQ 0x7E
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// For Test Chip Setting
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#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
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#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
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#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
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#define WMM_TEST_PAGE_NUM_HPQ 0x29
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#define WMM_TEST_PAGE_NUM_LPQ 0x29
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// Note: For Normal Chip Setting, modify later
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#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
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#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
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#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
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#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
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#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
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#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
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//-------------------------------------------------------------------------
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// Chip specific
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//-------------------------------------------------------------------------
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define CHIP_BONDING_88C_USB_MCARD 0x2
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#define CHIP_BONDING_88C_USB_HP 0x1
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#include "HalVerDef.h"
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#include "hal_com.h"
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//-------------------------------------------------------------------------
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// Channel Plan
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//-------------------------------------------------------------------------
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enum ChannelPlan
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{
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CHPL_FCC = 0,
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CHPL_IC = 1,
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CHPL_ETSI = 2,
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CHPL_SPAIN = 3,
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CHPL_FRANCE = 4,
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CHPL_MKK = 5,
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CHPL_MKK1 = 6,
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CHPL_ISRAEL = 7,
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CHPL_TELEC = 8,
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CHPL_GLOBAL = 9,
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CHPL_WORLD = 10,
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};
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#define HAL_EFUSE_MEMORY
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#define EFUSE_REAL_CONTENT_LEN 512
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#define EFUSE_MAP_LEN 128
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#define EFUSE_MAX_SECTION 16
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#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
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#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
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//
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// <Roger_Notes>
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// To prevent out of boundary programming case,
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// leave 1byte and program full section
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// 9bytes + 1byt + 5bytes and pre 1byte.
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// For worst case:
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// | 1byte|----8bytes----|1byte|--5bytes--|
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// | | Reserved(14bytes) |
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//
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// PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
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#define EFUSE_OOB_PROTECT_BYTES 15
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#define EFUSE_REAL_CONTENT_LEN_8723A 512
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#define EFUSE_MAP_LEN_8723A 256
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#define EFUSE_MAX_SECTION_8723A 32
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//========================================================
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// EFUSE for BT definition
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//========================================================
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#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
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#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
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#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
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#define EFUSE_BT_MAX_SECTION 128 // 1024/8
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#define EFUSE_PROTECT_BYTES_BANK 16
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//
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// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
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//
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typedef enum _RT_MULTI_FUNC {
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RT_MULTI_FUNC_NONE = 0x00,
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RT_MULTI_FUNC_WIFI = 0x01,
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RT_MULTI_FUNC_BT = 0x02,
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RT_MULTI_FUNC_GPS = 0x04,
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} RT_MULTI_FUNC, *PRT_MULTI_FUNC;
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//
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// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
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//
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typedef enum _RT_POLARITY_CTL {
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RT_POLARITY_LOW_ACT = 0,
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RT_POLARITY_HIGH_ACT = 1,
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} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
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// For RTL8723 regulator mode. by tynli. 2011.01.14.
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typedef enum _RT_REGULATOR_MODE {
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RT_SWITCHING_REGULATOR = 0,
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RT_LDO_REGULATOR = 1,
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} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
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// Description: Determine the types of C2H events that are the same in driver and Fw.
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// Fisrt constructed by tynli. 2009.10.09.
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typedef enum _RTL8192C_C2H_EVT
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{
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C2H_DBG = 0,
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C2H_TSF = 1,
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C2H_AP_RPT_RSP = 2,
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C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet.
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C2H_BT_RSSI = 4,
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C2H_BT_OP_MODE = 5,
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C2H_EXT_RA_RPT = 6,
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C2H_HW_INFO_EXCH = 10,
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C2H_C2H_H2C_TEST = 11,
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C2H_BT_INFO = 12,
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C2H_BT_MP_INFO = 15,
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MAX_C2HEVENT
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} RTL8192C_C2H_EVT;
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typedef struct hal_data_8723a
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{
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HAL_VERSION VersionID;
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RT_CUSTOMER_ID CustomerID;
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u16 FirmwareVersion;
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u16 FirmwareVersionRev;
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u16 FirmwareSubVersion;
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u16 FirmwareSignature;
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//current WIFI_PHY values
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u32 ReceiveConfig;
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WIRELESS_MODE CurrentWirelessMode;
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HT_CHANNEL_WIDTH CurrentChannelBW;
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u8 CurrentChannel;
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u8 nCur40MhzPrimeSC;// Control channel sub-carrier
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u16 BasicRateSet;
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//rf_ctrl
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u8 rf_chip;
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u8 rf_type;
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u8 NumTotalRFPath;
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u8 BoardType;
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u8 CrystalCap;
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//
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// EEPROM setting.
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//
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u8 EEPROMVersion;
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u16 EEPROMVID;
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u16 EEPROMPID;
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u16 EEPROMSVID;
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u16 EEPROMSDID;
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u8 EEPROMCustomerID;
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u8 EEPROMSubCustomerID;
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u8 EEPROMRegulatory;
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u8 EEPROMThermalMeter;
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u8 EEPROMBluetoothCoexist;
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u8 EEPROMBluetoothType;
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u8 EEPROMBluetoothAntNum;
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u8 EEPROMBluetoothAntIsolation;
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u8 EEPROMBluetoothRadioShared;
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u8 bTXPowerDataReadFromEEPORM;
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u8 bAPKThermalMeterIgnore;
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u8 bIQKInitialized;
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u8 bAntennaDetected;
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u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
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u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
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u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
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u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
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// For power group
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u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
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// Read/write are allow for following hardware information variables
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u8 framesync;
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u32 framesyncC34;
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u8 framesyncMonitor;
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u8 DefaultInitialGain[4];
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u8 pwrGroupCnt;
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u32 MCSTxPowerLevelOriginalOffset[7][16];
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u32 CCKTxPowerLevelOriginalOffset;
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u32 AntennaTxPath; // Antenna path Tx
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u32 AntennaRxPath; // Antenna path Rx
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u8 ExternalPA;
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u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
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//u32 LedControlNum;
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//u32 LedControlMode;
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//u32 TxPowerTrackControl;
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u8 b1x1RecvCombine; // for 1T1R receive combining
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// For EDCA Turbo mode
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// u8 bIsAnyNonBEPkts; // Adapter->recvpriv.bIsAnyNonBEPkts
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// u8 bCurrentTurboEDCA;
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// u8 bForcedDisableTurboEDCA;
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// u8 bIsCurRDLState; // pdmpriv->prv_traffic_idx
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u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
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//vivi, for tx power tracking, 20080407
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//u16 TSSI_13dBm;
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//u32 Pwr_Track;
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// The current Tx Power Level
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u8 CurrentCckTxPwrIdx;
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u8 CurrentOfdm24GTxPwrIdx;
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BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
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BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
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u32 RfRegChnlVal[2];
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u8 bCckHighPower;
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//RDG enable
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BOOLEAN bRDGEnable;
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//for host message to fw
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u8 LastHMEBoxNum;
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u8 fw_ractrl;
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u8 RegTxPause;
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// Beacon function related global variable.
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u32 RegBcnCtrlVal;
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u8 RegFwHwTxQCtrl;
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u8 RegReg542;
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struct dm_priv dmpriv;
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DM_ODM_T odmpriv;
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//_lock odm_stainfo_lock;
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#ifdef DBG_CONFIG_ERROR_DETECT
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struct sreset_priv srestpriv;
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#endif
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#ifdef CONFIG_BT_COEXIST
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u8 bBTMode;
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// BT only.
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BT30Info BtInfo;
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// For bluetooth co-existance
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BT_COEXIST_STR bt_coexist;
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#endif
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#ifdef CONFIG_ANTENNA_DIVERSITY
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u8 CurAntenna;
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// SW Antenna Switch
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s32 RSSI_sum_A;
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s32 RSSI_sum_B;
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s32 RSSI_cnt_A;
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s32 RSSI_cnt_B;
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u8 RSSI_test;
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u8 AntDivCfg;
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#endif
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u8 bDumpRxPkt;//for debug
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u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
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// 2010/08/09 MH Add CU power down mode.
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u8 pwrdown;
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// Add for dual MAC 0--Mac0 1--Mac1
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u32 interfaceIndex;
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u8 OutEpQueueSel;
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u8 OutEpNumber;
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// 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
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BOOLEAN UsbRxHighSpeedMode;
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// 2010/11/22 MH Add for slim combo debug mode selective.
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// This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
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BOOLEAN SlimComboDbg;
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//
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// Add For EEPROM Efuse switch and Efuse Shadow map Setting
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//
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u8 EepromOrEfuse;
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// u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
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u16 EfuseUsedBytes;
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u8 EfuseUsedPercentage;
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#ifdef HAL_EFUSE_MEMORY
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EFUSE_HAL EfuseHal;
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#endif
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// Interrupt relatd register information.
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u32 SysIntrStatus;
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u32 SysIntrMask;
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//
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// 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an
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// independent file in the future.
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//
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//------------------------8723-----------------------------------------//
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RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
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RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
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RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
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//------------------------8723-----------------------------------------//
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//
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// 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an
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// independent file in the future.
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BOOLEAN bMACFuncEnable;
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#ifdef CONFIG_P2P
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struct P2P_PS_Offload_t p2p_ps_offload;
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#endif
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//
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// For USB Interface HAL related
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//
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#ifdef CONFIG_USB_HCI
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u32 UsbBulkOutSize;
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// Interrupt relatd register information.
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u32 IntArray[2];
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u32 IntrMask[2];
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#endif
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//
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// For SDIO Interface HAL related
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//
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// Auto FSM to Turn On, include clock, isolation, power control for MAC only
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u8 bMacPwrCtrlOn;
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#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
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//
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// SDIO ISR Related
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//
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// u32 IntrMask[1];
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// u32 IntrMaskToSet[1];
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// LOG_INTERRUPT InterruptLog;
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u32 sdio_himr;
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u32 sdio_hisr;
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//
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// SDIO Tx FIFO related.
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//
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// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
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u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
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_lock SdioTxFIFOFreePageLock;
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//
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// SDIO Rx FIFO related.
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//
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u8 SdioRxFIFOCnt;
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u16 SdioRxFIFOSize;
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#endif
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} HAL_DATA_8723A, *PHAL_DATA_8723A;
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#if 0
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#define HAL_DATA_TYPE HAL_DATA_8723A
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#define PHAL_DATA_TYPE PHAL_DATA_8723A
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#else
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typedef struct hal_data_8723a HAL_DATA_TYPE, *PHAL_DATA_TYPE;
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#endif
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#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
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#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
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#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
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#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
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typedef struct rxreport_8723a
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{
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u32 pktlen:14;
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u32 crc32:1;
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u32 icverr:1;
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u32 drvinfosize:4;
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u32 security:3;
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u32 qos:1;
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u32 shift:2;
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u32 physt:1;
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u32 swdec:1;
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u32 ls:1;
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u32 fs:1;
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u32 eor:1;
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u32 own:1;
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u32 macid:5;
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u32 tid:4;
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u32 hwrsvd:4;
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u32 amsdu:1;
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u32 paggr:1;
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u32 faggr:1;
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u32 a1fit:4;
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u32 a2fit:4;
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u32 pam:1;
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u32 pwr:1;
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u32 md:1;
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u32 mf:1;
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u32 type:2;
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u32 mc:1;
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u32 bc:1;
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u32 seq:12;
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u32 frag:4;
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u32 nextpktlen:14;
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u32 nextind:1;
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u32 rsvd0831:1;
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u32 rxmcs:6;
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u32 rxht:1;
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u32 gf:1;
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u32 splcp:1;
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u32 bw:1;
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u32 htc:1;
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u32 eosp:1;
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u32 bssidfit:2;
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u32 rsvd1214:16;
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u32 unicastwake:1;
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u32 magicwake:1;
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u32 pattern0match:1;
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u32 pattern1match:1;
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u32 pattern2match:1;
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u32 pattern3match:1;
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u32 pattern4match:1;
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u32 pattern5match:1;
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u32 pattern6match:1;
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u32 pattern7match:1;
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u32 pattern8match:1;
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u32 pattern9match:1;
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u32 patternamatch:1;
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u32 patternbmatch:1;
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u32 patterncmatch:1;
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u32 rsvd1613:19;
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u32 tsfl;
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u32 bassn:12;
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u32 bavld:1;
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u32 rsvd2413:19;
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} RXREPORT, *PRXREPORT;
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typedef struct phystatus_8723a
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{
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u32 rxgain_a:7;
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u32 trsw_a:1;
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u32 rxgain_b:7;
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u32 trsw_b:1;
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u32 chcorr_l:16;
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u32 sigqualcck:8;
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u32 cfo_a:8;
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u32 cfo_b:8;
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u32 chcorr_h:8;
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u32 noisepwrdb_h:8;
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u32 cfo_tail_a:8;
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u32 cfo_tail_b:8;
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u32 rsvd0824:8;
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u32 rsvd1200:8;
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u32 rxevm_a:8;
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u32 rxevm_b:8;
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u32 rxsnr_a:8;
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u32 rxsnr_b:8;
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u32 noisepwrdb_l:8;
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u32 rsvd1616:8;
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u32 postsnr_a:8;
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u32 postsnr_b:8;
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u32 csi_a:8;
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u32 csi_b:8;
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u32 targetcsi_a:8;
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u32 targetcsi_b:8;
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u32 sigevm:8;
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u32 maxexpwr:8;
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u32 exintflag:1;
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u32 sgien:1;
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u32 rxsc:2;
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u32 idlelong:1;
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u32 anttrainen:1;
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u32 antselb:1;
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u32 antsel:1;
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} PHYSTATUS, *PPHYSTATUS;
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// rtl8723a_hal_init.c
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int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware);
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s32 rtl8723a_FirmwareDownload(PADAPTER padapter);
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void rtl8723a_FirmwareSelfReset(PADAPTER padapter);
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void rtl8723a_InitializeFirmwareVars(PADAPTER padapter);
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void _8051Reset8723A(PADAPTER padapter);
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void rtl8723a_InitAntenna_Selection(PADAPTER padapter);
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void rtl8723a_DeinitAntenna_Selection(PADAPTER padapter);
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void rtl8723a_CheckAntenna_Selection(PADAPTER padapter);
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void rtl8723a_init_default_value(PADAPTER padapter);
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s32 InitLLTTable(PADAPTER padapter, u32 boundary);
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s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
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s32 CardDisableWithoutHWSM(PADAPTER padapter);
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// EFuse
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u8 GetEEPROMSize8723A(PADAPTER padapter);
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void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
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void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
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void Hal_EfuseParseTxPowerInfo_8723A(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
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void Hal_EfuseParseBTCoexistInfo_8723A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
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void Hal_EfuseParseEEPROMVer(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
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void rtl8723a_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
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void Hal_EfuseParseCustomerID(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
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void Hal_EfuseParseAntennaDiversity(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
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void Hal_EfuseParseRateIndicationOption(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
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void Hal_EfuseParseXtal_8723A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
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void Hal_EfuseParseThermalMeter_8723A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
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//RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan);
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//VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter);
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//void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoloadFail);
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void Hal_InitChannelPlan(PADAPTER padapter);
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void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc);
|
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void SetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
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void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
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#ifdef CONFIG_BT_COEXIST
|
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void rtl8723a_SingleDualAntennaDetection(PADAPTER padapter);
|
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#endif
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|
|
// register
|
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void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
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void rtl8723a_InitBeaconParameters(PADAPTER padapter);
|
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void rtl8723a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
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|
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void rtl8723a_start_thread(_adapter *padapter);
|
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void rtl8723a_stop_thread(_adapter *padapter);
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|
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s32 c2h_id_filter_ccx_8723a(u8 id);
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|
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#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
|
void rtl8723a_init_checkbthang_workqueue(_adapter * padapter);
|
|
void rtl8723a_free_checkbthang_workqueue(_adapter * padapter);
|
|
void rtl8723a_cancel_checkbthang_workqueue(_adapter * padapter);
|
|
void rtl8723a_hal_check_bt_hang(_adapter * padapter);
|
|
#endif
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|
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#ifdef CONFIG_RF_GAIN_OFFSET
|
|
void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
|
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#endif //CONFIG_RF_GAIN_OFFSET
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|
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#endif
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