mirror of
https://github.com/lwfinger/rtl8188eu.git
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677 lines
19 KiB
C
677 lines
19 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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/******************************************************************************
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*
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*
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* Module: rtl8192c_rf6052.c ( Source C File)
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*
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* Note: Provide RF 6052 series relative API.
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*
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* Function:
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*
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* Export:
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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*
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* 09/25/2008 MHC Create initial version.
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* 11/05/2008 MHC Add API for tw power setting.
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*
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*
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******************************************************************************/
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#define _RTL8188E_RF6052_C_
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#include <osdep_service.h>
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#include <drv_types.h>
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#include <rtl8188e_hal.h>
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/*---------------------------Define Local Constant---------------------------*/
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/* Define local structure for debug!!!!! */
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struct rf_shadow {
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/* Shadow register value */
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u32 Value;
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/* Compare or not flag */
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u8 Compare;
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/* Record If it had ever modified unpredicted */
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u8 ErrorOrNot;
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/* Recorver Flag */
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u8 Recorver;
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/* */
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u8 Driver_Write;
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};
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/*---------------------------Define Local Constant---------------------------*/
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/*------------------------Define global variable-----------------------------*/
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/*------------------------Define global variable-----------------------------*/
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/*------------------------Define local variable------------------------------*/
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/* 2008/11/20 MH For Debug only, RF */
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static struct rf_shadow RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
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/*------------------------Define local variable------------------------------*/
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/*-----------------------------------------------------------------------------
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* Function: RF_ChangeTxPath
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*
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* Overview: For RL6052, we must change some RF settign for 1T or 2T.
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*
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* Input: u2Byte DataRate 0x80-8f, 0x90-9f
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 09/25/2008 MHC Create Version 0.
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* Firmwaer support the utility later.
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*
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*---------------------------------------------------------------------------*/
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void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
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u16 DataRate)
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{
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/* We do not support gain table change inACUT now !!!! Delete later !!! */
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} /* RF_ChangeTxPath */
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetBandwidth()
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*
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: struct adapter * Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Note: For RF type 0222D
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*---------------------------------------------------------------------------*/
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void
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rtl8188e_PHY_RF6052SetBandwidth(
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struct adapter * Adapter,
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enum ht_channel_width Bandwidth) /* 20M or 40M */
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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switch (Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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break;
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case HT_CHANNEL_WIDTH_40:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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break;
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default:
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/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
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break;
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}
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}
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetCckTxPower
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*
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* Overview:
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*
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* Input: NONE
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 11/05/2008 MHC Simulate 8192series..
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*
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*---------------------------------------------------------------------------*/
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void
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rtl8188e_PHY_RF6052SetCckTxPower(
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struct adapter * Adapter,
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u8* pPowerlevel)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
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/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
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u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
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bool TurboScanOff = false;
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u8 idx1, idx2;
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u8* ptr;
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u8 direction;
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/* FOR CE ,must disable turbo scan */
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TurboScanOff = true;
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if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
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{
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TxAGC[RF_PATH_A] = 0x3f3f3f3f;
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TxAGC[RF_PATH_B] = 0x3f3f3f3f;
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TurboScanOff = true;/* disable turbo scan */
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if (TurboScanOff)
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{
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for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
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if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
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TxAGC[idx1] = 0x20;
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}
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}
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}
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else
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{
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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{
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TxAGC[RF_PATH_A] = 0x10101010;
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TxAGC[RF_PATH_B] = 0x10101010;
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}
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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{
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TxAGC[RF_PATH_A] = 0x00000000;
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TxAGC[RF_PATH_B] = 0x00000000;
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}
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else
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{
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for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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}
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if (pHalData->EEPROMRegulatory==0)
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{
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tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
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(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
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TxAGC[RF_PATH_A] += tmpval;
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tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
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(pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
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TxAGC[RF_PATH_B] += tmpval;
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}
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}
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}
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for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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ptr = (u8*)(&(TxAGC[idx1]));
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for (idx2=0; idx2<4; idx2++)
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{
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if (*ptr > RF6052_MAX_TX_PWR)
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*ptr = RF6052_MAX_TX_PWR;
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ptr++;
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}
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}
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ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
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if (direction == 1) /* Increase TX pwoer */
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{
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TxAGC[0] += pwrtrac_value;
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TxAGC[1] += pwrtrac_value;
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}
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else if (direction == 2) /* Decrease TX pwoer */
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{
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TxAGC[0] -= pwrtrac_value;
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TxAGC[1] -= pwrtrac_value;
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}
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/* rf-A cck tx power */
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tmpval = TxAGC[RF_PATH_A]&0xff;
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PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
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tmpval = TxAGC[RF_PATH_A]>>8;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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/* rf-B cck tx power */
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tmpval = TxAGC[RF_PATH_B]>>24;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
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tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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} /* PHY_RF6052SetCckTxPower */
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/* */
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/* powerbase0 for OFDM rates */
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/* powerbase1 for HT MCS rates */
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/* */
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static void getPowerBase88E(
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struct adapter * Adapter,
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u8* pPowerLevelOFDM,
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u8* pPowerLevelBW20,
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u8* pPowerLevelBW40,
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u8 Channel,
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u32* OfdmBase,
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u32* MCSBase
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)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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u32 powerBase0, powerBase1;
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u8 Legacy_pwrdiff=0;
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s8 HT20_pwrdiff=0;
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u8 i, powerlevel[2];
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for (i=0; i<2; i++)
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{
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powerBase0 = pPowerLevelOFDM[i];
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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*(OfdmBase+i) = powerBase0;
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}
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for (i=0; i<pHalData->NumTotalRFPath; i++)
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{
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/* Check HT20 to HT40 diff */
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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{
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powerlevel[i] = pPowerLevelBW20[i];
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}
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else
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{
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powerlevel[i] = pPowerLevelBW40[i];
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}
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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*(MCSBase+i) = powerBase1;
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}
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}
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static void getTxPowerWriteValByRegulatory88E(
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struct adapter * Adapter,
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u8 Channel,
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u8 index,
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u32* powerBase0,
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u32* powerBase1,
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u32* pOutWriteVal
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)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
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s1Byte pwr_diff=0;
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u4Byte writeVal, customer_limit, rf;
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u1Byte Regulatory = pHalData->EEPROMRegulatory;
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/* */
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/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
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/* */
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for (rf=0; rf<2; rf++) {
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switch (Regulatory)
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{
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case 0: /* Realtek better performance */
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/* increase power diff defined by Realtek for large power */
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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break;
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case 1: /* Realtek regulatory */
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/* increase power diff defined by Realtek for regulatory */
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{
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if (pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
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{
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if (Channel < 3) /* Chanel 1-2 */
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chnlGroup = 0;
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else if (Channel < 6) /* Channel 3-5 */
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chnlGroup = 1;
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else if (Channel <9) /* Channel 6-8 */
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chnlGroup = 2;
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else if (Channel <12) /* Channel 9-11 */
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chnlGroup = 3;
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else if (Channel <14) /* Channel 12-13 */
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chnlGroup = 4;
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else if (Channel ==14) /* Channel 14 */
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chnlGroup = 5;
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}
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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}
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break;
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case 2: /* Better regulatory */
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/* don't increase any power diff */
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writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
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break;
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case 3: /* Customer defined power diff. */
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/* increase power diff defined by customer. */
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chnlGroup = 0;
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if (index < 2)
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pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
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else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
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else
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customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
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if (pwr_diff >= customer_pwr_limit)
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pwr_diff = 0;
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else
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pwr_diff = customer_pwr_limit - pwr_diff;
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for (i=0; i<4; i++)
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{
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pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
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if (pwr_diff_limit[i] > pwr_diff)
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pwr_diff_limit[i] = pwr_diff;
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}
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customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
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(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
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writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
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break;
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default:
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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break;
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}
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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/* 92d do not need this */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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writeVal = 0x14141414;
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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writeVal = 0x00000000;
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/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
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/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
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{
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writeVal = writeVal - 0x06060606;
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}
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
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{
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writeVal = writeVal ;
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}
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*(pOutWriteVal+rf) = writeVal;
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}
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}
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static void writeOFDMPowerReg88E(
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struct adapter * Adapter,
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u8 index,
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u32* pValue
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)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
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rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
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rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
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u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
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rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
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rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
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u8 i, rf, pwr_val[4];
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u32 writeVal;
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u16 RegOffset;
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for (rf=0; rf<2; rf++)
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{
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writeVal = pValue[rf];
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for (i=0; i<4; i++)
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{
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pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
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if (pwr_val[i] > RF6052_MAX_TX_PWR)
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pwr_val[i] = RF6052_MAX_TX_PWR;
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}
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writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
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if (rf == 0)
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RegOffset = RegOffset_A[index];
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else
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RegOffset = RegOffset_B[index];
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PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
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/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
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if (((pHalData->rf_type == RF_2T2R) &&
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(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
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|
((pHalData->rf_type != RF_2T2R) &&
|
|
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
|
|
{
|
|
writeVal = pwr_val[3];
|
|
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
|
|
RegOffset = 0xc90;
|
|
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
|
|
RegOffset = 0xc98;
|
|
for (i=0; i<3; i++)
|
|
{
|
|
if (i!=2)
|
|
writeVal = (writeVal>8)?(writeVal-8):0;
|
|
else
|
|
writeVal = (writeVal>6)?(writeVal-6):0;
|
|
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*-----------------------------------------------------------------------------
|
|
* Function: PHY_RF6052SetOFDMTxPower
|
|
*
|
|
* Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
|
|
* different channel and read original value in TX power register area from
|
|
* 0xe00. We increase offset and original value to be correct tx pwr.
|
|
*
|
|
* Input: NONE
|
|
*
|
|
* Output: NONE
|
|
*
|
|
* Return: NONE
|
|
*
|
|
* Revised History:
|
|
* When Who Remark
|
|
* 11/05/2008 MHC Simulate 8192 series method.
|
|
* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
|
|
* A/B pwr difference or legacy/HT pwr diff.
|
|
* 2. We concern with path B legacy/HT OFDM difference.
|
|
* 01/22/2009 MHC Support new EPRO format from SD3.
|
|
*
|
|
*---------------------------------------------------------------------------*/
|
|
|
|
void
|
|
rtl8188e_PHY_RF6052SetOFDMTxPower(
|
|
struct adapter * Adapter,
|
|
u8* pPowerLevelOFDM,
|
|
u8* pPowerLevelBW20,
|
|
u8* pPowerLevelBW40,
|
|
u8 Channel)
|
|
{
|
|
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
|
u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
|
|
u8 direction;
|
|
u8 index = 0;
|
|
|
|
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
|
|
|
|
/* */
|
|
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
|
|
/* This is ued to fix unstable power tracking mode. */
|
|
/* */
|
|
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
|
|
|
|
for (index=0; index<6; index++)
|
|
{
|
|
getTxPowerWriteValByRegulatory88E(Adapter, Channel, index,
|
|
&powerBase0[0], &powerBase1[0], &writeVal[0]);
|
|
|
|
if (direction == 1)
|
|
{
|
|
writeVal[0] += pwrtrac_value;
|
|
writeVal[1] += pwrtrac_value;
|
|
}
|
|
else if (direction == 2)
|
|
{
|
|
writeVal[0] -= pwrtrac_value;
|
|
writeVal[1] -= pwrtrac_value;
|
|
}
|
|
|
|
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
|
|
}
|
|
}
|
|
|
|
static void
|
|
phy_RF6052_Config_HardCode(
|
|
struct adapter * Adapter
|
|
)
|
|
{
|
|
}
|
|
|
|
static int
|
|
phy_RF6052_Config_ParaFile(
|
|
struct adapter * Adapter
|
|
)
|
|
{
|
|
u32 u4RegValue;
|
|
u8 eRFPath;
|
|
struct bb_reg_def *pPhyReg;
|
|
int rtStatus = _SUCCESS;
|
|
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
|
static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
|
|
static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
|
|
|
|
/* 3----------------------------------------------------------------- */
|
|
/* 3 <2> Initialize RF */
|
|
/* 3----------------------------------------------------------------- */
|
|
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
|
{
|
|
|
|
pPhyReg = &pHalData->PHYRegDef[eRFPath];
|
|
|
|
/*----Store original RFENV control type----*/
|
|
switch (eRFPath) {
|
|
case RF_PATH_A:
|
|
case RF_PATH_C:
|
|
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
|
|
break;
|
|
case RF_PATH_B :
|
|
case RF_PATH_D:
|
|
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
|
|
break;
|
|
}
|
|
|
|
/*----Set RF_ENV enable----*/
|
|
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
|
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
|
|
|
/*----Set RF_ENV output high----*/
|
|
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
|
|
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
|
|
|
/* Set bit number of Address and Data for RF register */
|
|
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
|
|
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
|
|
|
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
|
|
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
|
|
|
/*----Initialize RF fom connfiguration file----*/
|
|
switch (eRFPath) {
|
|
case RF_PATH_A:
|
|
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
|
rtStatus= _FAIL;
|
|
break;
|
|
case RF_PATH_B:
|
|
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
|
rtStatus= _FAIL;
|
|
break;
|
|
case RF_PATH_C:
|
|
break;
|
|
case RF_PATH_D:
|
|
break;
|
|
}
|
|
|
|
/*----Restore RFENV control type----*/;
|
|
switch (eRFPath)
|
|
{
|
|
case RF_PATH_A:
|
|
case RF_PATH_C:
|
|
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
|
|
break;
|
|
case RF_PATH_B :
|
|
case RF_PATH_D:
|
|
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
|
|
break;
|
|
}
|
|
|
|
if (rtStatus != _SUCCESS)
|
|
goto phy_RF6052_Config_ParaFile_Fail;
|
|
|
|
}
|
|
|
|
return rtStatus;
|
|
|
|
phy_RF6052_Config_ParaFile_Fail:
|
|
return rtStatus;
|
|
}
|
|
|
|
|
|
int
|
|
PHY_RF6052_Config8188E(
|
|
struct adapter * Adapter)
|
|
{
|
|
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
|
int rtStatus = _SUCCESS;
|
|
|
|
/* */
|
|
/* Initialize general global value */
|
|
/* */
|
|
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
|
|
if (pHalData->rf_type == RF_1T1R)
|
|
pHalData->NumTotalRFPath = 1;
|
|
else
|
|
pHalData->NumTotalRFPath = 2;
|
|
|
|
/* */
|
|
/* Config BB and RF */
|
|
/* */
|
|
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
|
|
return rtStatus;
|
|
}
|
|
|
|
/* End of HalRf6052.c */
|