mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-25 14:03:40 +00:00
19db43ecbd
This driver was added to the kernel with version 3.12. The changes in that version are now brought back to the GitHub repo. Essentually all of the code is updated. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
276 lines
8.6 KiB
C
276 lines
8.6 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __INC_HAL8188EPHYCFG_H__
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#define __INC_HAL8188EPHYCFG_H__
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 /* us */
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#define AntennaDiversityValue 0x80
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#define IQK_MAC_REG_NUM 4
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#define IQK_ADDA_REG_NUM 16
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#define IQK_BB_REG_NUM 9
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#define HP_THERMAL_NUM 8
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#define MAX_AGGR_NUM 0x07
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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enum sw_chnl_cmd_id {
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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CmdID_WritePortUlong,
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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};
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/* 1. Switch channel related */
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struct sw_chnl_cmd {
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enum sw_chnl_cmd_id CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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};
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enum hw90_block {
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4, /* Never use this */
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};
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enum rf_radio_path {
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RF_PATH_A = 0, /* Radio Path A */
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RF_PATH_B = 1, /* Radio Path B */
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RF_PATH_C = 2, /* Radio Path C */
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RF_PATH_D = 3, /* Radio Path D */
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};
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#define MAX_PG_GROUP 13
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#define RF_PATH_MAX 2
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#define MAX_RF_PATH RF_PATH_MAX
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#define MAX_TX_COUNT 4 /* path numbers */
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#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
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#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
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*ch9~11, ch12~13, CH 14
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* total three groups */
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#define CHANNEL_GROUP_MAX_88E 6
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enum wireless_mode {
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WIRELESS_MODE_UNKNOWN = 0x00,
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WIRELESS_MODE_A = BIT2,
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WIRELESS_MODE_B = BIT0,
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WIRELESS_MODE_G = BIT1,
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WIRELESS_MODE_AUTO = BIT5,
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WIRELESS_MODE_N_24G = BIT3,
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WIRELESS_MODE_N_5G = BIT4,
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WIRELESS_MODE_AC = BIT6
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};
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enum phy_rate_tx_offset_area {
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RA_OFFSET_LEGACY_OFDM1,
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RA_OFFSET_LEGACY_OFDM2,
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RA_OFFSET_HT_OFDM1,
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RA_OFFSET_HT_OFDM2,
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RA_OFFSET_HT_OFDM3,
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RA_OFFSET_HT_OFDM4,
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RA_OFFSET_HT_CCK,
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};
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/* BB/RF related */
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enum RF_TYPE_8190P {
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RF_TYPE_MIN, /* 0 */
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RF_8225 = 1, /* 1 11b/g RF for verification only */
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RF_8256 = 2, /* 2 11b/g/n */
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RF_8258 = 3, /* 3 11a/b/g/n RF */
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RF_6052 = 4, /* 4 11b/g/n RF */
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/* TODO: We should remove this psudo PHY RF after we get new RF. */
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RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */
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};
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struct bb_reg_def {
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u32 rfintfs; /* set software control: */
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/* 0x870~0x877[8 bytes] */
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u32 rfintfi; /* readback data: */
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/* 0x8e0~0x8e7[8 bytes] */
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u32 rfintfo; /* output data: */
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/* 0x860~0x86f [16 bytes] */
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u32 rfintfe; /* output enable: */
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/* 0x860~0x86f [16 bytes] */
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u32 rf3wireOffset; /* LSSI data: */
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/* 0x840~0x84f [16 bytes] */
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u32 rfLSSI_Select; /* BB Band Select: */
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/* 0x878~0x87f [8 bytes] */
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u32 rfTxGainStage; /* Tx gain stage: */
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/* 0x80c~0x80f [4 bytes] */
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u32 rfHSSIPara1; /* wire parameter control1 : */
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/* 0x820~0x823,0x828~0x82b,
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* 0x830~0x833, 0x838~0x83b [16 bytes] */
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u32 rfHSSIPara2; /* wire parameter control2 : */
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/* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
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* 0x83c~0x83f [16 bytes] */
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u32 rfSwitchControl; /* Tx Rx antenna control : */
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/* 0x858~0x85f [16 bytes] */
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u32 rfAGCControl1; /* AGC parameter control1 : */
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/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
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* 0xc68~0xc6b [16 bytes] */
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u32 rfAGCControl2; /* AGC parameter control2 : */
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/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
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* 0xc6c~0xc6f [16 bytes] */
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u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
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/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
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* 0xc2c~0xc2f [16 bytes] */
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u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
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* Rx DC notch filter : */
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/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
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* 0xc28~0xc2b [16 bytes] */
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u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
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/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
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* 0xc98~0xc9b [16 bytes] */
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u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
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/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
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* 0xc9c~0xc9f [16 bytes] */
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u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
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/* 0x8a0~0x8af [16 bytes] */
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u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
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* Path A and B */
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};
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struct ant_sel_ofdm {
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 OFDM_TXSC:2;
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u32 reserved:2;
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};
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struct ant_sel_cck {
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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};
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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/* */
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/* BB and RF register read/write */
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/* */
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u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
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void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
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u32 mask, u32 data);
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u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
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u32 regaddr, u32 mask);
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void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
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u32 regaddr, u32 mask, u32 data);
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/* Initialization related function */
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8188E(struct adapter *adapter);
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int PHY_BBConfig8188E(struct adapter *adapter);
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int PHY_RFConfig8188E(struct adapter *adapter);
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/* RF config */
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int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *adapter, u8 *filename,
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enum rf_radio_path rfpath);
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int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *adapter,
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enum rf_radio_path rfpath);
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/* Read initi reg value for tx power setting. */
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void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
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/* BB TX Power R/W */
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void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
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void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
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bool PHY_UpdateTxPowerDbm8188E(struct adapter *adapter, int power);
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void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
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/* Switch bandwidth for 8192S */
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void PHY_SetBWMode8188E(struct adapter *adapter,
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enum ht_channel_width chnlwidth, unsigned char offset);
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/* channel switch related funciton */
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void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
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/* Call after initialization */
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void ChkFwCmdIoDone(struct adapter *adapter);
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/* BB/MAC/RF other monitor API */
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void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
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void PHY_SwitchEphyParameter(struct adapter *adapter);
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void PHY_EnableHostClkReq(struct adapter *adapter);
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bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
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void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
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u32 mask, u32 data);
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/*--------------------------Exported Function prototype---------------------*/
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#define PHY_QueryBBReg(adapt, regaddr, mask) \
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rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask))
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#define PHY_SetBBReg(adapt, regaddr, bitmask, data) \
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rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data))
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#define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \
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rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask))
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#define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \
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rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data))
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#define PHY_SetMacReg PHY_SetBBReg
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#define SIC_HW_SUPPORT 0
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#define SIC_MAX_POLL_CNT 5
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#define SIC_CMD_READY 0
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#define SIC_CMD_WRITE 1
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#define SIC_CMD_READ 2
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#define SIC_CMD_REG 0x1EB /* 1byte */
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#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
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#define SIC_DATA_REG 0x1EC /* 1bc~1bf */
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#endif /* __INC_HAL8192CPHYCFG_H */
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