mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-25 14:03:40 +00:00
194 lines
4.8 KiB
C
194 lines
4.8 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HALHWOUTSRC_H__
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#define __HALHWOUTSRC_H__
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//============================================================
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// Definition
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//============================================================
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//
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//-----------------------------------------------------------
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// CCK Rates, TxHT = 0
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#define DESC92C_RATE1M 0x00
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#define DESC92C_RATE2M 0x01
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#define DESC92C_RATE5_5M 0x02
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#define DESC92C_RATE11M 0x03
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// OFDM Rates, TxHT = 0
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#define DESC92C_RATE6M 0x04
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#define DESC92C_RATE9M 0x05
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#define DESC92C_RATE12M 0x06
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#define DESC92C_RATE18M 0x07
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#define DESC92C_RATE24M 0x08
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#define DESC92C_RATE36M 0x09
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#define DESC92C_RATE48M 0x0a
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#define DESC92C_RATE54M 0x0b
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// MCS Rates, TxHT = 1
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#define DESC92C_RATEMCS0 0x0c
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#define DESC92C_RATEMCS1 0x0d
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#define DESC92C_RATEMCS2 0x0e
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#define DESC92C_RATEMCS3 0x0f
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#define DESC92C_RATEMCS4 0x10
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#define DESC92C_RATEMCS5 0x11
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#define DESC92C_RATEMCS6 0x12
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#define DESC92C_RATEMCS7 0x13
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#define DESC92C_RATEMCS8 0x14
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#define DESC92C_RATEMCS9 0x15
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#define DESC92C_RATEMCS10 0x16
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#define DESC92C_RATEMCS11 0x17
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#define DESC92C_RATEMCS12 0x18
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#define DESC92C_RATEMCS13 0x19
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#define DESC92C_RATEMCS14 0x1a
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#define DESC92C_RATEMCS15 0x1b
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#define DESC92C_RATEMCS15_SG 0x1c
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#define DESC92C_RATEMCS32 0x20
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//============================================================
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// structure and define
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//============================================================
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typedef struct _Phy_Rx_AGC_Info
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{
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#ifdef __LITTLE_ENDIAN
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u1Byte gain:7,trsw:1;
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#else
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u1Byte trsw:1,gain:7;
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#endif
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} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
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typedef struct _Phy_Status_Rpt_8192cd
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{
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PHY_RX_AGC_INFO_T path_agc[2];
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u1Byte ch_corr[2];
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u1Byte cck_sig_qual_ofdm_pwdb_all;
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u1Byte cck_agc_rpt_ofdm_cfosho_a;
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u1Byte cck_rpt_b_ofdm_cfosho_b;
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u1Byte rsvd_1;//ch_corr_msb;
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u1Byte noise_power_db_msb;
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u1Byte path_cfotail[2];
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u1Byte pcts_mask[2];
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s1Byte stream_rxevm[2];
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u1Byte path_rxsnr[2];
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u1Byte noise_power_db_lsb;
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u1Byte rsvd_2[3];
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u1Byte stream_csi[2];
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u1Byte stream_target_csi[2];
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s1Byte sig_evm;
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u1Byte rsvd_3;
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#ifdef __LITTLE_ENDIAN
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u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
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u1Byte sgi_en:1;
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u1Byte rxsc:2;
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u1Byte idle_long:1;
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u1Byte r_ant_train_en:1;
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u1Byte ant_sel_b:1;
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u1Byte ant_sel:1;
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#else // _BIG_ENDIAN_
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u1Byte ant_sel:1;
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u1Byte ant_sel_b:1;
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u1Byte r_ant_train_en:1;
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u1Byte idle_long:1;
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u1Byte rxsc:2;
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u1Byte sgi_en:1;
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u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
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#endif
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} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
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typedef struct _Phy_Status_Rpt_8195
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{
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PHY_RX_AGC_INFO_T path_agc[2];
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u1Byte ch_num[2];
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u1Byte cck_sig_qual_ofdm_pwdb_all;
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u1Byte cck_agc_rpt_ofdm_cfosho_a;
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u1Byte cck_bb_pwr_ofdm_cfosho_b;
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u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
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u1Byte rsvd_1;
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u1Byte path_cfotail[2];
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u1Byte pcts_mask[2];
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s1Byte stream_rxevm[2];
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u1Byte path_rxsnr[2];
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u1Byte rsvd_2[2];
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u1Byte stream_snr[2];
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u1Byte stream_csi[2];
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u1Byte rsvd_3[2];
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s1Byte sig_evm;
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u1Byte rsvd_4;
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#ifdef __LITTLE_ENDIAN
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u1Byte antidx_anta:3;
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u1Byte antidx_antb:3;
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u1Byte rsvd_5:2;
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#else // __BIG_ENDIAN_
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u1Byte rsvd_5:2;
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u1Byte antidx_antb:3;
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u1Byte antidx_anta:3;
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#endif
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} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
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void
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odm_Init_RSSIForDM(
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PDM_ODM_T pDM_Odm
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);
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void
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ODM_PhyStatusQuery(
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PDM_ODM_T pDM_Odm,
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PODM_PHY_INFO_T pPhyInfo,
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pu1Byte pPhyStatus,
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PODM_PACKET_INFO_T pPktinfo
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);
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void
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ODM_MacStatusQuery(
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PDM_ODM_T pDM_Odm,
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pu1Byte pMacStatus,
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u1Byte MacID,
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bool bPacketMatchBSSID,
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bool bPacketToSelf,
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bool bPacketBeacon
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);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP))
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HAL_STATUS
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ODM_ConfigRFWithHeaderFile(
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PDM_ODM_T pDM_Odm,
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ODM_RF_RADIO_PATH_E Content,
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ODM_RF_RADIO_PATH_E eRFPath
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);
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HAL_STATUS
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ODM_ConfigBBWithHeaderFile(
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PDM_ODM_T pDM_Odm,
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ODM_BB_Config_Type ConfigType
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);
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HAL_STATUS
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ODM_ConfigMACWithHeaderFile(
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PDM_ODM_T pDM_Odm
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);
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#endif
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#endif
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