mirror of
https://github.com/lwfinger/rtl8188eu.git
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342 lines
14 KiB
C
342 lines
14 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HAL8188EPWRSEQ_H__
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#define __HAL8188EPWRSEQ_H__
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#include "pwrseqcmd.h"
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/*
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Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
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There are 6 HW Power States:
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0: POFF--Power Off
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1: PDN--Power Down
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2: CARDEMU--Card Emulation
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3: ACT--Active Mode
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4: LPS--Low Power State
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5: SUS--Suspend
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The transision from different states are defined below
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TRANS_CARDEMU_TO_ACT
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TRANS_ACT_TO_CARDEMU
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TRANS_CARDEMU_TO_SUS
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TRANS_SUS_TO_CARDEMU
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TRANS_CARDEMU_TO_PDN
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TRANS_ACT_TO_LPS
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TRANS_LPS_TO_ACT
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TRANS_END
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PWR SEQ Version: rtl8188E_PwrSeq_V09.h
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*/
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#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
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#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
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#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
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#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
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#define RTL8188E_TRANS_END_STEPS 1
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#define RTL8188E_TRANS_CARDEMU_TO_ACT \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
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* },
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* comment here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \
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/* wait till 0x04[17] = 1 power ready*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
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/* 0x02[1:0] = 0 reset BB*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \
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/* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \
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/*0x04[12:11] = 2b'00 disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \
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/*0x04[8] = 1 polling until return 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \
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/*wait till 0x04[8] = 0*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
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/*LDO normal mode*/ \
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{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
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/*SDIO Driving*/
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#define RTL8188E_TRANS_ACT_TO_CARDEMU \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
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* },
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* comments here
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*/ \
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{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
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/*0x1F[7:0] = 0 turn off RF*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
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/*LDO Sleep mode*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
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/*0x04[9] = 1 turn off MAC by HW state machine*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \
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/*wait till 0x04[9] = 0 polling until return 0 to disable*/
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#define RTL8188E_TRANS_CARDEMU_TO_SUS \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
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/* 0x04[12:11] = 2b'01enable WL suspend */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \
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/* 0x04[12:11] = 2b'11enable WL suspend for PCIe */ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, 0xFF, BIT7}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT4, 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT4, BIT4}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
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/*wait power state to suspend*/
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#define RTL8188E_TRANS_SUS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
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/*wait power state to suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
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/*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, 0xFF, 0}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT4, 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
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/*wait power state to suspend*/
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#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
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/*wait power state to suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_PDN \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
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/* 0x04[16] = 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
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/* 0x04[15] = 1*/
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#define RTL8188E_TRANS_PDN_TO_CARDEMU \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \
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/* 0x04[15] = 0*/
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/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
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#define RTL8188E_TRANS_ACT_TO_LPS \
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/* format
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* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
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/*CCK and OFDM are disabled,and clock are gated*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \
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PWRSEQ_DELAY_US},/*Delay 1us*/ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||
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|
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\
|
||
|
|
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \
|
||
|
|
/*Respond TxOK to scheduler*/
|
||
|
|
|
||
|
|
|
||
|
|
#define RTL8188E_TRANS_LPS_TO_ACT \
|
||
|
|
/* format
|
||
|
|
* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
|
||
|
|
* value },
|
||
|
|
* comments here
|
||
|
|
*/ \
|
||
|
|
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
|
||
|
|
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
|
||
|
|
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
|
||
|
|
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
|
||
|
|
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
|
||
|
|
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
|
||
|
|
/* 0x08[4] = 0 switch TSF to 40M */ \
|
||
|
|
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, \
|
||
|
|
/* Polling 0x109[7]=0 TSF in 40M */ \
|
||
|
|
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, \
|
||
|
|
/* 0x29[7:6] = 2b'00 enable BB clock */ \
|
||
|
|
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
|
||
|
|
/* 0x101[1] = 1 */ \
|
||
|
|
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
|
||
|
|
/* 0x100[7:0] = 0xFF enable WMAC TRX */ \
|
||
|
|
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \
|
||
|
|
/* 0x02[1:0] = 2b'11 enable BB macro */ \
|
||
|
|
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
|
||
|
|
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||
|
|
|
||
|
|
#define RTL8188E_TRANS_END \
|
||
|
|
/* format
|
||
|
|
* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
|
||
|
|
* value },
|
||
|
|
* comments here
|
||
|
|
*/ \
|
||
|
|
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
|
||
|
|
PWR_CMD_END, 0, 0},
|
||
|
|
|
||
|
|
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_power_on_flow
|
||
|
|
[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_radio_off_flow
|
||
|
|
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_card_disable_flow
|
||
|
|
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||
|
|
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||
|
|
RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_card_enable_flow
|
||
|
|
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||
|
|
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
|
||
|
|
RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_suspend_flow[
|
||
|
|
RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||
|
|
RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
|
||
|
|
RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_resume_flow
|
||
|
|
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||
|
|
RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
|
||
|
|
RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_hwpdn_flow
|
||
|
|
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
|
||
|
|
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_enter_lps_flow
|
||
|
|
[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
|
||
|
|
extern struct wl_pwr_cfg rtl8188E_leave_lps_flow
|
||
|
|
[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
|
||
|
|
|
||
|
|
#endif /* __HAL8188EPWRSEQ_H__ */
|