2013-05-08 21:45:39 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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2013-05-19 04:28:07 +00:00
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*
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2013-05-08 21:45:39 +00:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#include <osdep_service.h>
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#include <drv_types.h>
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#include <hal_intf.h>
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#include <hal_com.h>
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#include <rtl8188e_hal.h>
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#define _HAL_INIT_C_
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2013-07-22 22:43:38 +00:00
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void dump_chip_info(struct HAL_VERSION ChipVersion)
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2013-05-08 21:45:39 +00:00
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{
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2013-05-27 22:32:24 +00:00
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uint cnt = 0;
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char buf[128];
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2013-05-08 21:45:39 +00:00
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2013-05-09 04:04:25 +00:00
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if (IS_81XXC(ChipVersion)){
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2013-05-08 21:45:39 +00:00
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cnt += sprintf((buf+cnt), "Chip Version Info: %s_", IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
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2013-05-26 17:17:22 +00:00
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} else if (IS_92D(ChipVersion)){
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2013-05-08 21:45:39 +00:00
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cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192D_");
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2013-05-26 17:17:22 +00:00
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} else if (IS_8723_SERIES(ChipVersion)){
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2013-05-08 21:45:39 +00:00
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cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723A_");
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2013-05-26 17:17:22 +00:00
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} else if (IS_8188E(ChipVersion)){
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2013-05-08 21:45:39 +00:00
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cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_");
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}
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cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
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cnt += sprintf((buf+cnt), "%s_", IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC");
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2013-05-26 17:17:22 +00:00
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if (IS_A_CUT(ChipVersion))
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cnt += sprintf((buf+cnt), "A_CUT_");
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else if (IS_B_CUT(ChipVersion))
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cnt += sprintf((buf+cnt), "B_CUT_");
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else if (IS_C_CUT(ChipVersion))
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cnt += sprintf((buf+cnt), "C_CUT_");
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else if (IS_D_CUT(ChipVersion))
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cnt += sprintf((buf+cnt), "D_CUT_");
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else if (IS_E_CUT(ChipVersion))
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cnt += sprintf((buf+cnt), "E_CUT_");
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else
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cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
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2013-05-08 21:45:39 +00:00
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2013-05-26 17:17:22 +00:00
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if (IS_1T1R(ChipVersion))
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cnt += sprintf((buf+cnt), "1T1R_");
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else if (IS_1T2R(ChipVersion))
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cnt += sprintf((buf+cnt), "1T2R_");
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else if (IS_2T2R(ChipVersion))
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cnt += sprintf((buf+cnt), "2T2R_");
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else
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cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
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2013-05-08 21:45:39 +00:00
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cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
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2013-05-26 17:17:22 +00:00
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pr_info("%s", buf);
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2013-05-08 21:45:39 +00:00
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}
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#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
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2013-07-10 18:25:07 +00:00
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u8 /* return the final channel plan decision */
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2013-05-08 21:45:39 +00:00
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hal_com_get_channel_plan(
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2013-07-27 01:08:39 +00:00
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struct adapter * padapter,
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2013-07-10 18:25:07 +00:00
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u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */
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u8 sw_channel_plan, /* channel plan from SW (registry/module param) */
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u8 def_channel_plan, /* channel plan used when the former two is invalid */
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2013-05-25 20:45:50 +00:00
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bool AutoLoadFail
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2013-05-08 21:45:39 +00:00
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)
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{
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u8 swConfig;
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u8 chnlPlan;
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2013-05-26 03:02:10 +00:00
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swConfig = true;
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2013-05-08 21:45:39 +00:00
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if (!AutoLoadFail)
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{
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if (!rtw_is_channel_plan_valid(sw_channel_plan))
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2013-05-26 03:02:10 +00:00
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swConfig = false;
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2013-05-08 21:45:39 +00:00
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if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
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2013-05-26 03:02:10 +00:00
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swConfig = false;
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2013-05-08 21:45:39 +00:00
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}
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2013-05-26 03:02:10 +00:00
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if (swConfig == true)
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2013-05-08 21:45:39 +00:00
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chnlPlan = sw_channel_plan;
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else
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chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
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if (!rtw_is_channel_plan_valid(chnlPlan))
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chnlPlan = def_channel_plan;
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return chnlPlan;
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}
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u8 MRateToHwRate(u8 rate)
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{
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u8 ret = DESC_RATE1M;
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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switch (rate) {
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/* CCK and OFDM non-HT rates */
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case IEEE80211_CCK_RATE_1MB:
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ret = DESC_RATE1M;
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break;
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case IEEE80211_CCK_RATE_2MB:
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ret = DESC_RATE2M;
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break;
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case IEEE80211_CCK_RATE_5MB:
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ret = DESC_RATE5_5M;
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break;
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case IEEE80211_CCK_RATE_11MB:
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ret = DESC_RATE11M;
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break;
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case IEEE80211_OFDM_RATE_6MB:
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ret = DESC_RATE6M;
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break;
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case IEEE80211_OFDM_RATE_9MB:
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ret = DESC_RATE9M;
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break;
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case IEEE80211_OFDM_RATE_12MB:
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ret = DESC_RATE12M;
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break;
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case IEEE80211_OFDM_RATE_18MB:
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ret = DESC_RATE18M;
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break;
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case IEEE80211_OFDM_RATE_24MB:
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ret = DESC_RATE24M;
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break;
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case IEEE80211_OFDM_RATE_36MB:
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ret = DESC_RATE36M;
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break;
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case IEEE80211_OFDM_RATE_48MB:
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ret = DESC_RATE48M;
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break;
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case IEEE80211_OFDM_RATE_54MB:
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ret = DESC_RATE54M;
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break;
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default:
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break;
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2013-05-08 21:45:39 +00:00
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}
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return ret;
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}
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void HalSetBrateCfg(
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2013-07-27 01:08:39 +00:00
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struct adapter * Adapter,
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2013-05-27 03:51:56 +00:00
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u8 *mBratesOS,
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u16 *pBrateCfg)
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2013-05-08 21:45:39 +00:00
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{
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u8 i, is_brate, brate;
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2013-05-27 03:51:56 +00:00
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for (i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++) {
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2013-05-08 21:45:39 +00:00
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is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
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brate = mBratesOS[i] & 0x7f;
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2013-05-19 04:28:07 +00:00
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2013-05-27 03:51:56 +00:00
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if ( is_brate ) {
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switch (brate) {
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case IEEE80211_CCK_RATE_1MB:
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*pBrateCfg |= RATE_1M;
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break;
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case IEEE80211_CCK_RATE_2MB:
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*pBrateCfg |= RATE_2M;
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break;
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case IEEE80211_CCK_RATE_5MB:
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*pBrateCfg |= RATE_5_5M;
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break;
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case IEEE80211_CCK_RATE_11MB:
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*pBrateCfg |= RATE_11M;
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break;
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case IEEE80211_OFDM_RATE_6MB:
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*pBrateCfg |= RATE_6M;
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break;
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case IEEE80211_OFDM_RATE_9MB:
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*pBrateCfg |= RATE_9M;
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break;
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case IEEE80211_OFDM_RATE_12MB:
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*pBrateCfg |= RATE_12M;
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break;
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case IEEE80211_OFDM_RATE_18MB:
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*pBrateCfg |= RATE_18M;
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break;
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case IEEE80211_OFDM_RATE_24MB:
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*pBrateCfg |= RATE_24M;
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break;
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case IEEE80211_OFDM_RATE_36MB:
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*pBrateCfg |= RATE_36M;
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break;
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case IEEE80211_OFDM_RATE_48MB:
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*pBrateCfg |= RATE_48M;
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break;
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case IEEE80211_OFDM_RATE_54MB:
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*pBrateCfg |= RATE_54M;
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break;
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2013-05-08 21:45:39 +00:00
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}
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}
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}
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}
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2013-07-27 01:08:39 +00:00
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static void _OneOutPipeMapping(struct adapter * pAdapter)
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2013-05-08 21:45:39 +00:00
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{
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struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
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pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
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pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
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pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
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pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
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pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
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pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
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2013-05-08 21:45:39 +00:00
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}
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2013-07-27 01:08:39 +00:00
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static void _TwoOutPipeMapping(struct adapter * pAdapter, bool bWIFICfg)
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2013-05-08 21:45:39 +00:00
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{
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struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
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2013-07-10 18:25:07 +00:00
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if (bWIFICfg){ /* WMM */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
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/* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
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/* 0:H, 1:L */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
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pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
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pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
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pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
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pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
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pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
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pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
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2013-05-19 04:28:07 +00:00
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2013-05-08 21:45:39 +00:00
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}
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2013-07-10 18:25:07 +00:00
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else{/* typical setting */
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2013-05-08 21:45:39 +00:00
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
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/* 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */
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/* 0:H, 1:L */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
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pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
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pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
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pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
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pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
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pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
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pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
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2013-05-19 04:28:07 +00:00
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2013-05-08 21:45:39 +00:00
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}
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2013-05-19 04:28:07 +00:00
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2013-05-08 21:45:39 +00:00
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}
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2013-05-19 04:37:45 +00:00
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static void _ThreeOutPipeMapping(
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2013-07-27 01:08:39 +00:00
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struct adapter * pAdapter,
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2013-05-25 20:45:50 +00:00
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bool bWIFICfg
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2013-05-08 21:45:39 +00:00
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)
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{
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struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
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2013-07-10 18:25:07 +00:00
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if (bWIFICfg){/* for WMM */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
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/* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
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/* 0:H, 1:N, 2:L */
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
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pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
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pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
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pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
|
2013-05-08 21:45:39 +00:00
|
|
|
|
2013-07-10 18:25:07 +00:00
|
|
|
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
|
|
|
|
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
|
|
|
|
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
|
|
|
|
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
|
2013-05-19 04:28:07 +00:00
|
|
|
|
2013-07-10 18:25:07 +00:00
|
|
|
} else {/* typical setting */
|
|
|
|
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
|
|
|
|
/* 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
|
|
|
|
/* 0:H, 1:N, 2:L */
|
2013-05-19 04:28:07 +00:00
|
|
|
|
2013-07-10 18:25:07 +00:00
|
|
|
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
|
|
|
|
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
|
|
|
|
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
|
|
|
|
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
|
2013-05-19 04:28:07 +00:00
|
|
|
|
2013-07-10 18:25:07 +00:00
|
|
|
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
|
|
|
|
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
|
|
|
|
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
|
|
|
|
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
|
2013-05-08 21:45:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2013-05-19 04:48:10 +00:00
|
|
|
bool
|
2013-05-08 21:45:39 +00:00
|
|
|
Hal_MappingOutPipe(
|
2013-07-27 01:08:39 +00:00
|
|
|
struct adapter * pAdapter,
|
2013-05-25 20:45:50 +00:00
|
|
|
u8 NumOutPipe
|
2013-05-08 21:45:39 +00:00
|
|
|
)
|
|
|
|
{
|
|
|
|
struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
|
|
|
|
|
2013-05-26 03:02:10 +00:00
|
|
|
bool bWIFICfg = (pregistrypriv->wifi_spec) ?true:false;
|
2013-05-19 04:28:07 +00:00
|
|
|
|
2013-05-26 03:02:10 +00:00
|
|
|
bool result = true;
|
2013-05-08 21:45:39 +00:00
|
|
|
|
2013-05-09 04:04:25 +00:00
|
|
|
switch (NumOutPipe)
|
2013-05-08 21:45:39 +00:00
|
|
|
{
|
|
|
|
case 2:
|
|
|
|
_TwoOutPipeMapping(pAdapter, bWIFICfg);
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
_ThreeOutPipeMapping(pAdapter, bWIFICfg);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
_OneOutPipeMapping(pAdapter);
|
|
|
|
break;
|
|
|
|
default:
|
2013-05-26 03:02:10 +00:00
|
|
|
result = false;
|
2013-05-08 21:45:39 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
2013-05-19 04:28:07 +00:00
|
|
|
|
2013-05-08 21:45:39 +00:00
|
|
|
}
|
|
|
|
|
2013-07-27 01:08:39 +00:00
|
|
|
void hal_init_macaddr(struct adapter *adapter)
|
2013-05-08 21:45:39 +00:00
|
|
|
{
|
|
|
|
rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
|
|
|
|
}
|
|
|
|
|
2013-05-19 04:28:07 +00:00
|
|
|
/*
|
2013-05-08 21:45:39 +00:00
|
|
|
* C2H event format:
|
2013-05-19 04:28:07 +00:00
|
|
|
* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
|
|
|
|
* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
|
2013-05-08 21:45:39 +00:00
|
|
|
*/
|
|
|
|
|
2013-07-27 01:08:39 +00:00
|
|
|
void c2h_evt_clear(struct adapter *adapter)
|
2013-05-08 21:45:39 +00:00
|
|
|
{
|
|
|
|
rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
|
|
|
|
}
|
|
|
|
|
2013-07-27 01:08:39 +00:00
|
|
|
s32 c2h_evt_read(struct adapter *adapter, u8 *buf)
|
2013-05-08 21:45:39 +00:00
|
|
|
{
|
|
|
|
s32 ret = _FAIL;
|
|
|
|
struct c2h_evt_hdr *c2h_evt;
|
|
|
|
int i;
|
|
|
|
u8 trigger;
|
|
|
|
|
|
|
|
if (buf == NULL)
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
|
|
|
|
|
|
|
|
if (trigger == C2H_EVT_HOST_CLOSE) {
|
|
|
|
goto exit; /* Not ready */
|
|
|
|
} else if (trigger != C2H_EVT_FW_CLOSE) {
|
|
|
|
goto clear_evt; /* Not a valid value */
|
|
|
|
}
|
|
|
|
|
|
|
|
c2h_evt = (struct c2h_evt_hdr *)buf;
|
|
|
|
|
|
|
|
_rtw_memset(c2h_evt, 0, 16);
|
|
|
|
|
|
|
|
*buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
|
2013-05-19 04:28:07 +00:00
|
|
|
*(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
|
2013-05-08 21:45:39 +00:00
|
|
|
|
|
|
|
RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ",
|
|
|
|
&c2h_evt , sizeof(c2h_evt));
|
|
|
|
|
|
|
|
if (0) {
|
2013-05-25 23:35:42 +00:00
|
|
|
DBG_88E("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
|
2013-05-08 21:45:39 +00:00
|
|
|
, c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read the content */
|
|
|
|
for (i = 0; i < c2h_evt->plen; i++)
|
|
|
|
c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + sizeof(*c2h_evt) + i);
|
|
|
|
|
|
|
|
RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
|
|
|
|
c2h_evt->payload, c2h_evt->plen);
|
|
|
|
|
|
|
|
ret = _SUCCESS;
|
|
|
|
|
|
|
|
clear_evt:
|
2013-05-19 04:28:07 +00:00
|
|
|
/*
|
2013-05-08 21:45:39 +00:00
|
|
|
* Clear event to notify FW we have read the command.
|
|
|
|
* If this field isn't clear, the FW won't update the next command message.
|
|
|
|
*/
|
|
|
|
c2h_evt_clear(adapter);
|
|
|
|
exit:
|
|
|
|
return ret;
|
|
|
|
}
|