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rtl8188eu: Remove code for chips other than RTL8188EU

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2014-12-30 14:52:15 -06:00
parent 3a518f1886
commit 007b33ebde
13 changed files with 11 additions and 1008 deletions
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5
hal/HalHWImg8188E_BB.c
View file

@ -24,7 +24,6 @@
#include <rtw_iol.h> #include <rtw_iol.h>
#endif #endif
#if (RTL8188E_SUPPORT == 1)
static BOOLEAN static BOOLEAN
CheckCondition( CheckCondition(
const u4Byte Condition, const u4Byte Condition,
@ -1441,7 +1440,3 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
} }
} }
#endif // end of HWIMG_SUPPORT

3
hal/HalHWImg8188E_BB.h
View file

@ -18,7 +18,6 @@
* *
******************************************************************************/ ******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_BB_8188E_HW_IMG_H #ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H #define __INC_BB_8188E_HW_IMG_H
@ -66,6 +65,4 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm IN PDM_ODM_T pDM_Odm
); );
#endif
#endif // end of HWIMG_SUPPORT #endif // end of HWIMG_SUPPORT

3
hal/HalHWImg8188E_MAC.c
View file

@ -22,7 +22,6 @@
#ifdef CONFIG_IOL_IOREG_CFG #ifdef CONFIG_IOL_IOREG_CFG
#include <rtw_iol.h> #include <rtw_iol.h>
#endif #endif
#if (RTL8188E_SUPPORT == 1)
static BOOLEAN static BOOLEAN
CheckCondition( CheckCondition(
const u4Byte Condition, const u4Byte Condition,
@ -497,5 +496,3 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
} }
} }
#endif // end of HWIMG_SUPPORT

3
hal/HalHWImg8188E_MAC.h
View file

@ -18,7 +18,6 @@
* *
******************************************************************************/ ******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MAC_8188E_HW_IMG_H #ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H #define __INC_MAC_8188E_HW_IMG_H
@ -43,5 +42,3 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E( // TC: Test Chip, MP: MP Chip
); );
#endif #endif
#endif // end of HWIMG_SUPPORT

4
hal/HalHWImg8188E_RF.c
View file

@ -24,7 +24,6 @@
#include <rtw_iol.h> #include <rtw_iol.h>
#endif #endif
#if (RTL8188E_SUPPORT == 1)
static BOOLEAN static BOOLEAN
CheckCondition( CheckCondition(
const u4Byte Condition, const u4Byte Condition,
@ -563,6 +562,3 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
} }
} }
#endif // end of HWIMG_SUPPORT

4
hal/HalHWImg8188E_RF.h
View file

@ -18,7 +18,6 @@
* *
******************************************************************************/ ******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_RF_8188E_HW_IMG_H #ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H #define __INC_RF_8188E_HW_IMG_H
@ -40,6 +39,5 @@ void
ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
IN PDM_ODM_T pDM_Odm IN PDM_ODM_T pDM_Odm
); );
#endif
#endif // end of HWIMG_SUPPORT
#endif

823
hal/odm.c
View file

File diff suppressed because it is too large Load diff

59
hal/odm_HWConfig.c
View file

@ -630,21 +630,7 @@ odm_Process_RSSIForDM(
pDM_Odm->RxRate = pPktinfo->Rate; pDM_Odm->RxRate = pPktinfo->Rate;
#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))
if(pDM_Odm->SupportICType & ODM_RTL8192C|ODM_RTL8192D)
{
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
//if(pPktinfo->bPacketBeacon)
//{
// DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate);
//}
ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID, pPhyInfo->RxPWDBAll, isCCKrate);
}
}
#endif
//-----------------Smart Antenna Debug Message------------------// //-----------------Smart Antenna Debug Message------------------//
#if (RTL8188E_SUPPORT == 1)
if(pDM_Odm->SupportICType == ODM_RTL8188E) if(pDM_Odm->SupportICType == ODM_RTL8188E)
{ {
u1Byte antsel_tr_mux; u1Byte antsel_tr_mux;
@ -679,7 +665,6 @@ odm_Process_RSSIForDM(
} }
} }
#endif
#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) #endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
//-----------------Smart Antenna Debug Message------------------// //-----------------Smart Antenna Debug Message------------------//
@ -896,20 +881,6 @@ ODM_ConfigRFWithHeaderFile(
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
#if (RTL8723A_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8723A)
{
if(eRFPath == ODM_RF_PATH_A)
READ_AND_CONFIG_MP(8723A,_RadioA_1T_);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8723RadioA_1TArray\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8723RadioB_1TArray\n"));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath));
//rtStatus = RT_STATUS_SUCCESS;
#endif
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E) if (pDM_Odm->SupportICType == ODM_RTL8188E)
{ {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter)) if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
@ -924,7 +895,6 @@ ODM_ConfigRFWithHeaderFile(
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath));
//rtStatus = RT_STATUS_SUCCESS; //rtStatus = RT_STATUS_SUCCESS;
#endif
return HAL_STATUS_SUCCESS; return HAL_STATUS_SUCCESS;
} }
@ -935,24 +905,6 @@ ODM_ConfigBBWithHeaderFile(
IN ODM_BB_Config_Type ConfigType IN ODM_BB_Config_Type ConfigType
) )
{ {
#if (RTL8723A_SUPPORT == 1)
if(pDM_Odm->SupportICType == ODM_RTL8723A)
{
if(ConfigType == CONFIG_BB_PHY_REG)
{
READ_AND_CONFIG_MP(8723A,_PHY_REG_1T_);
}
else if(ConfigType == CONFIG_BB_AGC_TAB)
{
READ_AND_CONFIG_MP(8723A,_AGC_TAB_1T_);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n"));
}
#endif
#if (RTL8188E_SUPPORT == 1)
if(pDM_Odm->SupportICType == ODM_RTL8188E) if(pDM_Odm->SupportICType == ODM_RTL8188E)
{ {
@ -976,8 +928,6 @@ ODM_ConfigBBWithHeaderFile(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n")); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n"));
} }
} }
#endif
return HAL_STATUS_SUCCESS; return HAL_STATUS_SUCCESS;
} }
@ -987,13 +937,6 @@ ODM_ConfigMACWithHeaderFile(
) )
{ {
u1Byte result = HAL_STATUS_SUCCESS; u1Byte result = HAL_STATUS_SUCCESS;
#if (RTL8723A_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8723A)
{
READ_AND_CONFIG_MP(8723A,_MAC_REG_);
}
#endif
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E) if (pDM_Odm->SupportICType == ODM_RTL8188E)
{ {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter)) if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
@ -1001,7 +944,5 @@ ODM_ConfigMACWithHeaderFile(
else else
result =READ_AND_CONFIG(8188E,_MAC_REG_); result =READ_AND_CONFIG(8188E,_MAC_REG_);
} }
#endif
return result; return result;
} }

26
hal/odm_RTL8188E.c
View file

@ -24,8 +24,6 @@
#include "odm_precomp.h" #include "odm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void void
ODM_DIG_LowerBound_88E( ODM_DIG_LowerBound_88E(
IN PDM_ODM_T pDM_Odm IN PDM_ODM_T pDM_Odm
@ -611,27 +609,3 @@ odm_DynamicPrimaryCCA(
return; return;
} }
#else //#if (RTL8188E_SUPPORT == 1)
void
ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
{
}
void
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm)
{
}
void
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm
)
{
}
BOOLEAN
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm
)
{
return FALSE;
}
#endif //#if (RTL8188E_SUPPORT == 1)

3
hal/odm_RegConfig8188E.c
View file

@ -20,8 +20,6 @@
#include "odm_precomp.h" #include "odm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void void
odm_ConfigRFReg_8188E( odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm, IN PDM_ODM_T pDM_Odm,
@ -197,4 +195,3 @@ odm_ConfigBB_PHY_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
} }
} }
#endif

4
hal/odm_RegConfig8188E.h
View file

@ -20,8 +20,6 @@
#ifndef __INC_ODM_REGCONFIG_H_8188E #ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E #define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void void
odm_ConfigRFReg_8188E( odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm, IN PDM_ODM_T pDM_Odm,
@ -75,6 +73,6 @@ odm_ConfigBB_PHY_8188E(
IN u4Byte Bitmask, IN u4Byte Bitmask,
IN u4Byte Data IN u4Byte Data
); );
#endif
#endif // end of SUPPORT #endif // end of SUPPORT

48
hal/odm_precomp.h
View file

@ -36,29 +36,7 @@
//2 Hardware Parameter Files //2 Hardware Parameter Files
#if(RTL8192CE_SUPPORT ==1) #include "Hal8188EFWImg_CE.h"
#include "rtl8192c/Hal8192CEFWImg_CE.h"
#include "rtl8192c/Hal8192CEPHYImg_CE.h"
#include "rtl8192c/Hal8192CEMACImg_CE.h"
#elif(RTL8192CU_SUPPORT ==1)
#include "rtl8192c/Hal8192CUFWImg_CE.h"
#include "rtl8192c/Hal8192CUPHYImg_CE.h"
#include "rtl8192c/Hal8192CUMACImg_CE.h"
#elif(RTL8192DE_SUPPORT ==1)
#include "rtl8192d/Hal8192DEFWImg_CE.h"
#include "rtl8192d/Hal8192DEPHYImg_CE.h"
#include "rtl8192d/Hal8192DEMACImg_CE.h"
#elif(RTL8192DU_SUPPORT ==1)
#include "rtl8192d/Hal8192DUFWImg_CE.h"
#include "rtl8192d/Hal8192DUPHYImg_CE.h"
#include "rtl8192d/Hal8192DUMACImg_CE.h"
#elif(RTL8723AS_SUPPORT==1)
#include "rtl8723a/Hal8723SHWImg_CE.h"
#elif(RTL8723AU_SUPPORT==1)
#include "rtl8723a/Hal8723UHWImg_CE.h"
#elif(RTL8188E_SUPPORT==1)
#include "Hal8188EFWImg_CE.h"
#endif
//2 OutSrc Header Files //2 OutSrc Header Files
@ -68,24 +46,10 @@
#include "odm_RegDefine11AC.h" #include "odm_RegDefine11AC.h"
#include "odm_RegDefine11N.h" #include "odm_RegDefine11N.h"
#include "HalPhyRf.h" #include "HalPhyRf.h"
#if (RTL8192C_SUPPORT==1) #include "HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#ifdef CONFIG_INTEL_PROXIM #include "Hal8188ERateAdaptive.h"//for RA,Power training
#include "../proxim/intel_proxim.h" #include "rtl8188e_hal.h"
#endif
#include "rtl8192c/HalDMOutSrc8192C_CE.h"
#include <rtl8192c_hal.h>
#elif (RTL8192D_SUPPORT==1)
#include "rtl8192d/HalDMOutSrc8192D_CE.h"
#include "rtl8192d_hal.h"
#elif (RTL8723A_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
#include "rtl8723a_hal.h"
#elif (RTL8188E_SUPPORT==1)
#include "HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e_hal.h"
#endif
#include "odm_interface.h" #include "odm_interface.h"
#include "odm_reg.h" #include "odm_reg.h"
@ -102,9 +66,7 @@
#endif #endif
#ifdef CONFIG_WOWLAN #ifdef CONFIG_WOWLAN
#if (RTL8188E_SUPPORT==1)
#include "HalHWImg8188E_FW.h" #include "HalHWImg8188E_FW.h"
#endif
#endif //CONFIG_WOWLAN #endif //CONFIG_WOWLAN
#include "odm_RegConfig8188E.h" #include "odm_RegConfig8188E.h"

30
hal/rtl8188e_phycfg.c
View file

@ -147,9 +147,7 @@ sic_Read4Byte(
) )
{ {
u32 u4ret=0xffffffff; u32 u4ret=0xffffffff;
#if RTL8188E_SUPPORT == 1
u8 retry = 0; u8 retry = 0;
#endif
//RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset)); //RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset));
@ -170,17 +168,11 @@ sic_Read4Byte(
//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ); //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ);
//RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ)); //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ));
#if RTL8188E_SUPPORT == 1
retry = 4; retry = 4;
while(retry--){ while(retry--){
rtw_udelay_os(50); rtw_udelay_os(50);
//PlatformStallExecution(50); //PlatformStallExecution(50);
} }
#else
rtw_udelay_os(200);
//PlatformStallExecution(200);
#endif
if(sic_IsSICReady(Adapter)) if(sic_IsSICReady(Adapter))
{ {
u4ret = rtw_read32(Adapter, SIC_DATA_REG); u4ret = rtw_read32(Adapter, SIC_DATA_REG);
@ -200,40 +192,20 @@ sic_Write4Byte(
u32 data u32 data
) )
{ {
#if RTL8188E_SUPPORT == 1
u8 retry = 6; u8 retry = 6;
#endif
//DbgPrint("=>Write 0x%x = 0x%x\n", offset, data);
//RTPRINT(FPHY, PHY_SICW, ("[SIC], sic_Write4Byte(): write offset(%#x)=0x%x\n", offset, data));
if(sic_IsSICReady(Adapter)) if(sic_IsSICReady(Adapter))
{ {
#if(SIC_HW_SUPPORT == 1) #if(SIC_HW_SUPPORT == 1)
rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE); rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);
//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);
//RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREWRITE));
#endif #endif
rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));
//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));
//RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));
rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));
//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));
//RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", (SIC_ADDR_REG+1), (u1Byte)((offset&0xff00)>>8)));
rtw_write32(Adapter, SIC_DATA_REG, (u32)data); rtw_write32(Adapter, SIC_DATA_REG, (u32)data);
//PlatformEFIOWrite4Byte(Adapter, SIC_DATA_REG, (u4Byte)data);
//RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_DATA_REG, data));
rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE); rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);
//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);
//RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_WRITE));
#if RTL8188E_SUPPORT == 1
while(retry--){ while(retry--){
rtw_udelay_os(50); rtw_udelay_os(50);
//PlatformStallExecution(50);
} }
#else
rtw_udelay_os(150);
//PlatformStallExecution(150);
#endif
} }
} }
//============================================================ //============================================================