rtl8188eu: Place driver rtl8188EUS_rtl8189ES_linux_v4.1.8_9499.20131104 in branch v4.1.8_9499

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>

Makefile

@@ -1,5 +1,11 @@
 EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
 EXTRA_CFLAGS += -O1
+#EXTRA_CFLAGS += -O3
+#EXTRA_CFLAGS += -Wall
+#EXTRA_CFLAGS += -Wextra
+#EXTRA_CFLAGS += -Werror
+#EXTRA_CFLAGS += -pedantic
+#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes
 
 EXTRA_CFLAGS += -Wno-unused-variable
 EXTRA_CFLAGS += -Wno-unused-value
@@ -12,129 +18,791 @@ EXTRA_CFLAGS += -Wno-uninitialized
 
 EXTRA_CFLAGS += -I$(src)/include
 
-ccflags-y += -D__CHECK_ENDIAN__
+CONFIG_AUTOCFG_CP = y
-
-CONFIG_AUTOCFG_CP = n
 
+CONFIG_RTL8192C = n
+CONFIG_RTL8192D = n
+CONFIG_RTL8723A = n
 CONFIG_RTL8188E = y
 
 CONFIG_USB_HCI = y
+CONFIG_PCI_HCI = n
+CONFIG_SDIO_HCI = n
+CONFIG_GSPI_HCI = n
 
+CONFIG_MP_INCLUDED = y
+CONFIG_POWER_SAVING = y
+CONFIG_USB_AUTOSUSPEND = n
+CONFIG_HW_PWRP_DETECTION = n
+CONFIG_WIFI_TEST = n
 CONFIG_BT_COEXIST = n
+CONFIG_RTL8192CU_REDEFINE_1X1 = n
+CONFIG_INTEL_WIDI = n
+CONFIG_WAPI_SUPPORT = n
+CONFIG_EFUSE_CONFIG_FILE = n
+CONFIG_EXT_CLK = n
+CONFIG_FTP_PROTECT = n
 CONFIG_WOWLAN = n
+CONFIG_GPIO_WAKEUP = n
+CONFIG_ODM_ADAPTIVITY = n
+CONFIG_MMC_PM_KEEP_POWER = n
+
+CONFIG_PLATFORM_I386_PC = y
+CONFIG_PLATFORM_ANDROID_X86 = n
+CONFIG_PLATFORM_JB_X86 = n
+CONFIG_PLATFORM_ARM_S3C2K4 = n
+CONFIG_PLATFORM_ARM_PXA2XX = n
+CONFIG_PLATFORM_ARM_S3C6K4 = n
+CONFIG_PLATFORM_MIPS_RMI = n
+CONFIG_PLATFORM_RTD2880B = n
+CONFIG_PLATFORM_MIPS_AR9132 = n
+CONFIG_PLATFORM_RTK_DMP = n
+CONFIG_PLATFORM_MIPS_PLM = n
+CONFIG_PLATFORM_MSTAR389 = n
+CONFIG_PLATFORM_MT53XX = n
+CONFIG_PLATFORM_ARM_MX51_241H = n
+CONFIG_PLATFORM_ACTIONS_ATJ227X = n
+CONFIG_PLATFORM_TEGRA3_CARDHU = n
+CONFIG_PLATFORM_TEGRA4_DALMORE = n
+CONFIG_PLATFORM_ARM_TCC8900 = n
+CONFIG_PLATFORM_ARM_TCC8920 = n
+CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
+CONFIG_PLATFORM_ARM_RK2818 = n
+CONFIG_PLATFORM_ARM_URBETTER = n
+CONFIG_PLATFORM_ARM_TI_PANDA = n
+CONFIG_PLATFORM_MIPS_JZ4760 = n
+CONFIG_PLATFORM_DMP_PHILIPS = n
+CONFIG_PLATFORM_TI_DM365 = n
+CONFIG_PLATFORM_MSTAR_TITANIA12 = n
+CONFIG_PLATFORM_MSTAR = n
+CONFIG_PLATFORM_SZEBOOK = n
+CONFIG_PLATFORM_ARM_SUNxI = n
+CONFIG_PLATFORM_ARM_SUN6I = n
+CONFIG_PLATFORM_ARM_SUN7I = n
+CONFIG_PLATFORM_ACTIONS_ATM702X = n
+CONFIG_PLATFORM_MN10300 = n
+CONFIG_PLATFORM_ACTIONS_ATV5201 = n
+
+CONFIG_DRVEXT_MODULE = n
 
 export TopDIR ?= $(shell pwd)
 
 
-OUTSRC_FILES :=				\
+OUTSRC_FILES := hal/OUTSRC/odm_debug.o	\
-		hal/HalHWImg8188E_MAC.o	\
+								hal/OUTSRC/odm_interface.o\
-		hal/HalHWImg8188E_BB.o	\
+								hal/OUTSRC/odm_HWConfig.o\
-		hal/HalHWImg8188E_RF.o	\
+								hal/OUTSRC/odm.o\
-		hal/HalPhyRf.o		\
+		hal/OUTSRC/HalPhyRf.o
-		hal/HalPhyRf_8188e.o	\
+										
-		hal/HalPwrSeqCmd.o	\
+ifeq ($(CONFIG_RTL8192C), y)
-		hal/Hal8188EPwrSeq.o	\
+RTL871X = rtl8192c
-		hal/Hal8188ERateAdaptive.o\
+
-		hal/hal_intf.o		\
+ifeq ($(CONFIG_USB_HCI), y)
-		hal/hal_com.o		\
+MODULE_NAME = 8192cu
-		hal/odm.o		\
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192CUFWImg_CE.o	\
-		hal/odm_debug.o		\
+								hal/OUTSRC/$(RTL871X)/Hal8192CUPHYImg_CE.o	\
-		hal/odm_interface.o	\
+								hal/OUTSRC/$(RTL871X)/Hal8192CUMACImg_CE.o
-		hal/odm_HWConfig.o	\
+endif
-		hal/odm_RegConfig8188E.o\
+
-		hal/odm_RTL8188E.o	\
+ifeq ($(CONFIG_PCI_HCI), y)
-		hal/rtl8188e_cmd.o	\
+MODULE_NAME = 8192ce
-		hal/rtl8188e_dm.o	\
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192CEFWImg_CE.o	\
-		hal/rtl8188e_hal_init.o	\
+								hal/OUTSRC/$(RTL871X)/Hal8192CEPHYImg_CE.o	\
-		hal/rtl8188e_mp.o	\
+								hal/OUTSRC/$(RTL871X)/Hal8192CEMACImg_CE.o
-		hal/rtl8188e_phycfg.o	\
+endif
-		hal/rtl8188e_rf6052.o	\
+
-		hal/rtl8188e_rxdesc.o	\
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/odm_RTL8192C.o\
-		hal/rtl8188e_sreset.o	\
+								hal/OUTSRC/$(RTL871X)/HalDMOutSrc8192C_CE.o
-		hal/rtl8188e_xmit.o	\
+
-		hal/rtl8188eu_led.o	\
+CHIP_FILES := \
-		hal/rtl8188eu_recv.o	\
+	hal/$(RTL871X)/$(RTL871X)_sreset.o \
-		hal/rtl8188eu_xmit.o	\
+	hal/$(RTL871X)/$(RTL871X)_xmit.o
-		hal/usb_halinit.o	\
+CHIP_FILES += $(OUTSRC_FILES)
-		hal/usb_ops_linux.o
+
+endif
+
+ifeq ($(CONFIG_RTL8192D), y)
+RTL871X = rtl8192d
+
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8192du
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192DUFWImg_CE.o \
+								hal/OUTSRC/$(RTL871X)/Hal8192DUPHYImg_CE.o \
+								hal/OUTSRC/$(RTL871X)/Hal8192DUMACImg_CE.o
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8192de
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8192DEFWImg_CE.o \
+								hal/OUTSRC/$(RTL871X)/Hal8192DEPHYImg_CE.o \
+								hal/OUTSRC/$(RTL871X)/Hal8192DEMACImg_CE.o
+endif
+
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/odm_RTL8192D.o\
+								hal/OUTSRC/$(RTL871X)/HalDMOutSrc8192D_CE.o
+CHIP_FILES := \
+	hal/$(RTL871X)/$(RTL871X)_xmit.o
+CHIP_FILES += $(OUTSRC_FILES)
+endif
+
+ifeq ($(CONFIG_RTL8723A), y)
+
+RTL871X = rtl8723a
+
+HAL_COMM_FILES := hal/$(RTL871X)/$(RTL871X)_xmit.o \
+								hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+ifeq ($(CONFIG_GSPI_HCI), y)
+MODULE_NAME = 8723as
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723SHWImg_CE.o
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8723as
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723SHWImg_CE.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8723au
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723UHWImg_CE.o
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8723ae
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/Hal8723EHWImg_CE.o
+endif
+
+#hal/OUTSRC/$(RTL871X)/HalHWImg8723A_FW.o
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/HalHWImg8723A_BB.o\
+								hal/OUTSRC/$(RTL871X)/HalHWImg8723A_MAC.o\
+								hal/OUTSRC/$(RTL871X)/HalHWImg8723A_RF.o\
+								hal/OUTSRC/$(RTL871X)/odm_RegConfig8723A.o
+
+OUTSRC_FILES += hal/OUTSRC/rtl8192c/HalDMOutSrc8192C_CE.o
+clean_more ?=
+clean_more += clean_odm-8192c
+
+PWRSEQ_FILES := hal/HalPwrSeqCmd.o \
+				hal/$(RTL871X)/Hal8723PwrSeq.o
+
+CHIP_FILES += $(HAL_COMM_FILES) $(OUTSRC_FILES) $(PWRSEQ_FILES)
+
+ifeq ($(CONFIG_BT_COEXIST), y)
+CHIP_FILES += hal/$(RTL871X)/rtl8723a_bt-coexist.o
+endif
+
+endif
+
+ifeq ($(CONFIG_RTL8188E), y)
 
 RTL871X = rtl8188e
+HAL_COMM_FILES := hal/$(RTL871X)/$(RTL871X)_xmit.o\
+									hal/$(RTL871X)/$(RTL871X)_sreset.o
 
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8189es
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8188eu
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8188ee
+endif
+
+#hal/OUTSRC/$(RTL871X)/HalHWImg8188E_FW.o
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/HalHWImg8188E_MAC.o\
+		hal/OUTSRC/$(RTL871X)/HalHWImg8188E_BB.o\
+		hal/OUTSRC/$(RTL871X)/HalHWImg8188E_RF.o\
+		hal/OUTSRC/$(RTL871X)/Hal8188EFWImg_CE.o\
+		hal/OUTSRC/$(RTL871X)/HalPhyRf_8188e.o\
+		hal/OUTSRC/$(RTL871X)/odm_RegConfig8188E.o\
+		hal/OUTSRC/$(RTL871X)/Hal8188ERateAdaptive.o\
+		hal/OUTSRC/$(RTL871X)/odm_RTL8188E.o
+
+ifeq ($(CONFIG_RTL8188E), y)
+ifeq ($(CONFIG_WOWLAN), y)
+OUTSRC_FILES += hal/OUTSRC/$(RTL871X)/HalHWImg8188E_FW.o
+endif
+endif
+
+PWRSEQ_FILES := hal/HalPwrSeqCmd.o \
+				hal/$(RTL871X)/Hal8188EPwrSeq.o
+
+CHIP_FILES += $(HAL_COMM_FILES) $(OUTSRC_FILES) $(PWRSEQ_FILES) 
+
+endif
+
+
+ifeq ($(CONFIG_GSPI_HCI), y)
+HCI_NAME = gspi
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+HCI_NAME = sdio
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
 HCI_NAME = usb
+endif
 
-_OS_INTFS_FILES :=				\
+ifeq ($(CONFIG_PCI_HCI), y)
-			os_dep/ioctl_linux.o	\
+HCI_NAME = pci
-			os_dep/mlme_linux.o	\
+endif
-			os_dep/os_intfs.o	\
-			os_dep/osdep_service.o	\
-			os_dep/recv_linux.o	\
-			os_dep/rtw_android.o	\
-			os_dep/usb_intf.o	\
-			os_dep/usb_ops_linux.o	\
-			os_dep/xmit_linux.o
 
 
+_OS_INTFS_FILES :=	os_dep/osdep_service.o \
+			os_dep/linux/os_intfs.o \
+			os_dep/linux/$(HCI_NAME)_intf.o \
+			os_dep/linux/$(HCI_NAME)_ops_linux.o \
+			os_dep/linux/ioctl_linux.o \
+			os_dep/linux/xmit_linux.o \
+			os_dep/linux/mlme_linux.o \
+			os_dep/linux/recv_linux.o \
+			os_dep/linux/ioctl_cfg80211.o \
+			os_dep/linux/rtw_android.o
 
+ifeq ($(CONFIG_SDIO_HCI), y)
+_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
+_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
+endif
 
-_HAL_INTFS_FILES += $(OUTSRC_FILES)
+ifeq ($(CONFIG_GSPI_HCI), y)
+_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
+_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
+endif
+
+_HAL_INTFS_FILES :=	hal/hal_intf.o \
+			hal/hal_com.o \
+			hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+ifeq ($(CONFIG_GSPI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+endif
+endif
+
+ifeq ($(CONFIG_MP_INCLUDED), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_mp.o
+endif
+
+_HAL_INTFS_FILES += $(CHIP_FILES)
 
 
 ifeq ($(CONFIG_AUTOCFG_CP), y)
 
-$(shell cp $(TopDIR)/autoconf_rtl8188e_usb_linux.h $(TopDIR)/include/autoconf.h)
+ifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy) 
+$(shell cp $(TopDIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+else
+$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+endif
+endif
+
+
+ifeq ($(CONFIG_USB_HCI), y)
+ifeq ($(CONFIG_USB_AUTOSUSPEND), y)
+EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND
+endif
+endif
+
+ifeq ($(CONFIG_MP_INCLUDED), y)
+#MODULE_NAME := $(MODULE_NAME)_mp
+EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED
+endif
+
+ifeq ($(CONFIG_POWER_SAVING), y)
+EXTRA_CFLAGS += -DCONFIG_POWER_SAVING
+endif
+
+ifeq ($(CONFIG_HW_PWRP_DETECTION), y)
+EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION
+endif
+
+ifeq ($(CONFIG_WIFI_TEST), y)
+EXTRA_CFLAGS += -DCONFIG_WIFI_TEST
 endif
 
 ifeq ($(CONFIG_BT_COEXIST), y)
 EXTRA_CFLAGS += -DCONFIG_BT_COEXIST
 endif
 
-ifeq ($(CONFIG_WOWLAN), y)
+ifeq ($(CONFIG_RTL8192CU_REDEFINE_1X1), y)
-EXTRA_CFLAGS += -DCONFIG_WOWLAN
+EXTRA_CFLAGS += -DRTL8192C_RECONFIG_TO_1T1R
 endif
 
-SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ | sed -e s/ppc/powerpc/ | sed -e s/armv.l/arm/)
+ifeq ($(CONFIG_INTEL_WIDI), y)
+EXTRA_CFLAGS += -DCONFIG_INTEL_WIDI
+endif
 
+ifeq ($(CONFIG_WAPI_SUPPORT), y)
+EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT
+endif
+
+ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)
+EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE
+endif
+
+ifeq ($(CONFIG_EXT_CLK), y)
+EXTRA_CFLAGS += -DCONFIG_EXT_CLK
+endif
+
+ifeq ($(CONFIG_FTP_PROTECT), y)
+EXTRA_CFLAGS += -DCONFIG_FTP_PROTECT
+endif
+
+ifeq ($(CONFIG_ODM_ADAPTIVITY), y)
+EXTRA_CFLAGS += -DCONFIG_ODM_ADAPTIVITY
+endif
+
+ifeq ($(CONFIG_MMC_PM_KEEP_POWER), y)
+EXTRA_CFLAGS += -DCONFIG_MMC_PM_KEEP_POWER
+endif
+
+ifeq ($(CONFIG_RTL8188E), y)
+ifeq ($(CONFIG_WOWLAN), y)
+EXTRA_CFLAGS += -DCONFIG_WOWLAN
+EXTRA_CFLAGS += -DCONFIG_MMC_PM_KEEP_POWER
+endif
+ifeq ($(CONFIG_GPIO_WAKEUP), y)
+EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP
+endif
+endif
+
+ifeq ($(CONFIG_RTL8188E), y)
+ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)
+EXTRA_CFLAGS += -DCONFIG_RF_GAIN_OFFSET
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
 ARCH ?= $(SUBARCH)
 CROSS_COMPILE ?=
 KVER  := $(shell uname -r)
-KSRC ?= /lib/modules/$(KVER)/build
+KSRC := /lib/modules/$(KVER)/build
-MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless
+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
 INSTALL_PREFIX :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X
+#ARCH := arm
+ARCH := $(R_ARCH)
+#CROSS_COMPILE := arm-none-linux-gnueabi-
+CROSS_COMPILE := $(R_CROSS_COMPILE)
+KVER:= 3.4.0
+#KSRC := ../../../../build/out/kernel
+KSRC := $(KERNEL_BUILD_PATH)
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
+CROSS_COMPILE := arm-eabi-
+KSRC := $(shell pwd)/../../../Android/kernel
+ARCH := arm
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
+ARCH:=mips
+CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
+KVER:= 2.6.28.9
+KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR
+ARCH:=arm
+CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-
+KVER:= 3.1.10
+KSRC:= /usr/src/Mstar_kernel/3.1.10/
+endif
+
+ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH := $(SUBARCH)
+CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
+KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_JB_X86), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH := $(SUBARCH)
+CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
+KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-none-linux-gnueabi-
+KVER  := 2.6.34.1
+KSRC ?= /usr/src/linux-2.6.34.1
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-linux-
+KVER  := 2.6.24.7_$(ARCH)
+KSRC := /usr/src/kernels/linux-$(KVER)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-none-linux-gnueabi-
+KVER  := 2.6.34.1
+KSRC ?= /usr/src/linux-2.6.34.1
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
+ARCH:=
+CROSS_COMPILE:=
+KVER:=
+KSRC:=
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH:=mips
+CROSS_COMPILE:=mipsisa32r2-uclibc-
+KVER:=
+KSRC:= /root/work/kernel_realtek
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH:=mips
+CROSS_COMPILE:=mipsisa32r2-uclibc-
+KVER:=
+KSRC:= /root/work/kernel_realtek
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
+ARCH:=mips
+CROSS_COMPILE:= mips-linux-gnu-
+KVER:= 2.6.28.10
+KSRC:= /home/mstar/mstar_linux/2.6.28.9/
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH := mips
+CROSS_COMPILE := mips-openwrt-linux-
+KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9
+endif
+
+ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
+ARCH := mips
+#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
+CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
+KSRC ?=/usr/local/Jupiter/linux-2.6.12
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
+ARCH:=mips
+CROSS_COMPILE:=mipsel-linux-
+KVER:=
+KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
+endif
+
+ifeq ($(CONFIG_PLATFORM_MT53XX), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
+ARCH:= arm
+CROSS_COMPILE:= arm11_mtk_le-
+KVER:= 2.6.27
+KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
+ARCH := arm
+CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
+KVER  := 2.6.31
+KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
+endif
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
+ARCH := mips
+CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
+KVER  := 2.6.27
+KSRC := /home/cnsd4/project/actions/linux-2.6.27.28
+endif
+
+ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
+ARCH := arm
+CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
+KVER  := 2.6.18
+KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
+endif
+
+ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS -DCONFIG_MINIMAL_MEMORY_USAGE
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_DETECT_CPWM_BY_POLLING -DCONFIG_DETECT_C2H_BY_POLLING
+endif
+ARCH := arm
+CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
+KSRC := /usr/src/release_fae_version/kernel25_A7_281x
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH := arm
+CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-
+KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH := arm
+#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104
+CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /media/DATA-1/android-4.0/panda_kernel/omap
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH ?= mips
+CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
+KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_SZEBOOK), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH:=arm
+CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi- 
+KVER:= 2.6.31.6
+KSRC:= ../code/linux-2.6.31.6-2020/
+endif
+
+#Add setting for MN10300
+ifeq ($(CONFIG_PLATFORM_MN10300), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300
+ARCH := mn10300
+CROSS_COMPILE := mn10300-linux-
+KVER := 2.6.32.2
+KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2
+INSTALL_PREFIX :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ARM_SUNxI
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DDCONFIG_P2P_IPS
+# default setting for A10-EVB mmc0
+ifeq ($(CONFIG_SDIO_HCI), y)
+#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
+endif
+ARCH := arm
+#CROSS_COMPILE := arm-none-linux-gnueabi-
+CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
+KVER  := 3.0.8
+#KSRC:= ../lichee/linux-3.0/
+KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+# default setting for A31-EVB mmc0
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_A31_EVB
+endif
+
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
+KVER  := 3.3.0
+#KSRC:= ../lichee/linux-3.3/
+KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME := 8188eu_sw
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
+ARCH := arm
+# Cross compile setting for Android 4.2 SDK
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/sugar/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KVER  := 3.3.0
+#KSRC :=/home/android_sdk/Allwinner/a20/sugar/lichee/linux-3.3
+# Cross compile setting for Android 4.3 SDK
+CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KVER  := 3.4.39
+KSRC :=/home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4
+endif
+
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201
+ARCH := mips
+CROSS_COMPILE := mipsel-linux-gnu-
+KVER  := $(KERNEL_VER)
+KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)
+endif
+
+ifneq ($(USER_MODULE_NAME),)
+MODULE_NAME := $(USER_MODULE_NAME)
+endif
 
 ifneq ($(KERNELRELEASE),)
 
-rtk_core :=				\
+rtk_core :=	core/rtw_cmd.o \
-		core/rtw_ap.o		\
+		core/rtw_security.o \
-		core/rtw_br_ext.o	\
+		core/rtw_debug.o \
-		core/rtw_cmd.o		\
+		core/rtw_io.o \
-		core/rtw_debug.o	\
+		core/rtw_ioctl_query.o \
-		core/rtw_efuse.o	\
+		core/rtw_ioctl_set.o \
-		core/rtw_ieee80211.o	\
+		core/rtw_ieee80211.o \
-		core/rtw_io.o		\
+		core/rtw_mlme.o \
-		core/rtw_ioctl_set.o	\
+		core/rtw_mlme_ext.o \
-		core/rtw_iol.o		\
+		core/rtw_wlan_util.o \
-		core/rtw_led.o		\
+		core/rtw_pwrctrl.o \
-		core/rtw_mlme.o		\
+		core/rtw_rf.o \
-		core/rtw_mlme_ext.o	\
+		core/rtw_recv.o \
-		core/rtw_mp.o		\
+		core/rtw_sta_mgt.o \
-		core/rtw_mp_ioctl.o	\
+		core/rtw_ap.o \
-		core/rtw_pwrctrl.o	\
+		core/rtw_xmit.o	\
-		core/rtw_p2p.o		\
+		core/rtw_p2p.o \
-		core/rtw_recv.o		\
+		core/rtw_tdls.o \
-		core/rtw_rf.o		\
+		core/rtw_br_ext.o \
-		core/rtw_security.o	\
+		core/rtw_iol.o \
-		core/rtw_sreset.o	\
+		core/rtw_led.o \
-		core/rtw_sta_mgt.o	\
+		core/rtw_sreset.o \
-		core/rtw_wlan_util.o	\
+		core/rtw_odm.o
-		core/rtw_xmit.o	
 
-8188eu-y += $(rtk_core)
+$(MODULE_NAME)-y += $(rtk_core)
 
-8188eu-y += $(_HAL_INTFS_FILES)
+$(MODULE_NAME)-$(CONFIG_INTEL_WIDI) += core/rtw_intel_widi.o
 
-8188eu-y += $(_OS_INTFS_FILES)
+$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o	\
+					core/rtw_wapi_sms4.o
 
-obj-$(CONFIG_RTL8188EU) := 8188eu.o
+$(MODULE_NAME)-y += core/efuse/rtw_efuse.o
+
+$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
+
+$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
+
+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o \
+					core/rtw_mp_ioctl.o
+ifeq ($(CONFIG_RTL8723A), y)
+
+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o
+endif
+
+obj-$(CONFIG_RTL8188EU) := $(MODULE_NAME).o
 
 else
 
@@ -146,16 +814,14 @@ modules:
 	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd)  modules
 
 strip:
-	$(CROSS_COMPILE)strip 8188eu.ko --strip-unneeded
+	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
 
 install:
-	install -p -D -m 644 8188eu.ko  $(MODDESTDIR)/8188eu.ko
+	install -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)
 	/sbin/depmod -a ${KVER}
-	mkdir -p /lib/firmware/rtlwifi
-	cp -n rtl8188eufw.bin /lib/firmware/rtlwifi/.
 
 uninstall:
-	rm -f $(MODDESTDIR)/8188eu.ko
+	rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
 	/sbin/depmod -a ${KVER}
 
 config_r:
@@ -171,8 +837,14 @@ clean: $(clean_more)
 	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
 	rm -fr .tmp_versions
 	rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order
+	cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
 	cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hal/$(RTL871X)/$(HCI_NAME) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hal/$(RTL871X) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hal/OUTSRC/$(RTL871X) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko 
+	cd hal/OUTSRC/ ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko 
 	cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
 	cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
 endif
 

core/rtw_eeprom.c

@@ -0,0 +1,423 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTW_EEPROM_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+void up_clk(_adapter*	padapter,	 u16 *x)
+{
+_func_enter_;
+	*x = *x | _EESK;
+	rtw_write8(padapter, EE_9346CR, (u8)*x);
+	rtw_udelay_os(CLOCK_RATE);
+
+_func_exit_;
+	
+}
+
+void down_clk(_adapter *	padapter, u16 *x	)
+{
+_func_enter_;
+	*x = *x & ~_EESK;
+	rtw_write8(padapter, EE_9346CR, (u8)*x);
+	rtw_udelay_os(CLOCK_RATE);
+_func_exit_;	
+}
+
+void shift_out_bits(_adapter * padapter, u16 data, u16 count)
+{
+	u16 x,mask;
+_func_enter_;
+
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	mask = 0x01 << (count - 1);
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EEDO | _EEDI);
+
+	do
+	{
+		x &= ~_EEDI;
+		if(data & mask)
+			x |= _EEDI;
+		if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+		}
+		rtw_write8(padapter, EE_9346CR, (u8)x);
+		rtw_udelay_os(CLOCK_RATE);
+		up_clk(padapter, &x);
+		down_clk(padapter, &x);
+		mask = mask >> 1;
+	} while(mask);
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	x &= ~_EEDI;
+	rtw_write8(padapter, EE_9346CR, (u8)x);
+out:	
+_func_exit_;		
+}
+
+u16 shift_in_bits (_adapter * padapter)
+{
+	u16 x,d=0,i;
+_func_enter_;	
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~( _EEDO | _EEDI);
+	d = 0;
+
+	for(i=0; i<16; i++)
+	{
+		d = d << 1;
+		up_clk(padapter, &x);
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+		x = rtw_read8(padapter, EE_9346CR);
+
+		x &= ~(_EEDI);
+		if(x & _EEDO)
+		d |= 1;
+
+		down_clk(padapter, &x);
+	}
+out:	
+_func_exit_;		
+
+	return d;
+}
+
+void standby(_adapter *	padapter	)
+{
+	u8   x;
+_func_enter_;	
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EECS | _EESK);
+	rtw_write8(padapter, EE_9346CR,x);
+
+	rtw_udelay_os(CLOCK_RATE);
+	x |= _EECS;
+	rtw_write8(padapter, EE_9346CR, x);
+	rtw_udelay_os(CLOCK_RATE);
+_func_exit_;		
+}
+
+u16 wait_eeprom_cmd_done(_adapter* padapter)
+{
+	u8 	x;
+	u16	i,res=_FALSE;
+_func_enter_;	
+	standby(padapter );
+	for (i=0; i<200; i++) 
+	{
+		x = rtw_read8(padapter, EE_9346CR);
+		if (x & _EEDO){
+			res=_TRUE;
+			goto exit;
+			}
+		rtw_udelay_os(CLOCK_RATE);
+	}
+exit:	
+_func_exit_;			
+	return res;
+}
+
+void eeprom_clean(_adapter * padapter)
+{
+	u16 x;
+_func_enter_;		
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	x = rtw_read8(padapter, EE_9346CR);
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	x &= ~(_EECS | _EEDI);
+	rtw_write8(padapter, EE_9346CR, (u8)x);
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	up_clk(padapter, &x);
+		if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	down_clk(padapter, &x);
+out:	
+_func_exit_;			
+}
+
+void eeprom_write16(_adapter * padapter, u16 reg, u16 data)
+{
+	u8 x;
+#ifdef CONFIG_RTL8712
+	u8	tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
+	tmp8_ori=rtw_read8(padapter, 0x102502f1);
+	tmp8_new=tmp8_ori & 0xf7;
+	if(tmp8_ori != tmp8_new){	
+		rtw_write8(padapter, 0x102502f1, tmp8_new);
+		RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
+	}
+	tmp8_clk_ori=rtw_read8(padapter,0x10250003);
+	tmp8_clk_new=tmp8_clk_ori|0x20;
+	if(tmp8_clk_new!=tmp8_clk_ori){
+		RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
+		rtw_write8(padapter, 0x10250003, tmp8_clk_new);
+	}	
+#endif
+_func_enter_;		
+	
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
+	x |= _EEM1 | _EECS;
+	rtw_write8(padapter, EE_9346CR, x);
+
+	shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
+	
+	if(padapter->EepromAddressSize==8)	//CF+ and SDIO
+		shift_out_bits(padapter, 0, 6);
+	else									//USB
+		shift_out_bits(padapter, 0, 4);
+	
+	standby( padapter);
+
+// Commented out by rcnjko, 2004.0
+//	// Erase this particular word.  Write the erase opcode and register
+//	// number in that order. The opcode is 3bits in length; reg is 6 bits long.
+//	shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
+//	shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
+//
+//	if (wait_eeprom_cmd_done(Adapter ) == FALSE) 
+//	{
+//		return;
+//	}
+
+
+	standby(padapter );
+
+	// write the new word to the EEPROM
+
+	// send the write opcode the EEPORM
+	shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
+
+	// select which word in the EEPROM that we are writing to.
+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
+
+	// write the data to the selected EEPROM word.
+	shift_out_bits(padapter, data, 16);
+
+	if (wait_eeprom_cmd_done(padapter ) == _FALSE) 
+	{
+
+		goto exit;
+	}
+
+	standby(padapter );
+
+	shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
+	shift_out_bits(padapter, reg, 4);
+
+	eeprom_clean(padapter );
+exit:	
+#ifdef CONFIG_RTL8712
+	if(tmp8_clk_new!=tmp8_clk_ori)
+		rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
+	if(tmp8_new!=tmp8_ori)
+		rtw_write8(padapter, 0x102502f1, tmp8_ori);
+
+#endif
+_func_exit_;	
+	return;
+}
+
+u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
+{
+
+	u16 x;
+	u16 data=0;
+#ifdef CONFIG_RTL8712
+	u8	tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
+	tmp8_ori= rtw_read8(padapter, 0x102502f1);
+	tmp8_new = tmp8_ori & 0xf7;
+	if(tmp8_ori != tmp8_new){	
+		rtw_write8(padapter, 0x102502f1, tmp8_new);
+		RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
+	}
+	tmp8_clk_ori=rtw_read8(padapter,0x10250003);
+	tmp8_clk_new=tmp8_clk_ori|0x20;
+	if(tmp8_clk_new!=tmp8_clk_ori){
+		RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
+		rtw_write8(padapter, 0x10250003, tmp8_clk_new);
+	}	
+#endif
+_func_enter_;		
+
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	// select EEPROM, reset bits, set _EECS
+	x = rtw_read8(padapter, EE_9346CR);
+
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+
+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
+	x |= _EEM1 | _EECS;
+	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
+
+	// write the read opcode and register number in that order
+	// The opcode is 3bits in length, reg is 6 bits long
+	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
+
+	// Now read the data (16 bits) in from the selected EEPROM word
+	data = shift_in_bits(padapter);
+
+	eeprom_clean(padapter);
+out:	
+#ifdef CONFIG_RTL8712
+	if(tmp8_clk_new!=tmp8_clk_ori)
+		rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
+	if(tmp8_new!=tmp8_ori)
+		rtw_write8(padapter, 0x102502f1, tmp8_ori);
+
+#endif
+_func_exit_;		
+	return data;
+
+
+}
+
+
+
+
+//From even offset
+void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz) 
+{
+
+	u16 x, data16;
+	u32 i;
+_func_enter_;		
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+	// select EEPROM, reset bits, set _EECS
+	x = rtw_read8(padapter, EE_9346CR);
+
+	if(padapter->bSurpriseRemoved==_TRUE){
+		RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
+		goto out;
+	}
+
+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
+	x |= _EEM1 | _EECS;
+	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
+
+	// write the read opcode and register number in that order
+	// The opcode is 3bits in length, reg is 6 bits long
+	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
+
+
+	for(i=0; i<sz; i+=2)
+	{
+		data16 = shift_in_bits(padapter);
+		data[i] = data16 & 0xff;
+		data[i+1] = data16 >>8;		
+	}
+
+	eeprom_clean(padapter);
+out:	
+_func_exit_;		
+
+
+
+}
+
+
+//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg)
+u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf)
+{
+	u8 quotient, remainder, addr_2align_odd;
+	u16 reg, stmp , i=0, idx = 0;
+_func_enter_;		
+	reg = (u16)(addr_off >> 1);
+	addr_2align_odd = (u8)(addr_off & 0x1);
+
+	if(addr_2align_odd) //read that start at high part: e.g  1,3,5,7,9,...
+	{
+		stmp = eeprom_read16(padapter, reg);
+		rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short
+		reg++; sz--;
+	}
+	
+	quotient = sz >> 1;
+	remainder = sz & 0x1;
+
+	for( i=0 ; i < quotient; i++)
+	{
+		stmp = eeprom_read16(padapter, reg+i);
+		rbuf[idx++] = (u8) (stmp&0xff);
+		rbuf[idx++] = (u8) ((stmp>>8)&0xff);
+	}
+	
+	reg = reg+i;
+	if(remainder){ //end of read at lower part of short : 0,2,4,6,...
+		stmp = eeprom_read16(padapter, reg);
+		rbuf[idx] = (u8)(stmp & 0xff); 
+	}
+_func_exit_;		
+	return _TRUE;
+}
+
+
+
+VOID read_eeprom_content(_adapter *	padapter)
+{
+
+_func_enter_;		
+
+
+_func_exit_;		
+}
+

core/rtw_io.c

@@ -27,11 +27,20 @@ b. provides the protocol engine
 
 c. provides the software interface between caller and the hardware interface
 
+
 Compiler Flag Option:
 
-USB:
+1. CONFIG_SDIO_HCI:
+    a. USE_SYNC_IRP:  Only sync operations are provided.
+    b. USE_ASYNC_IRP:Both sync/async operations are provided.
+
+2. CONFIG_USB_HCI:
    a. USE_ASYNC_IRP: Both sync/async operations are provided.
 
+3. CONFIG_CFIO_HCI:
+   b. USE_SYNC_IRP: Only sync operations are provided.
+
+
 Only sync read/rtw_write_mem operations are provided.
 
 jackson@realtek.com.tw
@@ -39,203 +48,252 @@ jackson@realtek.com.tw
 */
 
 #define _RTW_IO_C_
+#include <drv_conf.h>
 #include <osdep_service.h>
 #include <drv_types.h>
 #include <rtw_io.h>
 #include <osdep_intf.h>
-#include <usb_ops.h>
 
-#define rtw_le16_to_cpu(val)		le16_to_cpu(val)
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+#error "Shall be Linux or Windows, but not both!\n"
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+#include <sdio_ops.h>
+#endif
+
+#ifdef CONFIG_GSPI_HCI
+#include <gspi_ops.h>
+#endif
+
+#ifdef CONFIG_USB_HCI
+#include <usb_ops.h>
+#endif
+
+#ifdef CONFIG_PCI_HCI
+#include <pci_ops.h>
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+#define rtw_le16_to_cpu(val) 		val
+#define rtw_le32_to_cpu(val)		val
+#define rtw_cpu_to_le16(val)		val
+#define rtw_cpu_to_le32(val)		val
+#else
+#define rtw_le16_to_cpu(val) 		le16_to_cpu(val)
 #define rtw_le32_to_cpu(val)		le32_to_cpu(val)
 #define rtw_cpu_to_le16(val)		cpu_to_le16(val)
 #define rtw_cpu_to_le32(val)		cpu_to_le32(val)
+#endif
 
-u8 _rtw_read8(struct adapter *adapter, u32 addr)
+
+u8 _rtw_read8(_adapter *adapter, u32 addr)
 {
 	u8 r_val;
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
-	struct	intf_hdl *pintfhdl = &(pio_priv->intf);
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
-
+	_func_enter_;
-	
 	_read8 = pintfhdl->io_ops._read8;
-	r_val = _read8(pintfhdl, addr);
 
+	r_val = _read8(pintfhdl, addr);
+	_func_exit_;
 	return r_val;
 }
 
-u16 _rtw_read16(struct adapter *adapter, u32 addr)
+u16 _rtw_read16(_adapter *adapter, u32 addr)
 {
 	u16 r_val;
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-	u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
+	u16 	(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
-
+	_func_enter_;
 	_read16 = pintfhdl->io_ops._read16;
 
 	r_val = _read16(pintfhdl, addr);
-
+	_func_exit_;
-	return r_val;
+	return rtw_le16_to_cpu(r_val);
 }
 
-u32 _rtw_read32(struct adapter *adapter, u32 addr)
+u32 _rtw_read32(_adapter *adapter, u32 addr)
 {
 	u32 r_val;
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-	u32	(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
+	u32 	(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
-
+	_func_enter_;
 	_read32 = pintfhdl->io_ops._read32;
 
 	r_val = _read32(pintfhdl, addr);
+	_func_exit_;
+	return rtw_le32_to_cpu(r_val);
 
-	return r_val;
 }
 
-int _rtw_write8(struct adapter *adapter, u32 addr, u8 val)
+int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
 	int ret;
-	
+	_func_enter_;
 	_write8 = pintfhdl->io_ops._write8;
 
 	ret = _write8(pintfhdl, addr, val);
-	
+	_func_exit_;
 	
 	return RTW_STATUS_CODE(ret);
 }
-
+int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
-int _rtw_write16(struct adapter *adapter, u32 addr, u16 val)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
 	int ret;
-	
+	_func_enter_;
 	_write16 = pintfhdl->io_ops._write16;
 
+	val = rtw_cpu_to_le16(val);
 	ret = _write16(pintfhdl, addr, val);
-	
+	_func_exit_;
 
 	return RTW_STATUS_CODE(ret);
 }
-int _rtw_write32(struct adapter *adapter, u32 addr, u32 val)
+int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
 	int ret;
-	
+	_func_enter_;
 	_write32 = pintfhdl->io_ops._write32;
 	
+	val = rtw_cpu_to_le32(val);
 	ret = _write32(pintfhdl, addr, val);
-	
+	_func_exit_;
 
 	return RTW_STATUS_CODE(ret);
 }
 
-int _rtw_writeN(struct adapter *adapter, u32 addr , u32 length , u8 *pdata)
+int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
-	struct	intf_hdl *pintfhdl = (struct intf_hdl *)(&(pio_priv->intf));
+        struct	intf_hdl	*pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
-	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
+	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata);
 	int ret;
-	
+	_func_enter_;
 	_writeN = pintfhdl->io_ops._writeN;
 
-	ret = _writeN(pintfhdl, addr, length, pdata);
+	ret = _writeN(pintfhdl, addr,length,pdata);
-	
+	_func_exit_;
 
 	return RTW_STATUS_CODE(ret);
 }
-int _rtw_write8_async(struct adapter *adapter, u32 addr, u8 val)
+int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
 	int ret;
-	
+	_func_enter_;
 	_write8_async = pintfhdl->io_ops._write8_async;
 
 	ret = _write8_async(pintfhdl, addr, val);
-	
+	_func_exit_;
 
 	return RTW_STATUS_CODE(ret);
 }
-
+int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
-int _rtw_write16_async(struct adapter *adapter, u32 addr, u16 val)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
 	int ret;
-
+	_func_enter_;
 	_write16_async = pintfhdl->io_ops._write16_async;
+	val = rtw_cpu_to_le16(val);
 	ret = _write16_async(pintfhdl, addr, val);
+	_func_exit_;
 
 	return RTW_STATUS_CODE(ret);
 }
-
+int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
-int _rtw_write32_async(struct adapter *adapter, u32 addr, u32 val)
 {
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
 	int ret;
-
+	_func_enter_;
 	_write32_async = pintfhdl->io_ops._write32_async;
+	val = rtw_cpu_to_le32(val);
 	ret = _write32_async(pintfhdl, addr, val);
+	_func_exit_;
 
 	return RTW_STATUS_CODE(ret);
 }
 
-void _rtw_read_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
 {
 	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 
+	_func_enter_;
 
-	if (adapter->bDriverStopped || adapter->bSurpriseRemoved) {
+	if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
-	     RT_TRACE(_module_rtl871x_io_c_, _drv_info_,
+	{
-		      ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)",
+	     RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));	    
-		      adapter->bDriverStopped, adapter->bSurpriseRemoved));
 	     return;
 	}
+
 	_read_mem = pintfhdl->io_ops._read_mem;
+
 	_read_mem(pintfhdl, addr, cnt, pmem);
 
+	_func_exit_;
+
 }
 
-void _rtw_write_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
 {
 	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 
-	
+	_func_enter_;
 
 	_write_mem = pintfhdl->io_ops._write_mem;
 
 	_write_mem(pintfhdl, addr, cnt, pmem);
 
+	_func_exit_;
 
 }
 
-void _rtw_read_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
 {
 	u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 
+	_func_enter_;
 
-
+	if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
-	if (adapter->bDriverStopped || adapter->bSurpriseRemoved) {
+	{
-	     RT_TRACE(_module_rtl871x_io_c_, _drv_info_,
+	     RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));	    
-		      ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)",
-		      adapter->bDriverStopped, adapter->bSurpriseRemoved));
 	     return;
 	}
 
@@ -243,10 +301,11 @@ void _rtw_read_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
 
 	_read_port(pintfhdl, addr, cnt, pmem);
 
+	_func_exit_;
 
 }
 
-void _rtw_read_port_cancel(struct adapter *adapter)
+void _rtw_read_port_cancel(_adapter *adapter)
 {
 	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
 	struct io_priv *pio_priv = &adapter->iopriv;
@@ -254,29 +313,31 @@ void _rtw_read_port_cancel(struct adapter *adapter)
 
 	_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
 
-	if (_read_port_cancel)
+	if(_read_port_cancel)
 		_read_port_cancel(pintfhdl);
+
 }
 
-u32 _rtw_write_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
 {
 	u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	//struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue;
 	struct io_priv *pio_priv = &adapter->iopriv;
 	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
 	u32 ret = _SUCCESS;
 
-	
+	_func_enter_;
 
 	_write_port = pintfhdl->io_ops._write_port;
 	
 	ret = _write_port(pintfhdl, addr, cnt, pmem);
 
-	 
+	 _func_exit_;
 
 	return ret;
 }
 
-u32 _rtw_write_port_and_wait(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
+u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
 {
 	int ret = _SUCCESS;
 	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
@@ -293,7 +354,7 @@ u32 _rtw_write_port_and_wait(struct adapter *adapter, u32 addr, u32 cnt, u8 *pme
 	 return ret;
 }
 
-void _rtw_write_port_cancel(struct adapter *adapter)
+void _rtw_write_port_cancel(_adapter *adapter)
 {
 	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
 	struct io_priv *pio_priv = &adapter->iopriv;
@@ -301,11 +362,12 @@ void _rtw_write_port_cancel(struct adapter *adapter)
 
 	_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
 
-	if (_write_port_cancel)
+	if(_write_port_cancel)
 		_write_port_cancel(pintfhdl);
+
 }
 
-int rtw_init_io_priv(struct adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops))
+int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops))
 {
 	struct io_priv	*piopriv = &padapter->iopriv;
 	struct intf_hdl *pintf = &piopriv->intf;
@@ -321,3 +383,127 @@ int rtw_init_io_priv(struct adapter *padapter, void (*set_intf_ops)(struct _io_o
 
 	return _SUCCESS;
 }
+
+/*
+* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR
+* @return _TRUE:
+* @return _FALSE:
+*/
+int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
+{
+	int ret = _FALSE;
+	int value;
+	if( (value=ATOMIC_INC_RETURN(&dvobj->continual_io_error)) > MAX_CONTINUAL_IO_ERR) {
+		DBG_871X("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR);
+		ret = _TRUE;
+	} else {
+		//DBG_871X("[dvobj:%p] continual_io_error:%d\n", dvobj, value);
+	}
+	return ret;
+}
+
+/*
+* Set the continual_io_error of this @param dvobjprive to 0
+*/
+void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
+{
+	ATOMIC_SET(&dvobj->continual_io_error, 0);	
+}
+
+#ifdef DBG_IO
+
+u16 read_sniff_ranges[][2] = {
+	//{0x550, 0x551},
+}; 
+
+u16 write_sniff_ranges[][2] = {
+	//{0x550, 0x551},
+	//{0x4c, 0x4c},
+}; 
+
+int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2;
+int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2;
+
+bool match_read_sniff_ranges(u16 addr, u16 len)
+{
+	int i;
+	for (i = 0; i<read_sniff_num; i++) {
+		if (addr + len > read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1])
+			return _TRUE;
+	}
+	
+	return _FALSE;
+}
+
+bool match_write_sniff_ranges(u16 addr, u16 len)
+{
+	int i;
+	for (i = 0; i<write_sniff_num; i++) {
+		if (addr + len > write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1])
+			return _TRUE;
+	}
+	
+	return _FALSE;
+}
+
+u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u8 val = _rtw_read8(adapter, addr);
+
+	if (match_read_sniff_ranges(addr, 1))
+		DBG_871X("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val);
+
+	return val;
+}
+
+u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u16 val = _rtw_read16(adapter, addr);
+	
+	if (match_read_sniff_ranges(addr, 2))
+		DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val);
+
+	return val;
+}
+
+u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u32 val = _rtw_read32(adapter, addr);
+	
+	if (match_read_sniff_ranges(addr, 4))
+		DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val);
+
+	return val;
+}
+
+int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, 1))
+		DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val);
+	
+	return _rtw_write8(adapter, addr, val);
+}
+int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, 2))
+		DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val);
+	
+	return _rtw_write16(adapter, addr, val);
+}
+int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, 4))
+		DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val);
+	
+	return _rtw_write32(adapter, addr, val);
+}
+int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, length))
+		DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length);
+
+	return _rtw_writeN(adapter, addr, length, data);
+}
+#endif
+
+

core/rtw_ioctl_query.c

@@ -0,0 +1,196 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTW_IOCTL_QUERY_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_ioctl_query.h>
+#include <wifi.h>
+
+
+#ifdef PLATFORM_WINDOWS
+//
+// Added for WPA2-PSK, by Annie, 2005-09-20.
+//
+u8
+query_802_11_capability(
+	_adapter*		Adapter,
+	u8*			pucBuf,
+	u32 *		pulOutLen
+)
+{
+	static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] = 
+	{
+		{Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled}, 
+		{Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled},
+		{Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled}, 
+		{Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled},
+		{Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled}, 
+		{Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled}, 
+		{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled}, 
+		{Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled}, 
+		{Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled}, 
+		{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled}
+	};	
+	static ULONG	ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
+	NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf;
+	u8*	pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported;
+
+
+	pCap->Length = sizeof(NDIS_802_11_CAPABILITY);
+	if(ulNumOfPairSupported > 1 )
+		pCap->Length += 	(ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
+	
+	pCap->Version = 2;	
+	pCap->NoOfPMKIDs = NUM_PMKID_CACHE;	
+	pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported;
+
+	if( sizeof (szAuthEnc) <= 240 )		// 240 = 256 - 4*4	// SecurityInfo.szCapability: only 256 bytes in size.
+	{
+		_rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc,  sizeof (szAuthEnc) );
+		*pulOutLen = pCap->Length;
+		return _TRUE;
+	}
+	else
+	{
+		*pulOutLen = 0;
+		RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n"));
+		return _FALSE;
+	}
+}
+
+u8 query_802_11_association_information(	_adapter *padapter,PNDIS_802_11_ASSOCIATION_INFORMATION	pAssocInfo)
+{
+	struct wlan_network *tgt_network;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct	security_priv  *psecuritypriv=&(padapter->securitypriv);
+	WLAN_BSSID_EX	*psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss);					
+	u8 *	pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
+	unsigned char i,*auth_ie,*supp_ie;
+
+	//NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
+	_rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
+	//pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
+
+	//------------------------------------------------------
+	// Association Request related information
+	//------------------------------------------------------
+	// Req_1. AvailableRequestFixedIEs
+	if(psecnetwork!=NULL){
+		
+	pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS;
+	pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10];
+	_rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress,
+		& psecnetwork->MacAddress, 6);
+
+	pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
+
+	if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE)
+	{
+		
+		if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2)
+			pDest[0] =48;		//RSN Information Element
+		else 
+			pDest[0] =221;	//WPA(SSN) Information Element
+		
+		RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0]));
+		supp_ie=&psecuritypriv->supplicant_ie[0];
+		for(i=0;i<supp_ie[0];i++)
+		{
+			RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,supp_ie[i]));
+		}
+
+		i=13;	//0~11 is fixed information element		
+		RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("i= %d tgt_network->network.IELength=%d\n\n", i,(int)psecnetwork->IELength));
+		while((i<supp_ie[0]) && (i<256)){
+			if((unsigned char)supp_ie[i]==pDest[0]){
+						_rtw_memcpy((u8 *)(pDest),
+							&supp_ie[i], 
+							supp_ie[1+i]+2);
+			
+				break;
+			}
+			
+			i=i+supp_ie[i+1]+2;
+			if(supp_ie[1+i]==0)
+				i=i+1;
+			RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("iteration i=%d IEs [%d] = 0x%x \n\n", i,i,supp_ie[i+1]));
+			
+		}
+		
+
+		pAssocInfo->RequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4);
+
+	}
+	
+
+		RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n"));
+
+	}
+	
+
+	//------------------------------------------------------
+	// Association Response related information
+	//------------------------------------------------------
+
+	if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE)
+	{
+		tgt_network =&(pmlmepriv->cur_network);
+		if(tgt_network!=NULL){
+		pAssocInfo->AvailableResponseFixedIEs =
+				NDIS_802_11_AI_RESFI_CAPABILITIES
+				|NDIS_802_11_AI_RESFI_ASSOCIATIONID
+				;
+
+		pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10];
+		pAssocInfo->ResponseFixedIEs.StatusCode = 0;
+		pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid;
+
+		pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength;
+		auth_ie=&psecuritypriv->authenticator_ie[0];
+
+		for(i=0;i<auth_ie[0];i++)
+			RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,auth_ie[i]));
+
+		i=auth_ie[0]-12;
+		if(i>0){
+			_rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i);
+			pAssocInfo->ResponseIELength =i; 
+		}
+
+
+		pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;  
+
+
+		RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n"));
+		}
+	}												  	
+	RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n"));
+_func_exit_;
+
+	return _TRUE;
+}
+#endif
+

core/rtw_iol.c

@@ -20,24 +20,26 @@
 
 #include<rtw_iol.h>
 
-struct xmit_frame	*rtw_IOL_accquire_xmit_frame(struct adapter  *adapter)
+#ifdef CONFIG_IOL
+struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
 {
 	struct xmit_frame	*xmit_frame;
 	struct xmit_buf	*xmitbuf;
 	struct pkt_attrib	*pattrib;
 	struct xmit_priv	*pxmitpriv = &(adapter->xmitpriv);
 
-	xmit_frame = rtw_alloc_xmitframe(pxmitpriv);
+#if 1
-	if (xmit_frame == NULL) {
+	if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
-		DBG_88E("%s rtw_alloc_xmitframe return null\n", __func__);
+	{
+		DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
 		goto exit;
 	}
 	
-	xmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
-	if (xmitbuf == NULL) {
+	{
-		DBG_88E("%s rtw_alloc_xmitbuf return null\n", __func__);
+		DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
 		rtw_free_xmitframe(pxmitpriv, xmit_frame);
-		xmit_frame = NULL;
+		xmit_frame=NULL;
 		goto exit;
 	}
 	
@@ -48,14 +50,28 @@ struct xmit_frame	*rtw_IOL_accquire_xmit_frame(struct adapter  *adapter)
 
 	pattrib = &xmit_frame->attrib;
 	update_mgntframe_attrib(adapter, pattrib);
-	pattrib->qsel = 0x10;/* Beacon */
+	pattrib->qsel = 0x10;//Beacon	
 	pattrib->subtype = WIFI_BEACON;	
-	pattrib->pktlen = 0;
+	pattrib->pktlen = pattrib->last_txcmdsz = 0;
-	pattrib->last_txcmdsz = 0;
+
+#else
+	if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL)
+	{
+		DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
+	}
+	else {
+		pattrib = &xmit_frame->attrib;
+		update_mgntframe_attrib(adapter, pattrib);
+		pattrib->qsel = 0x10;
+		pattrib->pktlen = pattrib->last_txcmdsz = 0;
+	}
+#endif
+
 exit:
 	return xmit_frame;
 }
 
+
 int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
 {
 	struct pkt_attrib	*pattrib = &xmit_frame->attrib;
@@ -65,145 +81,323 @@ int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len
 	buf_offset = TXDESC_OFFSET;
 	ori_len = buf_offset+pattrib->pktlen;
 
-	/* check if the io_buf can accommodate new cmds */
+	//check if the io_buf can accommodate new cmds
-	if (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
+	if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
-		DBG_88E("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n",
+		DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
-			__func__ , ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
+			, ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
 		return _FAIL;
 	}
 
-	memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
+	_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
 	pattrib->pktlen += cmd_len;
 	pattrib->last_txcmdsz += cmd_len;
 
+	//DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen);
+	
 	return _SUCCESS;
 }
-
+bool rtw_IOL_applied(ADAPTER *adapter)
-bool rtw_IOL_applied(struct adapter  *adapter)
 {	
-	if (1 == adapter->registrypriv.fw_iol)
+	if(1 == adapter->registrypriv.fw_iol)
-		return true;
+		return _TRUE;
 
-	if ((2 == adapter->registrypriv.fw_iol) && (!adapter_to_dvobj(adapter)->ishighspeed))
+#ifdef CONFIG_USB_HCI
-		return true;
+	if((2 == adapter->registrypriv.fw_iol) && (!adapter_to_dvobj(adapter)->ishighspeed))
-	return false;
+		return _TRUE;
-}
+#endif
-
+
-int rtw_IOL_exec_cmds_sync(struct adapter  *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+	return _FALSE;
-{
+}
-	return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms, bndy_cnt);
+/*
+bool rtw_IOL_applied(ADAPTER *adapter)
+{
+	if(adapter->registrypriv.fw_iol)
+		return _TRUE;
+
+#ifdef CONFIG_USB_HCI
+	if(!adapter_to_dvobj(adapter)->ishighspeed)
+		return _TRUE;
+#endif
+
+	return _FALSE;
+}
+*/
+
+int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+{
+	return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms,bndy_cnt);
 }
 
+#ifdef CONFIG_IOL_NEW_GENERATION
 int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
 {
 	return _SUCCESS;
 }
-
 int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)
 {
-	struct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0};
+	struct ioreg_cfg cmd = {8,IOREG_CMD_WB_REG,0x0, 0x0,0x0};
 
+	//RTW_PUT_LE16((u8*)&cmd.address, addr);	
+	//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	
 	cmd.address = cpu_to_le16(addr);	
 	cmd.data = cpu_to_le32(value);
 	
-	if (mask != 0xFF) {
+	if(mask!=0xFF)
+	{
 		cmd.length = 12;
+		//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	
 		cmd.mask = cpu_to_le32(mask);
 	}	
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
-}
 		
+	//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
+
+}
 int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)
 {
-	struct ioreg_cfg cmd = {8, IOREG_CMD_WW_REG, 0x0, 0x0, 0x0};
+	struct ioreg_cfg cmd = {8,IOREG_CMD_WW_REG,0x0, 0x0,0x0};
 
+	//RTW_PUT_LE16((u8*)&cmd.address, addr);	
+	//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	
 	cmd.address = cpu_to_le16(addr);	
 	cmd.data = cpu_to_le32(value);
 	
-	if (mask != 0xFFFF) {
+	if(mask!=0xFFFF)
+	{
 		cmd.length = 12;
+		//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	
 		cmd.mask =  cpu_to_le32(mask);
 	}	
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
-}
 		
+	//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
+	
+}
 int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
 {
-	struct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0};
+	struct ioreg_cfg cmd = {8,IOREG_CMD_WD_REG,0x0, 0x0,0x0};
 
+	//RTW_PUT_LE16((u8*)&cmd.address, addr);	
+	//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	
 	cmd.address = cpu_to_le16(addr);	
 	cmd.data = cpu_to_le32(value);
 	
-	if (mask != 0xFFFFFFFF) {
+	if(mask!=0xFFFFFFFF)
+	{
 		cmd.length = 12;
+		//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	
 		cmd.mask =  cpu_to_le32(mask);
 	}	
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
+		
+	//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
+	
 }
 
 int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
 {
-	struct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0};
+	struct ioreg_cfg cmd = {8,IOREG_CMD_W_RF,0x0, 0x0,0x0};
 
-	cmd.address = cpu_to_le16((rf_path<<8) | ((addr) & 0xFF));
+	//RTW_PUT_LE16((u8*)&cmd.address, addr);	
+	//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	
+	cmd.address = (rf_path<<8) |((addr) &0xFF);	
 	cmd.data = cpu_to_le32(value);
 	
-	if (mask != 0x000FFFFF) {
+	if(mask!=0x000FFFFF)
+	{
 		cmd.length = 12;
+		//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	
 		cmd.mask =  cpu_to_le32(mask);
 	}	
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
+		
+	//DBG_871X("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
+	
 }
 
+
+
 int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
 {
-	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
+	struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0};
+	//RTW_PUT_LE16((u8*)&cmd.address, us);	
 	cmd.address = cpu_to_le16(us);	
 
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
+	//DBG_871X("%s %u\n", __FUNCTION__, us);
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
 }
 
 int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
 {
-	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
+	struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0};
 
+	//RTW_PUT_LE16((u8*)&cmd.address, ms);	
 	cmd.address = cpu_to_le16(ms);	
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
-}
 
+	//DBG_871X("%s %u\n", __FUNCTION__, ms);
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
+}
 int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
 {	
-	struct ioreg_cfg cmd = {4, IOREG_CMD_END, cpu_to_le16(0xFFFF), cpu_to_le32(0xFF), 0x0};
+	struct ioreg_cfg cmd = {4,IOREG_CMD_END,0xFFFF, 0xFF,0x0};
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
 
-	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
 }
 
 u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
 {	
-	u8 is_cmd_bndy = false;
+	u8 is_cmd_bndy = _FALSE;
-	if (((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256) {
+	if(((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256){
 		rtw_IOL_append_END_cmd(pxmit_frame);
-		pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256);
+		pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256 );
 		
+		//printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen);
 		pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
-		is_cmd_bndy = true;
+		is_cmd_bndy = _TRUE;	
 	}
 	return is_cmd_bndy;
 }
 
-void rtw_IOL_cmd_buf_dump(struct adapter  *Adapter, int buf_len, u8 *pbuf)
+void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf)
 {
 	int i;
-	int j = 1;
+	int j=1;
 	
-	pr_info("###### %s ######\n", __func__);
+	printk("###### %s ######\n",__FUNCTION__);
-	for (i = 0; i < buf_len; i++) {
+	for(i=0;i< buf_len;i++){
-		printk("%02x-", *(pbuf+i));
+		printk("%02x-",*(pbuf+i));
 			
-		if (j%32 == 0)
+		if(j%32 ==0) printk("\n");j++;				
-			printk("\n");
-		j++;
 	}
 	printk("\n");
-	pr_info("=============ioreg_cmd len=%d===============\n", buf_len);
+	printk("============= ioreg_cmd len = %d =============== \n",buf_len);	
 }
+
+
+#else //CONFIG_IOL_NEW_GENERATION
+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
+{	
+	IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
+	
+	RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
+}
+
+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
+	
+	RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
+	RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
+}
+
+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
+	
+	RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
+	RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
+}
+
+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
+	u8* pos = (u8 *)&cmd;
+	
+	RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
+	RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
+}
+
+#ifdef DBG_IO
+int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, 1))
+		DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value);
+
+	return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
+}
+
+int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, 2))
+		DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value);
+
+	return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
+}
+
+int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
+{
+	if (match_write_sniff_ranges(addr, 4))
+		DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value);
+
+	return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
+}
+#endif
+
+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
+	
+	RTW_PUT_BE32((u8*)&cmd.value, (u32)us);
+
+	//DBG_871X("%s %u\n", __FUNCTION__, us);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
+}
+
+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
+	
+	RTW_PUT_BE32((u8*)&cmd.value, (u32)ms);
+
+	//DBG_871X("%s %u\n", __FUNCTION__, ms);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
+}
+
+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
+{	
+	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
+
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8*)&end_cmd, 8);
+
+}
+
+int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
+{
+	struct xmit_frame	*xmit_frame;
+
+	if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL)
+		return _FAIL;
+
+	if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL)
+		return _FAIL;
+
+	return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,0);
+}
+
+int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
+{
+	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
+	return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms);
+}
+#endif //CONFIG_IOL_NEW_GENERATION
+
+
+
+
+#endif //CONFIG_IOL
+

core/rtw_odm.c

@@ -0,0 +1,217 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include <rtw_odm.h>
+#ifdef CONFIG_RTL8192C
+#include <rtl8192c_hal.h>
+#endif
+#ifdef CONFIG_RTL8192D
+#include <rtl8192d_hal.h>
+#endif
+#ifdef CONFIG_RTL8723A
+#include <rtl8723a_hal.h>
+#endif
+#ifdef CONFIG_RTL8188E
+#include <rtl8188e_hal.h>
+#endif
+
+const char *odm_comp_str[] = {
+	"ODM_COMP_DIG",
+	"ODM_COMP_RA_MASK",
+	"ODM_COMP_DYNAMIC_TXPWR",
+	"ODM_COMP_FA_CNT",
+	"ODM_COMP_RSSI_MONITOR",
+	"ODM_COMP_CCK_PD",
+	"ODM_COMP_ANT_DIV",
+	"ODM_COMP_PWR_SAVE",
+	"ODM_COMP_PWR_TRAIN",
+	"ODM_COMP_RATE_ADAPTIVE",
+	"ODM_COMP_PATH_DIV",
+	"ODM_COMP_PSD",
+	"ODM_COMP_DYNAMIC_PRICCA",
+	"ODM_COMP_RXHP",
+	NULL,
+	NULL,
+	"ODM_COMP_EDCA_TURBO",
+	"ODM_COMP_EARLY_MODE",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"ODM_COMP_TX_PWR_TRACK",
+	"ODM_COMP_RX_GAIN_TRACK",
+	"ODM_COMP_CALIBRATION",
+	NULL,
+	NULL,
+	NULL,
+	"ODM_COMP_COMMON",
+	"ODM_COMP_INIT",
+};
+
+#define RTW_ODM_COMP_MAX 32
+
+const char *odm_ability_str[] = {
+	"ODM_BB_DIG",
+	"ODM_BB_RA_MASK",
+	"ODM_BB_DYNAMIC_TXPWR",
+	"ODM_BB_FA_CNT",
+	"ODM_BB_RSSI_MONITOR",
+	"ODM_BB_CCK_PD	",
+	"ODM_BB_ANT_DIV",
+	"ODM_BB_PWR_SAVE",
+	"ODM_BB_PWR_TRAIN",
+	"ODM_BB_RATE_ADAPTIVE",
+	"ODM_BB_PATH_DIV",
+	"ODM_BB_PSD",
+	"ODM_BB_RXHP",
+	"ODM_BB_ADAPTIVITY",
+	"ODM_BB_DYNAMIC_ATC",
+	NULL,
+	"ODM_MAC_EDCA_TURBO",
+	"ODM_MAC_EARLY_MODE",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"ODM_RF_TX_PWR_TRACK",
+	"ODM_RF_RX_GAIN_TRACK",
+	"ODM_RF_CALIBRATION",
+};
+
+#define RTW_ODM_ABILITY_MAX 27
+
+const char *odm_dbg_level_str[] = {
+	NULL,
+	"ODM_DBG_OFF",
+	"ODM_DBG_SERIOUS",
+	"ODM_DBG_WARNING",
+	"ODM_DBG_LOUD",
+	"ODM_DBG_TRACE	",
+};
+
+#define RTW_ODM_DBG_LEVEL_NUM 6
+
+int _rtw_odm_dbg_comp_msg(_adapter *adapter, char *buf, int len)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	DM_ODM_T *odm = &pHalData->odmpriv;
+	int cnt = 0;
+	u64 dbg_comp;
+	int i;
+
+	rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
+	cnt += snprintf(buf+cnt, len-cnt, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
+	for (i=0;i<RTW_ODM_COMP_MAX;i++) {
+		if (odm_comp_str[i])
+		cnt += snprintf(buf+cnt, len-cnt, "%cBIT%-2d %s\n",
+			(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
+	}
+
+	return cnt;
+}
+
+void rtw_odm_dbg_comp_msg(_adapter *adapter)
+{
+	char buf[768] = {0};
+
+	_rtw_odm_dbg_comp_msg(adapter, buf, 768);
+	DBG_871X_LEVEL(_drv_always_, "\n%s", buf);
+}
+
+inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
+{
+	rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
+}
+
+int _rtw_odm_dbg_level_msg(_adapter *adapter, char *buf, int len)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	DM_ODM_T *odm = &pHalData->odmpriv;
+	int cnt = 0;
+	u32 dbg_level;
+	int i;
+
+	rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
+	cnt += snprintf(buf+cnt, len-cnt, "odm.DebugDebugLevel = %u\n", dbg_level);
+	for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
+		if (odm_dbg_level_str[i])
+			cnt += snprintf(buf+cnt, len-cnt, "%u %s\n", i, odm_dbg_level_str[i]);
+	}
+
+	return cnt;
+}
+
+void rtw_odm_dbg_level_msg(_adapter *adapter)
+{
+	char buf[100] = {0};
+
+	_rtw_odm_dbg_comp_msg(adapter, buf, 100);
+	DBG_871X_LEVEL(_drv_always_, "\n%s", buf);
+}
+
+inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
+{
+	rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
+}
+
+int _rtw_odm_adaptivity_parm_msg(_adapter *adapter, char *buf, int len)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	DM_ODM_T *odm = &pHalData->odmpriv;
+
+	return snprintf(buf, len,
+		"%10s %16s %8s %10s %11s %14s\n"
+		"0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n",
+		"TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound",
+		(u8)odm->TH_L2H_ini,
+		odm->TH_EDCCA_HL_diff,
+		odm->IGI_Base,
+		odm->ForceEDCCA,
+		odm->AdapEn_RSSI,
+		odm->IGI_LowerBound
+	);
+}
+
+void rtw_odm_adaptivity_parm_msg(_adapter *adapter)
+{
+	char buf[256] = {0};
+
+	_rtw_odm_dbg_comp_msg(adapter, buf, 256);
+	DBG_871X_LEVEL(_drv_always_, "\n%s", buf);
+}
+
+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
+	s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	DM_ODM_T *odm = &pHalData->odmpriv;
+
+	odm->TH_L2H_ini = TH_L2H_ini;
+	odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
+	odm->IGI_Base = IGI_Base;
+	odm->ForceEDCCA = ForceEDCCA;
+	odm->AdapEn_RSSI = AdapEn_RSSI;
+	odm->IGI_LowerBound = IGI_LowerBound;
+}
+

core/rtw_rf.c

@@ -19,47 +19,51 @@
  ******************************************************************************/
 #define _RTW_RF_C_
 
+#include <drv_conf.h>
 #include <osdep_service.h>
 #include <drv_types.h>
 #include <recv_osdep.h>
 #include <xmit_osdep.h>
 
+
 struct ch_freq {
 	u32 channel;
 	u32 frequency;
 };
 
-static struct ch_freq ch_freq_map[] = {
+struct ch_freq ch_freq_map[] = {
-	{1, 2412}, {2, 2417}, {3, 2422}, {4, 2427}, {5, 2432},
+	{1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432},
-	{6, 2437}, {7, 2442}, {8, 2447}, {9, 2452}, {10, 2457},
+	{6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457},
-	{11, 2462}, {12, 2467}, {13, 2472}, {14, 2484},
+	{11, 2462},{12, 2467},{13, 2472},{14, 2484},
 	/*  UNII */
-	{36, 5180}, {40, 5200}, {44, 5220}, {48, 5240}, {52, 5260},
+	{36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260},
-	{56, 5280}, {60, 5300}, {64, 5320}, {149, 5745}, {153, 5765},
+	{56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765},
-	{157, 5785}, {161, 5805}, {165, 5825}, {167, 5835}, {169, 5845},
+	{157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845},
-	{171, 5855}, {173, 5865},
+	{171, 5855},{173, 5865},
 	/* HiperLAN2 */
-	{100, 5500}, {104, 5520}, {108, 5540}, {112, 5560}, {116, 5580},
+	{100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580},
-	{120, 5600}, {124, 5620}, {128, 5640}, {132, 5660}, {136, 5680},
+	{120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680},
 	{140, 5700},
 	/* Japan MMAC */
-	{34, 5170}, {38, 5190}, {42, 5210}, {46, 5230},
+	{34, 5170},{38, 5190},{42, 5210},{46, 5230},
 	/*  Japan */
-	{184, 4920}, {188, 4940}, {192, 4960}, {196, 4980},
+	{184, 4920},{188, 4940},{192, 4960},{196, 4980},
 	{208, 5040},/* Japan, means J08 */
 	{212, 5060},/* Japan, means J12 */
 	{216, 5080},/* Japan, means J16 */
 };
 
-static int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
+int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
 
 u32 rtw_ch2freq(u32 channel)
 {
 	u8	i;
 	u32	freq = 0;
 
-	for (i = 0; i < ch_freq_map_num; i++) {
+	for (i = 0; i < ch_freq_map_num; i++)
-		if (channel == ch_freq_map[i].channel) {
+	{
+		if (channel == ch_freq_map[i].channel)
+		{
 			freq = ch_freq_map[i].frequency;
 				break;
 		}
@@ -75,8 +79,10 @@ u32 rtw_freq2ch(u32 freq)
 	u8	i;
 	u32	ch = 0;
 
-	for (i = 0; i < ch_freq_map_num; i++) {
+	for (i = 0; i < ch_freq_map_num; i++)
-		if (freq == ch_freq_map[i].frequency) {
+	{
+		if (freq == ch_freq_map[i].frequency)
+		{
 			ch = ch_freq_map[i].channel;
 				break;
 		}
@@ -86,3 +92,4 @@ u32 rtw_freq2ch(u32 freq)
 
 	return ch;
 }
+

core/rtw_sreset.c

@@ -18,62 +18,339 @@
  *
  ******************************************************************************/
 
-#include <rtw_sreset.h>
+#include<rtw_sreset.h>
 
-void sreset_init_value(struct adapter *padapter)
+void sreset_init_value(_adapter *padapter)
 {
-	struct hal_data_8188e	*pHalData = GET_HAL_DATA(padapter);
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
 	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
 
 	_rtw_mutex_init(&psrtpriv->silentreset_mutex);
-	psrtpriv->silent_reset_inprogress = false;
+	psrtpriv->silent_reset_inprogress = _FALSE;
 	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
-	psrtpriv->last_tx_time = 0;
+	psrtpriv->last_tx_time =0;
-	psrtpriv->last_tx_complete_time = 0;
+	psrtpriv->last_tx_complete_time =0;
+#endif
 }
-void sreset_reset_value(struct adapter *padapter)
+void sreset_reset_value(_adapter *padapter)
 {
-	struct hal_data_8188e	*pHalData = GET_HAL_DATA(padapter);
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
 	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
 
-	psrtpriv->silent_reset_inprogress = false;
+	//psrtpriv->silent_reset_inprogress = _FALSE;
 	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
-	psrtpriv->last_tx_time = 0;
+	psrtpriv->last_tx_time =0;
-	psrtpriv->last_tx_complete_time = 0;
+	psrtpriv->last_tx_complete_time =0;
+#endif
 }
 
-u8 sreset_get_wifi_status(struct adapter *padapter)
+u8 sreset_get_wifi_status(_adapter *padapter)
 {
-	struct hal_data_8188e	*pHalData = GET_HAL_DATA(padapter);
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
 	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
 
 	u8 status = WIFI_STATUS_SUCCESS;
 	u32 val32 = 0;
-
+	_irqL irqL;
-	if (psrtpriv->silent_reset_inprogress)
+	if(psrtpriv->silent_reset_inprogress == _TRUE)
+        {
 		return status;
-	val32 = rtw_read32(padapter, REG_TXDMA_STATUS);
+	}
-	if (val32 == 0xeaeaeaea) {
+	val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
+	if(val32==0xeaeaeaea){
 		psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
-	} else if (val32 != 0) {
+	}
-		DBG_88E("txdmastatu(%x)\n", val32);
+	else if(val32!=0){
+		DBG_8192C("txdmastatu(%x)\n",val32);
 		psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
 	}
 
-	if (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) {
+	if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status)
-		DBG_88E("==>%s error_status(0x%x)\n", __func__, psrtpriv->Wifi_Error_Status);
+	{
-		status = (psrtpriv->Wifi_Error_Status & (~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
+		DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
+		status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
 	}
-	DBG_88E("==> %s wifi_status(0x%x)\n", __func__, status);
+	DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
 
-	/* status restore */
+	//status restore
 	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
 
 	return status;
+#else
+	return WIFI_STATUS_SUCCESS;
+#endif
 }
 
-void sreset_set_wifi_error_status(struct adapter *padapter, u32 status)
+void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
 {
-	struct hal_data_8188e	*pHalData = GET_HAL_DATA(padapter);
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
 	pHalData->srestpriv.Wifi_Error_Status = status;
+#endif
 }
+
+void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
+{
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	pHalData->srestpriv.dbg_trigger_point = tgp;
+#endif
+}
+
+bool sreset_inprogress(_adapter *padapter)
+{
+#if defined(DBG_CONFIG_ERROR_RESET)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	return pHalData->srestpriv.silent_reset_inprogress;
+#else
+	return _FALSE;
+#endif
+}
+
+void sreset_restore_security_station(_adapter *padapter)
+{
+	u8 EntryId = 0;
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+	struct sta_priv * pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	struct security_priv* psecuritypriv=&(padapter->securitypriv);
+	struct mlme_ext_info	*pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
+
+	{
+		u8 val8;
+
+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
+			val8 = 0xcc;
+		#ifdef CONFIG_WAPI_SUPPORT
+		} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
+			//Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey.
+			val8 = 0x4c;
+		#endif
+		} else {
+			val8 = 0xcf;
+		}
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
+	}
+
+	#if 0
+	if (	( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) ||
+		( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ ))
+	{
+
+		for(EntryId=0; EntryId<4; EntryId++)
+		{
+			if(EntryId == psecuritypriv->dot11PrivacyKeyIndex)
+				rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1,_FALSE);
+			else
+				rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0,_FALSE);
+		}
+
+	}
+	else
+	#endif
+	if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
+		(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
+	{
+		psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
+		if (psta == NULL) {
+			//DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
+		}
+		else
+		{
+			//pairwise key
+			rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE,_FALSE);
+			//group key
+			rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE);
+		}
+	}
+}
+
+void sreset_restore_network_station(_adapter *padapter)
+{
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	#if 0
+	{
+	//=======================================================
+	// reset related register of Beacon control
+
+	//set MSR to nolink
+	Set_MSR(padapter, _HW_STATE_NOLINK_);		
+	// reject all data frame
+	rtw_write16(padapter, REG_RXFLTMAP2,0x00);
+	//reset TSF
+	rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
+
+	// disable update TSF
+	SetBcnCtrlReg(padapter, BIT(4), 0);
+
+	//=======================================================
+	}
+	#endif
+	
+	rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_FALSE);
+
+	{
+		u8 threshold;
+		#ifdef CONFIG_USB_HCI
+		// TH=1 => means that invalidate usb rx aggregation
+		// TH=0 => means that validate usb rx aggregation, use init value.
+		if(mlmepriv->htpriv.ht_option) {
+			if(padapter->registrypriv.wifi_spec==1)		
+				threshold = 1;
+			else
+				threshold = 0;
+			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
+		} else {
+			threshold = 1;
+			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
+		}
+		#endif
+	}
+
+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+
+	//disable dynamic functions, such as high power, DIG
+	//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
+	
+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
+
+	{
+		u8	join_type = 0;
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+	}
+
+	Set_MSR(padapter, (pmlmeinfo->state & 0x3));
+
+	mlmeext_joinbss_event_callback(padapter, 1);
+	//restore Sequence No.
+	rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
+
+	sreset_restore_security_station(padapter);
+}
+
+
+void sreset_restore_network_status(_adapter *padapter)
+{
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
+		DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+		sreset_restore_network_station(padapter);
+	} else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
+		DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+		rtw_ap_restore_network(padapter);
+	} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
+		DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+	} else {
+		DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+	}
+}
+
+void sreset_stop_adapter(_adapter *padapter)
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+
+	if (padapter == NULL)
+		return;
+
+	DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	if (!rtw_netif_queue_stopped(padapter->pnetdev))
+		rtw_netif_stop_queue(padapter->pnetdev);
+
+	rtw_cancel_all_timer(padapter);
+
+	/* TODO: OS and HCI independent */
+	#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
+	tasklet_kill(&pxmitpriv->xmit_tasklet);
+	#endif
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
+		rtw_scan_abort(padapter);
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
+	{
+		rtw_set_roaming(padapter, 0);
+		_rtw_join_timeout_handler(padapter);
+	}
+
+}
+
+void sreset_start_adapter(_adapter *padapter)
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+
+	if (padapter == NULL)
+		return;
+
+	DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED)) {
+		sreset_restore_network_status(padapter);
+	}
+
+	/* TODO: OS and HCI independent */
+	#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+	#endif
+
+	_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
+
+	if (rtw_netif_queue_stopped(padapter->pnetdev))
+		rtw_netif_wake_queue(padapter->pnetdev);
+
+}
+
+void sreset_reset(_adapter *padapter)
+{
+#ifdef DBG_CONFIG_ERROR_RESET
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	_irqL irqL;
+	u32 start = rtw_get_current_time();
+
+	DBG_871X("%s\n", __FUNCTION__);
+
+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
+
+	_enter_pwrlock(&pwrpriv->lock);
+
+	psrtpriv->silent_reset_inprogress = _TRUE;
+	pwrpriv->change_rfpwrstate = rf_off;
+
+	sreset_stop_adapter(padapter);
+	#ifdef CONFIG_CONCURRENT_MODE
+	sreset_stop_adapter(padapter->pbuddy_adapter);
+	#endif
+
+	#ifdef CONFIG_IPS
+	_ips_enter(padapter);
+	_ips_leave(padapter);
+	#endif
+
+	sreset_start_adapter(padapter);
+	#ifdef CONFIG_CONCURRENT_MODE
+	sreset_start_adapter(padapter->pbuddy_adapter);
+	#endif
+
+	psrtpriv->silent_reset_inprogress = _FALSE;
+
+	_exit_pwrlock(&pwrpriv->lock);
+
+	DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
+#endif
+}
+

core/rtw_wapi_sms4.c

@@ -0,0 +1,923 @@
+#ifdef CONFIG_WAPI_SUPPORT
+
+#include <linux/unistd.h>
+#include <linux/etherdevice.h>
+#include <drv_types.h>
+#include <rtw_wapi.h>
+
+
+#ifdef CONFIG_WAPI_SW_SMS4
+
+#define WAPI_LITTLE_ENDIAN
+//#define BIG_ENDIAN
+#define ENCRYPT  0
+#define DECRYPT  1
+
+
+/**********************************************************
+ **********************************************************/
+const u8 Sbox[256] = {
+0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05,
+0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99,
+0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62,
+0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x94,0xfa,0x75,0x8f,0x3f,0xa6,
+0x47,0x07,0xa7,0xfc,0xf3,0x73,0x17,0xba,0x83,0x59,0x3c,0x19,0xe6,0x85,0x4f,0xa8,
+0x68,0x6b,0x81,0xb2,0x71,0x64,0xda,0x8b,0xf8,0xeb,0x0f,0x4b,0x70,0x56,0x9d,0x35,
+0x1e,0x24,0x0e,0x5e,0x63,0x58,0xd1,0xa2,0x25,0x22,0x7c,0x3b,0x01,0x21,0x78,0x87,
+0xd4,0x00,0x46,0x57,0x9f,0xd3,0x27,0x52,0x4c,0x36,0x02,0xe7,0xa0,0xc4,0xc8,0x9e,
+0xea,0xbf,0x8a,0xd2,0x40,0xc7,0x38,0xb5,0xa3,0xf7,0xf2,0xce,0xf9,0x61,0x15,0xa1,
+0xe0,0xae,0x5d,0xa4,0x9b,0x34,0x1a,0x55,0xad,0x93,0x32,0x30,0xf5,0x8c,0xb1,0xe3,
+0x1d,0xf6,0xe2,0x2e,0x82,0x66,0xca,0x60,0xc0,0x29,0x23,0xab,0x0d,0x53,0x4e,0x6f,
+0xd5,0xdb,0x37,0x45,0xde,0xfd,0x8e,0x2f,0x03,0xff,0x6a,0x72,0x6d,0x6c,0x5b,0x51,
+0x8d,0x1b,0xaf,0x92,0xbb,0xdd,0xbc,0x7f,0x11,0xd9,0x5c,0x41,0x1f,0x10,0x5a,0xd8,
+0x0a,0xc1,0x31,0x88,0xa5,0xcd,0x7b,0xbd,0x2d,0x74,0xd0,0x12,0xb8,0xe5,0xb4,0xb0,
+0x89,0x69,0x97,0x4a,0x0c,0x96,0x77,0x7e,0x65,0xb9,0xf1,0x09,0xc5,0x6e,0xc6,0x84,
+0x18,0xf0,0x7d,0xec,0x3a,0xdc,0x4d,0x20,0x79,0xee,0x5f,0x3e,0xd7,0xcb,0x39,0x48
+};
+
+const u32 CK[32] = {
+	0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
+	0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
+	0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
+	0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
+	0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
+	0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
+	0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
+	0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 };
+
+#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y))))
+
+#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \
+                     Sbox[(_A) >> 16 & 0xFF] << 16 | \
+                     Sbox[(_A) >>  8 & 0xFF] <<  8 | \
+                     Sbox[(_A) & 0xFF])
+
+#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24))
+#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23))
+
+static void
+xor_block(void *dst, void *src1, void *src2)
+/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned  */
+{
+    ((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0];
+    ((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1];
+    ((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2];
+    ((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3];
+}
+
+
+void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk)
+{
+	 u32 r, mid, x0, x1, x2, x3, *p;
+	 p = (u32 *)Input;
+	 x0 = p[0];
+	 x1 = p[1];
+	 x2 = p[2];
+	 x3 = p[3];
+#ifdef WAPI_LITTLE_ENDIAN
+	 x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
+	 x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
+	 x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
+	 x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
+#endif
+	 for (r = 0; r < 32; r += 4)
+	 {
+		  mid = x1 ^ x2 ^ x3 ^ rk[r + 0];
+		  mid = ByteSub(mid);
+		  x0 ^= L1(mid);
+		  mid = x2 ^ x3 ^ x0 ^ rk[r + 1];
+		  mid = ByteSub(mid);
+		  x1 ^= L1(mid);
+		  mid = x3 ^ x0 ^ x1 ^ rk[r + 2];
+		  mid = ByteSub(mid);
+		  x2 ^= L1(mid);
+		  mid = x0 ^ x1 ^ x2 ^ rk[r + 3];
+		  mid = ByteSub(mid);
+		  x3 ^= L1(mid);
+	 }
+#ifdef WAPI_LITTLE_ENDIAN
+	 x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
+	 x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
+	 x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
+	 x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
+#endif
+	 p = (u32 *)Output;
+	 p[0] = x3;
+	 p[1] = x2;
+	 p[2] = x1;
+	 p[3] = x0;
+}
+
+
+
+void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag)
+{
+	 u32 r, mid, x0, x1, x2, x3, *p;
+
+	 p = (u32 *)Key;
+	 x0 = p[0];
+	 x1 = p[1];
+	 x2 = p[2];
+	 x3 = p[3];
+#ifdef WAPI_LITTLE_ENDIAN
+	 x0 = Rotl(x0, 16); x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
+	 x1 = Rotl(x1, 16); x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
+	 x2 = Rotl(x2, 16); x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
+	 x3 = Rotl(x3, 16); x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
+#endif
+
+	 x0 ^= 0xa3b1bac6;
+	 x1 ^= 0x56aa3350;
+	 x2 ^= 0x677d9197;
+	 x3 ^= 0xb27022dc;
+	 for (r = 0; r < 32; r += 4)
+	 {
+		  mid = x1 ^ x2 ^ x3 ^ CK[r + 0];
+		  mid = ByteSub(mid);
+		  rk[r + 0] = x0 ^= L2(mid);
+		  mid = x2 ^ x3 ^ x0 ^ CK[r + 1];
+		  mid = ByteSub(mid);
+		  rk[r + 1] = x1 ^= L2(mid);
+		  mid = x3 ^ x0 ^ x1 ^ CK[r + 2];
+		  mid = ByteSub(mid);
+		  rk[r + 2] = x2 ^= L2(mid);
+		  mid = x0 ^ x1 ^ x2 ^ CK[r + 3];
+		  mid = ByteSub(mid);
+		  rk[r + 3] = x3 ^= L2(mid);
+	 }
+	 if (CryptFlag == DECRYPT)
+	 {
+	 	  for (r = 0; r < 16; r++)
+	 	  	 mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid;
+	 }
+}
+
+
+void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
+                                                u8 *Output, u16 *OutputLength, u32 CryptFlag)
+{
+	u32 blockNum,i,j, rk[32];
+	u16 remainder;
+	u8 blockIn[16],blockOut[16], tempIV[16], k;
+
+	*OutputLength = 0;
+	remainder = InputLength & 0x0F;
+	blockNum = InputLength >> 4;
+	if(remainder !=0)
+		blockNum++;
+	else
+		remainder = 16;
+
+	for(k=0;k<16;k++)
+		tempIV[k] = IV[15-k];
+
+	memcpy(blockIn, tempIV, 16);
+
+      SMS4KeyExt((u8 *)Key, rk,CryptFlag);
+
+	for(i=0; i<blockNum-1; i++)
+	{
+		SMS4Crypt((u8 *)blockIn, blockOut, rk);
+             xor_block(&Output[i*16], &Input[i*16], blockOut);
+		memcpy(blockIn,blockOut,16);
+	}
+
+	*OutputLength = i*16;
+
+	SMS4Crypt((u8 *)blockIn, blockOut, rk);
+
+	for(j=0; j<remainder; j++)
+	{
+		Output[i*16+j] = Input[i*16+j] ^ blockOut[j];
+	}
+      *OutputLength += remainder;
+
+}
+
+void WapiSMS4Encryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
+                                                    u8 *Output, u16 *OutputLength)
+{
+
+	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
+}
+
+void WapiSMS4Decryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
+                                                    u8 *Output, u16 *OutputLength)
+{
+	// OFB mode: is also ENCRYPT flag
+	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
+}
+
+void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length,
+                                                 u8 *Input2, u16 Input2Length, u8 *Output, u8 *OutputLength)
+{
+	u32 blockNum, i, remainder, rk[32];
+	u8 BlockIn[16], BlockOut[16], TempBlock[16], tempIV[16], k;
+
+	*OutputLength = 0;
+	remainder = Input1Length & 0x0F;
+	blockNum = Input1Length >> 4;
+
+	for(k=0;k<16;k++)
+		tempIV[k] = IV[15-k];
+
+	memcpy(BlockIn, tempIV, 16);
+
+	SMS4KeyExt((u8 *)Key, rk, ENCRYPT);
+
+	SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+
+	for(i=0; i<blockNum; i++){
+		xor_block(BlockIn, (Input1+i*16), BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	if(remainder !=0){
+		memset(TempBlock, 0, 16);
+		memcpy(TempBlock, (Input1+blockNum*16), remainder);
+
+		xor_block(BlockIn, TempBlock, BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+      }
+
+	remainder = Input2Length & 0x0F;
+	blockNum = Input2Length >> 4;
+
+  	for(i=0; i<blockNum; i++){
+		xor_block(BlockIn, (Input2+i*16), BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	if(remainder !=0){
+		memset(TempBlock, 0, 16);
+		memcpy(TempBlock, (Input2+blockNum*16), remainder);
+
+		xor_block(BlockIn, TempBlock, BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	memcpy(Output, BlockOut, 16);
+	*OutputLength = 16;
+}
+
+void SecCalculateMicSMS4(
+	u8		KeyIdx,
+	u8        *MicKey,
+	u8        *pHeader,
+	u8        *pData,
+	u16       DataLen,
+	u8        *MicBuffer
+	)
+{
+#if 0
+	struct ieee80211_hdr_3addr_qos *header;
+	u8 TempBuf[34], TempLen = 32, MicLen, QosOffset, *IV;
+	u16 *pTemp, fc;
+
+	WAPI_TRACE(WAPI_TX|WAPI_RX, "=========>%s\n", __FUNCTION__);
+
+	header = (struct ieee80211_hdr_3addr_qos *)pHeader;
+	memset(TempBuf, 0, 34);
+	memcpy(TempBuf, pHeader, 2); //FrameCtrl
+	pTemp = (u16*)TempBuf;
+	*pTemp &= 0xc78f;       //bit4,5,6,11,12,13
+
+	memcpy((TempBuf+2), (pHeader+4), 12); //Addr1, Addr2
+	memcpy((TempBuf+14), (pHeader+22), 2); // SeqCtrl
+	pTemp = (u16*)(TempBuf + 14);
+	*pTemp &= 0x000f;
+
+	memcpy((TempBuf+16), (pHeader+16), 6); //Addr3
+
+	fc = le16_to_cpu(header->frame_ctl);
+
+
+
+	if (GetFrDs((u16*)&fc) && GetToDs((u16 *)&fc))
+	{
+		memcpy((TempBuf+22), (pHeader+24), 6);
+		QosOffset = 30;
+	}else{
+		memset((TempBuf+22), 0, 6);
+		QosOffset = 24;
+	}
+
+	if((fc & 0x0088) == 0x0088){
+		memcpy((TempBuf+28), (pHeader+QosOffset), 2);
+		TempLen += 2;
+		//IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2;
+		IV = pHeader + QosOffset + 2 + 2;
+	}else{
+		IV = pHeader + QosOffset + 2;
+		//IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2;
+	}
+
+	TempBuf[TempLen-1] = (u8)(DataLen & 0xff);
+	TempBuf[TempLen-2] = (u8)((DataLen & 0xff00)>>8);
+	TempBuf[TempLen-4] = KeyIdx;
+
+	WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16);
+	WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16);
+	WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen);
+	WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen);
+
+	WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen,
+	                                             pData, DataLen, MicBuffer, &MicLen);
+
+	if (MicLen != 16)
+		WAPI_TRACE(WAPI_ERR,"%s: MIC Length Error!!\n",__FUNCTION__);
+
+	WAPI_TRACE(WAPI_TX|WAPI_RX, "<=========%s\n", __FUNCTION__);
+#endif
+}
+
+/* AddCount: 1 or 2.
+ *  If overflow, return 1,
+ *  else return 0.
+ */
+u8 WapiIncreasePN(u8 *PN, u8 AddCount)
+{
+	u8  i;
+
+	if (NULL == PN)
+		return 1;
+	//YJ,test,091102
+	/*
+	if(AddCount == 2){
+		DBG_8192C("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]);
+		if(PN[0] == 0x48){
+			PN[0] += AddCount;
+			return 1;
+		}else{
+			PN[0] += AddCount;
+			return 0;
+		}
+	}
+	*/
+	//YJ,test,091102,end
+
+	for (i=0; i<16; i++)
+	{
+		if (PN[i] + AddCount <= 0xff)
+		{
+			PN[i] += AddCount;
+			return 0;
+		}
+		else
+		{
+			PN[i] += AddCount;
+			AddCount = 1;
+		}
+	}
+	return 1;
+}
+
+
+void WapiGetLastRxUnicastPNForQoSData(
+	u8 			UserPriority,
+	PRT_WAPI_STA_INFO    pWapiStaInfo,
+	u8 *PNOut
+)
+{
+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
+	switch(UserPriority)
+	{
+		case 0:
+		case 3:
+			      memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBEQueue,16);
+			      break;
+		case 1:
+		case 2:
+			      memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBKQueue,16);
+			      break;
+		case 4:
+		case 5:
+			      memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVIQueue,16);
+			      break;
+		case 6:
+		case 7:
+			      memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVOQueue,16);
+			      break;
+		default:
+				WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__);
+				break;
+	}
+	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
+}
+
+
+void WapiSetLastRxUnicastPNForQoSData(
+	u8 		UserPriority,
+	u8           *PNIn,
+	PRT_WAPI_STA_INFO    pWapiStaInfo
+)
+{
+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
+	switch(UserPriority)
+	{
+		case 0:
+		case 3:
+			      memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue,PNIn,16);
+			      break;
+		case 1:
+		case 2:
+			      memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue,PNIn,16);
+			      break;
+		case 4:
+		case 5:
+			      memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue,PNIn,16);
+			      break;
+		case 6:
+		case 7:
+			      memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue,PNIn,16);
+			      break;
+		default:
+				WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__);
+				break;
+	}
+	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
+}
+
+
+/****************************************************************************
+ FALSE not RX-Reorder
+ TRUE do RX Reorder
+add to support WAPI to N-mode
+*****************************************************************************/
+u8 WapiCheckPnInSwDecrypt(
+	_adapter *padapter,
+	struct sk_buff *pskb
+)
+{
+	u8 				ret = false;
+
+#if 0
+	struct ieee80211_hdr_3addr_qos *header;
+	u16 				fc;
+	u8				*pDaddr, *pTaddr, *pRaddr;
+
+	header = (struct ieee80211_hdr_3addr_qos *)pskb->data;
+	pTaddr = header->addr2;
+	pRaddr = header->addr1;
+	fc = le16_to_cpu(header->frame_ctl);
+
+	if(GetToDs(&fc))
+		pDaddr = header->addr3;
+	else
+		pDaddr = header->addr1;
+
+	if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0)
+		&&	! (pDaddr)
+		&& (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE))
+		//&& ieee->pHTInfo->bCurrentHTSupport &&
+		//ieee->pHTInfo->bCurRxReorderEnable)
+		ret = false;
+	else
+		ret = true;
+#endif
+	WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret);
+	return ret;
+}
+
+int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe)
+{
+	struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib;
+	u8 * frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
+	u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL;
+	u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0;
+	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
+	int ret = 0;
+
+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
+
+	return ret;
+#if 0
+	hdr_len = sMacHdrLng;
+	if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE)
+	{
+		hdr_len += 2;
+	}
+	//hdr_len += SNAP_SIZE + sizeof(u16);
+
+	pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len);
+	memmove(pos, pos+padapter->wapiInfo.extra_prefix_len, hdr_len);
+
+	pSecHeader = pskb->data + hdr_len;
+	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader;
+	pRA = pskb->data + 4;
+
+	WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len);
+
+	//Address 1 is always receiver's address
+	if( IS_MCAST(pRA) ){
+		if(!pWapiInfo->wapiTxMsk.bTxEnable){
+			WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__);
+			return -2;
+		}
+		if(pWapiInfo->wapiTxMsk.keyId <= 1){
+			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
+			pWapiExt->Reserved = 0;
+			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
+			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
+			if (bPNOverflow){
+				// Update MSK Notification.
+				WAPI_TRACE(WAPI_ERR,"===============>%s():multicast PN overflow\n",__FUNCTION__);
+				rtw_wapi_app_event_handler(padapter,NULL,0,pRA, false, false, true, 0, false);
+			}
+		}else{
+			WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Multicast KeyIdx!!\n",__FUNCTION__);
+			ret = -3;
+		}
+	}
+    	else{
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if(!memcmp(pWapiSta->PeerMacAddr,pRA,6)){
+    				bFindMatchPeer = true;
+				break;
+			}
+		}
+		if (bFindMatchPeer){
+			if((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)){
+				WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__);
+				return -4;
+			}
+			if (pWapiSta->wapiUsk.keyId <= 1){
+				if(pWapiSta->wapiUskUpdate.bTxEnable)
+					pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
+				else
+					pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
+
+				pWapiExt->Reserved = 0;
+				bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
+				memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
+				if (bPNOverflow){
+					// Update USK Notification.
+					WAPI_TRACE(WAPI_ERR,"===============>%s():unicast PN overflow\n",__FUNCTION__);
+					rtw_wapi_app_event_handler(padapter,NULL,0,pWapiSta->PeerMacAddr, false, true, false, 0, false);
+				}
+			}else{
+				WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Unicast KeyIdx!!\n",__FUNCTION__);
+				ret = -5;
+			}
+		}
+		else{
+			WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta "MAC_FMT"!!\n",__FUNCTION__, MAC_ARG(pRA));
+			ret = -6;
+		}
+    	}
+
+	WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len);
+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
+	return ret;
+#endif
+}
+
+// WAPI SW Enc: must have done Coalesce!
+void SecSWSMS4Encryption(
+	_adapter *padapter,
+	u8 * pxmitframe
+	)
+{
+	PRT_WAPI_T		pWapiInfo = &padapter->wapiInfo;
+	PRT_WAPI_STA_INFO   pWapiSta = NULL;
+	u8 *pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE;
+	struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib;
+
+	u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL;
+	u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16];
+	u16 OutputLength;
+
+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
+
+	WAPI_TRACE(WAPI_TX,"hdrlen: %d \n",pattrib->hdrlen);
+
+	return;
+
+	DataOffset = pattrib->hdrlen + pattrib->iv_len;
+
+	pRA = pframe + 4;
+
+
+	if( IS_MCAST(pRA) ){
+		KeyIdx = pWapiInfo->wapiTxMsk.keyId;
+		pIV = pWapiInfo->lastTxMulticastPN;
+		pMicKey = pWapiInfo->wapiTxMsk.micKey;
+		pDataKey = pWapiInfo->wapiTxMsk.dataKey;
+	}else{
+		if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){
+			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+				if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)){
+					bFindMatchPeer = true;
+					break;
+				}
+			}
+
+			if (bFindMatchPeer){
+				if (pWapiSta->wapiUskUpdate.bTxEnable){
+					KeyIdx = pWapiSta->wapiUskUpdate.keyId;
+					WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
+					pIV = pWapiSta->lastTxUnicastPN;
+					pMicKey = pWapiSta->wapiUskUpdate.micKey;
+					pDataKey = pWapiSta->wapiUskUpdate.dataKey;
+				}else{
+					KeyIdx = pWapiSta->wapiUsk.keyId;
+					WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
+					pIV = pWapiSta->lastTxUnicastPN;
+					pMicKey = pWapiSta->wapiUsk.micKey;
+					pDataKey = pWapiSta->wapiUsk.dataKey;
+				}
+  			}else{
+				WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta!!\n",__FUNCTION__);
+				return;
+			}
+		}else{
+			WAPI_TRACE(WAPI_ERR,"%s: wapiSTAUsedList is empty!!\n",__FUNCTION__);
+			return;
+		}
+	}
+
+	SecPtr = pframe;
+	SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr+DataOffset), pattrib->pktlen, MicBuffer);
+
+	WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len);
+
+	memcpy(pframe+pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen-pattrib->icv_len,
+			(u8 *)MicBuffer,
+			padapter->wapiInfo.extra_postfix_len
+			);
+
+
+	WapiSMS4Encryption(pDataKey, pIV, (SecPtr+DataOffset),pattrib->pktlen+pattrib->icv_len, (SecPtr+DataOffset), &OutputLength);
+
+	WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption",pframe,pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen);
+
+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
+}
+
+u8 SecSWSMS4Decryption(
+	_adapter *padapter,
+	u8 		*precv_frame,
+	struct recv_priv *precv_priv
+	)
+{
+	PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
+	struct recv_frame_hdr *precv_hdr;
+	PRT_WAPI_STA_INFO   pWapiSta = NULL;
+	u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false;
+	u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16];
+	u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos;
+	u8 TID = 0;
+	u16 OutputLength, DataLen;
+	u8   bQosData;
+	struct sk_buff * 	pskb;
+
+	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
+
+	return 0;
+
+	precv_hdr = &((union recv_frame*)precv_frame)->u.hdr;
+	pskb = (struct sk_buff *)(precv_hdr->rx_data);
+	precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb);
+	WAPI_TRACE(WAPI_RX, "=========>%s: check PN  %d\n", __FUNCTION__,precv_hdr->bWapiCheckPNInDecrypt);
+	WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len);
+
+	IVOffset = sMacHdrLng;
+	bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE;
+	if (bQosData){
+		IVOffset += 2;
+	}
+
+	//if(GetHTC())
+	//	IVOffset += 4;
+
+	//IVOffset += SNAP_SIZE + sizeof(u16);
+
+	DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len;
+
+	pRA = pskb->data + 4;
+	pTA = pskb->data + 10;
+	KeyIdx = *(pskb->data + IVOffset);
+	pRecvPN = pskb->data + IVOffset + 2;
+	pSecData = pskb->data + DataOffset;
+	DataLen = pskb->len - DataOffset;
+	pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len;
+	TID = GetTid(pskb->data);
+
+	if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)){
+				bFindMatchPeer = true;
+				break;
+			}
+		}
+	}
+
+	if (!bFindMatchPeer){
+		WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA));
+		return false;
+	}
+
+	if( IS_MCAST(pRA) ){
+		WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__);
+		if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet){
+			pLastRxPN = pWapiSta->lastRxMulticastPN;
+			if (!WapiComparePN(pRecvPN, pLastRxPN)){
+				WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__);
+				WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16);
+				WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16);
+				return false;
+			}
+
+			memcpy(pLastRxPN, pRecvPN, 16);
+			pMicKey = pWapiSta->wapiMsk.micKey;
+			pDataKey = pWapiSta->wapiMsk.dataKey;
+		}else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet){
+			WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__);
+			bUseUpdatedKey = true;
+			memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16);
+			pMicKey = pWapiSta->wapiMskUpdate.micKey;
+			pDataKey = pWapiSta->wapiMskUpdate.dataKey;
+		}else{
+			WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__,KeyIdx);
+			return false;
+		}
+	}
+	else{
+		WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__);
+		if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet){
+			WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__);
+			if(precv_hdr->bWapiCheckPNInDecrypt){
+				if(GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE){
+					WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS);
+					pLastRxPN = lastRxPNforQoS;
+				}else{
+					pLastRxPN = pWapiSta->lastRxUnicastPN;
+				}
+				if (!WapiComparePN(pRecvPN, pLastRxPN)){
+					return false;
+				}
+				if(bQosData){
+					WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
+				}else{
+					memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
+				}
+			}else{
+				memcpy(precv_hdr->WapiTempPN,pRecvPN,16);
+			}
+
+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE))
+			{
+				if ((pRecvPN[0] & 0x1) == 0){
+					WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__);
+					return false;
+				}
+			}
+
+			pMicKey = pWapiSta->wapiUsk.micKey;
+			pDataKey = pWapiSta->wapiUsk.dataKey;
+		}
+		else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet ){
+			WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__);
+			if(pWapiSta->bAuthenticatorInUpdata)
+				bUseUpdatedKey = true;
+			else
+				bUseUpdatedKey = false;
+
+			if(bQosData){
+				WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
+			}else{
+				memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
+			}
+			pMicKey = pWapiSta->wapiUskUpdate.micKey;
+			pDataKey = pWapiSta->wapiUskUpdate.dataKey;
+		}else{
+			WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId, pWapiSta->wapiUskUpdate.keyId);
+			//dump_buf(pskb->data,pskb->len);
+			return false;
+		}
+	}
+
+	WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16);
+	WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16);
+	WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength);
+
+	if (OutputLength != DataLen)
+		WAPI_TRACE(WAPI_ERR, "%s:  Output Length Error!!!!\n", __FUNCTION__);
+
+	WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len);
+
+	DataLen -= padapter->wapiInfo.extra_postfix_len;
+
+	SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer);
+
+	WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN);
+	WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN);
+
+	if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)){
+		WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__);
+		if (bUseUpdatedKey){
+			// delete the old key
+			if ( IS_MCAST(pRA) ){
+				WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__);
+				pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId;
+				memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16);
+				memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16);
+				pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false;
+			}else{
+				WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__);
+				pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
+				memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
+				memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
+				pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false;
+			}
+		}
+	}else{
+		WAPI_TRACE(WAPI_ERR, "%s:  Check MIC Error, Dropped !!!!\n", __FUNCTION__);
+		return false;
+	}
+
+	pos = pskb->data;
+	memmove(pos+padapter->wapiInfo.extra_prefix_len, pos, IVOffset);
+	skb_pull(pskb, padapter->wapiInfo.extra_prefix_len);
+
+	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
+
+	return true;
+}
+
+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+
+	u8	*pframe;
+	u32 res = _SUCCESS;
+
+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable))
+	{
+		WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+	if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL)
+		return _FAIL;
+
+	pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET;
+
+	SecSWSMS4Encryption(padapter, pxmitframe);
+
+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
+	return res;
+}
+
+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
+{
+	u8	*pframe;
+	u32 res = _SUCCESS;
+
+	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable))
+	{
+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+
+	//drop packet when hw decrypt fail
+       //return tempraily
+	return _FAIL;
+
+	//pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data;
+
+	if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv))
+	{
+		WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n",__FUNCTION__);
+		return _FAIL;
+	}
+
+	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
+	return res;
+}
+
+#else
+
+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+	WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__);
+	WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__);
+	return _SUCCESS;
+}
+
+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
+{
+	WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__);
+	WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__);
+	return _SUCCESS;
+}
+
+#endif
+
+#endif

hal/HalPwrSeqCmd.c

@@ -33,100 +33,155 @@ Major Change History:
 	2011-07-07 Roger            Create.
 
 --*/
-
 #include <HalPwrSeqCmd.h>
+#ifdef CONFIG_SDIO_HCI
+#include <sdio_ops.h>
+#elif defined(CONFIG_GSPI_HCI)
+#include <gspi_ops.h>
+#endif
 
-/*	Description: */
+//
-/*		This routine deals with the Power Configuration CMDs parsing
+//	Description:
- *		for RTL8723/RTL8188E Series IC.
+//		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
- *	Assumption:
+//
- *		We should follow specific format which was released from HW SD.
+//	Assumption:
- */
+//		We should follow specific format which was released from HW SD.
-u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
+//
-		       u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[])
+//	2011.07.07, added by Roger.
+//
+u8 HalPwrSeqCmdParsing(
+	PADAPTER		padapter,
+	u8				CutVersion,
+	u8				FabVersion,
+	u8				InterfaceType,
+	WLAN_PWR_CFG	PwrSeqCmd[])
 {
-	struct wl_pwr_cfg pwrcfgcmd = {0};
+	WLAN_PWR_CFG 	PwrCfgCmd = {0};
-	u8 poll_bit = false;
+	u8				bPollingBit = _FALSE;
-	u32 aryidx = 0;
+	u32				AryIdx = 0;
-	u8 value = 0;
+	u8				value = 0;
-	u32 offset = 0;
+	u32				offset = 0;
-	u32 poll_count = 0; /*  polling autoload done. */
+	u32				pollingCount = 0; // polling autoload done.
-	u32 max_poll_count = 5000;
+	u32				maxPollingCnt = 5000;
 
 	do {
-		pwrcfgcmd = pwrseqcmd[aryidx];
+		PwrCfgCmd = PwrSeqCmd[AryIdx];
 
 		RT_TRACE(_module_hal_init_c_ , _drv_info_,
-			 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
+				 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
-			 GET_PWR_CFG_OFFSET(pwrcfgcmd),
+					GET_PWR_CFG_OFFSET(PwrCfgCmd),
-			 GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
+					GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
-			 GET_PWR_CFG_FAB_MASK(pwrcfgcmd),
+					GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
-			 GET_PWR_CFG_INTF_MASK(pwrcfgcmd),
+					GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
-			 GET_PWR_CFG_BASE(pwrcfgcmd),
+					GET_PWR_CFG_BASE(PwrCfgCmd),
-			 GET_PWR_CFG_CMD(pwrcfgcmd),
+					GET_PWR_CFG_CMD(PwrCfgCmd),
-			 GET_PWR_CFG_MASK(pwrcfgcmd),
+					GET_PWR_CFG_MASK(PwrCfgCmd),
-			 GET_PWR_CFG_VALUE(pwrcfgcmd)));
+					GET_PWR_CFG_VALUE(PwrCfgCmd)));
 
-		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
+		//2 Only Handle the command whose FAB, CUT, and Interface are matched
-		if ((GET_PWR_CFG_FAB_MASK(pwrcfgcmd) & fab_vers) &&
+		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
-		    (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) &&
+			(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
-		    (GET_PWR_CFG_INTF_MASK(pwrcfgcmd) & ifacetype)) {
+			(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
-			switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
+		{
-			case PWR_CMD_READ:
+			switch (GET_PWR_CFG_CMD(PwrCfgCmd))
-				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
+			{
-				break;
+				case PWR_CMD_READ:
-			case PWR_CMD_WRITE:
+					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
-				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
+					break;
-				offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
 
-				/*  Read the value from system register */
+				case PWR_CMD_WRITE:
-				value = rtw_read8(padapter, offset);
+					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
+					offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
 
-				value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
+#ifdef CONFIG_SDIO_HCI
-				value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd));
+					//
+					// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
+					// 2011.07.07.
+					//
+					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
+					{
+						// Read Back SDIO Local value
+						value = SdioLocalCmd52Read1Byte(padapter, offset);
 
-				/*  Write the value back to system register */
+						value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
-				rtw_write8(padapter, offset, value);
+						value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
-				break;
-			case PWR_CMD_POLLING:
-				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
 
-				poll_bit = false;
+						// Write Back SDIO Local value
-				offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
+						SdioLocalCmd52Write1Byte(padapter, offset, value);
-				do {
+					}
+					else
+#endif
+					{
+#ifdef CONFIG_GSPI_HCI
+						if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
+							offset = SPI_LOCAL_OFFSET | offset;
+#endif
+						// Read the value from system register
 						value = rtw_read8(padapter, offset);
 
-					value &= GET_PWR_CFG_MASK(pwrcfgcmd);
+						value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
-					if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))
+						value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
-						poll_bit = true;
-					else
-						rtw_udelay_os(10);
 
-					if (poll_count++ > max_poll_count) {
+						// Write the value back to sytem register
-						DBG_88E("Fail to polling Offset[%#x]\n", offset);
+						rtw_write8(padapter, offset, value);
-						return false;
 					}
-				} while (!poll_bit);
+					break;
-				break;
+
-			case PWR_CMD_DELAY:
+				case PWR_CMD_POLLING:
-				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
+					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
-				if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
+
-					rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd));
+					bPollingBit = _FALSE;
-				else
+					offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
-					rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
+#ifdef CONFIG_GSPI_HCI
-				break;
+					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-			case PWR_CMD_END:
+						offset = SPI_LOCAL_OFFSET | offset;
-				/*  When this command is parsed, end the process */
+#endif
-				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
+					do {
-				return true;
+#ifdef CONFIG_SDIO_HCI
-				break;
+						if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-			default:
+							value = SdioLocalCmd52Read1Byte(padapter, offset);
-				RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
+						else
-				break;
+#endif
+							value = rtw_read8(padapter, offset);
+
+						value &= GET_PWR_CFG_MASK(PwrCfgCmd);
+						if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
+							bPollingBit = _TRUE;
+						else
+							rtw_udelay_os(10);
+
+						if (pollingCount++ > maxPollingCnt) {
+							DBG_871X("Fail to polling Offset[%#x]\n", offset);
+							return _FALSE;
+						}
+					} while (!bPollingBit);
+
+					break;
+
+				case PWR_CMD_DELAY:
+					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
+					if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
+						rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
+					else
+						rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
+					break;
+
+				case PWR_CMD_END:
+					// When this command is parsed, end the process
+					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
+					return _TRUE;
+					break;
+
+				default:
+					RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
+					break;
 			}
 		}
 
-		aryidx++;/* Add Array Index */
+		AryIdx++;//Add Array Index
-	} while (1);
+	}while(1);
-	return true;
+
+	return _TRUE;
 }
+
+

hal/OUTSRC/HalPhyRf.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+ #ifndef __HAL_PHY_RF_H__
+ #define __HAL_PHY_RF_H__
+ 
+ #if(DM_ODM_SUPPORT_TYPE & ODM_MP)
+ #define MAX_TOLERANCE		5
+ #define IQK_DELAY_TIME		1		//ms
+ 
+ //
+// BB/MAC/RF other monitor API
+//
+
+void	PHY_SetMonitorMode8192C(IN	PADAPTER	pAdapter,
+										IN	BOOLEAN		bEnableMonitorMode	);
+										
+//
+// IQ calibrate
+//
+void	
+PHY_IQCalibrate_8192C(		IN	PADAPTER	pAdapter,	
+							IN	BOOLEAN 	bReCovery);
+							
+//
+// LC calibrate
+//
+void	
+PHY_LCCalibrate_8192C(		IN	PADAPTER	pAdapter);
+
+//
+// AP calibrate
+//
+void	
+PHY_APCalibrate_8192C(		IN	PADAPTER	pAdapter,
+								IN 	s1Byte		delta);
+#endif
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+VOID
+ODM_ResetIQKResult(
+	IN PDM_ODM_T	pDM_Odm 
+);
+u1Byte 
+ODM_GetRightChnlPlaceforIQK(
+    IN u1Byte chnl
+);
+
+
+#endif	// #ifndef __HAL_PHY_RF_H__
+

hal/OUTSRC/odm_HWConfig.h

@@ -0,0 +1,195 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__HALHWOUTSRC_H__
+#define __HALHWOUTSRC_H__
+
+//============================================================
+// Definition 
+//============================================================
+//
+//-----------------------------------------------------------
+// CCK Rates, TxHT = 0
+#define DESC92C_RATE1M					0x00
+#define DESC92C_RATE2M					0x01
+#define DESC92C_RATE5_5M				0x02
+#define DESC92C_RATE11M				0x03
+
+// OFDM Rates, TxHT = 0
+#define DESC92C_RATE6M					0x04
+#define DESC92C_RATE9M					0x05
+#define DESC92C_RATE12M				0x06
+#define DESC92C_RATE18M				0x07
+#define DESC92C_RATE24M				0x08
+#define DESC92C_RATE36M				0x09
+#define DESC92C_RATE48M				0x0a
+#define DESC92C_RATE54M				0x0b
+
+// MCS Rates, TxHT = 1
+#define DESC92C_RATEMCS0				0x0c
+#define DESC92C_RATEMCS1				0x0d
+#define DESC92C_RATEMCS2				0x0e
+#define DESC92C_RATEMCS3				0x0f
+#define DESC92C_RATEMCS4				0x10
+#define DESC92C_RATEMCS5				0x11
+#define DESC92C_RATEMCS6				0x12
+#define DESC92C_RATEMCS7				0x13
+#define DESC92C_RATEMCS8				0x14
+#define DESC92C_RATEMCS9				0x15
+#define DESC92C_RATEMCS10				0x16
+#define DESC92C_RATEMCS11				0x17
+#define DESC92C_RATEMCS12				0x18
+#define DESC92C_RATEMCS13				0x19
+#define DESC92C_RATEMCS14				0x1a
+#define DESC92C_RATEMCS15				0x1b
+#define DESC92C_RATEMCS15_SG			0x1c
+#define DESC92C_RATEMCS32				0x20
+
+
+//============================================================
+// structure and define
+//============================================================
+
+typedef struct _Phy_Rx_AGC_Info
+{
+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+		u1Byte	gain:7,trsw:1;			
+	#else			
+		u1Byte	trsw:1,gain:7;
+	#endif
+} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
+
+typedef struct _Phy_Status_Rpt_8192cd
+{
+	PHY_RX_AGC_INFO_T path_agc[2];
+	u1Byte 	ch_corr[2];									
+	u1Byte	cck_sig_qual_ofdm_pwdb_all;
+	u1Byte	cck_agc_rpt_ofdm_cfosho_a;
+	u1Byte	cck_rpt_b_ofdm_cfosho_b;
+	u1Byte 	rsvd_1;//ch_corr_msb;
+	u1Byte 	noise_power_db_msb;
+	u1Byte	path_cfotail[2];	
+	u1Byte	pcts_mask[2];	
+	s1Byte	stream_rxevm[2];	
+	u1Byte	path_rxsnr[2];
+	u1Byte 	noise_power_db_lsb;
+	u1Byte	rsvd_2[3];
+	u1Byte 	stream_csi[2];
+	u1Byte 	stream_target_csi[2];
+	s1Byte 	sig_evm;
+	u1Byte 	rsvd_3;	
+
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+	u1Byte 	antsel_rx_keep_2:1;	//ex_intf_flg:1;
+	u1Byte 	sgi_en:1;
+	u1Byte 	rxsc:2;	
+	u1Byte 	idle_long:1;
+	u1Byte 	r_ant_train_en:1;
+	u1Byte 	ant_sel_b:1;
+	u1Byte 	ant_sel:1;	
+#else	// _BIG_ENDIAN_	
+	u1Byte 	ant_sel:1;	
+	u1Byte 	ant_sel_b:1;
+	u1Byte 	r_ant_train_en:1;
+	u1Byte 	idle_long:1;
+	u1Byte 	rxsc:2;
+	u1Byte 	sgi_en:1;
+	u1Byte 	antsel_rx_keep_2:1;	//ex_intf_flg:1;
+#endif
+} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
+
+
+typedef struct _Phy_Status_Rpt_8195
+{
+	PHY_RX_AGC_INFO_T path_agc[2];
+	u1Byte 	ch_num[2];									
+	u1Byte	cck_sig_qual_ofdm_pwdb_all;
+	u1Byte	cck_agc_rpt_ofdm_cfosho_a;
+	u1Byte	cck_bb_pwr_ofdm_cfosho_b;
+	u1Byte    cck_rx_path;	//CCK_RX_PATH [3:0] (with regA07[3:0] definition)	
+	u1Byte 	rsvd_1;	
+	u1Byte	path_cfotail[2];	
+	u1Byte	pcts_mask[2];	
+	s1Byte	stream_rxevm[2];	
+	u1Byte	path_rxsnr[2];
+	u1Byte	rsvd_2[2];	
+	u1Byte 	stream_snr[2];	
+	u1Byte 	stream_csi[2];
+	u1Byte	rsvd_3[2];
+	s1Byte 	sig_evm;
+	u1Byte 	rsvd_4;	
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+	u1Byte 	antidx_anta:3;
+	u1Byte 	antidx_antb:3;
+	u1Byte 	rsvd_5:2;
+#else	// _BIG_ENDIAN_	
+	u1Byte 	rsvd_5:2;
+	u1Byte 	antidx_antb:3;
+	u1Byte 	antidx_anta:3;	
+#endif
+} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
+
+
+VOID
+odm_Init_RSSIForDM(
+	IN OUT	PDM_ODM_T	pDM_Odm
+	);
+
+VOID
+ODM_PhyStatusQuery(
+	IN OUT	PDM_ODM_T					pDM_Odm,
+	OUT		PODM_PHY_INFO_T			pPhyInfo,
+	IN 		pu1Byte						pPhyStatus,	
+	IN		PODM_PACKET_INFO_T			pPktinfo
+	);
+
+VOID
+ODM_MacStatusQuery(
+	IN OUT	PDM_ODM_T					pDM_Odm,
+	IN 		pu1Byte						pMacStatus,
+	IN		u1Byte						MacID,	
+	IN		BOOLEAN						bPacketMatchBSSID,
+	IN		BOOLEAN						bPacketToSelf,
+	IN		BOOLEAN						bPacketBeacon
+	);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP))
+HAL_STATUS
+ODM_ConfigRFWithHeaderFile(
+	IN	PDM_ODM_T	      pDM_Odm,
+	IN 	ODM_RF_RADIO_PATH_E 	Content,
+	IN 	ODM_RF_RADIO_PATH_E 	eRFPath
+	);
+
+HAL_STATUS
+ODM_ConfigBBWithHeaderFile(
+	IN  	PDM_ODM_T	                	pDM_Odm,
+	IN	ODM_BB_Config_Type		ConfigType
+    );
+
+HAL_STATUS
+ODM_ConfigMACWithHeaderFile(
+	IN  	PDM_ODM_T	pDM_Odm
+    );
+#endif
+
+
+#endif
+

hal/OUTSRC/odm_RegDefine11AC.h

@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__ODM_REGDEFINE11AC_H__
+#define __ODM_REGDEFINE11AC_H__
+
+//2 RF REG LIST
+
+
+
+//2 BB REG LIST
+//PAGE 8
+//PAGE 9
+#define	ODM_REG_OFDM_FA_RST_11AC		0x9A4
+//PAGE A
+#define	ODM_REG_CCK_CCA_11AC				0xA0A
+#define	ODM_REG_CCK_FA_RST_11AC			0xA2C
+#define	ODM_REG_CCK_FA_11AC				0xA5C
+//PAGE C
+#define	ODM_REG_IGI_A_11AC				0xC50
+//PAGE E
+#define	ODM_REG_IGI_B_11AC				0xE50
+//PAGE F
+#define	ODM_REG_OFDM_FA_11AC			0xF48
+
+
+//2 MAC REG LIST
+
+
+
+
+//DIG Related
+#define	ODM_BIT_IGI_11AC				0xFFFFFFFF
+
+
+
+#endif
+

hal/OUTSRC/odm_RegDefine11N.h

@@ -0,0 +1,172 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__ODM_REGDEFINE11N_H__
+#define __ODM_REGDEFINE11N_H__
+
+
+//2 RF REG LIST
+#define	ODM_REG_RF_MODE_11N				0x00
+#define	ODM_REG_RF_0B_11N				0x0B
+#define	ODM_REG_CHNBW_11N				0x18
+#define	ODM_REG_T_METER_11N				0x24
+#define	ODM_REG_RF_25_11N				0x25
+#define	ODM_REG_RF_26_11N				0x26
+#define	ODM_REG_RF_27_11N				0x27
+#define	ODM_REG_RF_2B_11N				0x2B
+#define	ODM_REG_RF_2C_11N				0x2C
+#define	ODM_REG_RXRF_A3_11N				0x3C
+#define	ODM_REG_T_METER_92D_11N			0x42
+#define	ODM_REG_T_METER_88E_11N			0x42
+
+
+
+//2 BB REG LIST
+//PAGE 8
+#define	ODM_REG_BB_CTRL_11N				0x800
+#define	ODM_REG_RF_PIN_11N				0x804
+#define	ODM_REG_PSD_CTRL_11N				0x808
+#define	ODM_REG_TX_ANT_CTRL_11N			0x80C
+#define	ODM_REG_BB_PWR_SAV5_11N			0x818
+#define	ODM_REG_CCK_RPT_FORMAT_11N		0x824
+#define	ODM_REG_RX_DEFUALT_A_11N		0x858
+#define	ODM_REG_RX_DEFUALT_B_11N		0x85A
+#define	ODM_REG_BB_PWR_SAV3_11N			0x85C
+#define	ODM_REG_ANTSEL_CTRL_11N			0x860
+#define	ODM_REG_RX_ANT_CTRL_11N			0x864
+#define	ODM_REG_PIN_CTRL_11N				0x870
+#define	ODM_REG_BB_PWR_SAV1_11N			0x874
+#define	ODM_REG_ANTSEL_PATH_11N			0x878
+#define	ODM_REG_BB_3WIRE_11N			0x88C
+#define	ODM_REG_SC_CNT_11N				0x8C4
+#define	ODM_REG_PSD_DATA_11N			0x8B4
+//PAGE 9
+#define	ODM_REG_ANT_MAPPING1_11N		0x914
+#define	ODM_REG_ANT_MAPPING2_11N		0x918
+//PAGE A
+#define	ODM_REG_CCK_ANTDIV_PARA1_11N	0xA00
+#define	ODM_REG_CCK_CCA_11N				0xA0A
+#define	ODM_REG_CCK_ANTDIV_PARA2_11N	0xA0C
+#define	ODM_REG_CCK_ANTDIV_PARA3_11N	0xA10
+#define	ODM_REG_CCK_ANTDIV_PARA4_11N	0xA14
+#define	ODM_REG_CCK_FILTER_PARA1_11N	0xA22
+#define	ODM_REG_CCK_FILTER_PARA2_11N	0xA23
+#define	ODM_REG_CCK_FILTER_PARA3_11N	0xA24
+#define	ODM_REG_CCK_FILTER_PARA4_11N	0xA25
+#define	ODM_REG_CCK_FILTER_PARA5_11N	0xA26
+#define	ODM_REG_CCK_FILTER_PARA6_11N	0xA27
+#define	ODM_REG_CCK_FILTER_PARA7_11N	0xA28
+#define	ODM_REG_CCK_FILTER_PARA8_11N	0xA29
+#define	ODM_REG_CCK_FA_RST_11N			0xA2C
+#define	ODM_REG_CCK_FA_MSB_11N			0xA58
+#define	ODM_REG_CCK_FA_LSB_11N			0xA5C
+#define	ODM_REG_CCK_CCA_CNT_11N			0xA60
+#define	ODM_REG_BB_PWR_SAV4_11N			0xA74
+//PAGE B
+#define	ODM_REG_LNA_SWITCH_11N			0xB2C
+#define	ODM_REG_PATH_SWITCH_11N			0xB30
+#define	ODM_REG_RSSI_CTRL_11N			0xB38
+#define	ODM_REG_CONFIG_ANTA_11N			0xB68
+#define	ODM_REG_RSSI_BT_11N				0xB9C
+//PAGE C
+#define	ODM_REG_OFDM_FA_HOLDC_11N		0xC00
+#define	ODM_REG_RX_PATH_11N				0xC04
+#define	ODM_REG_TRMUX_11N				0xC08
+#define	ODM_REG_OFDM_FA_RSTC_11N		0xC0C
+#define	ODM_REG_RXIQI_MATRIX_11N		0xC14
+#define	ODM_REG_TXIQK_MATRIX_LSB1_11N	0xC4C
+#define	ODM_REG_IGI_A_11N				0xC50
+#define	ODM_REG_ANTDIV_PARA2_11N		0xC54
+#define	ODM_REG_IGI_B_11N					0xC58
+#define	ODM_REG_ANTDIV_PARA3_11N		0xC5C
+#define	ODM_REG_BB_PWR_SAV2_11N			0xC70
+#define	ODM_REG_RX_OFF_11N				0xC7C
+#define	ODM_REG_TXIQK_MATRIXA_11N		0xC80
+#define	ODM_REG_TXIQK_MATRIXB_11N		0xC88
+#define	ODM_REG_TXIQK_MATRIXA_LSB2_11N	0xC94
+#define	ODM_REG_TXIQK_MATRIXB_LSB2_11N	0xC9C
+#define	ODM_REG_RXIQK_MATRIX_LSB_11N	0xCA0
+#define	ODM_REG_ANTDIV_PARA1_11N		0xCA4
+#define	ODM_REG_OFDM_FA_TYPE1_11N		0xCF0
+//PAGE D
+#define	ODM_REG_OFDM_FA_RSTD_11N		0xD00
+#define	ODM_REG_OFDM_FA_TYPE2_11N		0xDA0
+#define	ODM_REG_OFDM_FA_TYPE3_11N		0xDA4
+#define	ODM_REG_OFDM_FA_TYPE4_11N		0xDA8
+//PAGE E
+#define	ODM_REG_TXAGC_A_6_18_11N		0xE00
+#define	ODM_REG_TXAGC_A_24_54_11N		0xE04
+#define	ODM_REG_TXAGC_A_1_MCS32_11N	0xE08
+#define	ODM_REG_TXAGC_A_MCS0_3_11N		0xE10
+#define	ODM_REG_TXAGC_A_MCS4_7_11N		0xE14
+#define	ODM_REG_TXAGC_A_MCS8_11_11N	0xE18
+#define	ODM_REG_TXAGC_A_MCS12_15_11N	0xE1C
+#define	ODM_REG_FPGA0_IQK_11N			0xE28
+#define	ODM_REG_TXIQK_TONE_A_11N		0xE30
+#define	ODM_REG_RXIQK_TONE_A_11N		0xE34
+#define	ODM_REG_TXIQK_PI_A_11N			0xE38
+#define	ODM_REG_RXIQK_PI_A_11N			0xE3C
+#define	ODM_REG_TXIQK_11N				0xE40
+#define	ODM_REG_RXIQK_11N				0xE44
+#define	ODM_REG_IQK_AGC_PTS_11N			0xE48
+#define	ODM_REG_IQK_AGC_RSP_11N			0xE4C
+#define	ODM_REG_BLUETOOTH_11N			0xE6C
+#define	ODM_REG_RX_WAIT_CCA_11N			0xE70
+#define	ODM_REG_TX_CCK_RFON_11N			0xE74
+#define	ODM_REG_TX_CCK_BBON_11N			0xE78
+#define	ODM_REG_OFDM_RFON_11N			0xE7C
+#define	ODM_REG_OFDM_BBON_11N			0xE80
+#define 	ODM_REG_TX2RX_11N				0xE84
+#define	ODM_REG_TX2TX_11N				0xE88
+#define	ODM_REG_RX_CCK_11N				0xE8C
+#define	ODM_REG_RX_OFDM_11N				0xED0
+#define	ODM_REG_RX_WAIT_RIFS_11N		0xED4
+#define	ODM_REG_RX2RX_11N				0xED8
+#define	ODM_REG_STANDBY_11N				0xEDC
+#define	ODM_REG_SLEEP_11N				0xEE0
+#define	ODM_REG_PMPD_ANAEN_11N			0xEEC
+
+
+
+
+
+
+
+//2 MAC REG LIST
+#define	ODM_REG_BB_RST_11N				0x02
+#define	ODM_REG_ANTSEL_PIN_11N			0x4C
+#define	ODM_REG_EARLY_MODE_11N			0x4D0
+#define	ODM_REG_RSSI_MONITOR_11N		0x4FE
+#define	ODM_REG_EDCA_VO_11N				0x500
+#define	ODM_REG_EDCA_VI_11N				0x504
+#define	ODM_REG_EDCA_BE_11N				0x508
+#define	ODM_REG_EDCA_BK_11N				0x50C
+#define	ODM_REG_TXPAUSE_11N				0x522
+#define	ODM_REG_RESP_TX_11N				0x6D8
+#define	ODM_REG_ANT_TRAIN_PARA1_11N	0x7b0
+#define	ODM_REG_ANT_TRAIN_PARA2_11N	0x7b4
+
+
+//DIG Related
+#define	ODM_BIT_IGI_11N					0x0000007F
+
+
+#endif
+

hal/OUTSRC/odm_debug.c

@@ -0,0 +1,627 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+//============================================================
+// include files
+//============================================================
+
+#include "odm_precomp.h"
+
+VOID 
+ODM_InitDebugSetting(
+	IN		PDM_ODM_T		pDM_Odm
+	)
+{
+pDM_Odm->DebugLevel				= 	ODM_DBG_TRACE;
+
+pDM_Odm->DebugComponents			= 
+\
+#if DBG
+//BB Functions
+//									ODM_COMP_DIG					|
+//									ODM_COMP_RA_MASK				|
+//									ODM_COMP_DYNAMIC_TXPWR		|
+//									ODM_COMP_FA_CNT				|
+//									ODM_COMP_RSSI_MONITOR			|
+//									ODM_COMP_CCK_PD				|
+//									ODM_COMP_ANT_DIV				|
+//									ODM_COMP_PWR_SAVE				|
+//									ODM_COMP_PWR_TRAIN			|
+//									ODM_COMP_RATE_ADAPTIVE		|
+//									ODM_COMP_PATH_DIV				|
+//									ODM_COMP_DYNAMIC_PRICCA		|
+//									ODM_COMP_RXHP					|
+
+//MAC Functions
+//									ODM_COMP_EDCA_TURBO			|
+//									ODM_COMP_EARLY_MODE			|
+//RF Functions
+//									ODM_COMP_TX_PWR_TRACK			|
+//									ODM_COMP_RX_GAIN_TRACK		|
+//									ODM_COMP_CALIBRATION			|
+//Common
+//									ODM_COMP_COMMON				|
+//									ODM_COMP_INIT					|
+#endif
+									0;
+}
+
+#if 0
+/*------------------Declare variable-----------------------
+// Define debug flag array for common debug print macro. */
+u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX];
+
+/* Define debug print header for every service module. */
+ODM_DBGP_HEAD_T	ODM_DBGP_Head;
+
+
+/*-----------------------------------------------------------------------------
+ * Function:    DBGP_Flag_Init
+ *
+ * Overview:    Refresh all debug print control flag content to zero.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ *  When		Who		Remark
+ *  10/20/2006	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+extern	void	ODM_DBGP_Flag_Init(void)
+{    
+    u1Byte i;
+    
+	for (i = 0; i < ODM_DBGP_TYPE_MAX; i++)
+	{
+ 		ODM_DBGP_Type[i] = 0;
+	}
+    
+#ifndef ADSL_AP_BUILD_WORKAROUND
+#if DBG		
+	// 2010/06/02 MH Free build driver can not out any debug message!!!
+	// Init Debug flag enable condition
+
+	ODM_DBGP_Type[FINIT]			=	\
+//								INIT_EEPROM						|
+//								INIT_TxPower						|
+//								INIT_IQK							|
+//								INIT_RF							|
+								0;
+
+	ODM_DBGP_Type[FDM]			=	\
+//								WA_IOT							|
+//								DM_PWDB						|
+//								DM_Monitor						|
+//								DM_DIG				|
+//								DM_EDCA_Turbo		|
+//								DM_BT30				|
+								0;
+
+	ODM_DBGP_Type[FIOCTL]		= 	\
+//								IOCTL_IRP						|
+//								IOCTL_IRP_DETAIL					|
+//								IOCTL_IRP_STATISTICS				|
+//								IOCTL_IRP_HANDLE				|
+//								IOCTL_BT_HCICMD					|
+//								IOCTL_BT_HCICMD_DETAIL			|
+//								IOCTL_BT_HCICMD_EXT				|
+//								IOCTL_BT_EVENT					|
+//								IOCTL_BT_EVENT_DETAIL			|
+//								IOCTL_BT_EVENT_PERIODICAL		|
+//								IOCTL_BT_TX_ACLDATA			|
+//								IOCTL_BT_TX_ACLDATA_DETAIL		|
+//								IOCTL_BT_RX_ACLDATA				|
+//								IOCTL_BT_RX_ACLDATA_DETAIL		|
+//								IOCTL_BT_TP						|
+//								IOCTL_STATE						|
+//								IOCTL_BT_LOGO					|
+//								IOCTL_CALLBACK_FUN				|
+//								IOCTL_PARSE_BT_PKT				|
+								0;
+
+	ODM_DBGP_Type[FBT]			= 	\
+//								BT_TRACE						|
+								0;
+
+	ODM_DBGP_Type[FEEPROM]		=	\
+//								EEPROM_W						|
+//								EFUSE_PG						|
+//								EFUSE_READ_ALL					|
+//								EFUSE_ANALYSIS					|
+//								EFUSE_PG_DETAIL					|
+								0;
+
+	ODM_DBGP_Type[FDBG_CTRL]	= 	\
+//								DBG_CTRL_TRACE					|
+//								DBG_CTRL_INBAND_NOISE			|
+								0;
+	
+	// 2011/07/20 MH Add for short cut 
+	ODM_DBGP_Type[FSHORT_CUT] = 	\
+//								SHCUT_TX 						| 
+//								SHCUT_RX						|
+								0;
+	
+#endif	
+#endif
+	/* Define debug header of every service module. */
+	//ODM_DBGP_Head.pMANS	= "\n\r[MANS] ";
+	//ODM_DBGP_Head.pRTOS	= "\n\r[RTOS] ";
+	//ODM_DBGP_Head.pALM	= "\n\r[ALM]  ";
+	//ODM_DBGP_Head.pPEM	= "\n\r[PEM]  ";
+	//ODM_DBGP_Head.pCMPK	= "\n\r[CMPK] ";
+	//ODM_DBGP_Head.pRAPD	= "\n\r[RAPD] ";
+	//ODM_DBGP_Head.pTXPB	= "\n\r[TXPB] ";
+	//ODM_DBGP_Head.pQUMG	= "\n\r[QUMG] ";
+    	
+}	/* DBGP_Flag_Init */
+
+#endif
+
+
+#if 0
+u4Byte GlobalDebugLevel			= 	DBG_LOUD;
+//
+// 2009/06/22 MH Allow Fre build to print none debug info at init time.
+//
+#if DBG
+u8Byte GlobalDebugComponents	= 	\
+//									COMP_TRACE				|
+//									COMP_DBG				|
+//									COMP_INIT				|
+//									COMP_OID_QUERY			|
+//									COMP_OID_SET			|
+//									COMP_RECV				|
+//									COMP_SEND				|
+//									COMP_IO					|
+//									COMP_POWER				|
+//									COMP_MLME				|
+//									COMP_SCAN				|
+//									COMP_SYSTEM			|
+//									COMP_SEC				|
+//									COMP_AP				|
+//									COMP_TURBO				|
+//									COMP_QOS				|
+//									COMP_AUTHENTICATOR	|
+//									COMP_BEACON			|
+//									COMP_ANTENNA			|
+//									COMP_RATE				|
+//									COMP_EVENTS			|
+//									COMP_FPGA				|
+//									COMP_RM				|
+//									COMP_MP				|
+//									COMP_RXDESC			|
+//									COMP_CKIP				|
+//									COMP_DIG				|
+//									COMP_TXAGC				|
+//									COMP_HIPWR				|
+//									COMP_HALDM				|
+//									COMP_RSNA				|
+//									COMP_INDIC				|
+//									COMP_LED				|
+//									COMP_RF					|
+//									COMP_DUALMACSWITCH	|
+//									COMP_EASY_CONCURRENT	|
+
+//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
+//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
+//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+//									COMP_HT				|
+//									COMP_POWER_TRACKING 	|
+//									COMP_RX_REORDER		|
+//									COMP_AMSDU 			|
+//									COMP_WPS				|
+//									COMP_RATR				|
+//									COMP_RESET 				|
+//									COMP_CMD				|
+//									COMP_EFUSE				|
+//									COMP_MESH_INTERWORKING |
+//									COMP_CCX				|	
+//									COMP_IOCTL				|
+//									COMP_GP 				|
+//									COMP_TXAGG				|
+//									COMP_BB_POWERSAVING	|
+//									COMP_SWAS				|
+//									COMP_P2P				|
+//									COMP_MUX				|
+//									COMP_FUNC				|
+//									COMP_TDLS				|
+//									COMP_OMNIPEEK			|
+//									COMP_PSD				|
+									0;
+
+
+#else
+#define FuncEntry
+#define FuncExit
+u8Byte GlobalDebugComponents	= 0;
+#endif
+
+#if (RT_PLATFORM==PLATFORM_LINUX) 
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
+EXPORT_SYMBOL(GlobalDebugComponents);
+EXPORT_SYMBOL(GlobalDebugLevel);
+#endif
+#endif
+
+/*------------------Declare variable-----------------------
+// Define debug flag array for common debug print macro. */
+u4Byte			DBGP_Type[DBGP_TYPE_MAX];
+
+/* Define debug print header for every service module. */
+DBGP_HEAD_T		DBGP_Head;
+
+
+/*-----------------------------------------------------------------------------
+ * Function:    DBGP_Flag_Init
+ *
+ * Overview:    Refresh all debug print control flag content to zero.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ *  When		Who		Remark
+ *  10/20/2006	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+extern	void	DBGP_Flag_Init(void)
+{    
+    u1Byte	i;
+    
+	for (i = 0; i < DBGP_TYPE_MAX; i++)
+	{
+ 		DBGP_Type[i] = 0;
+	}
+    
+#if DBG		
+	// 2010/06/02 MH Free build driver can not out any debug message!!!
+	// Init Debug flag enable condition
+
+	DBGP_Type[FINIT]			=	\
+//								INIT_EEPROM						|
+//								INIT_TxPower						|
+//								INIT_IQK							|
+//								INIT_RF							|
+								0;
+
+	DBGP_Type[FDM]			=	\
+//								WA_IOT							|
+//								DM_PWDB						|
+//								DM_Monitor						|
+//								DM_DIG				|
+//								DM_EDCA_Turbo		|
+//								DM_BT30				|
+								0;
+
+	DBGP_Type[FIOCTL]		= 	\
+//								IOCTL_IRP						|
+//								IOCTL_IRP_DETAIL					|
+//								IOCTL_IRP_STATISTICS				|
+//								IOCTL_IRP_HANDLE				|
+//								IOCTL_BT_HCICMD					|
+//								IOCTL_BT_HCICMD_DETAIL			|
+//								IOCTL_BT_HCICMD_EXT				|
+//								IOCTL_BT_EVENT					|
+//								IOCTL_BT_EVENT_DETAIL			|
+//								IOCTL_BT_EVENT_PERIODICAL		|
+//								IOCTL_BT_TX_ACLDATA			|
+//								IOCTL_BT_TX_ACLDATA_DETAIL		|
+//								IOCTL_BT_RX_ACLDATA				|
+//								IOCTL_BT_RX_ACLDATA_DETAIL		|
+//								IOCTL_BT_TP						|
+//								IOCTL_STATE						|
+//								IOCTL_BT_LOGO					|
+//								IOCTL_CALLBACK_FUN				|
+//								IOCTL_PARSE_BT_PKT				|
+								0;
+
+	DBGP_Type[FBT]			= 	\
+//								BT_TRACE						|
+								0;
+
+	DBGP_Type[FEEPROM]		=	\
+//								EEPROM_W						|
+//								EFUSE_PG						|
+//								EFUSE_READ_ALL					|
+//								EFUSE_ANALYSIS					|
+//								EFUSE_PG_DETAIL					|
+								0;
+
+	DBGP_Type[FDBG_CTRL]	= 	\
+//								DBG_CTRL_TRACE					|
+//								DBG_CTRL_INBAND_NOISE			|
+								0;
+	
+	// 2011/07/20 MH Add for short cut 
+	DBGP_Type[FSHORT_CUT] = 	\
+//								SHCUT_TX 						| 
+//								SHCUT_RX						|
+								0;
+	
+#endif	
+	/* Define debug header of every service module. */
+	DBGP_Head.pMANS	= "\n\r[MANS] ";
+	DBGP_Head.pRTOS	= "\n\r[RTOS] ";
+	DBGP_Head.pALM	= "\n\r[ALM]  ";
+	DBGP_Head.pPEM	= "\n\r[PEM]  ";
+	DBGP_Head.pCMPK	= "\n\r[CMPK] ";
+	DBGP_Head.pRAPD	= "\n\r[RAPD] ";
+	DBGP_Head.pTXPB	= "\n\r[TXPB] ";
+	DBGP_Head.pQUMG	= "\n\r[QUMG] ";
+    	
+}	/* DBGP_Flag_Init */
+
+
+/*-----------------------------------------------------------------------------
+ * Function:    DBG_PrintAllFlag
+ *
+ * Overview:    Print All debug flag
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ *  When		Who		Remark
+ *  12/10/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+extern	void	DBG_PrintAllFlag(void)
+{
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 0    FQoS\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 1    FTX\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 2    FRX\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 3    FSEC\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 4    FMGNT\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 5    FMLME\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 6    FRESOURCE\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 7    FBEACON\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 8    FISR\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 9    FPHY\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 11   FMP\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 12   FPWR\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 13   FDM\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 14   FDBG_CTRL\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 15   FC2H\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("DBGFLAG 16   FBT\n"));			
+}	// DBG_PrintAllFlag
+
+
+extern	void	DBG_PrintAllComp(void)
+{
+	u1Byte	i;
+	
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("GlobalDebugComponents Definition\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT0    COMP_TRACE\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT1    COMP_DBG\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT2    COMP_INIT\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT3    COMP_OID_QUERY\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT4    COMP_OID_SET\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT5    COMP_RECV\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT6    COMP_SEND\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT7    COMP_IO\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT8    COMP_POWER\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT9   COMP_MLME\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT10   COMP_SCAN\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT11   COMP_SYSTEM\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT12   COMP_SEC\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT13   COMP_AP\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT14   COMP_TURBO\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT15   COMP_QOS\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT16   COMP_AUTHENTICATOR\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT17   COMP_BEACON\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT18   COMP_BEACON\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT19   COMP_RATE\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT20   COMP_EVENTS\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT21   COMP_FPGA\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT22   COMP_RM\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT23   COMP_MP\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT24   COMP_RXDESC\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT25   COMP_CKIP\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT26   COMP_DIG\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT27   COMP_TXAGC\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT28   COMP_HIPWR\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT29   COMP_HALDM\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT30   COMP_RSNA\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT31   COMP_INDIC\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT32   COMP_LED\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT33   COMP_RF\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT34   COMP_HT\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT35   COMP_POWER_TRACKING\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT36   COMP_POWER_TRACKING\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT37   COMP_AMSDU\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT38   COMP_WPS\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT39   COMP_RATR\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT40   COMP_RESET\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT41   COMP_CMD\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT42   COMP_EFUSE\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT43   COMP_MESH_INTERWORKING\n"));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT43   COMP_CCX\n"));		
+	
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents));
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("Enable DBG COMP ="));
+	for (i = 0; i < 64; i++)
+	{
+		if (GlobalDebugComponents & ((u8Byte)0x1 << i) )
+		{
+			ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT%02d |\n", i));
+		}
+	}
+	ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("\n"));
+	
+}	// DBG_PrintAllComp
+
+
+/*-----------------------------------------------------------------------------
+ * Function:    DBG_PrintFlagEvent
+ *
+ * Overview:    Print dedicated debug flag event
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ *  When		Who		Remark
+ *  12/10/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+extern	void	DBG_PrintFlagEvent(u1Byte	DbgFlag)
+{
+	switch(DbgFlag)
+	{
+		case	FQoS:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    QoS_INIT\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    QoS_VISTA\n"));
+		break;
+
+		case	FTX:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    TX_DESC\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    TX_DESC_TID\n"));
+		break;
+
+		case	FRX:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    RX_DATA\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    RX_PHY_STS\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 2    RX_PHY_SS\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 3    RX_PHY_SQ\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 4    RX_PHY_ASTS\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 5    RX_ERR_LEN\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 6    RX_DEFRAG\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 7    RX_ERR_RATE\n"));
+		break;
+
+		case	FSEC:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("NA\n"));
+		break;
+
+		case	FMGNT:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("NA\n"));
+		break;
+
+		case	FMLME:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    MEDIA_STS\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    LINK_STS\n"));		
+		break;
+
+		case	FRESOURCE:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    OS_CHK\n"));
+		break;
+
+		case	FBEACON:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    BCN_SHOW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    BCN_PEER\n"));		
+		break;
+
+		case	FISR:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    ISR_CHK\n"));
+		break;
+
+		case	FPHY:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    PHY_BBR\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    PHY_BBW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 2    PHY_RFR\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 3    PHY_RFW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 4    PHY_MACR\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 5    PHY_MACW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 6    PHY_ALLR\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 7    PHY_ALLW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 8    PHY_TXPWR\n"));
+		break;
+
+		case	FMP:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    MP_RX\n"));
+		break;
+		
+		case	FEEPROM:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    EEPROM_W\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    EFUSE_PG\n"));		
+		break;
+		
+		case	FPWR:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    LPS\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    IPS\n"));		
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 2    PWRSW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 3    PWRHW\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 4    PWRHAL\n"));
+		break;
+
+		case	FDM:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    WA_IOT\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    DM_PWDB\n"));		
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 2    DM_Monitor\n"));		
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 3    DM_DIG\n"));		
+		break;
+
+		case	FDBG_CTRL:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    DBG_CTRL_TRACE\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    DBG_CTRL_INBAND_NOISE\n"));		
+		break;
+		
+		case	FC2H:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    C2H_Summary\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    C2H_PacketData\n"));		
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 2    C2H_ContentData\n"));		
+		break;
+		
+		case	FBT:
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 0    BT_TRACE\n"));
+		ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, 	("BIT 1    BT_RFPoll\n"));		
+		break;		
+		
+		default:
+			break;
+	}
+
+}	// DBG_PrintFlagEvent
+
+
+extern	void	DBG_DumpMem(const u1Byte DbgComp, 
+							const u1Byte DbgLevel, 
+							pu1Byte pMem, 
+							u2Byte Len)
+{
+	u2Byte i;
+
+	for (i=0;i<((Len>>3) + 1);i++)
+	{
+		ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n",
+					*(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)),
+					*(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7))));
+		
+	}
+}
+
+
+#endif
+

hal/OUTSRC/odm_debug.h

@@ -0,0 +1,905 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__ODM_DBG_H__
+#define __ODM_DBG_H__
+
+
+//-----------------------------------------------------------------------------
+//	Define the debug levels
+//
+//	1.	DBG_TRACE and DBG_LOUD are used for normal cases.
+//	So that, they can help SW engineer to develope or trace states changed 
+//	and also help HW enginner to trace every operation to and from HW, 
+//	e.g IO, Tx, Rx. 
+//
+//	2.	DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, 
+//	which help us to debug SW or HW.
+//
+//-----------------------------------------------------------------------------
+//
+//	Never used in a call to ODM_RT_TRACE()!
+//
+#define ODM_DBG_OFF					1
+
+//
+//	Fatal bug. 
+//	For example, Tx/Rx/IO locked up, OS hangs, memory access violation, 
+//	resource allocation failed, unexpected HW behavior, HW BUG and so on.
+//
+#define ODM_DBG_SERIOUS				2
+
+//
+//	Abnormal, rare, or unexpeted cases.
+//	For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
+//
+#define ODM_DBG_WARNING				3
+
+//
+//	Normal case with useful information about current SW or HW state. 
+//	For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, 
+//	SW protocol state change, dynamic mechanism state change and so on.
+//
+#define ODM_DBG_LOUD					4
+
+//
+//	Normal case with detail execution flow or information.
+//
+#define ODM_DBG_TRACE					5
+
+//-----------------------------------------------------------------------------
+// Define the tracing components
+//
+//-----------------------------------------------------------------------------
+//BB Functions
+#define ODM_COMP_DIG					BIT0	
+#define ODM_COMP_RA_MASK				BIT1	
+#define ODM_COMP_DYNAMIC_TXPWR		BIT2
+#define ODM_COMP_FA_CNT				BIT3
+#define ODM_COMP_RSSI_MONITOR		BIT4
+#define ODM_COMP_CCK_PD				BIT5
+#define ODM_COMP_ANT_DIV				BIT6
+#define ODM_COMP_PWR_SAVE			BIT7
+#define ODM_COMP_PWR_TRAIN			BIT8
+#define ODM_COMP_RATE_ADAPTIVE		BIT9
+#define ODM_COMP_PATH_DIV				BIT10
+#define ODM_COMP_PSD					BIT11
+#define ODM_COMP_DYNAMIC_PRICCA		BIT12
+#define ODM_COMP_RXHP				BIT13			
+//MAC Functions
+#define ODM_COMP_EDCA_TURBO			BIT16
+#define ODM_COMP_EARLY_MODE			BIT17
+//RF Functions
+#define ODM_COMP_TX_PWR_TRACK		BIT24
+#define ODM_COMP_RX_GAIN_TRACK		BIT25
+#define ODM_COMP_CALIBRATION			BIT26
+//Common Functions
+#define ODM_COMP_COMMON				BIT30
+#define ODM_COMP_INIT					BIT31
+
+/*------------------------Export Marco Definition---------------------------*/
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+#define RT_PRINTK				DbgPrint
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#define DbgPrint	printk
+	#define RT_PRINTK(fmt, args...)	DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
+#else
+	#define DbgPrint	panic_printk
+#define RT_PRINTK(fmt, args...)	DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
+#endif
+
+#ifndef ASSERT
+	#define ASSERT(expr)
+#endif
+
+#if DBG
+#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)									\
+		if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel))	\
+		{																			\
+			if(pDM_Odm->SupportICType == ODM_RTL8192C)								\
+				DbgPrint("[ODM-92C] ");												\
+			else if(pDM_Odm->SupportICType == ODM_RTL8192D)							\
+				DbgPrint("[ODM-92D] ");												\
+			else if(pDM_Odm->SupportICType == ODM_RTL8723A)							\
+				DbgPrint("[ODM-8723A] ");												\
+			else if(pDM_Odm->SupportICType == ODM_RTL8188E)							\
+				DbgPrint("[ODM-8188E] ");												\
+			else if(pDM_Odm->SupportICType == ODM_RTL8812)							\
+				DbgPrint("[ODM-8812] ");												\
+			else if(pDM_Odm->SupportICType == ODM_RTL8821)							\
+				DbgPrint("[ODM-8821] ");												\
+			RT_PRINTK fmt;															\
+		}
+
+#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)									\
+		if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel))	\
+		{																			\
+			RT_PRINTK fmt;															\
+		}
+
+#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)											\
+		if(!(expr)) {																	\
+			DbgPrint( "Assertion failed! %s at ......\n", #expr);								\
+			DbgPrint( "      ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__);			\
+			RT_PRINTK fmt;															\
+			ASSERT(FALSE);															\
+		}
+#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
+#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
+#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
+
+#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)						\
+			if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	__ptr = (pu1Byte)ptr;											\
+				DbgPrint("[ODM] ");													\
+				DbgPrint(title_str);												\
+				DbgPrint(" ");														\
+				for( __i=0; __i<6; __i++ )												\
+					DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-");						\
+				DbgPrint("\n");														\
+			}
+#else
+#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
+#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
+#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
+#define ODM_dbg_enter()
+#define ODM_dbg_exit()
+#define ODM_dbg_trace(str)
+#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
+#endif
+
+
+VOID 
+ODM_InitDebugSetting(
+	IN		PDM_ODM_T		pDM_Odm
+	);
+
+
+
+#if 0
+#if DBG
+#define DbgPrint printk
+
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)								\
+			{																		\
+				char			*szTitle = _TitleString;									\
+				pu1Byte		pbtHexData = _HexData;									\
+				u4Byte		u4bHexDataLen = _HexDataLen;							\
+				u4Byte		__i;														\
+				DbgPrint("%s", szTitle);													\
+				for (__i=0;__i<u4bHexDataLen;__i++)									\
+				{																	\
+					if ((__i & 15) == 0) 												\
+					{																\
+						DbgPrint("\n");												\
+					}																\
+					DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? "  " : " ") );		\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+// RT_PRINT_XXX macros: implemented for debugging purpose.
+// Added by Annie, 2005-11-21.
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)			\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_HexData;										\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				for( __i=0; __i<(int)_HexDataLen; __i++ )								\
+				{																	\
+					DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");			\
+					if (((__i + 1) % 16) == 0)	DbgPrint("\n");							\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)								\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(" ");															\
+				for( __i=0; __i<6; __i++ )												\
+					DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-");							\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)					\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int __i, __j;															\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint("\n");														\
+				for( __i=0; __i<(int)_AddNum; __i++ )									\
+				{																	\
+					for( __j=0; __j<6; __j++ )											\
+						DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-");				\
+					DbgPrint("\n");													\
+				}																	\
+			}
+
+// Added by Annie, 2005-11-22.
+#define	MAX_STR_LEN	64
+#define	PRINTABLE(_ch)	(_ch>=' ' &&_ch<='~' )	// I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
+
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)							\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int		__i;															\
+				u1Byte	buffer[MAX_STR_LEN];											\
+				int	length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ;				\
+				PlatformZeroMemory( buffer, MAX_STR_LEN );							\
+				PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length );						\
+				for( __i=0; __i<MAX_STR_LEN; __i++ )									\
+				{																	\
+					if( !PRINTABLE(buffer[__i]) )	buffer[__i] = '?';						\
+				}																	\
+				buffer[length] = '\0';													\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(": %d, <%s>\n", _Len, buffer);									\
+			}
+			
+#else	// of #if DBG
+#define DbgPrint(...)	
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
+#endif	// of #if DBG
+
+#endif	
+
+
+#if 0
+/* Define debug print header for every service module.*/
+typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
+{
+	const char 	*pMANS;
+	const char 	*pRTOS;
+	const char 	*pALM;
+	const char 	*pPEM;
+	const char 	*pCMPK;
+	const char 	*pRAPD;
+	const char 	*pTXPB;
+	const char 	*pQUMG;
+}ODM_DBGP_HEAD_T;
+
+
+/* Define different debug flag for dedicated service modules in debug flag array. */
+// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
+typedef enum tag_ODM_DBGP_Flag_Type_Definition
+{
+	ODM_FTX				= 0,
+	ODM_FRX				,	
+	ODM_FPHY				,
+	ODM_FPWR				,
+	ODM_FDM				,
+	ODM_FC2H				,
+	ODM_FBT				,
+	ODM_DBGP_TYPE_MAX
+}ODM_DBGP_FLAG_E;
+
+
+// Define TX relative debug bit				--> FTX
+#define		ODM_TX_DESC			BIT0
+#define		ODM_TX_DESC_TID		BIT1
+#define		ODM_TX_PATH			BIT2
+
+// Define RX relative debug  bit				--> FRX
+#define		ODM_RX_DATA				BIT0	
+#define		ODM_RX_PHY_STS			BIT1
+#define		ODM_RX_PHY_SS				BIT2
+#define		ODM_RX_PHY_SQ				BIT3
+#define		ODM_RX_PHY_ASTS			BIT4
+#define		ODM_RX_ERR_LEN			BIT5
+#define		ODM_RX_DEFRAG				BIT6
+#define		ODM_RX_ERR_RATE			BIT7
+#define		ODM_RX_PATH				BIT8
+#define		ODM_RX_BEACON				BIT9
+
+// Define PHY-BB/RF/MAC check module bit		--> FPHY
+#define		ODM_PHY_BBR				BIT0
+#define		ODM_PHY_BBW				BIT1
+#define		ODM_PHY_RFR				BIT2
+#define		ODM_PHY_RFW				BIT3
+#define		ODM_PHY_MACR				BIT4
+#define		ODM_PHY_MACW				BIT5
+#define		ODM_PHY_ALLR				BIT6
+#define		ODM_PHY_ALLW				BIT7
+#define		ODM_PHY_TXPWR			BIT8
+#define		ODM_PHY_PWRDIFF			BIT9
+#define		ODM_PHY_SICR				BIT10
+#define		ODM_PHY_SICW				BIT11
+
+
+
+
+extern	u4Byte ODM_GlobalDebugLevel;
+
+
+#if DBG
+extern	u8Byte ODM_GlobalDebugComponents;
+#endif
+#endif
+#if 0
+
+//-----------------------------------------------------------------------------
+//	Define the debug levels
+//
+//	1.	DBG_TRACE and DBG_LOUD are used for normal cases.
+//	So that, they can help SW engineer to develope or trace states changed 
+//	and also help HW enginner to trace every operation to and from HW, 
+//	e.g IO, Tx, Rx. 
+//
+//	2.	DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, 
+//	which help us to debug SW or HW.
+//
+//-----------------------------------------------------------------------------
+//
+//	Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
+//
+#define DBG_OFF					0
+
+//
+//	Deprecated! Don't use it! 
+//	TODO: fix related debug message!
+//
+//#define DBG_SEC					1
+
+//
+//	Fatal bug. 
+//	For example, Tx/Rx/IO locked up, OS hangs, memory access violation, 
+//	resource allocation failed, unexpected HW behavior, HW BUG and so on.
+//
+#define DBG_SERIOUS				2
+
+//
+//	Abnormal, rare, or unexpeted cases.
+//	For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
+//
+#define DBG_WARNING				3
+
+//
+//	Normal case with useful information about current SW or HW state. 
+//	For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, 
+//	SW protocol state change, dynamic mechanism state change and so on.
+//
+#define DBG_LOUD				4
+
+//
+//	Normal case with detail execution flow or information.
+//
+#define DBG_TRACE				5
+
+
+
+//-----------------------------------------------------------------------------
+// Define the tracing components
+//
+//-----------------------------------------------------------------------------
+#define COMP_TRACE				BIT0		// For function call tracing.
+#define COMP_DBG				BIT1		// Only for temporary debug message.
+#define COMP_INIT				BIT2		// during driver initialization / halt / reset.
+#define COMP_OID_QUERY				BIT3		// Query OID.
+#define COMP_OID_SET				BIT4		// Set OID.
+#define COMP_RECV				BIT5		// Reveive part data path.
+#define COMP_SEND				BIT6		// Send part path.
+#define COMP_IO					BIT7		// I/O Related. Added by Annie, 2006-03-02.
+#define COMP_POWER				BIT8		// 802.11 Power Save mode or System/Device Power state related.
+#define COMP_MLME				BIT9		// 802.11 link related: join/start BSS, leave BSS.
+#define COMP_SCAN				BIT10	// For site survey.
+#define COMP_SYSTEM				BIT11	// For general platform function.
+#define COMP_SEC				BIT12	// For Security.
+#define COMP_AP					BIT13	// For AP mode related.
+#define COMP_TURBO				BIT14	// For Turbo Mode related. By Annie, 2005-10-21.
+#define COMP_QOS				BIT15	// For QoS.
+#define COMP_AUTHENTICATOR			BIT16	// For AP mode Authenticator. Added by Annie, 2006-01-30.
+#define COMP_BEACON				BIT17	// For Beacon related, by rcnjko.
+#define COMP_ANTENNA				BIT18	// For Antenna diversity related, by rcnjko. 
+#define COMP_RATE				BIT19	// For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS				0x00000080	// Event handling
+#define COMP_EVENTS				BIT20	// Event handling
+#define COMP_FPGA				BIT21	// For FPGA verfication 
+#define COMP_RM					BIT22	// For Radio Measurement. 
+#define COMP_MP					BIT23	// For mass production test, by shien chang, 2006.07.13
+#define COMP_RXDESC				BIT24	// Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
+#define COMP_CKIP				BIT25	// For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
+#define COMP_DIG				BIT26	// For DIG, 2006.09.25, by rcnjko.
+#define COMP_TXAGC				BIT27	// For Tx power, 060928, by rcnjko. 
+#define COMP_HIPWR				BIT28	// For High Power Mechanism, 060928, by rcnjko. 
+#define COMP_HALDM				BIT29	// For HW Dynamic Mechanism, 061010, by rcnjko. 
+#define COMP_RSNA				BIT30	// For RSNA IBSS , 061201, by CCW. 
+#define COMP_INDIC				BIT31	// For link indication
+#define COMP_LED				BIT32	// For LED.
+#define COMP_RF					BIT33	// For RF.
+//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
+//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
+//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+#define COMP_HT					BIT34	// For 802.11n HT related information. by Emily 2006-8-11
+#define COMP_POWER_TRACKING			BIT35	//FOR 8190 TX POWER TRACKING
+#define COMP_RX_REORDER				BIT36	// 8190 Rx Reorder
+#define COMP_AMSDU				BIT37	// For A-MSDU Debugging
+#define COMP_WPS				BIT38   //WPS Debug Message 
+#define COMP_RATR				BIT39	
+#define COMP_RESET				BIT40
+// For debug command to print on dbgview!!
+#define COMP_CMD				BIT41
+#define COMP_EFUSE				BIT42
+#define COMP_MESH_INTERWORKING 			BIT43
+#define COMP_CCX				BIT44	//CCX Debug Flag
+#define	COMP_IOCTL				BIT45	// IO Control
+#define COMP_GP					BIT46	// For generic parser.
+#define COMP_TXAGG				BIT47
+#define COMP_HVL                            	BIT48     // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
+#define COMP_TEST				BIT49
+#define COMP_BB_POWERSAVING	BIT50
+#define COMP_SWAS				BIT51	// For SW Antenna Switch
+#define COMP_P2P				BIT52
+#define COMP_MUX				BIT53
+#define COMP_FUNC				BIT54
+#define COMP_TDLS				BIT55
+#define COMP_OMNIPEEK			BIT56
+#define COMP_DUALMACSWITCH	BIT60	// 2010/12/27 Add for Dual mac mode debug
+#define COMP_EASY_CONCURRENT	BIT61	// 2010/12/27 Add for easy cncurrent mode debug
+#define COMP_PSD				BIT63	//2011/3/9 Add for WLAN PSD for BT AFH
+
+#define COMP_DFS                                BIT62
+
+#define	COMP_ALL				UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
+// For debug print flag to use
+/*------------------------------Define structure----------------------------*/
+/* 2007/07/13 MH  *//*------For DeBuG Print modeue------*/
+
+/* Defnie structure to store different debug flag variable. Every debug flag 
+     is a UINT32 integer and you can assign 32 different events. */
+typedef struct tag_DBGP_Debug_Flag_Structure
+{
+	u4Byte	Mans;			/* Main Scheduler module. */
+	u4Byte	Rtos;			/* RTOS module. */
+	u4Byte	Alarm;		/* Alarm module. */	
+	u4Byte	Pm;			/* Performance monitor module. */	
+}DBGP_FLAG_T;
+
+/* Define debug print header for every service module.*/
+typedef struct tag_DBGP_Service_Module_Header_Name_Structure
+{
+	const char 	*pMANS;
+	const char 	*pRTOS;
+	const char 	*pALM;
+	const char 	*pPEM;
+	const char 	*pCMPK;
+	const char 	*pRAPD;
+	const char 	*pTXPB;
+	const char 	*pQUMG;
+}DBGP_HEAD_T;
+
+
+/* Define different debug flag for dedicated service modules in debug flag array. */
+// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
+typedef enum tag_DBGP_Flag_Type_Definition
+{
+	FQoS				= 0,	
+	FTX					= 1,
+	FRX					= 2,	
+	FSEC				= 3,
+	FMGNT				= 4,
+	FMLME				= 5,
+	FRESOURCE			= 6,
+	FBEACON				= 7,
+	FISR				= 8,
+	FPHY				= 9,
+	FMP					= 10,
+	FEEPROM			= 11,
+	FPWR				= 12,
+	FDM					= 13,
+	FDBG_CTRL			= 14,
+	FC2H				= 15,
+	FBT					= 16,
+	FINIT				= 17,
+	FIOCTL				= 18,
+	FSHORT_CUT			= 19,
+	DBGP_TYPE_MAX
+}DBGP_FLAG_E;
+
+
+// Define Qos Relative debug flag bit		--> FQoS
+#define		QoS_INIT			BIT0
+#define		QoS_VISTA			BIT1
+
+// Define TX relative debug bit				--> FTX
+#define		TX_DESC			BIT0
+#define		TX_DESC_TID		BIT1
+#define		TX_PATH			BIT2
+
+// Define RX relative debug  bit				--> FRX
+#define		RX_DATA				BIT0	
+#define		RX_PHY_STS				BIT1
+#define		RX_PHY_SS				BIT2
+#define		RX_PHY_SQ				BIT3
+#define		RX_PHY_ASTS			BIT4
+#define		RX_ERR_LEN			BIT5
+#define		RX_DEFRAG			BIT6
+#define		RX_ERR_RATE			BIT7
+#define		RX_PATH				BIT8
+#define		RX_BEACON				BIT9
+
+// Define Security relative debug  bit			--> FSEC
+
+// Define MGNT relative debug bit			--> FMGNT
+
+// Define MLME relative debug bit				--> FMLME
+#define		MEDIA_STS			BIT0
+#define		LINK_STS			BIT1
+
+// Define OS resource check module bit		--> FRESOURCE
+#define		OS_CHK				BIT0
+
+// Define beacon content check module bit		--> FBEACON
+#define		BCN_SHOW			BIT0
+#define		BCN_PEER			BIT1
+
+// Define ISR/IMR check module bit		--> FISR
+#define		ISR_CHK				BIT0
+
+// Define PHY-BB/RF/MAC check module bit		--> FPHY
+#define		PHY_BBR				BIT0
+#define		PHY_BBW				BIT1
+#define		PHY_RFR				BIT2
+#define		PHY_RFW				BIT3
+#define		PHY_MACR				BIT4
+#define		PHY_MACW				BIT5
+#define		PHY_ALLR				BIT6
+#define		PHY_ALLW				BIT7
+#define		PHY_TXPWR				BIT8
+#define		PHY_PWRDIFF			BIT9
+#define		PHY_SICR				BIT10
+#define		PHY_SICW				BIT11
+
+// Define MPT driver check module bit		--> FMP
+#define		MP_RX					BIT0
+#define		MP_SWICH_CH			BIT1
+
+// Define EEPROM and EFUSE  check module bit		--> FEEPROM
+#define		EEPROM_W					BIT0
+#define		EFUSE_PG					BIT1
+#define		EFUSE_READ_ALL			BIT2
+#define		EFUSE_ANALYSIS				BIT3
+#define		EFUSE_PG_DETAIL			BIT4
+
+// Define power save  check module bit		--> FPWR
+#define		LPS					BIT0
+#define		IPS					BIT1
+#define		PWRSW				BIT2
+#define		PWRHW				BIT3
+#define		PWRHAL				BIT4
+
+// Define Dynamic Mechanism check module bit		--> FDM
+#define		WA_IOT				BIT0
+#define		DM_PWDB			BIT1
+#define		DM_Monitor			BIT2
+#define		DM_DIG				BIT3
+#define		DM_EDCA_Turbo		BIT4
+#define		DM_BT30			BIT5
+
+// Define Dbg Control module bit		--> FDBG_CTRL
+#define		DBG_CTRL_TRACE			BIT0
+#define		DBG_CTRL_INBAND_NOISE	BIT1
+
+// Define FW C2H Cmd check module bit		--> FC2H
+#define		C2H_Summary				BIT0
+#define		C2H_PacketData				BIT1
+#define		C2H_ContentData			BIT2
+// Define BT Cmd check module bit		--> FBT
+#define		BT_TRACE					BIT0
+#define		BT_RFPoll					BIT1
+
+// Define init check for module bit		--> FINIT
+#define		INIT_EEPROM				BIT0
+#define		INIT_TxPower				BIT1
+#define		INIT_IQK					BIT2
+#define		INIT_RF						BIT3
+
+// Define IOCTL Cmd check module bit		--> FIOCTL
+// section 1 : IRP related
+#define		IOCTL_IRP						BIT0
+#define		IOCTL_IRP_DETAIL				BIT1
+#define		IOCTL_IRP_STATISTICS			BIT2
+#define		IOCTL_IRP_HANDLE				BIT3
+// section 2 : HCI command/event
+#define		IOCTL_BT_HCICMD				BIT8
+#define		IOCTL_BT_HCICMD_DETAIL		BIT9
+#define		IOCTL_BT_HCICMD_EXT			BIT10
+#define		IOCTL_BT_EVENT					BIT11
+#define		IOCTL_BT_EVENT_DETAIL			BIT12
+#define		IOCTL_BT_EVENT_PERIODICAL		BIT13
+// section 3 : BT tx/rx data and throughput
+#define		IOCTL_BT_TX_ACLDATA			BIT16
+#define		IOCTL_BT_TX_ACLDATA_DETAIL	BIT17
+#define		IOCTL_BT_RX_ACLDATA			BIT18
+#define		IOCTL_BT_RX_ACLDATA_DETAIL	BIT19
+#define		IOCTL_BT_TP					BIT20
+// section 4 : BT connection state machine.
+#define 		IOCTL_STATE					BIT21	
+#define		IOCTL_BT_LOGO					BIT22
+// section 5 : BT function trace
+#define		IOCTL_CALLBACK_FUN			BIT24
+#define		IOCTL_PARSE_BT_PKT			BIT25
+#define		IOCTL_BT_TX_PKT				BIT26
+#define		IOCTL_BT_FLAG_MON				BIT27
+
+//
+// Define init check for module bit		--> FSHORT_CUT
+// 2011/07/20 MH Add for short but definition.
+//
+#define		SHCUT_TX				BIT0
+#define		SHCUT_RX				BIT1
+
+
+/* 2007/07/13 MH  *//*------For DeBuG Print modeue------*/
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
+#define RT_PRINTK(fmt, args...)    printk( "%s(): " fmt, __FUNCTION__, ## args);
+
+#if DBG
+#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)											\
+		if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel))	\
+		{																	\
+			RT_PRINTK fmt;													\
+		}
+
+#define RT_TRACE_F(comp, level, fmt)											\
+		if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel))	\
+		{																	\
+			RT_PRINTK fmt;													\
+		}
+
+#define RT_ASSERT(expr,fmt)													\
+		if(!(expr)) {															\
+			printk( "Assertion failed! %s at ......\n", #expr);							\
+			printk( "      ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__);	\
+		}
+#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
+#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
+#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
+#else
+#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
+#define RT_TRACE_F(comp, level, fmt)
+#define RT_ASSERT(expr, fmt)
+#define dbg_enter()
+#define dbg_exit()
+#define dbg_trace(str)
+#endif
+
+#if DBG
+#define DbgPrint printk
+
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)								\
+			{																		\
+				char			*szTitle = _TitleString;									\
+				pu1Byte		pbtHexData = _HexData;									\
+				u4Byte		u4bHexDataLen = _HexDataLen;							\
+				u4Byte		__i;														\
+				DbgPrint("%s", szTitle);													\
+				for (__i=0;__i<u4bHexDataLen;__i++)									\
+				{																	\
+					if ((__i & 15) == 0) 												\
+					{																\
+						DbgPrint("\n");												\
+					}																\
+					DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? "  " : " ") );		\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+// RT_PRINT_XXX macros: implemented for debugging purpose.
+// Added by Annie, 2005-11-21.
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)			\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_HexData;										\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				for( __i=0; __i<(int)_HexDataLen; __i++ )								\
+				{																	\
+					DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");			\
+					if (((__i + 1) % 16) == 0)	DbgPrint("\n");							\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)								\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(" ");															\
+				for( __i=0; __i<6; __i++ )												\
+					DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-");							\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)					\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int __i, __j;															\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint("\n");														\
+				for( __i=0; __i<(int)_AddNum; __i++ )									\
+				{																	\
+					for( __j=0; __j<6; __j++ )											\
+						DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-");				\
+					DbgPrint("\n");													\
+				}																	\
+			}
+
+// Added by Annie, 2005-11-22.
+#define	MAX_STR_LEN	64
+#define	PRINTABLE(_ch)	(_ch>=' ' &&_ch<='~' )	// I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
+
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)							\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int		__i;															\
+				u1Byte	buffer[MAX_STR_LEN];											\
+				int	length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ;				\
+				PlatformZeroMemory( buffer, MAX_STR_LEN );							\
+				PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length );						\
+				for( __i=0; __i<MAX_STR_LEN; __i++ )									\
+				{																	\
+					if( !PRINTABLE(buffer[__i]) )	buffer[__i] = '?';						\
+				}																	\
+				buffer[length] = '\0';													\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(": %d, <%s>\n", _Len, buffer);									\
+			}
+			
+#else	// of #if DBG
+#define DbgPrint(...)	
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
+#endif	// of #if DBG
+
+
+
+#endif	// #if (DM_ODM_SUPPORT_TYPE != ODM_MP)
+
+#define		DEBUG_PRINT				1
+
+// Please add new OS's print API by yourself
+
+//#if (RT_PLATFORM==PLATFORM_WINDOWS) 
+#if (DEBUG_PRINT == 1) && DBG
+#define	RTPRINT(dbgtype, dbgflag, printstr)\
+{\
+	if (DBGP_Type[dbgtype] & dbgflag)\
+	{\
+		DbgPrint printstr;\
+	}\
+}
+
+#define	RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
+{\
+	if (DBGP_Type[dbgtype] & dbgflag)\
+	{\
+				int __i;						\
+				pu1Byte	ptr = (pu1Byte)_Ptr;	\
+				DbgPrint printstr;				\
+				DbgPrint(" ");					\
+				for( __i=0; __i<6; __i++ )		\
+					DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-");		\
+				DbgPrint("\n");							\
+	}\
+}
+
+#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
+{\
+	if (DBGP_Type[dbgtype] & dbgflag)\
+	{\
+		int __i;									\
+		pu1Byte	ptr = (pu1Byte)_HexData;			\
+		DbgPrint(_TitleString);					\
+		for( __i=0; __i<(int)_HexDataLen; __i++ )	\
+		{										\
+			DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");\
+			if (((__i + 1) % 16) == 0)	DbgPrint("\n");\
+		}										\
+		DbgPrint("\n");							\
+	}\
+}
+#define FuncEntry        FunctionIn(COMP_FUNC)
+#define FuncExit          FunctionOut(COMP_FUNC)
+
+#define FunctionIn(_comp)		ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n",  __FUNCTION__))
+#define FunctionOut(_comp)		ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n",  __FUNCTION__))
+
+
+#else
+
+#define	DBGP(dbgtype, dbgflag, printstr)
+#define	RTPRINT(dbgtype, dbgflag, printstr)
+#define	RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)
+#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
+#define FuncEntry       
+#define FuncExit          
+#define FunctionIn(_comp)
+#define FunctionOut(_comp)
+#endif
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+extern	u4Byte			DBGP_Type[DBGP_TYPE_MAX];
+extern	DBGP_HEAD_T	DBGP_Head;
+
+/*------------------------Export global variable----------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+extern	void	DBGP_Flag_Init(void);
+extern	void	DBG_PrintAllFlag(void);
+extern	void	DBG_PrintAllComp(void);
+extern	void	DBG_PrintFlagEvent(u1Byte	DbgFlag);
+extern	void	DBG_DumpMem(const u1Byte DbgComp, 
+							const u1Byte DbgLevel, 
+							pu1Byte pMem, 
+							u2Byte Len);
+
+/*--------------------------Exported Function prototype---------------------*/
+
+
+
+
+
+
+
+
+
+extern u4Byte GlobalDebugLevel;
+extern u8Byte GlobalDebugComponents;
+
+
+#endif
+
+
+#endif	// __ODM_DBG_H__
+

hal/OUTSRC/odm_interface.c

@@ -0,0 +1,666 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+//============================================================
+// include files
+//============================================================
+
+#include "odm_precomp.h"
+//
+// ODM IO Relative API.
+//
+
+u1Byte
+ODM_Read1Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	prtl8192cd_priv	priv	= pDM_Odm->priv;
+	return	RTL_R8(RegAddr);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return rtw_read8(Adapter,RegAddr);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return	PlatformEFIORead1Byte(Adapter, RegAddr);
+#endif	
+
+}
+
+
+u2Byte
+ODM_Read2Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	prtl8192cd_priv	priv	= pDM_Odm->priv;
+	return	RTL_R16(RegAddr);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return rtw_read16(Adapter,RegAddr);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return	PlatformEFIORead2Byte(Adapter, RegAddr);
+#endif	
+
+}
+
+
+u4Byte
+ODM_Read4Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	prtl8192cd_priv	priv	= pDM_Odm->priv;
+	return	RTL_R32(RegAddr);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return rtw_read32(Adapter,RegAddr);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return	PlatformEFIORead4Byte(Adapter, RegAddr);
+#endif	
+
+}
+
+
+VOID
+ODM_Write1Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u1Byte			Data
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	prtl8192cd_priv	priv	= pDM_Odm->priv;
+	RTL_W8(RegAddr, Data);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	rtw_write8(Adapter,RegAddr, Data);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformEFIOWrite1Byte(Adapter, RegAddr, Data);
+#endif
+	
+}
+
+
+VOID
+ODM_Write2Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u2Byte			Data
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	prtl8192cd_priv	priv	= pDM_Odm->priv;
+	RTL_W16(RegAddr, Data);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	rtw_write16(Adapter,RegAddr, Data);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
+#endif	
+
+}
+
+
+VOID
+ODM_Write4Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			Data
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	prtl8192cd_priv	priv	= pDM_Odm->priv;
+	RTL_W32(RegAddr, Data);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	rtw_write32(Adapter,RegAddr, Data);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformEFIOWrite4Byte(Adapter, RegAddr, Data);
+#endif	
+
+}
+
+
+VOID
+ODM_SetMACReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask,
+	IN	u4Byte		Data
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
+#endif	
+}
+
+
+u4Byte 
+ODM_GetMACReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
+#endif	
+}
+
+
+VOID
+ODM_SetBBReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask,
+	IN	u4Byte		Data
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
+#endif	
+}
+
+
+u4Byte 
+ODM_GetBBReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
+#endif	
+}
+
+
+VOID
+ODM_SetRFReg(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	ODM_RF_RADIO_PATH_E	eRFPath,
+	IN	u4Byte				RegAddr,
+	IN	u4Byte				BitMask,
+	IN	u4Byte				Data
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
+#endif	
+}
+
+
+u4Byte 
+ODM_GetRFReg(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	ODM_RF_RADIO_PATH_E	eRFPath,
+	IN	u4Byte				RegAddr,
+	IN	u4Byte				BitMask
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1);
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
+#endif	
+}
+
+
+
+
+//
+// ODM Memory relative API.
+//
+VOID
+ODM_AllocateMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT	PVOID		*pPtr,
+	IN	u4Byte		length
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	*pPtr = kmalloc(length, GFP_ATOMIC);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
+	*pPtr = rtw_zvmalloc(length);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformAllocateMemory(Adapter, pPtr, length);
+#endif	
+}
+
+// length could be ignored, used to detect memory leakage.
+VOID
+ODM_FreeMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT	PVOID		pPtr,
+	IN	u4Byte		length
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	kfree(pPtr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )	
+	rtw_vmfree(pPtr, length);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	//PADAPTER    Adapter = pDM_Odm->Adapter;
+	PlatformFreeMemory(pPtr, length);
+#endif	
+}
+s4Byte ODM_CompareMemory(
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	PVOID           pBuf1,
+      IN	PVOID           pBuf2,
+      IN	u4Byte          length
+       )
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	return memcmp(pBuf1,pBuf2,length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )	
+	return _rtw_memcmp(pBuf1,pBuf2,length);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)	
+	return PlatformCompareMemory(pBuf1,pBuf2,length);
+#endif	
+}
+
+
+
+//
+// ODM MISC relative API.
+//
+VOID
+ODM_AcquireSpinLock(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	RT_SPINLOCK_TYPE	type
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformAcquireSpinLock(Adapter, type);
+#endif	
+}
+VOID
+ODM_ReleaseSpinLock(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	RT_SPINLOCK_TYPE	type
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformReleaseSpinLock(Adapter, type);
+#endif	
+}
+
+//
+// Work item relative API. FOr MP driver only~!
+//
+VOID
+ODM_InitializeWorkItem(	
+	IN 	PDM_ODM_T					pDM_Odm,
+	IN	PRT_WORK_ITEM				pRtWorkItem,
+	IN	RT_WORKITEM_CALL_BACK		RtWorkItemCallback,
+	IN	PVOID						pContext,
+	IN	const char*					szID
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID);
+#endif	
+}
+
+
+VOID
+ODM_StartWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformStartWorkItem(pRtWorkItem);
+#endif	
+}
+
+
+VOID
+ODM_StopWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformStopWorkItem(pRtWorkItem);
+#endif	
+}
+
+
+VOID
+ODM_FreeWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformFreeWorkItem(pRtWorkItem);
+#endif	
+}
+
+
+VOID
+ODM_ScheduleWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformScheduleWorkItem(pRtWorkItem);
+#endif	
+}
+
+
+VOID
+ODM_IsWorkItemScheduled(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformIsWorkItemScheduled(pRtWorkItem);
+#endif	
+}
+
+
+
+//
+// ODM Timer relative API.
+//
+VOID
+ODM_StallExecution(	
+	IN	u4Byte	usDelay
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_udelay_os(usDelay);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformStallExecution(usDelay);
+#endif	
+}
+
+VOID
+ODM_delay_ms(IN u4Byte	ms)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	delay_ms(ms);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_mdelay_os(ms);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	delay_ms(ms);
+#endif			
+}
+
+VOID
+ODM_delay_us(IN u4Byte	us)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	delay_us(us);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_udelay_os(us);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PlatformStallExecution(us);
+#endif			
+}
+
+VOID
+ODM_sleep_ms(IN u4Byte	ms)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_msleep_os(ms);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)	
+#endif		
+}
+
+VOID
+ODM_sleep_us(IN u4Byte	us)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_usleep_os(us);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)	
+#endif		
+}
+
+VOID
+ODM_SetTimer(	
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER 		pTimer, 
+	IN	u4Byte 			msDelay
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	mod_timer(pTimer, jiffies + (msDelay+9)/10);	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	_set_timer(pTimer,msDelay ); //ms
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER		Adapter = pDM_Odm->Adapter;
+	PlatformSetTimer(Adapter, pTimer, msDelay);
+#endif	
+
+}
+
+VOID
+ODM_InitializeTimer(
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	PRT_TIMER 			pTimer, 
+	IN	RT_TIMER_CALL_BACK	CallBackFunc, 
+	IN	PVOID				pContext,
+	IN	const char*			szID
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	pTimer->function = CallBackFunc;
+	pTimer->data = (unsigned long)pDM_Odm;
+	init_timer(pTimer);	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	PADAPTER Adapter = pDM_Odm->Adapter;
+	_init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER Adapter = pDM_Odm->Adapter;
+	PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID);
+#endif	
+}
+
+
+VOID
+ODM_CancelTimer(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER		pTimer
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	del_timer_sync(pTimer);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+	_cancel_timer_ex(pTimer);
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+	PADAPTER Adapter = pDM_Odm->Adapter;
+	PlatformCancelTimer(Adapter, pTimer);
+#endif
+}
+
+
+VOID
+ODM_ReleaseTimer(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER		pTimer
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
+
+	PADAPTER Adapter = pDM_Odm->Adapter;
+
+    // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. 
+    // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail.
+    if (pTimer == 0) 
+    {
+        ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n"));
+        return;
+    }
+        
+	PlatformReleaseTimer(Adapter, pTimer);
+#endif
+}
+
+
+//
+// ODM FW relative API.
+//
+#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
+VOID
+ODM_FillH2CCmd(
+	IN	PADAPTER		Adapter,
+	IN	u1Byte 	ElementID,
+	IN	u4Byte 	CmdLen,
+	IN	pu1Byte	pCmdBuffer
+)
+{
+	if(IS_HARDWARE_TYPE_JAGUAR(Adapter))
+	{
+		switch(ElementID)
+		{
+		case ODM_H2C_RSSI_REPORT:
+			FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer);
+		default:
+			break;
+		}
+
+	}
+	else if(IS_HARDWARE_TYPE_8188E(Adapter))
+	{
+		switch(ElementID)
+		{
+		case ODM_H2C_PSD_RESULT:
+			FillH2CCmd88E(Adapter, H2C_88E_PSD_RESULT, CmdLen, pCmdBuffer);
+		default:
+			break;
+		}
+	}
+	else
+	{
+		switch(ElementID)
+		{
+		case ODM_H2C_RSSI_REPORT:
+			FillH2CCmd92C(Adapter, H2C_RSSI_REPORT, CmdLen, pCmdBuffer);
+		case ODM_H2C_PSD_RESULT:
+			FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, CmdLen, pCmdBuffer);
+		default:
+			break;
+		}
+	}
+}
+#else
+u4Byte
+ODM_FillH2CCmd(	
+	IN	pu1Byte		pH2CBuffer,
+	IN	u4Byte		H2CBufferLen,
+	IN	u4Byte		CmdNum,
+	IN	pu4Byte		pElementID,
+	IN	pu4Byte		pCmdLen,
+	IN	pu1Byte*		pCmbBuffer,
+	IN	pu1Byte		CmdStartSeq
+	)
+{
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	
+#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)	
+	//FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq);
+	return	FALSE;
+#endif
+
+	return	TRUE;
+}
+#endif
+
+
+
+
+

hal/OUTSRC/odm_interface.h

@@ -0,0 +1,374 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__ODM_INTERFACE_H__
+#define __ODM_INTERFACE_H__
+
+
+
+//
+// =========== Constant/Structure/Enum/... Define
+//
+
+
+
+//
+// =========== Macro Define
+//
+
+#define _reg_all(_name)			ODM_##_name
+#define _reg_ic(_name, _ic)		ODM_##_name##_ic
+#define _bit_all(_name)			BIT_##_name
+#define _bit_ic(_name, _ic)		BIT_##_name##_ic
+
+// _cat: implemented by Token-Pasting Operator.
+#if 0
+#define _cat(_name, _ic_type, _func)								\
+	( 																		\
+		_func##_all(_name)										\
+	)
+#endif
+
+/*===================================
+
+#define ODM_REG_DIG_11N		0xC50
+#define ODM_REG_DIG_11AC	0xDDD
+
+ODM_REG(DIG,_pDM_Odm)
+=====================================*/
+
+#define _reg_11N(_name)			ODM_REG_##_name##_11N 
+#define _reg_11AC(_name)		ODM_REG_##_name##_11AC
+#define _bit_11N(_name)			ODM_BIT_##_name##_11N 
+#define _bit_11AC(_name)		ODM_BIT_##_name##_11AC
+
+#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES.
+#define _cat(_name, _ic_type, _func)									\
+	( 															\
+		((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name):		\
+		_func##_11AC(_name)									\
+	)
+#endif
+#if 0 // only sample code
+#define _cat(_name, _ic_type, _func)									\
+	( 															\
+		((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C):		\
+		((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D):		\
+		((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S):		\
+		((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A):		\
+		((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E):		\
+		_func##_ic(_name, _8195)									\
+	)
+#endif
+
+// _name: name of register or bit.
+// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" 
+//        gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
+#define ODM_REG(_name, _pDM_Odm)	_cat(_name, _pDM_Odm->SupportICType, _reg)
+#define ODM_BIT(_name, _pDM_Odm)	_cat(_name, _pDM_Odm->SupportICType, _bit)
+
+typedef enum _ODM_H2C_CMD 
+{
+	ODM_H2C_RSSI_REPORT = 0,
+	ODM_H2C_PSD_RESULT=1,	
+	ODM_H2C_PathDiv = 2,               
+	ODM_MAX_H2CCMD
+}ODM_H2C_CMD;
+
+
+//
+// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
+// Suggest HW team to use thread instead of workitem. Windows also support the feature.
+//
+#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
+typedef  void *PRT_WORK_ITEM ;
+typedef  void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
+typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
+
+#if 0
+typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
+	
+typedef struct _RT_WORK_ITEM
+{
+	
+	RT_WORKITEM_HANDLE			Handle;			// Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
+	PVOID						Adapter;		// Pointer to Adapter object.
+	PVOID						pContext;		// Parameter to passed to CallBackFunc(). 
+	RT_WORKITEM_CALL_BACK		CallbackFunc;	// Callback function of the workitem.
+	u1Byte						RefCount;		// 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. 
+	PVOID						pPlatformExt;	// Pointer to platform-dependent extension.	
+	BOOLEAN						bFree;
+	char						szID[36];		// An identity string of this workitem.
+}RT_WORK_ITEM, *PRT_WORK_ITEM;
+
+#endif
+
+
+#endif
+
+//
+// =========== Extern Variable ??? It should be forbidden.
+//
+
+
+//
+// =========== EXtern Function Prototype
+//
+
+
+u1Byte
+ODM_Read1Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	);
+
+u2Byte
+ODM_Read2Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	);
+
+u4Byte
+ODM_Read4Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	);
+
+VOID
+ODM_Write1Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u1Byte			Data
+	);
+
+VOID
+ODM_Write2Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u2Byte			Data
+	);
+
+VOID
+ODM_Write4Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			Data
+	);
+
+VOID
+ODM_SetMACReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask,
+	IN	u4Byte		Data
+	);
+
+u4Byte 
+ODM_GetMACReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask
+	);
+
+VOID
+ODM_SetBBReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask,
+	IN	u4Byte		Data
+	);
+
+u4Byte 
+ODM_GetBBReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask
+	);
+
+VOID
+ODM_SetRFReg(	
+	IN 	PDM_ODM_T				pDM_Odm,
+	IN	ODM_RF_RADIO_PATH_E	eRFPath,
+	IN	u4Byte					RegAddr,
+	IN	u4Byte					BitMask,
+	IN	u4Byte					Data
+	);
+
+u4Byte 
+ODM_GetRFReg(	
+	IN 	PDM_ODM_T				pDM_Odm,
+	IN	ODM_RF_RADIO_PATH_E	eRFPath,
+	IN	u4Byte					RegAddr,
+	IN	u4Byte					BitMask
+	);
+
+
+//
+// Memory Relative Function.
+//
+VOID
+ODM_AllocateMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT	PVOID		*pPtr,
+	IN	u4Byte		length
+	);
+VOID
+ODM_FreeMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT	PVOID		pPtr,
+	IN	u4Byte		length
+	);
+
+s4Byte ODM_CompareMemory(
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	PVOID           pBuf1,
+      IN	PVOID           pBuf2,
+      IN	u4Byte          length
+       );
+	
+//
+// ODM MISC-spin lock relative API.
+//
+VOID
+ODM_AcquireSpinLock(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	RT_SPINLOCK_TYPE	type
+	);
+
+VOID
+ODM_ReleaseSpinLock(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	RT_SPINLOCK_TYPE	type
+	);
+
+
+//
+// ODM MISC-workitem relative API.
+//
+VOID
+ODM_InitializeWorkItem(	
+	IN 	PDM_ODM_T					pDM_Odm,
+	IN	PRT_WORK_ITEM				pRtWorkItem,
+	IN	RT_WORKITEM_CALL_BACK		RtWorkItemCallback,
+	IN	PVOID						pContext,
+	IN	const char*					szID
+	);
+
+VOID
+ODM_StartWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_StopWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_FreeWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_ScheduleWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_IsWorkItemScheduled(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+//
+// ODM Timer relative API.
+//
+VOID
+ODM_StallExecution(	
+	IN	u4Byte	usDelay
+	);
+
+VOID
+ODM_delay_ms(IN u4Byte	ms);
+
+
+VOID
+ODM_delay_us(IN u4Byte	us);
+
+VOID
+ODM_sleep_ms(IN u4Byte	ms);
+
+VOID
+ODM_sleep_us(IN u4Byte	us);
+
+VOID
+ODM_SetTimer(	
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER 		pTimer, 
+	IN	u4Byte 			msDelay
+	);
+
+VOID
+ODM_InitializeTimer(
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	PRT_TIMER 			pTimer, 
+	IN	RT_TIMER_CALL_BACK	CallBackFunc, 
+	IN	PVOID				pContext,
+	IN	const char*			szID
+	);
+
+VOID
+ODM_CancelTimer(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER		pTimer
+	);
+
+VOID
+ODM_ReleaseTimer(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER		pTimer
+	);
+
+
+//
+// ODM FW relative API.
+//
+#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
+VOID
+ODM_FillH2CCmd(
+	IN	PADAPTER		Adapter,
+	IN	u1Byte 	ElementID,
+	IN	u4Byte 	CmdLen,
+	IN	pu1Byte	pCmdBuffer
+);
+#else
+u4Byte
+ODM_FillH2CCmd(	
+	IN	pu1Byte		pH2CBuffer,
+	IN	u4Byte		H2CBufferLen,
+	IN	u4Byte		CmdNum,
+	IN	pu4Byte		pElementID,
+	IN	pu4Byte		pCmdLen,
+	IN	pu1Byte*		pCmbBuffer,
+	IN	pu1Byte		CmdStartSeq
+	);
+#endif
+#endif	// __ODM_INTERFACE_H__
+

hal/OUTSRC/odm_precomp.h

@@ -0,0 +1,222 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__ODM_PRECOMP_H__
+#define __ODM_PRECOMP_H__
+
+#include "odm_types.h"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+#include "Precomp.h"		// We need to include mp_precomp.h due to batch file setting.
+
+#else
+
+#define		TEST_FALG___		1
+
+#endif
+
+//2 Config Flags and Structs - defined by each ODM Type
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#include "../8192cd_cfg.h"
+	#include "../odm_inc.h"
+
+	#include "../8192cd.h"
+	#include "../8192cd_util.h"
+	#ifdef _BIG_ENDIAN_
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_BIG
+	#else
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#endif
+
+	#ifdef AP_BUILD_WORKAROUND
+	#include "../8192cd_headers.h"
+	#include "../8192cd_debug.h"		
+	#endif
+	
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+	// Flags
+	#include "../8192cd_cfg.h"		// OUTSRC needs ADSL config flags.
+	#include "../odm_inc.h"			// OUTSRC needs some extra flags.
+	// Data Structure
+	#include "../common_types.h"	// OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
+	#include "../8192cd.h"			// OUTSRC needs basic ADSL struct definition.
+	#include "../8192cd_util.h"		// OUTSRC needs basic I/O function.
+	#ifdef _BIG_ENDIAN_
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_BIG
+	#else
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#endif
+
+	#ifdef ADSL_AP_BUILD_WORKAROUND
+	// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
+	#include "../8192cd_headers.h"
+	#include "../8192cd_debug.h"	
+	#endif	
+	
+#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
+	#include <drv_conf.h>
+	#include <osdep_service.h>
+	#include <drv_types.h>
+	#include <rtw_byteorder.h>
+	#include <hal_intf.h>	
+		
+#elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
+	#include "Mp_Precomp.h"
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+#endif
+
+ 
+//2 Hardware Parameter Files
+
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#if (RTL8192C_SUPPORT==1)
+	#include "rtl8192c/Hal8192CEFWImg_AP.h"
+	#include "rtl8192c/Hal8192CEPHYImg_AP.h"
+	#include "rtl8192c/Hal8192CEMACImg_AP.h"
+#endif
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+	#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
+	#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
+	#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#if(RTL8192CE_SUPPORT ==1)
+	#include "rtl8192c/Hal8192CEFWImg_CE.h"
+	#include "rtl8192c/Hal8192CEPHYImg_CE.h"
+	#include "rtl8192c/Hal8192CEMACImg_CE.h"	
+	#elif(RTL8192CU_SUPPORT ==1)
+	#include "rtl8192c/Hal8192CUFWImg_CE.h"
+	#include "rtl8192c/Hal8192CUPHYImg_CE.h"
+	#include "rtl8192c/Hal8192CUMACImg_CE.h"
+	#elif(RTL8192DE_SUPPORT ==1)
+	#include "rtl8192d/Hal8192DEFWImg_CE.h"
+	#include "rtl8192d/Hal8192DEPHYImg_CE.h"
+	#include "rtl8192d/Hal8192DEMACImg_CE.h"	
+	#elif(RTL8192DU_SUPPORT ==1)
+	#include "rtl8192d/Hal8192DUFWImg_CE.h"
+	#include "rtl8192d/Hal8192DUPHYImg_CE.h"
+	#include "rtl8192d/Hal8192DUMACImg_CE.h"	
+	#elif(RTL8723AS_SUPPORT==1)
+	#include "rtl8723a/Hal8723SHWImg_CE.h"
+	#elif(RTL8723AU_SUPPORT==1)
+	#include "rtl8723a/Hal8723UHWImg_CE.h"	 
+	#elif(RTL8188E_SUPPORT==1)
+	#include "rtl8188e/Hal8188EFWImg_CE.h"	
+	#endif
+#elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
+
+#endif
+
+
+//2 OutSrc Header Files
+
+#include "odm.h"
+#include "odm_HWConfig.h"
+#include "odm_debug.h"
+#include "odm_RegDefine11AC.h"
+#include "odm_RegDefine11N.h"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#if (RTL8192C_SUPPORT==1)
+	#include "rtl8192c/HalDMOutSrc8192C_AP.h"
+#endif
+#if (RTL8188E_SUPPORT==1)
+		#include "rtl8188e/Hal8188ERateAdaptive.h"//for  RA,Power training
+#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+	#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#include "HalPhyRf.h"
+	#if (RTL8192C_SUPPORT==1) 
+		#ifdef CONFIG_INTEL_PROXIM
+		#include "../proxim/intel_proxim.h"	
+		#endif	
+		#include  "rtl8192c/HalDMOutSrc8192C_CE.h"
+		#include <rtl8192c_hal.h>
+	#elif (RTL8192D_SUPPORT==1)
+		#include  "rtl8192d/HalDMOutSrc8192D_CE.h"
+		#include  "rtl8192d_hal.h"
+	#elif (RTL8723A_SUPPORT==1)
+		#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
+		#include "rtl8723a_hal.h"  
+	#elif (RTL8188E_SUPPORT==1)		
+		#include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
+		#include "rtl8188e/Hal8188ERateAdaptive.h"//for  RA,Power training
+		#include "rtl8188e_hal.h"  	
+	#endif
+
+#endif
+
+#include "odm_interface.h"
+#include "odm_reg.h"
+
+#if (RTL8192C_SUPPORT==1) 
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#include "rtl8192c/Hal8192CHWImg_MAC.h"
+#include "rtl8192c/Hal8192CHWImg_RF.h"
+#include "rtl8192c/Hal8192CHWImg_BB.h"
+#include "rtl8192c/Hal8192CHWImg_FW.h"
+#endif
+#include "rtl8192c/odm_RTL8192C.h"
+#endif
+#if (RTL8192D_SUPPORT==1) 
+#include "rtl8192d/odm_RTL8192D.h"
+#endif
+
+#if (RTL8723A_SUPPORT==1) 
+#include "rtl8723a/HalHWImg8723A_MAC.h"
+#include "rtl8723a/HalHWImg8723A_RF.h"
+#include "rtl8723a/HalHWImg8723A_BB.h"
+#include "rtl8723a/HalHWImg8723A_FW.h"
+#include "rtl8723a/odm_RegConfig8723A.h"
+#endif
+
+#if (RTL8188E_SUPPORT==1) 
+#include "rtl8188e/HalHWImg8188E_MAC.h"
+#include "rtl8188e/HalHWImg8188E_RF.h"
+#include "rtl8188e/HalHWImg8188E_BB.h"
+#include "rtl8188e/Hal8188EReg.h"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#include "rtl8188e/HalPhyRf_8188e.h"
+#endif
+
+#if (RTL8188E_FOR_TEST_CHIP >= 1) 
+#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h"
+#include "rtl8188e/HalHWImg8188E_TestChip_RF.h"
+#include "rtl8188e/HalHWImg8188E_TestChip_BB.h"
+#endif
+
+#ifdef CONFIG_WOWLAN
+#if (RTL8188E_SUPPORT==1)
+#include "rtl8188e/HalHWImg8188E_FW.h"
+#endif
+#endif //CONFIG_WOWLAN
+
+#include "rtl8188e/odm_RegConfig8188E.h"
+#include "rtl8188e/odm_RTL8188E.h"
+#endif
+
+#endif	// __ODM_PRECOMP_H__
+

hal/OUTSRC/odm_reg.h

@@ -0,0 +1,120 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//============================================================
+// File Name: odm_reg.h
+//
+// Description:
+//
+// This file is for general register definition.
+//
+//
+//============================================================
+#ifndef	__HAL_ODM_REG_H__
+#define __HAL_ODM_REG_H__
+
+//
+// Register Definition
+//
+
+//MAC REG
+#define	ODM_BB_RESET					0x002
+#define	ODM_DUMMY						0x4fe
+#define	ODM_EDCA_VO_PARAM			0x500
+#define	ODM_EDCA_VI_PARAM			0x504
+#define	ODM_EDCA_BE_PARAM			0x508
+#define	ODM_EDCA_BK_PARAM			0x50C
+#define	ODM_TXPAUSE					0x522
+
+//BB REG
+#define	ODM_FPGA_PHY0_PAGE8			0x800
+#define	ODM_PSD_SETTING				0x808
+#define	ODM_AFE_SETTING				0x818
+#define	ODM_TXAGC_B_6_18				0x830
+#define	ODM_TXAGC_B_24_54			0x834
+#define	ODM_TXAGC_B_MCS32_5			0x838
+#define	ODM_TXAGC_B_MCS0_MCS3		0x83c
+#define	ODM_TXAGC_B_MCS4_MCS7		0x848
+#define	ODM_TXAGC_B_MCS8_MCS11		0x84c
+#define	ODM_ANALOG_REGISTER			0x85c
+#define	ODM_RF_INTERFACE_OUTPUT		0x860
+#define	ODM_TXAGC_B_MCS12_MCS15	0x868
+#define	ODM_TXAGC_B_11_A_2_11		0x86c
+#define	ODM_AD_DA_LSB_MASK			0x874
+#define	ODM_ENABLE_3_WIRE			0x88c
+#define	ODM_PSD_REPORT				0x8b4
+#define	ODM_R_ANT_SELECT				0x90c
+#define	ODM_CCK_ANT_SELECT			0xa07
+#define	ODM_CCK_PD_THRESH			0xa0a
+#define	ODM_CCK_RF_REG1				0xa11
+#define	ODM_CCK_MATCH_FILTER			0xa20
+#define	ODM_CCK_RAKE_MAC				0xa2e
+#define	ODM_CCK_CNT_RESET			0xa2d
+#define	ODM_CCK_TX_DIVERSITY			0xa2f
+#define	ODM_CCK_FA_CNT_MSB			0xa5b
+#define	ODM_CCK_FA_CNT_LSB			0xa5c
+#define	ODM_CCK_NEW_FUNCTION		0xa75
+#define	ODM_OFDM_PHY0_PAGE_C		0xc00
+#define	ODM_OFDM_RX_ANT				0xc04
+#define	ODM_R_A_RXIQI					0xc14
+#define	ODM_R_A_AGC_CORE1			0xc50
+#define	ODM_R_A_AGC_CORE2			0xc54
+#define	ODM_R_B_AGC_CORE1			0xc58
+#define	ODM_R_AGC_PAR					0xc70
+#define	ODM_R_HTSTF_AGC_PAR			0xc7c
+#define	ODM_TX_PWR_TRAINING_A		0xc90
+#define	ODM_TX_PWR_TRAINING_B		0xc98
+#define	ODM_OFDM_FA_CNT1				0xcf0
+#define	ODM_OFDM_PHY0_PAGE_D		0xd00
+#define	ODM_OFDM_FA_CNT2				0xda0
+#define	ODM_OFDM_FA_CNT3				0xda4
+#define	ODM_OFDM_FA_CNT4				0xda8
+#define	ODM_TXAGC_A_6_18				0xe00
+#define	ODM_TXAGC_A_24_54			0xe04
+#define	ODM_TXAGC_A_1_MCS32			0xe08
+#define	ODM_TXAGC_A_MCS0_MCS3		0xe10
+#define	ODM_TXAGC_A_MCS4_MCS7		0xe14
+#define	ODM_TXAGC_A_MCS8_MCS11		0xe18
+#define	ODM_TXAGC_A_MCS12_MCS15		0xe1c
+
+//RF REG
+#define	ODM_GAIN_SETTING				0x00
+#define	ODM_CHANNEL					0x18
+
+//Ant Detect Reg
+#define	ODM_DPDT						0x300
+
+//PSD Init
+#define	ODM_PSDREG					0x808
+
+//92D Path Div
+#define	PATHDIV_REG					0xB30
+#define	PATHDIV_TRI					0xBA0
+
+
+//
+// Bitmap Definition
+//
+
+#define	BIT_FA_RESET					BIT0
+
+
+
+#endif
+

hal/OUTSRC/odm_types.h

@@ -0,0 +1,252 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __ODM_TYPES_H__
+#define __ODM_TYPES_H__
+
+//
+// Define Different SW team support
+//
+#define	ODM_AP		 	0x01	 //BIT0 
+#define	ODM_ADSL	 	0x02	//BIT1
+#define	ODM_CE		 	0x04	//BIT2
+#define	ODM_MP		 	0x08	//BIT3
+
+#define	DM_ODM_SUPPORT_TYPE			ODM_CE
+
+// Deifne HW endian support
+#define	ODM_ENDIAN_BIG	0
+#define	ODM_ENDIAN_LITTLE	1	
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
+#define 	RT_PCI_INTERFACE				1
+#define 	RT_USB_INTERFACE				2
+#define 	RT_SDIO_INTERFACE				3
+#endif
+
+typedef enum _HAL_STATUS{
+	HAL_STATUS_SUCCESS,
+	HAL_STATUS_FAILURE,
+	/*RT_STATUS_PENDING,
+	RT_STATUS_RESOURCE,
+	RT_STATUS_INVALID_CONTEXT,
+	RT_STATUS_INVALID_PARAMETER,
+	RT_STATUS_NOT_SUPPORT,
+	RT_STATUS_OS_API_FAILED,*/
+}HAL_STATUS,*PHAL_STATUS;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+typedef enum _RT_SPINLOCK_TYPE{
+	RT_TEMP =1,
+}RT_SPINLOCK_TYPE;
+#elif( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL))
+
+#define		VISTA_USB_RX_REVISE			0
+
+//
+// Declare for ODM spin lock defintion temporarily fro compile pass.
+//
+typedef enum _RT_SPINLOCK_TYPE{
+	RT_TX_SPINLOCK = 1,
+	RT_RX_SPINLOCK = 2,
+	RT_RM_SPINLOCK = 3,
+	RT_CAM_SPINLOCK = 4,
+	RT_SCAN_SPINLOCK = 5,
+	RT_LOG_SPINLOCK = 7, 
+	RT_BW_SPINLOCK = 8,
+	RT_CHNLOP_SPINLOCK = 9,
+	RT_RF_OPERATE_SPINLOCK = 10,
+	RT_INITIAL_SPINLOCK = 11,
+	RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
+#if VISTA_USB_RX_REVISE
+	RT_USBRX_CONTEXT_SPINLOCK = 13,
+	RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
+#endif
+	//Shall we define Ndis 6.2 SpinLock Here ?
+	RT_PORT_SPINLOCK=16,
+	RT_VNIC_SPINLOCK=17,
+	RT_HVL_SPINLOCK=18,	
+	RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
+
+	RT_BTData_SPINLOCK=25,
+
+	RT_WAPI_OPTION_SPINLOCK=26,
+	RT_WAPI_RX_SPINLOCK=27,
+
+      // add for 92D CCK control issue  
+	RT_CCK_PAGEA_SPINLOCK = 28,
+	RT_BUFFER_SPINLOCK = 29,
+	RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
+	RT_GEN_TEMP_BUF_SPINLOCK = 31,
+	RT_AWB_SPINLOCK = 32,
+	RT_FW_PS_SPINLOCK = 33,
+	RT_HW_TIMER_SPIN_LOCK = 34,
+	RT_MPT_WI_SPINLOCK = 35
+}RT_SPINLOCK_TYPE;
+
+#endif
+
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+	#define	STA_INFO_T			RT_WLAN_STA
+	#define	PSTA_INFO_T			PRT_WLAN_STA
+
+//    typedef unsigned long		u4Byte,*pu4Byte;
+	#define CONFIG_HW_ANTENNA_DIVERSITY 
+#define CONFIG_SW_ANTENNA_DIVERSITY 
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
+	#define ADSL_AP_BUILD_WORKAROUND
+	#define AP_BUILD_WORKAROUND
+	//
+
+	#ifdef AP_BUILD_WORKAROUND
+	#include "../typedef.h"
+	#else
+	typedef void					VOID,*PVOID;
+	typedef unsigned char			BOOLEAN,*PBOOLEAN;
+	typedef unsigned char			u1Byte,*pu1Byte;
+	typedef unsigned short			u2Byte,*pu2Byte;
+	typedef unsigned int			u4Byte,*pu4Byte;
+	typedef unsigned long long		u8Byte,*pu8Byte;
+	typedef char					s1Byte,*ps1Byte;
+	typedef short					s2Byte,*ps2Byte;
+	typedef long					s4Byte,*ps4Byte;
+	typedef long long				s8Byte,*ps8Byte;
+	#endif
+
+	typedef struct rtl8192cd_priv	*prtl8192cd_priv;
+	typedef struct stat_info		STA_INFO_T,*PSTA_INFO_T;
+	typedef struct timer_list		RT_TIMER, *PRT_TIMER;
+	typedef  void *					RT_TIMER_CALL_BACK;
+	
+	#define 	DEV_BUS_TYPE  		RT_PCI_INTERFACE
+	
+	#define _TRUE				1
+	#define _FALSE				0
+	
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+
+	// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
+	#define ADSL_AP_BUILD_WORKAROUND
+	#define ADSL_BUILD_WORKAROUND
+	//
+
+	typedef unsigned char		BOOLEAN,*PBOOLEAN;
+	typedef unsigned char		u1Byte,*pu1Byte;
+	typedef unsigned short		u2Byte,*pu2Byte;
+	typedef unsigned int			u4Byte,*pu4Byte;
+	typedef unsigned long long	u8Byte,*pu8Byte;
+	typedef char				s1Byte,*ps1Byte;
+	typedef short				s2Byte,*ps2Byte;
+	typedef long				s4Byte,*ps4Byte;
+	typedef long long			s8Byte,*ps8Byte;
+
+	typedef struct rtl8192cd_priv	*prtl8192cd_priv;
+	typedef struct stat_info		STA_INFO_T,*PSTA_INFO_T;
+	typedef struct timer_list		RT_TIMER, *PRT_TIMER;
+	typedef  void *				RT_TIMER_CALL_BACK;
+	
+	#define DEV_BUS_TYPE  	RT_PCI_INTERFACE
+	
+	#define _TRUE				1
+	#define _FALSE				0
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#include <basic_types.h>
+
+#if 0
+	typedef u8					u1Byte, *pu1Byte;
+	typedef u16					u2Byte,*pu2Byte;
+	typedef u32					u4Byte,*pu4Byte;
+	typedef u64					u8Byte,*pu8Byte;
+	typedef s8					s1Byte,*ps1Byte;
+	typedef s16					s2Byte,*ps2Byte;
+	typedef s32					s4Byte,*ps4Byte;
+	typedef s64					s8Byte,*ps8Byte;
+#else
+	#define u1Byte 		u8
+	#define pu1Byte 		u8*	
+
+	#define u2Byte 		u16
+	#define pu2Byte 		u16*		
+
+	#define u4Byte 		u32
+	#define pu4Byte 		u32*	
+
+	#define u8Byte 		u64
+	#define pu8Byte 		u64*
+
+	#define s1Byte 		s8
+	#define ps1Byte 		s8*	
+
+	#define s2Byte 		s16
+	#define ps2Byte 		s16*	
+
+	#define s4Byte 		s32
+	#define ps4Byte 		s32*	
+
+	#define s8Byte 		s64
+	#define ps8Byte 		s64*	
+	
+#endif
+	#ifdef CONFIG_USB_HCI
+		#define DEV_BUS_TYPE  	RT_USB_INTERFACE
+	#elif defined(CONFIG_PCI_HCI)
+		#define DEV_BUS_TYPE  	RT_PCI_INTERFACE
+	#elif defined(CONFIG_SDIO_HCI)
+		#define DEV_BUS_TYPE  	RT_SDIO_INTERFACE
+        #elif defined(CONFIG_GSPI_HCI)
+		#define DEV_BUS_TYPE  	RT_SDIO_INTERFACE
+	#endif
+	
+
+	#if defined(CONFIG_LITTLE_ENDIAN)	
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
+	#elif defined (CONFIG_BIG_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
+	#endif
+	
+	typedef struct timer_list		RT_TIMER, *PRT_TIMER;
+	typedef  void *				RT_TIMER_CALL_BACK;
+	#define	STA_INFO_T			struct sta_info
+	#define	PSTA_INFO_T		struct sta_info *
+		
+
+
+	#define TRUE 	_TRUE	
+	#define FALSE	_FALSE
+	
+
+	#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
+	#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
+	#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
+
+	//define useless flag to avoid compile warning
+	#define	USE_WORKITEM 			0
+	#define 	FOR_BRAZIL_PRETEST	0
+	#define	BT_30_SUPPORT			0
+	#define   FPGA_TWO_MAC_VERIFICATION	0
+#endif
+
+
+#endif // __ODM_TYPES_H__
+

hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c

@@ -0,0 +1,892 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+#include "../odm_precomp.h"
+ 
+const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength] = {
+0xE1, 0x88, 0x10, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01, 0x21, 0x11, 0x27, 0x30, 0x36, 0x00, 0x00, 
+0x2D, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x02, 0x45, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0xC1, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0xA1, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x56, 0xF7, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x42, 0x04, 0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0, 
+0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A, 0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C, 
+0xEC, 0x24, 0x89, 0xF8, 0xE6, 0xBC, 0x03, 0x02, 0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00, 
+0x40, 0xCE, 0x79, 0x04, 0x78, 0x80, 0x16, 0xE6, 0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1, 
+0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9, 0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF, 
+0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF, 0x04, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30, 
+0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50, 0x20, 0x05, 0x0C, 0x74, 0x88, 0x25, 0x0C, 0xF8, 
+0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8, 
+0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80, 0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5, 
+0x0C, 0x24, 0x89, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD, 
+0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0, 0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x88, 
+0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C, 0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF, 
+0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F, 0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F, 
+0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x88, 0xA6, 
+0x81, 0x74, 0x03, 0x60, 0x06, 0xFF, 0x08, 0x76, 0xFF, 0xDF, 0xFB, 0x7F, 0x04, 0xE4, 0x78, 0x80, 
+0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81, 0x76, 0x30, 0x90, 0x45, 0xDE, 0x74, 0x01, 0x93, 
+0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89, 0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2, 
+0x8C, 0xD2, 0xAF, 0x22, 0x03, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81, 
+0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE, 
+0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74, 0x88, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18, 
+0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09, 
+0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE, 0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81, 
+0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x88, 0x2E, 0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02, 
+0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09, 
+0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF, 0x24, 0x88, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F, 
+0x04, 0x90, 0x45, 0xDE, 0x93, 0xF6, 0x08, 0xEF, 0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 
+0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4, 
+0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF, 0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x88, 0x2F, 
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+0x06, 0x90, 0x06, 0x92, 0x74, 0x1C, 0xF0, 0xE4, 0x90, 0x81, 0x48, 0xF0, 0x22, 0x00, 0xBB, 0x8E, 
+};

hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h

@@ -0,0 +1,29 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+#ifndef __INC_HAL8188E_FW_IMG_H
+#define __INC_HAL8188E_FW_IMG_H
+
+//V10(1641)
+#define Rtl8188EFWImgArrayLength 13904
+
+extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
+
+#endif //__INC_HAL8188E_FW_IMG_H
+

hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h

@@ -0,0 +1,108 @@
+#ifndef __INC_RA_H
+#define __INC_RA_H
+/*++
+Copyright (c) Realtek Semiconductor Corp. All rights reserved.
+
+Module Name:
+	RateAdaptive.h
+	
+Abstract:
+	Prototype of RA and related data structure.
+	    
+Major Change History:
+	When       Who               What
+	---------- ---------------   -------------------------------
+	2011-08-12 Page            Create.	
+--*/
+
+// Rate adaptive define
+#define	PERENTRY	23
+#define	RETRYSIZE	5
+#define	RATESIZE	28
+#define	TX_RPT2_ITEM_SIZE 	8
+
+#if (DM_ODM_SUPPORT_TYPE  != ODM_MP)
+//
+// TX report 2 format in Rx desc
+//
+#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc)				LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
+#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
+#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
+
+#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr)						LE_BITS_TO_4BYTE( __pAddr, 0, 16)
+#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr)						LE_BITS_TO_1BYTE( __pAddr+2, 0, 8)
+#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr)						LE_BITS_TO_1BYTE( __pAddr+3, 0, 8)
+#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr)						LE_BITS_TO_1BYTE( __pAddr+4, 0, 8)
+#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr)						LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8)
+#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr)						LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8)
+#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr)						LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8)
+#endif
+
+// End rate adaptive define
+
+VOID
+ODM_RASupport_Init(
+	IN	PDM_ODM_T	pDM_Odm
+	);
+
+int 
+ODM_RAInfo_Init_all(
+	IN    PDM_ODM_T		pDM_Odm
+	);
+
+int 
+ODM_RAInfo_Init(
+	IN 	PDM_ODM_T 	pDM_Odm,
+	IN 	u1Byte 		MacID	
+	);
+
+u1Byte 
+ODM_RA_GetShortGI_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm, 
+	IN 	u1Byte 		MacID
+	);
+
+u1Byte 
+ODM_RA_GetDecisionRate_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm, 
+	IN 	u1Byte 		MacID
+	);
+
+u1Byte
+ODM_RA_GetHwPwrStatus_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm, 
+	IN 	u1Byte 		MacID
+	);
+VOID 
+ODM_RA_UpdateRateInfo_8188E(
+	IN PDM_ODM_T pDM_Odm,
+	IN u1Byte MacID,
+	IN u1Byte RateID, 
+	IN u4Byte RateMask,
+	IN u1Byte SGIEnable
+	);
+
+VOID 
+ODM_RA_SetRSSI_8188E(
+	IN 	PDM_ODM_T 		pDM_Odm, 
+	IN 	u1Byte 			MacID, 
+	IN 	u1Byte 			Rssi
+	);
+
+VOID
+ODM_RA_TxRPT2Handle_8188E(	
+	IN	PDM_ODM_T		pDM_Odm,
+	IN	pu1Byte			TxRPT_Buf,
+	IN	u2Byte			TxRPT_Len,
+	IN	u4Byte			MacIDValidEntry0,
+	IN	u4Byte			MacIDValidEntry1
+	);
+	
+
+VOID 
+ODM_RA_Set_TxRPT_Time(
+	IN	PDM_ODM_T		pDM_Odm,
+	IN	u2Byte 			minRptTime
+	);	
+#endif
+

hal/OUTSRC/rtl8188e/Hal8188EReg.h

@@ -0,0 +1,47 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//============================================================
+// File Name: Hal8188EReg.h
+//
+// Description:
+//
+// This file is for RTL8188E register definition.
+//
+//
+//============================================================
+#ifndef	__HAL_8188E_REG_H__
+#define __HAL_8188E_REG_H__
+
+//
+// Register Definition
+//
+#define TRX_ANTDIV_PATH             0x860
+#define RX_ANTDIV_PATH              0xb2c
+#define	ODM_R_A_AGC_CORE1_8188E		0xc50
+
+
+//
+// Bitmap Definition
+//
+#define	BIT_FA_RESET_8188E			BIT0
+
+
+#endif
+

hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h

@@ -0,0 +1,71 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_BB_8188E_HW_IMG_H
+#define __INC_BB_8188E_HW_IMG_H
+
+//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
+
+/******************************************************************************
+*                           AGC_TAB_1T.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_AGC_TAB_1T_8188E(
+	IN   PDM_ODM_T  pDM_Odm
+);
+/******************************************************************************
+*                           AGC_TAB_1T_ICUT.TXT
+******************************************************************************/
+
+void
+ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
+	IN   PDM_ODM_T  pDM_Odm
+);
+/******************************************************************************
+*                           PHY_REG_1T.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_PHY_REG_1T_8188E(
+	IN   PDM_ODM_T  pDM_Odm
+);
+/******************************************************************************
+*                           PHY_REG_1T_ICUT.TXT
+******************************************************************************/
+
+void
+ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
+	IN   PDM_ODM_T  pDM_Odm
+);
+
+/******************************************************************************
+*                           PHY_REG_PG.TXT
+******************************************************************************/
+
+void
+ODM_ReadAndConfig_PHY_REG_PG_8188E(
+	IN   PDM_ODM_T  pDM_Odm
+);
+
+#endif
+#endif // end of HWIMG_SUPPORT
+

hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_FW_8188E_HW_IMG_H
+#define __INC_FW_8188E_HW_IMG_H
+
+
+/******************************************************************************
+*                           FW_AP.TXT
+******************************************************************************/
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
+void
+ODM_ReadFirmware_8188E_FW_AP(
+     IN   PDM_ODM_T    pDM_Odm,
+     OUT  u1Byte       *pFirmware,
+     OUT  u4Byte       *pFirmwareSize
+);
+
+#else
+/******************************************************************************
+*                           FW_NIC.TXT
+******************************************************************************/
+#if 0
+void
+ODM_ReadFirmware_8188E_FW_NIC(
+     IN   PDM_ODM_T    pDM_Odm,
+     OUT  u1Byte       *pFirmware,
+     OUT  u4Byte       *pFirmwareSize
+);
+#endif
+/******************************************************************************
+*                           FW_WoWLAN.TXT
+******************************************************************************/
+#if 0
+void
+ODM_ReadFirmware_8188E_FW_WoWLAN(
+     IN   PDM_ODM_T    pDM_Odm,
+     OUT  u1Byte       *pFirmware,
+     OUT  u4Byte       *pFirmwareSize
+);
+#endif
+#define ArrayLength_8188E_FW_WoWLAN 15080
+extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
+#endif
+
+#endif
+#endif // end of HWIMG_SUPPORT

hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c

@@ -0,0 +1,502 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+
+#include "../odm_precomp.h"
+#ifdef CONFIG_IOL_IOREG_CFG
+#include <rtw_iol.h>
+#endif
+#if (RTL8188E_SUPPORT == 1)
+static BOOLEAN
+CheckCondition(
+    const u4Byte  Condition,
+    const u4Byte  Hex
+    )
+{
+    u4Byte _board     = (Hex & 0x000000FF);
+    u4Byte _interface = (Hex & 0x0000FF00) >> 8;
+    u4Byte _platform  = (Hex & 0x00FF0000) >> 16;
+    u4Byte cond = Condition;
+
+    if ( Condition == 0xCDCDCDCD )
+        return TRUE;
+
+    cond = Condition & 0x000000FF;
+    if ( (_board != cond) && (cond != 0xFF) )
+        return FALSE;
+
+    cond = Condition & 0x0000FF00;
+    cond = cond >> 8;
+    if ( ((_interface & cond) == 0) && (cond != 0x07) )
+        return FALSE;
+
+    cond = Condition & 0x00FF0000;
+    cond = cond >> 16;
+    if ( ((_platform & cond) == 0) && (cond != 0x0F) )
+        return FALSE;
+    return TRUE;
+}
+
+
+/******************************************************************************
+*                           MAC_REG.TXT
+******************************************************************************/
+
+u4Byte Array_MAC_REG_8188E[] = {
+		0x026, 0x00000041,		
+		0x027, 0x00000035,
+	0xFF0F0718, 0xABCD,
+		0x040, 0x0000000C,
+	0xCDCDCDCD, 0xCDCD,
+		0x040, 0x00000000,
+	0xFF0F0718, 0xDEAD,
+		0x428, 0x0000000A,
+		0x429, 0x00000010,
+		0x430, 0x00000000,
+		0x431, 0x00000001,
+		0x432, 0x00000002,
+		0x433, 0x00000004,
+		0x434, 0x00000005,
+		0x435, 0x00000006,
+		0x436, 0x00000007,
+		0x437, 0x00000008,
+		0x438, 0x00000000,
+		0x439, 0x00000000,
+		0x43A, 0x00000001,
+		0x43B, 0x00000002,
+		0x43C, 0x00000004,
+		0x43D, 0x00000005,
+		0x43E, 0x00000006,
+		0x43F, 0x00000007,
+		0x440, 0x0000005D,
+		0x441, 0x00000001,
+		0x442, 0x00000000,
+		0x444, 0x00000015,
+		0x445, 0x000000F0,
+		0x446, 0x0000000F,
+		0x447, 0x00000000,
+		0x458, 0x00000041,
+		0x459, 0x000000A8,
+		0x45A, 0x00000072,
+		0x45B, 0x000000B9,
+		0x460, 0x00000066,
+		0x461, 0x00000066,
+		0x480, 0x00000008,
+		0x4C8, 0x000000FF,
+		0x4C9, 0x00000008,
+		0x4CC, 0x000000FF,
+		0x4CD, 0x000000FF,
+		0x4CE, 0x00000001,
+		0x4D3, 0x00000001,
+		0x500, 0x00000026,
+		0x501, 0x000000A2,
+		0x502, 0x0000002F,
+		0x503, 0x00000000,
+		0x504, 0x00000028,
+		0x505, 0x000000A3,
+		0x506, 0x0000005E,
+		0x507, 0x00000000,
+		0x508, 0x0000002B,
+		0x509, 0x000000A4,
+		0x50A, 0x0000005E,
+		0x50B, 0x00000000,
+		0x50C, 0x0000004F,
+		0x50D, 0x000000A4,
+		0x50E, 0x00000000,
+		0x50F, 0x00000000,
+		0x512, 0x0000001C,
+		0x514, 0x0000000A,
+		0x516, 0x0000000A,
+		0x525, 0x0000004F,
+		0x550, 0x00000010,
+		0x551, 0x00000010,
+		0x559, 0x00000002,
+		0x55D, 0x000000FF,
+		0x605, 0x00000030,
+		0x608, 0x0000000E,
+		0x609, 0x0000002A,
+		0x620, 0x000000FF,
+		0x621, 0x000000FF,
+		0x622, 0x000000FF,
+		0x623, 0x000000FF,
+		0x624, 0x000000FF,
+		0x625, 0x000000FF,
+		0x626, 0x000000FF,
+		0x627, 0x000000FF,
+		0x652, 0x00000020,
+		0x63C, 0x0000000A,
+		0x63D, 0x0000000A,
+		0x63E, 0x0000000E,
+		0x63F, 0x0000000E,
+		0x640, 0x00000040,
+		0x66E, 0x00000005,
+		0x700, 0x00000021,
+		0x701, 0x00000043,
+		0x702, 0x00000065,
+		0x703, 0x00000087,
+		0x708, 0x00000021,
+		0x709, 0x00000043,
+		0x70A, 0x00000065,
+		0x70B, 0x00000087,	
+};
+
+HAL_STATUS
+ODM_ReadAndConfig_MAC_REG_8188E(
+ 	IN   PDM_ODM_T  pDM_Odm
+ 	)
+{
+	#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+	u4Byte     hex         = 0;
+	u4Byte     i           = 0;
+	u2Byte     count       = 0;
+	pu4Byte    ptr_array   = NULL;
+	u1Byte     platform    = pDM_Odm->SupportPlatform;
+	u1Byte     interfaceValue   = pDM_Odm->SupportInterface;
+	u1Byte     board       = pDM_Odm->BoardType;  
+	u4Byte     ArrayLen    = sizeof(Array_MAC_REG_8188E)/sizeof(u4Byte);
+	pu4Byte    Array       = Array_MAC_REG_8188E;
+	BOOLEAN		biol = FALSE;	
+	
+#ifdef CONFIG_IOL_IOREG_CFG 
+	PADAPTER	Adapter =  pDM_Odm->Adapter;	
+	struct xmit_frame	*pxmit_frame;	
+	u8 bndy_cnt = 1;
+	#ifdef CONFIG_IOL_IOREG_CFG_DBG
+	struct cmd_cmp cmpdata[ArrayLen];
+	u4Byte	cmpdata_idx=0;
+	#endif
+#endif //CONFIG_IOL_IOREG_CFG
+	HAL_STATUS rst =HAL_STATUS_SUCCESS;
+	hex += board;
+	hex += interfaceValue << 8;
+	hex += platform << 16;
+	hex += 0xFF000000;
+
+#ifdef CONFIG_IOL_IOREG_CFG 			
+	biol = rtw_IOL_applied(Adapter);
+	
+	if(biol){		
+		if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
+		{
+			printk("rtw_IOL_accquire_xmit_frame failed\n");
+			return HAL_STATUS_FAILURE;
+		}
+	}
+	
+#endif //CONFIG_IOL_IOREG_CFG
+	
+	for (i = 0; i < ArrayLen; i += 2 )
+	{
+		u4Byte v1 = Array[i];
+	    	u4Byte v2 = Array[i+1];
+	
+	    	// This (offset, data) pair meets the condition.
+	    	if ( v1 < 0xCDCDCDCD )
+	    	{
+	    		#ifdef CONFIG_IOL_IOREG_CFG 	
+				
+	 			if(biol){	
+					
+					if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+						bndy_cnt++;
+					rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF);
+					#ifdef CONFIG_IOL_IOREG_CFG_DBG
+						cmpdata[cmpdata_idx].addr = v1;
+						cmpdata[cmpdata_idx].value= v2;
+						cmpdata_idx++;
+					#endif					
+	 			}
+				else
+			#endif	//endif CONFIG_IOL_IOREG_CFG
+				{
+					odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
+				}
+				continue;
+	    	}
+	   	else
+	  	{ // This line is the start line of branch.
+	    		if ( !CheckCondition(Array[i], hex) )
+	    		{ // Discard the following (offset, data) pairs.
+	       		READ_NEXT_PAIR(v1, v2, i);
+				while (	v2 != 0xDEAD && 
+		             		v2 != 0xCDEF && 
+		               		v2 != 0xCDCD && i < ArrayLen -2)
+		            {
+		            		READ_NEXT_PAIR(v1, v2, i);
+				}
+		    		i -= 2; // prevent from for-loop += 2
+		    	}
+		    	else // Configure matched pairs and skip to end of if-else.
+		    	{
+		    		READ_NEXT_PAIR(v1, v2, i);
+		      		while (	v2 != 0xDEAD && 
+		      				v2 != 0xCDEF && 
+		             		v2 != 0xCDCD && i < ArrayLen -2)
+		             {
+		             	#ifdef CONFIG_IOL_IOREG_CFG 
+	 				if(biol){	
+						if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+							bndy_cnt++;
+						rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF);
+						#ifdef CONFIG_IOL_IOREG_CFG_DBG
+							cmpdata[cmpdata_idx].addr = v1;
+							cmpdata[cmpdata_idx].value= v2;
+							cmpdata_idx++;
+						#endif
+	 				}
+					else
+					#endif //#ifdef CONFIG_IOL_IOREG_CFG 
+					{
+						odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
+					}
+					
+		            		READ_NEXT_PAIR(v1, v2, i);
+		        	}
+
+		        	while (v2 != 0xDEAD && i < ArrayLen -2)
+		        	{
+		        		READ_NEXT_PAIR(v1, v2, i);
+		        	}
+		        
+		    	}
+		}	
+	}
+						
+#ifdef CONFIG_IOL_IOREG_CFG 
+	if(biol){
+		//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);		
+		
+		if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
+		{			
+			#ifdef CONFIG_IOL_IOREG_CFG_DBG			
+			printk("~~~ IOL Config MAC Success !!! \n");
+			//compare writed data
+			{
+				u4Byte idx;
+				u1Byte cdata;
+				// HAL_STATUS_FAILURE;
+				printk("  MAC data compare => array_len:%d \n",cmpdata_idx);
+				for(idx=0;idx< cmpdata_idx;idx++)
+				{
+					cdata = ODM_Read1Byte(pDM_Odm, cmpdata[idx].addr);
+					if(cdata != cmpdata[idx].value){
+						printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n",
+							cmpdata[idx].addr,cmpdata[idx].value,cdata);
+						//rst = HAL_STATUS_FAILURE;
+					}					
+				}	
+
+
+				//dump data from TX packet buffer
+				//if(rst == HAL_STATUS_FAILURE)
+				{
+					rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+				}	
+				
+			}
+			#endif //CONFIG_IOL_IOREG_CFG_DBG
+		
+		}
+		else{
+			printk("~~~ MAC IOL_exec_cmds Failed !!! \n");
+			#ifdef CONFIG_IOL_IOREG_CFG_DBG
+			{
+				//dump data from TX packet buffer				
+				rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+			}
+			#endif //CONFIG_IOL_IOREG_CFG_DBG
+			rst = HAL_STATUS_FAILURE;			
+		}
+		
+	}
+#endif	//#ifdef CONFIG_IOL_IOREG_CFG 
+	return rst;
+}
+
+/******************************************************************************
+*                           MAC_REG_ICUT.TXT
+******************************************************************************/
+
+u4Byte Array_MP_8188E_MAC_REG_ICUT[] = { 
+		0x026, 0x00000041,
+		0x027, 0x00000035,
+		0x428, 0x0000000A,
+		0x429, 0x00000010,
+		0x430, 0x00000000,
+		0x431, 0x00000001,
+		0x432, 0x00000002,
+		0x433, 0x00000004,
+		0x434, 0x00000005,
+		0x435, 0x00000006,
+		0x436, 0x00000007,
+		0x437, 0x00000008,
+		0x438, 0x00000000,
+		0x439, 0x00000000,
+		0x43A, 0x00000001,
+		0x43B, 0x00000002,
+		0x43C, 0x00000004,
+		0x43D, 0x00000005,
+		0x43E, 0x00000006,
+		0x43F, 0x00000007,
+		0x440, 0x0000005D,
+		0x441, 0x00000001,
+		0x442, 0x00000000,
+		0x444, 0x00000015,
+		0x445, 0x000000F0,
+		0x446, 0x0000000F,
+		0x447, 0x00000000,
+		0x458, 0x00000041,
+		0x459, 0x000000A8,
+		0x45A, 0x00000072,
+		0x45B, 0x000000B9,
+		0x460, 0x00000066,
+		0x461, 0x00000066,
+		0x480, 0x00000008,
+		0x4C8, 0x000000FF,
+		0x4C9, 0x00000008,
+		0x4CC, 0x000000FF,
+		0x4CD, 0x000000FF,
+		0x4CE, 0x00000001,
+		0x4D3, 0x00000001,
+		0x500, 0x00000026,
+		0x501, 0x000000A2,
+		0x502, 0x0000002F,
+		0x503, 0x00000000,
+		0x504, 0x00000028,
+		0x505, 0x000000A3,
+		0x506, 0x0000005E,
+		0x507, 0x00000000,
+		0x508, 0x0000002B,
+		0x509, 0x000000A4,
+		0x50A, 0x0000005E,
+		0x50B, 0x00000000,
+		0x50C, 0x0000004F,
+		0x50D, 0x000000A4,
+		0x50E, 0x00000000,
+		0x50F, 0x00000000,
+		0x512, 0x0000001C,
+		0x514, 0x0000000A,
+		0x516, 0x0000000A,
+		0x525, 0x0000004F,
+		0x550, 0x00000010,
+		0x551, 0x00000010,
+		0x559, 0x00000002,
+		0x55D, 0x000000FF,
+		0x605, 0x00000030,
+		0x608, 0x0000000E,
+		0x609, 0x0000002A,
+		0x620, 0x000000FF,
+		0x621, 0x000000FF,
+		0x622, 0x000000FF,
+		0x623, 0x000000FF,
+		0x624, 0x000000FF,
+		0x625, 0x000000FF,
+		0x626, 0x000000FF,
+		0x627, 0x000000FF,
+		0x652, 0x00000020,
+		0x63C, 0x0000000A,
+		0x63D, 0x0000000A,
+		0x63E, 0x0000000E,
+		0x63F, 0x0000000E,
+		0x640, 0x00000040,
+		0x66E, 0x00000005,
+		0x700, 0x00000021,
+		0x701, 0x00000043,
+		0x702, 0x00000065,
+		0x703, 0x00000087,
+		0x708, 0x00000021,
+		0x709, 0x00000043,
+		0x70A, 0x00000065,
+		0x70B, 0x00000087,
+
+};
+
+void
+ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
+ 	IN   PDM_ODM_T  pDM_Odm
+ 	)
+{
+	#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+	u4Byte     hex         = 0;
+	u4Byte     i           = 0;
+	u2Byte     count       = 0;
+	pu4Byte    ptr_array   = NULL;
+	u1Byte     platform    = pDM_Odm->SupportPlatform;
+	u1Byte     _interface   = pDM_Odm->SupportInterface;
+	u1Byte     board       = pDM_Odm->BoardType;  
+	u4Byte     ArrayLen    = sizeof(Array_MP_8188E_MAC_REG_ICUT)/sizeof(u4Byte);
+	pu4Byte    Array       = Array_MP_8188E_MAC_REG_ICUT;
+
+
+	hex += board;
+	hex += _interface << 8;
+	hex += platform << 16;
+	hex += 0xFF000000;
+	ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_MAC_REG_ICUT, hex = 0x%X\n", hex));
+
+	for (i = 0; i < ArrayLen; i += 2 )
+	{
+	    u4Byte v1 = Array[i];
+	    u4Byte v2 = Array[i+1];
+	
+	    // This (offset, data) pair meets the condition.
+	    if ( v1 < 0xCDCDCDCD )
+	    {
+	 		odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
+		    continue;
+	 	}
+		else
+		{ // This line is the start line of branch.
+		    if ( !CheckCondition(Array[i], hex) )
+		    { // Discard the following (offset, data) pairs.
+		        READ_NEXT_PAIR(v1, v2, i);
+		        while (v2 != 0xDEAD && 
+		               v2 != 0xCDEF && 
+		               v2 != 0xCDCD && i < ArrayLen -2)
+		        {
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+		        i -= 2; // prevent from for-loop += 2
+		    }
+		    else // Configure matched pairs and skip to end of if-else.
+		    {
+		        READ_NEXT_PAIR(v1, v2, i);
+		        while (v2 != 0xDEAD && 
+		               v2 != 0xCDEF && 
+		               v2 != 0xCDCD && i < ArrayLen -2)
+		        {
+	 				odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+
+		        while (v2 != 0xDEAD && i < ArrayLen -2)
+		        {
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+		        
+		    }
+		}	
+	}
+
+}
+
+#endif // end of HWIMG_SUPPORT
+

hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h

@@ -0,0 +1,47 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_MAC_8188E_HW_IMG_H
+#define __INC_MAC_8188E_HW_IMG_H
+
+//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
+
+/******************************************************************************
+*                           MAC_REG.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_MAC_REG_8188E(
+	IN   PDM_ODM_T  pDM_Odm
+);
+
+/******************************************************************************
+*                           MAC_REG_ICUT.TXT
+******************************************************************************/
+
+void
+ODM_ReadAndConfig_MAC_REG_ICUT_8188E( // TC: Test Chip, MP: MP Chip
+	IN   PDM_ODM_T  pDM_Odm
+);
+
+#endif
+#endif // end of HWIMG_SUPPORT
+

hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c

@@ -0,0 +1,569 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+
+#include "../odm_precomp.h"
+
+#ifdef CONFIG_IOL_IOREG_CFG
+#include <rtw_iol.h>
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+static BOOLEAN
+CheckCondition(
+    const u4Byte  Condition,
+    const u4Byte  Hex
+    )
+{
+    u4Byte _board     = (Hex & 0x000000FF);
+    u4Byte _interface = (Hex & 0x0000FF00) >> 8;
+    u4Byte _platform  = (Hex & 0x00FF0000) >> 16;
+    u4Byte cond = Condition;
+
+    if ( Condition == 0xCDCDCDCD )
+        return TRUE;
+
+    cond = Condition & 0x000000FF;
+    if ( (_board != cond) && (cond != 0xFF) )
+        return FALSE;
+
+    cond = Condition & 0x0000FF00;
+    cond = cond >> 8;
+    if ( ((_interface & cond) == 0) && (cond != 0x07) )
+        return FALSE;
+
+    cond = Condition & 0x00FF0000;
+    cond = cond >> 16;
+    if ( ((_platform & cond) == 0) && (cond != 0x0F) )
+        return FALSE;
+    return TRUE;
+}
+
+
+/******************************************************************************
+*                           RadioA_1T.TXT
+******************************************************************************/
+
+u4Byte Array_RadioA_1T_8188E[] = { 
+		0x000, 0x00030000,
+		0x008, 0x00084000,
+		0x018, 0x00000407,
+		0x019, 0x00000012,
+		0x01E, 0x00080009,
+		0x01F, 0x00000880,
+		0x02F, 0x0001A060,
+		0x03F, 0x00000000,
+		0x042, 0x000060C0,
+		0x057, 0x000D0000,
+		0x058, 0x000BE180,
+		0x067, 0x00001552,
+		0x083, 0x00000000,
+		0x0B0, 0x000FF8FC,
+		0x0B1, 0x00054400,
+		0x0B2, 0x000CCC19,
+		0x0B4, 0x00043003,
+		0x0B6, 0x0004953E,
+		0x0B7, 0x0001C718,
+		0x0B8, 0x000060FF,
+		0x0B9, 0x00080001,
+		0x0BA, 0x00040000,
+		0x0BB, 0x00000400,
+		0x0BF, 0x000C0000,
+		0x0C2, 0x00002400,
+		0x0C3, 0x00000009,
+		0x0C4, 0x00040C91,
+		0x0C5, 0x00099999,
+		0x0C6, 0x000000A3,
+		0x0C7, 0x00088820,
+		0x0C8, 0x00076C06,
+		0x0C9, 0x00000000,
+		0x0CA, 0x00080000,
+		0x0DF, 0x00000180,
+		0x0EF, 0x000001A0,
+		0x051, 0x0006B27D,
+	0xFF0F0400, 0xABCD,
+		0x052, 0x0007E4DD,
+	0xCDCDCDCD, 0xCDCD,
+		0x052, 0x0007E49D,
+	0xFF0F0400, 0xDEAD,
+		0x053, 0x00000073,
+		0x056, 0x00051FF3,
+		0x035, 0x00000086,
+		0x035, 0x00000186,
+		0x035, 0x00000286,
+		0x036, 0x00001C25,
+		0x036, 0x00009C25,
+		0x036, 0x00011C25,
+		0x036, 0x00019C25,
+		0x0B6, 0x00048538,
+		0x018, 0x00000C07,
+		0x05A, 0x0004BD00,
+		0x019, 0x000739D0,
+	0xFF0F0718, 0xABCD,
+		0x034, 0x0000A093,
+		0x034, 0x0000908F,
+		0x034, 0x0000808C,
+		0x034, 0x0000704F,
+		0x034, 0x0000604C,
+		0x034, 0x00005049,
+		0x034, 0x0000400C,
+		0x034, 0x00003009,
+		0x034, 0x00002006,
+		0x034, 0x00001003,
+		0x034, 0x00000000,
+	0xCDCDCDCD, 0xCDCD,
+		0x034, 0x0000ADF3,
+		0x034, 0x00009DF0,
+		0x034, 0x00008DED,
+		0x034, 0x00007DEA,
+		0x034, 0x00006DE7,
+		0x034, 0x000054EE,
+		0x034, 0x000044EB,
+		0x034, 0x000034E8,
+		0x034, 0x0000246B,
+		0x034, 0x00001468,
+		0x034, 0x0000006D,
+	0xFF0F0718, 0xDEAD,
+		0x000, 0x00030159,
+		0x084, 0x00068200,
+		0x086, 0x000000CE,
+		0x087, 0x00048A00,
+		0x08E, 0x00065540,
+		0x08F, 0x00088000,
+		0x0EF, 0x000020A0,
+		0x03B, 0x000F02B0,
+		0x03B, 0x000EF7B0,
+		0x03B, 0x000D4FB0,
+		0x03B, 0x000CF060,
+		0x03B, 0x000B0090,
+		0x03B, 0x000A0080,
+		0x03B, 0x00090080,
+		0x03B, 0x0008F780,
+		0x03B, 0x000722B0,
+		0x03B, 0x0006F7B0,
+		0x03B, 0x00054FB0,
+		0x03B, 0x0004F060,
+		0x03B, 0x00030090,
+		0x03B, 0x00020080,
+		0x03B, 0x00010080,
+		0x03B, 0x0000F780,
+		0x0EF, 0x000000A0,
+		0x000, 0x00010159,
+		0x018, 0x0000F407,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0x01F, 0x00080003,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0x01E, 0x00000001,
+		0x01F, 0x00080000,
+		0x000, 0x00033E60,
+
+};
+
+HAL_STATUS
+ODM_ReadAndConfig_RadioA_1T_8188E(
+ 	IN   PDM_ODM_T  pDM_Odm
+ 	)
+{
+	#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+	u4Byte     hex         = 0;
+	u4Byte     i           = 0;
+	u2Byte     count       = 0;
+	pu4Byte    ptr_array   = NULL;
+	u1Byte     platform    = pDM_Odm->SupportPlatform;
+	u1Byte     interfaceValue   = pDM_Odm->SupportInterface;
+	u1Byte     board       = pDM_Odm->BoardType;  
+	u4Byte     ArrayLen    = sizeof(Array_RadioA_1T_8188E)/sizeof(u4Byte);
+	pu4Byte    Array       = Array_RadioA_1T_8188E;
+	BOOLEAN		biol = FALSE;
+#ifdef CONFIG_IOL_IOREG_CFG 
+	PADAPTER	Adapter =  pDM_Odm->Adapter;	
+	struct xmit_frame	*pxmit_frame;	
+	u8 bndy_cnt = 1;
+	#ifdef CONFIG_IOL_IOREG_CFG_DBG
+	struct cmd_cmp cmpdata[ArrayLen];
+	u4Byte	cmpdata_idx=0;
+	#endif
+#endif//#ifdef CONFIG_IOL_IOREG_CFG 
+	HAL_STATUS rst =HAL_STATUS_SUCCESS;
+
+	hex += board;
+	hex += interfaceValue << 8;
+	hex += platform << 16;
+	hex += 0xFF000000;
+#ifdef CONFIG_IOL_IOREG_CFG 
+	biol = rtw_IOL_applied(Adapter);
+	
+	if(biol){		
+		if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
+		{
+			printk("rtw_IOL_accquire_xmit_frame failed\n");
+			return HAL_STATUS_FAILURE;
+		}
+	}		
+#endif//#ifdef CONFIG_IOL_IOREG_CFG 
+	
+	for (i = 0; i < ArrayLen; i += 2 )
+	{
+	    u4Byte v1 = Array[i];
+	    u4Byte v2 = Array[i+1];
+	
+	    // This (offset, data) pair meets the condition.
+	    if ( v1 < 0xCDCDCDCD )
+	    {
+	    		#ifdef CONFIG_IOL_IOREG_CFG 	
+	 		if(biol){	
+				if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+					bndy_cnt++;	
+				
+				if(v1 == 0xffe)
+				{ 					
+					rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);				
+				}
+				else if (v1 == 0xfd){
+					rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
+				}
+				else if (v1 == 0xfc){
+					rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
+				}
+				else if (v1 == 0xfb){
+					rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
+				}
+				else if (v1 == 0xfa){
+					rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5);
+				}
+				else if (v1 == 0xf9){
+					rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
+				}
+				else{
+					rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ;
+					#ifdef CONFIG_IOL_IOREG_CFG_DBG
+					cmpdata[cmpdata_idx].addr = v1;
+					cmpdata[cmpdata_idx].value= v2;
+					cmpdata_idx++;
+					#endif
+				}				
+ 
+	 		}
+			else
+			#endif	//#ifdef CONFIG_IOL_IOREG_CFG 
+			{
+		    		odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
+			}
+		    continue;
+	 	}
+		else
+		{ // This line is the start line of branch.
+		    if ( !CheckCondition(Array[i], hex) )
+		    { // Discard the following (offset, data) pairs.
+		        READ_NEXT_PAIR(v1, v2, i);
+		        while (v2 != 0xDEAD && 
+		               v2 != 0xCDEF && 
+		               v2 != 0xCDCD && i < ArrayLen -2)
+		        {
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+		        i -= 2; // prevent from for-loop += 2
+		    }
+		    else // Configure matched pairs and skip to end of if-else.
+		    {
+		        READ_NEXT_PAIR(v1, v2, i);
+		        while (v2 != 0xDEAD && 
+		               v2 != 0xCDEF && 
+		               v2 != 0xCDCD && i < ArrayLen -2)
+		        {
+		    		#ifdef CONFIG_IOL_IOREG_CFG 	
+		 		if(biol){	
+					if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+						bndy_cnt++;	
+					
+					if(v1 == 0xffe)
+					{ 							
+						rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);					
+					}
+					else if (v1 == 0xfd){
+						rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
+					}
+					else if (v1 == 0xfc){
+						rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
+					}
+					else if (v1 == 0xfb){
+						rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
+					}
+					else if (v1 == 0xfa){
+						rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5);
+					}
+					else if (v1 == 0xf9){
+						rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
+					}
+					else{
+						rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ;
+						#ifdef CONFIG_IOL_IOREG_CFG_DBG
+						cmpdata[cmpdata_idx].addr = v1;
+						cmpdata[cmpdata_idx].value= v2;
+						cmpdata_idx++;
+						#endif
+
+					}				
+	 
+		 		}
+				else
+				#endif	//#ifdef CONFIG_IOL_IOREG_CFG 
+				{
+		    			odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
+				}
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+
+		        while (v2 != 0xDEAD && i < ArrayLen -2)
+		        {
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+		        
+		    }
+		}	
+	}
+#ifdef CONFIG_IOL_IOREG_CFG 		
+	if(biol){
+		//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
+		if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
+		{			
+			#ifdef CONFIG_IOL_IOREG_CFG_DBG
+			printk("~~~ %s Success !!! \n",__FUNCTION__);
+			{
+				u4Byte idx;
+				u4Byte cdata;
+				printk("  %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx);
+				printk("### %s data compared !!###\n",__FUNCTION__);
+				for(idx=0;idx< cmpdata_idx;idx++)
+				{
+					cdata = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A,cmpdata[idx].addr,bRFRegOffsetMask);
+					if(cdata != cmpdata[idx].value){
+						printk("addr:0x%04x, data:(0x%02x : 0x%02x) \n",
+							cmpdata[idx].addr,cmpdata[idx].value,cdata);
+						rst = HAL_STATUS_FAILURE;
+					}					
+				}	
+				printk("### %s data compared !!###\n",__FUNCTION__);
+				//if(rst == HAL_STATUS_FAILURE)
+				{//dump data from TX packet buffer				
+					rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+				}
+			}
+			#endif //CONFIG_IOL_IOREG_CFG_DBG
+		
+		}
+		else{
+			rst = HAL_STATUS_FAILURE;
+			printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__);
+			#ifdef CONFIG_IOL_IOREG_CFG_DBG
+			{
+				//dump data from TX packet buffer				
+				rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+			}
+			#endif //CONFIG_IOL_IOREG_CFG_DBG
+		}
+	}
+
+	 
+#endif	//#ifdef CONFIG_IOL_IOREG_CFG 
+	return rst;
+}
+/******************************************************************************
+*                           RadioA_1T_ICUT.TXT
+******************************************************************************/
+
+u4Byte Array_MP_8188E_RadioA_1T_ICUT[] = { 
+		0x000, 0x00030000,
+		0x008, 0x00084000,
+		0x018, 0x00000407,
+		0x019, 0x00000012,
+		0x01E, 0x00080009,
+		0x01F, 0x00000880,
+		0x02F, 0x0001A060,
+		0x03F, 0x00000000,
+		0x042, 0x000060C0,
+		0x057, 0x000D0000,
+		0x058, 0x000BE180,
+		0x067, 0x00001552,
+		0x083, 0x00000000,
+		0x0B0, 0x000FF8FC,
+		0x0B1, 0x00054400,
+		0x0B2, 0x000CCC19,
+		0x0B4, 0x00043003,
+		0x0B6, 0x0004953E,
+		0x0B7, 0x0001C718,
+		0x0B8, 0x000060FF,
+		0x0B9, 0x00080001,
+		0x0BA, 0x00040000,
+		0x0BB, 0x00000400,
+		0x0BF, 0x000C0000,
+		0x0C2, 0x00002400,
+		0x0C3, 0x00000009,
+		0x0C4, 0x00040C91,
+		0x0C5, 0x00099999,
+		0x0C6, 0x000000A3,
+		0x0C7, 0x00088820,
+		0x0C8, 0x00076C06,
+		0x0C9, 0x00000000,
+		0x0CA, 0x00080000,
+		0x0DF, 0x00000180,
+		0x0EF, 0x000001A0,
+		0x051, 0x0006B27D,
+	0xFF0F0400, 0xABCD,
+		0x052, 0x0007E4DD,
+	0xCDCDCDCD, 0xCDCD,
+		0x052, 0x0007E49D,
+	0xFF0F0400, 0xDEAD,
+		0x053, 0x00000073,
+		0x056, 0x00051FF3,
+		0x035, 0x00000086,
+		0x035, 0x00000186,
+		0x035, 0x00000286,
+		0x036, 0x00001C25,
+		0x036, 0x00009C25,
+		0x036, 0x00011C25,
+		0x036, 0x00019C25,
+		0x0B6, 0x00048538,
+		0x018, 0x00000C07,
+		0x05A, 0x0004BD00,
+		0x019, 0x000739D0,
+		0x034, 0x0000ADF3,
+		0x034, 0x00009DF0,
+		0x034, 0x00008DED,
+		0x034, 0x00007DEA,
+		0x034, 0x00006DE7,
+		0x034, 0x000054EE,
+		0x034, 0x000044EB,
+		0x034, 0x000034E8,
+		0x034, 0x0000246B,
+		0x034, 0x00001468,
+		0x034, 0x0000006D,
+		0x000, 0x00030159,
+		0x084, 0x00068200,
+		0x086, 0x000000CE,
+		0x087, 0x00048A00,
+		0x08E, 0x00065540,
+		0x08F, 0x00088000,
+		0x0EF, 0x000020A0,
+		0x03B, 0x000F02B0,
+		0x03B, 0x000EF7B0,
+		0x03B, 0x000D4FB0,
+		0x03B, 0x000CF060,
+		0x03B, 0x000B0090,
+		0x03B, 0x000A0080,
+		0x03B, 0x00090080,
+		0x03B, 0x0008F780,
+		0x03B, 0x000722B0,
+		0x03B, 0x0006F7B0,
+		0x03B, 0x00054FB0,
+		0x03B, 0x0004F060,
+		0x03B, 0x00030090,
+		0x03B, 0x00020080,
+		0x03B, 0x00010080,
+		0x03B, 0x0000F780,
+		0x0EF, 0x000000A0,
+		0x000, 0x00010159,
+		0x018, 0x0000F407,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0x01F, 0x00080003,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0x01E, 0x00000001,
+		0x01F, 0x00080000,
+		0x000, 0x00033E60,
+
+};
+
+void
+ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
+ 	IN   PDM_ODM_T  pDM_Odm
+ 	)
+{
+	#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+	u4Byte     hex         = 0;
+	u4Byte     i           = 0;
+	u2Byte     count       = 0;
+	pu4Byte    ptr_array   = NULL;
+	u1Byte     platform    = pDM_Odm->SupportPlatform;
+	u1Byte     _interface   = pDM_Odm->SupportInterface;
+	u1Byte     board       = pDM_Odm->BoardType;  
+	u4Byte     ArrayLen    = sizeof(Array_MP_8188E_RadioA_1T_ICUT)/sizeof(u4Byte);
+	pu4Byte    Array       = Array_MP_8188E_RadioA_1T_ICUT;
+
+
+	hex += board;
+	hex += _interface << 8;
+	hex += platform << 16;
+	hex += 0xFF000000;
+	ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_RadioA_1T_ICUT, hex = 0x%X\n", hex));
+
+	for (i = 0; i < ArrayLen; i += 2 )
+	{
+	    u4Byte v1 = Array[i];
+	    u4Byte v2 = Array[i+1];
+	
+	    // This (offset, data) pair meets the condition.
+	    if ( v1 < 0xCDCDCDCD )
+	    {
+		    odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
+		    continue;
+	 	}
+		else
+		{ // This line is the start line of branch.
+		    if ( !CheckCondition(Array[i], hex) )
+		    { // Discard the following (offset, data) pairs.
+		        READ_NEXT_PAIR(v1, v2, i);
+		        while (v2 != 0xDEAD && 
+		               v2 != 0xCDEF && 
+		               v2 != 0xCDCD && i < ArrayLen -2)
+		        {
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+		        i -= 2; // prevent from for-loop += 2
+		    }
+		    else // Configure matched pairs and skip to end of if-else.
+		    {
+		        READ_NEXT_PAIR(v1, v2, i);
+		        while (v2 != 0xDEAD && 
+		               v2 != 0xCDEF && 
+		               v2 != 0xCDCD && i < ArrayLen -2)
+		        {
+		    		odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+
+		        while (v2 != 0xDEAD && i < ArrayLen -2)
+		        {
+		            READ_NEXT_PAIR(v1, v2, i);
+		        }
+		        
+		    }
+		}	
+	}
+
+}
+
+
+#endif // end of HWIMG_SUPPORT
+

hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h

@@ -0,0 +1,45 @@
+/****************************************************************************** 
+* 
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 
+* 
+* This program is free software; you can redistribute it and/or modify it 
+* under the terms of version 2 of the GNU General Public License as 
+* published by the Free Software Foundation. 
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT 
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 
+* more details. 
+* 
+* You should have received a copy of the GNU General Public License along with 
+* this program; if not, write to the Free Software Foundation, Inc., 
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 
+* 
+* 
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_RF_8188E_HW_IMG_H
+#define __INC_RF_8188E_HW_IMG_H
+
+//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
+
+/******************************************************************************
+*                           RadioA_1T.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_RadioA_1T_8188E(
+	IN   PDM_ODM_T  pDM_Odm
+);
+/******************************************************************************
+*                           RadioA_1T_ICUT.TXT
+******************************************************************************/
+
+void
+ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
+	IN   PDM_ODM_T  pDM_Odm
+);
+#endif
+#endif // end of HWIMG_SUPPORT
+

hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h

@@ -0,0 +1,141 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_8188E_H__
+#define __HAL_PHY_RF_8188E_H__
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define	IQK_DELAY_TIME_88E		10		//ms
+#define	index_mapping_NUM_88E	15
+#define AVG_THERMAL_NUM_88E	4
+
+typedef enum _PWRTRACK_CONTROL_METHOD {
+	BBSWING,
+	TXAGC
+} PWRTRACK_METHOD;
+
+
+VOID
+ODM_TxPwrTrackAdjust88E(
+	PDM_ODM_T	pDM_Odm,
+	u1Byte		Type,				// 0 = OFDM, 1 = CCK
+	pu1Byte		pDirection,			// 1 = +(increase) 2 = -(decrease)
+	pu4Byte		pOutWriteVal		// Tx tracking CCK/OFDM BB swing index adjust
+	);
+
+
+VOID
+odm_TXPowerTrackingCallback_ThermalMeter_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm
+#else
+	IN PADAPTER	Adapter
+#endif
+	);
+
+
+//1 7.	IQK
+
+void	
+PHY_IQCalibrate_8188E(	
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN PADAPTER	Adapter,
+#endif
+							IN	BOOLEAN 	bReCovery);
+
+
+//
+// LC calibrate
+//
+void	
+PHY_LCCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm
+#else
+	IN	PADAPTER	pAdapter
+#endif
+);
+
+//
+// AP calibrate
+//
+void	
+PHY_APCalibrate_8188E(		
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+							IN 	s1Byte		delta);
+void	
+PHY_DigitalPredistortion_8188E(		IN	PADAPTER	pAdapter);
+
+
+VOID
+_PHY_SaveADDARegisters(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+	IN	pu4Byte		ADDAReg,
+	IN	pu4Byte		ADDABackup,
+	IN	u4Byte		RegisterNum
+	);
+
+VOID
+_PHY_PathADDAOn(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+	IN	pu4Byte		ADDAReg,
+	IN	BOOLEAN		isPathAOn,
+	IN	BOOLEAN		is2T
+	);
+
+VOID
+_PHY_MACSettingCalibration(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+	IN	pu4Byte		MACReg,
+	IN	pu4Byte		MACBackup	
+	);
+
+
+VOID
+_PHY_PathAStandBy(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm
+#else
+	IN	PADAPTER	pAdapter
+#endif
+	);
+
+								
+#endif	// #ifndef __HAL_PHY_RF_8188E_H__
+

hal/OUTSRC/rtl8188e/odm_RTL8188E.h

@@ -0,0 +1,109 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef	__ODM_RTL8188E_H__
+#define __ODM_RTL8188E_H__
+
+#define	MAIN_ANT	0
+#define	AUX_ANT	1
+#define	MAIN_ANT_CG_TRX	1
+#define	AUX_ANT_CG_TRX	0
+#define	MAIN_ANT_CGCS_RX	0
+#define	AUX_ANT_CGCS_RX	1
+
+VOID
+ODM_DIG_LowerBound_88E(
+	IN		PDM_ODM_T		pDM_Odm
+);
+#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
+VOID
+odm_FastAntTrainingInit(
+	IN		PDM_ODM_T		pDM_Odm
+);
+#endif
+
+VOID
+ODM_AntennaDiversityInit_88E(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+VOID
+ODM_AntennaDiversity_88E
+(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+VOID
+ODM_SetTxAntByTxInfo_88E(
+	IN		PDM_ODM_T		pDM_Odm,
+	IN		pu1Byte			pDesc,
+	IN		u1Byte			macId	
+);
+#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
+VOID
+ODM_SetTxAntByTxInfo_88E(
+	IN		PDM_ODM_T		pDM_Odm	
+);
+#endif
+
+VOID
+ODM_UpdateRxIdleAnt_88E(
+	IN PDM_ODM_T pDM_Odm, 
+	IN u1Byte Ant
+);
+
+VOID
+ODM_AntselStatistics_88E(
+	IN		PDM_ODM_T		pDM_Odm,
+	IN		u1Byte			antsel_tr_mux,
+	IN		u4Byte			MacId,
+	IN		u1Byte			RxPWDBAll
+);
+
+#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
+VOID
+odm_FastAntTraining(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+VOID
+odm_FastAntTrainingCallback(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+VOID
+odm_FastAntTrainingWorkItemCallback(
+	IN		PDM_ODM_T		pDM_Odm
+);
+#endif
+VOID
+odm_PrimaryCCA_Init(
+	IN		PDM_ODM_T		pDM_Odm);
+
+BOOLEAN
+ODM_DynamicPrimaryCCA_DupRTS(
+	IN		PDM_ODM_T		pDM_Odm);
+
+VOID
+odm_DynamicPrimaryCCA(
+	IN		PDM_ODM_T		pDM_Odm);
+
+#endif
+

hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c

@@ -0,0 +1,209 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "../odm_precomp.h"
+
+#if (RTL8188E_SUPPORT == 1)  
+
+void
+odm_ConfigRFReg_8188E(
+	IN 	PDM_ODM_T 				pDM_Odm,
+	IN 	u4Byte 					Addr,
+	IN 	u4Byte 					Data,
+	IN  ODM_RF_RADIO_PATH_E     RF_PATH,
+	IN	u4Byte				    RegAddr
+	)
+{
+    if(Addr == 0xffe)
+	{ 					  
+		#ifdef CONFIG_LONG_DELAY_ISSUE
+		ODM_sleep_ms(50);
+		#else		
+		ODM_delay_ms(50);
+		#endif
+	}
+	else if (Addr == 0xfd)
+	{
+		ODM_delay_ms(5);
+	}
+	else if (Addr == 0xfc)
+	{
+		ODM_delay_ms(1);
+	}
+	else if (Addr == 0xfb)
+	{
+		ODM_delay_us(50);
+	}
+	else if (Addr == 0xfa)
+	{
+		ODM_delay_us(5);
+	}
+	else if (Addr == 0xf9)
+	{
+		ODM_delay_us(1);
+	}
+	else
+	{
+		ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
+		// Add 1us delay between BB/RF register setting.
+		ODM_delay_us(1);
+	}	
+}
+
+
+void 
+odm_ConfigRF_RadioA_8188E(
+	IN 	PDM_ODM_T 				pDM_Odm,
+	IN 	u4Byte 					Addr,
+	IN 	u4Byte 					Data
+	)
+{
+	u4Byte  content = 0x1000; // RF_Content: radioa_txt
+	u4Byte	maskforPhySet= (u4Byte)(content&0xE000);
+
+    odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
+
+    ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
+}
+
+void 
+odm_ConfigRF_RadioB_8188E(
+	IN 	PDM_ODM_T 				pDM_Odm,
+	IN 	u4Byte 					Addr,
+	IN 	u4Byte 					Data
+	)
+{
+	u4Byte  content = 0x1001; // RF_Content: radiob_txt
+	u4Byte	maskforPhySet= (u4Byte)(content&0xE000);
+
+    odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
+	
+	ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
+    
+}
+
+void 
+odm_ConfigMAC_8188E(
+ 	IN 	PDM_ODM_T 	pDM_Odm,
+ 	IN 	u4Byte 		Addr,
+ 	IN 	u1Byte 		Data
+ 	)
+{
+	ODM_Write1Byte(pDM_Odm, Addr, Data);
+	ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
+}
+
+void 
+odm_ConfigBB_AGC_8188E(
+    IN 	PDM_ODM_T 	pDM_Odm,
+    IN 	u4Byte 		Addr,
+    IN 	u4Byte 		Bitmask,
+    IN 	u4Byte 		Data
+    )
+{
+	ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);		
+	// Add 1us delay between BB/RF register setting.
+	ODM_delay_us(1);
+
+    ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
+}
+	
+void
+odm_ConfigBB_PHY_REG_PG_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm,
+    IN 	u4Byte 		Addr,
+    IN 	u4Byte 		Bitmask,
+    IN 	u4Byte 		Data
+    )
+{    
+	if (Addr == 0xfe){
+		#ifdef CONFIG_LONG_DELAY_ISSUE
+		ODM_sleep_ms(50);
+		#else		
+		ODM_delay_ms(50);
+		#endif
+	}
+	else if (Addr == 0xfd){
+		ODM_delay_ms(5);
+	}
+	else if (Addr == 0xfc){
+		ODM_delay_ms(1);
+	}
+	else if (Addr == 0xfb){
+		ODM_delay_us(50);
+	}
+	else if (Addr == 0xfa){
+		ODM_delay_us(5);
+	}
+	else if (Addr == 0xf9){
+		ODM_delay_us(1);
+	}
+	else{
+		ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
+
+	#if	!(DM_ODM_SUPPORT_TYPE&ODM_AP)
+		storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
+	#endif
+	}
+
+}
+
+void 
+odm_ConfigBB_PHY_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm,
+    IN 	u4Byte 		Addr,
+    IN 	u4Byte 		Bitmask,
+    IN 	u4Byte 		Data
+    )
+{    
+	if (Addr == 0xfe){
+		#ifdef CONFIG_LONG_DELAY_ISSUE
+		ODM_sleep_ms(50);
+		#else		
+		ODM_delay_ms(50);
+		#endif
+	}
+	else if (Addr == 0xfd){
+		ODM_delay_ms(5);
+	}
+	else if (Addr == 0xfc){
+		ODM_delay_ms(1);
+	}
+	else if (Addr == 0xfb){
+		ODM_delay_us(50);
+	}
+	else if (Addr == 0xfa){
+		ODM_delay_us(5);
+	}
+	else if (Addr == 0xf9){
+		ODM_delay_us(1);
+	}
+	else{
+		if (Addr == 0xa24)
+			pDM_Odm->RFCalibrateInfo.RegA24 = Data;			
+		ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);		
+	
+		// Add 1us delay between BB/RF register setting.
+		ODM_delay_us(1);
+    		ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
+	}
+}
+#endif
+

hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h

@@ -0,0 +1,80 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __INC_ODM_REGCONFIG_H_8188E
+#define __INC_ODM_REGCONFIG_H_8188E
+ 
+#if (RTL8188E_SUPPORT == 1)
+
+void
+odm_ConfigRFReg_8188E(
+	IN 	PDM_ODM_T 				pDM_Odm,
+	IN 	u4Byte 					Addr,
+	IN 	u4Byte 					Data,
+	IN  ODM_RF_RADIO_PATH_E     RF_PATH,
+	IN	u4Byte				    RegAddr
+	);
+
+void 
+odm_ConfigRF_RadioA_8188E(
+	IN 	PDM_ODM_T 				pDM_Odm,
+	IN 	u4Byte 					Addr,
+	IN 	u4Byte 					Data
+	);
+
+void 
+odm_ConfigRF_RadioB_8188E(
+	IN 	PDM_ODM_T 				pDM_Odm,
+	IN 	u4Byte 					Addr,
+	IN 	u4Byte 					Data
+	);
+
+void 
+odm_ConfigMAC_8188E(
+ 	IN 	PDM_ODM_T 	pDM_Odm,
+ 	IN 	u4Byte 		Addr,
+ 	IN 	u1Byte 		Data
+ 	);
+
+void 
+odm_ConfigBB_AGC_8188E(
+    IN 	PDM_ODM_T 	pDM_Odm,
+    IN 	u4Byte 		Addr,
+    IN 	u4Byte 		Bitmask,
+    IN 	u4Byte 		Data
+    );
+
+void
+odm_ConfigBB_PHY_REG_PG_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm,
+    IN 	u4Byte 		Addr,
+    IN 	u4Byte 		Bitmask,
+    IN 	u4Byte 		Data
+    );
+
+void 
+odm_ConfigBB_PHY_8188E(
+	IN 	PDM_ODM_T 	pDM_Odm,
+    IN 	u4Byte 		Addr,
+    IN 	u4Byte 		Bitmask,
+    IN 	u4Byte 		Data
+    );
+#endif
+#endif // end of SUPPORT
+

hal/hal_com.c

@@ -17,321 +17,334 @@
  *
  *
  ******************************************************************************/
+#include <drv_conf.h>
 #include <osdep_service.h>
 #include <drv_types.h>
+#include <rtw_byteorder.h>
 
 #include <hal_intf.h>
 #include <hal_com.h>
+
+#ifdef CONFIG_RTL8192C
+#include <rtl8192c_hal.h>
+#endif
+#ifdef CONFIG_RTL8192D
+#include <rtl8192d_hal.h>
+#endif
+#ifdef CONFIG_RTL8723A
+#include <rtl8723a_hal.h>
+#endif
+#ifdef CONFIG_RTL8188E
 #include <rtl8188e_hal.h>
+#endif
 
 #define _HAL_INIT_C_
 
-void dump_chip_info(struct HAL_VERSION	chip_vers)
+void dump_chip_info(HAL_VERSION	ChipVersion)
 {
-	uint cnt = 0;
+	int cnt = 0;
-	char buf[128];
+	u8 buf[128];
 
-	if (IS_81XXC(chip_vers)) {
+	if(IS_81XXC(ChipVersion)){
-		cnt += sprintf((buf+cnt), "Chip Version Info: %s_",
+		cnt += sprintf((buf+cnt), "Chip Version Info: %s_", IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
-			       IS_92C_SERIAL(chip_vers) ?
+	}
-			       "CHIP_8192C" : "CHIP_8188C");
+	else if(IS_92D(ChipVersion)){
-	} else if (IS_92D(chip_vers)) {
 		cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192D_");
-	} else if (IS_8723_SERIES(chip_vers)) {
+	}
+	else if(IS_8723_SERIES(ChipVersion)){
 		cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723A_");
-	} else if (IS_8188E(chip_vers)) {
+	}
+	else if(IS_8188E(ChipVersion)){
 		cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_");
 	}
 
-	cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(chip_vers) ?
+	cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
-		       "Normal_Chip" : "Test_Chip");
+	cnt += sprintf((buf+cnt), "%s_", IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC");
-	cnt += sprintf((buf+cnt), "%s_", IS_CHIP_VENDOR_TSMC(chip_vers) ?
+	if(IS_A_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "A_CUT_");
-		       "TSMC" : "UMC");
+	else if(IS_B_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "B_CUT_");
-	if (IS_A_CUT(chip_vers))
+	else if(IS_C_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "C_CUT_");
-		cnt += sprintf((buf+cnt), "A_CUT_");
+	else if(IS_D_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "D_CUT_");
-	else if (IS_B_CUT(chip_vers))
+	else if(IS_E_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "E_CUT_");
-		cnt += sprintf((buf+cnt), "B_CUT_");
+	else if(IS_I_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "I_CUT_");
-	else if (IS_C_CUT(chip_vers))
+	else if(IS_J_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "J_CUT_");
-		cnt += sprintf((buf+cnt), "C_CUT_");
+	else if(IS_K_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "K_CUT_");
-	else if (IS_D_CUT(chip_vers))
+	else cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
-		cnt += sprintf((buf+cnt), "D_CUT_");
-	else if (IS_E_CUT(chip_vers))
-		cnt += sprintf((buf+cnt), "E_CUT_");
-	else
-		cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_",
-			       chip_vers.CUTVersion);
 
-	if (IS_1T1R(chip_vers))
+	if(IS_1T1R(ChipVersion)) cnt += sprintf((buf+cnt), "1T1R_");
-		cnt += sprintf((buf+cnt), "1T1R_");
+	else if(IS_1T2R(ChipVersion)) cnt += sprintf((buf+cnt), "1T2R_");
-	else if (IS_1T2R(chip_vers))
+	else if(IS_2T2R(ChipVersion)) cnt += sprintf((buf+cnt), "2T2R_");
-		cnt += sprintf((buf+cnt), "1T2R_");
+	else cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
-	else if (IS_2T2R(chip_vers))
-		cnt += sprintf((buf+cnt), "2T2R_");
-	else
-		cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_",
-			       chip_vers.RFType);
 
-	cnt += sprintf((buf+cnt), "RomVer(%d)\n", chip_vers.ROMVer);
+	cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
 
-	pr_info("%s", buf);
+	DBG_871X("%s", buf);
 }
 
-#define	CHAN_PLAN_HW	0x80
 
-u8 /* return the final channel plan decision */
+#define	EEPROM_CHANNEL_PLAN_BY_HW_MASK	0x80
-hal_com_get_channel_plan(struct adapter *padapter, u8 hw_channel_plan,
+
-			 u8 sw_channel_plan, u8 def_channel_plan,
+u8	//return the final channel plan decision
-			 bool load_fail)
+hal_com_get_channel_plan(
+	IN	PADAPTER	padapter,
+	IN	u8			hw_channel_plan,	//channel plan from HW (efuse/eeprom)
+	IN	u8			sw_channel_plan,	//channel plan from SW (registry/module param)
+	IN	u8			def_channel_plan,	//channel plan used when the former two is invalid
+	IN	BOOLEAN		AutoLoadFail
+	)
 {
-	u8 sw_cfg;
+	u8 swConfig;
-	u8 chnlplan;
+	u8 chnlPlan;
 
-	sw_cfg = true;
+	swConfig = _TRUE;
-	if (!load_fail) {
+	if (!AutoLoadFail)
+	{
 		if (!rtw_is_channel_plan_valid(sw_channel_plan))
-			sw_cfg = false;
+			swConfig = _FALSE;
-		if (hw_channel_plan & CHAN_PLAN_HW)
+		if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
-			sw_cfg = false;
+			swConfig = _FALSE;
 	}
 
-	if (sw_cfg)
+	if (swConfig == _TRUE)
-		chnlplan = sw_channel_plan;
+		chnlPlan = sw_channel_plan;
 	else
-		chnlplan = hw_channel_plan & (~CHAN_PLAN_HW);
+		chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
 
-	if (!rtw_is_channel_plan_valid(chnlplan))
+	if (!rtw_is_channel_plan_valid(chnlPlan))
-		chnlplan = def_channel_plan;
+		chnlPlan = def_channel_plan;
 
-	return chnlplan;
+	return chnlPlan;
 }
 
-u8 MRateToHwRate(u8 rate)
+u8	MRateToHwRate(u8 rate)
 {
-	u8 ret = DESC_RATE1M;
+	u8	ret = DESC_RATE1M;
 		
-	switch (rate) {
+	switch(rate)
-		/*  CCK and OFDM non-HT rates */
+	{
-	case IEEE80211_CCK_RATE_1MB:
+		// CCK and OFDM non-HT rates
-		ret = DESC_RATE1M;
+	case IEEE80211_CCK_RATE_1MB:	ret = DESC_RATE1M;	break;
-		break;
+	case IEEE80211_CCK_RATE_2MB:	ret = DESC_RATE2M;	break;
-	case IEEE80211_CCK_RATE_2MB:
+	case IEEE80211_CCK_RATE_5MB:	ret = DESC_RATE5_5M;	break;
-		ret = DESC_RATE2M;
+	case IEEE80211_CCK_RATE_11MB:	ret = DESC_RATE11M;	break;
-		break;
+	case IEEE80211_OFDM_RATE_6MB:	ret = DESC_RATE6M;	break;
-	case IEEE80211_CCK_RATE_5MB:
+	case IEEE80211_OFDM_RATE_9MB:	ret = DESC_RATE9M;	break;
-		ret = DESC_RATE5_5M;
+	case IEEE80211_OFDM_RATE_12MB:	ret = DESC_RATE12M;	break;
-		break;
+	case IEEE80211_OFDM_RATE_18MB:	ret = DESC_RATE18M;	break;
-	case IEEE80211_CCK_RATE_11MB:
+	case IEEE80211_OFDM_RATE_24MB:	ret = DESC_RATE24M;	break;
-		ret = DESC_RATE11M;
+	case IEEE80211_OFDM_RATE_36MB:	ret = DESC_RATE36M;	break;
-		break;
+	case IEEE80211_OFDM_RATE_48MB:	ret = DESC_RATE48M;	break;
-	case IEEE80211_OFDM_RATE_6MB:
+	case IEEE80211_OFDM_RATE_54MB:	ret = DESC_RATE54M;	break;
-		ret = DESC_RATE6M;
+
-		break;
+		// HT rates since here
-	case IEEE80211_OFDM_RATE_9MB:
+	//case MGN_MCS0:		ret = DESC_RATEMCS0;	break;
-		ret = DESC_RATE9M;
+	//case MGN_MCS1:		ret = DESC_RATEMCS1;	break;
-		break;
+	//case MGN_MCS2:		ret = DESC_RATEMCS2;	break;
-	case IEEE80211_OFDM_RATE_12MB:
+	//case MGN_MCS3:		ret = DESC_RATEMCS3;	break;
-		ret = DESC_RATE12M;
+	//case MGN_MCS4:		ret = DESC_RATEMCS4;	break;
-		break;
+	//case MGN_MCS5:		ret = DESC_RATEMCS5;	break;
-	case IEEE80211_OFDM_RATE_18MB:
+	//case MGN_MCS6:		ret = DESC_RATEMCS6;	break;
-		ret = DESC_RATE18M;
+	//case MGN_MCS7:		ret = DESC_RATEMCS7;	break;
-		break;
+
-	case IEEE80211_OFDM_RATE_24MB:
+	default:		break;
-		ret = DESC_RATE24M;
-		break;
-	case IEEE80211_OFDM_RATE_36MB:
-		ret = DESC_RATE36M;
-		break;
-	case IEEE80211_OFDM_RATE_48MB:
-		ret = DESC_RATE48M;
-		break;
-	case IEEE80211_OFDM_RATE_54MB:
-		ret = DESC_RATE54M;
-		break;
-	default:
-		break;
 	}
+
 	return ret;
 }
 
-void HalSetBrateCfg(struct adapter *adapt, u8 *brates, u16 *rate_cfg)
+void	HalSetBrateCfg(
+	IN PADAPTER		Adapter,
+	IN u8			*mBratesOS,
+	OUT u16			*pBrateCfg)
 {
-	u8 i, is_brate, brate;
+	u8	i, is_brate, brate;
 
-	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+	for(i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
-		is_brate = brates[i] & IEEE80211_BASIC_RATE_MASK;
+	{
-		brate = brates[i] & 0x7f;
+		is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
+		brate = mBratesOS[i] & 0x7f;
 		
-		if (is_brate) {
+		if( is_brate )
-			switch (brate) {
+		{		
-			case IEEE80211_CCK_RATE_1MB:
+			switch(brate)
-				*rate_cfg |= RATE_1M;
+			{
-				break;
+				case IEEE80211_CCK_RATE_1MB:	*pBrateCfg |= RATE_1M;	break;
-			case IEEE80211_CCK_RATE_2MB:
+				case IEEE80211_CCK_RATE_2MB:	*pBrateCfg |= RATE_2M;	break;
-				*rate_cfg |= RATE_2M;
+				case IEEE80211_CCK_RATE_5MB:	*pBrateCfg |= RATE_5_5M;break;
-				break;
+				case IEEE80211_CCK_RATE_11MB:	*pBrateCfg |= RATE_11M;	break;
-			case IEEE80211_CCK_RATE_5MB:
+				case IEEE80211_OFDM_RATE_6MB:	*pBrateCfg |= RATE_6M;	break;
-				*rate_cfg |= RATE_5_5M;
+				case IEEE80211_OFDM_RATE_9MB:	*pBrateCfg |= RATE_9M;	break;
-				break;
+				case IEEE80211_OFDM_RATE_12MB:	*pBrateCfg |= RATE_12M;	break;
-			case IEEE80211_CCK_RATE_11MB:
+				case IEEE80211_OFDM_RATE_18MB:	*pBrateCfg |= RATE_18M;	break;
-				*rate_cfg |= RATE_11M;
+				case IEEE80211_OFDM_RATE_24MB:	*pBrateCfg |= RATE_24M;	break;
-				break;
+				case IEEE80211_OFDM_RATE_36MB:	*pBrateCfg |= RATE_36M;	break;
-			case IEEE80211_OFDM_RATE_6MB:
+				case IEEE80211_OFDM_RATE_48MB:	*pBrateCfg |= RATE_48M;	break;
-				*rate_cfg |= RATE_6M;
+				case IEEE80211_OFDM_RATE_54MB:	*pBrateCfg |= RATE_54M;	break;
-				break;
-			case IEEE80211_OFDM_RATE_9MB:
-				*rate_cfg |= RATE_9M;
-				break;
-			case IEEE80211_OFDM_RATE_12MB:
-				*rate_cfg |= RATE_12M;
-				break;
-			case IEEE80211_OFDM_RATE_18MB:
-				*rate_cfg |= RATE_18M;
-				break;
-			case IEEE80211_OFDM_RATE_24MB:
-				*rate_cfg |= RATE_24M;
-				break;
-			case IEEE80211_OFDM_RATE_36MB:
-				*rate_cfg |= RATE_36M;
-				break;
-			case IEEE80211_OFDM_RATE_48MB:
-				*rate_cfg |= RATE_48M;
-				break;
-			case IEEE80211_OFDM_RATE_54MB:
-				*rate_cfg |= RATE_54M;
-				break;
 			}
 		}
 	}
 }
 
-static void one_out_pipe(struct adapter *adapter)
+static VOID
+_OneOutPipeMapping(
+	IN	PADAPTER	pAdapter
+	)
 {
-	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
 
-	pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+	pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
-	pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
+	pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
-	pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
+	pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE
-	pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
+	pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
 	
-	pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+	pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
-	pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+	pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
-	pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+	pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
-	pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+	pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 }
 
-static void two_out_pipe(struct adapter *adapter, bool wifi_cfg)
+static VOID
+_TwoOutPipeMapping(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN	 	bWIFICfg
+	)
 {
-	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
 
-	if (wifi_cfg) { /* WMM */
+	if(bWIFICfg){ //WMM
-		/* BK, BE, VI, VO, BCN,	CMD, MGT, HIGH, HCCA */
-		/*  0,  1,  0,  1,   0,   0,   0,    0,    0}; */
-		/* 0:H, 1:L */
 		
-		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
+		//	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA 
-		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
+		//{  0, 	1, 	0, 	1, 	0, 	0, 	0, 	0, 		0	};
-		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
+		//0:H, 1:L 
-		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 		
-		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO
-		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
-		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
-		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
 		
-	} else {/* typical setting */
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
-		/* BK, BE, VI, VO, BCN,	CMD, MGT, HIGH, HCCA */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
-		/*  1,	1,  0,  0,   0,   0,   0,    0,    0}; */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
-		/* 0:H, 1:L */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 		
-		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
-		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
-		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
-
-		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 	}
+	else{//typical setting
+
+		
+		//BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA 
+		//{  1, 	1, 	0, 	0, 	0, 	0, 	0, 	0, 		0	};			
+		//0:H, 1:L 
+		
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
+		
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD	
+		
+	}
+	
 }
 
-static void three_out_pipe(struct adapter *adapter, bool wifi_cfg)
+static VOID _ThreeOutPipeMapping(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN	 	bWIFICfg
+	)
 {
-	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
 
-	if (wifi_cfg) {/* for WMM */
+	if(bWIFICfg){//for WMM
-		/* BK, BE, VI, VO, BCN,	CMD, MGT, HIGH, HCCA */
-		/*  1,	2,  1,  0,   0,   0,   0,    0,    0}; */
-		/* 0:H, 1:N, 2:L */
 		
-		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+		//	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA 
-		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
+		//{  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};
-		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
+		//0:H, 1:N, 2:L 
-		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 		
-		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
-		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
-		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
-		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
 		
-	} else {/* typical setting */
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
-		/* BK, BE, VI, VO, BCN,	CMD, MGT, HIGH, HCCA */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
-		/*  2,  2,  1,  0,   0,   0,   0,    0,    0}; */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
-		/* 0:H, 1:N, 2:L */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 		
-		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
-		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
-		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
-
-		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 	}
+	else{//typical setting
+
+		
+		//	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA 
+		//{  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			
+		//0:H, 1:N, 2:L 
+		
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK
+		
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD	
+	}
+
 }
 
-bool Hal_MappingOutPipe(struct adapter *adapter, u8 numoutpipe)
+BOOLEAN
+Hal_MappingOutPipe(
+	IN	PADAPTER	pAdapter,
+	IN	u8		NumOutPipe
+	)
 {
-	struct registry_priv *pregistrypriv = &adapter->registrypriv;
+	struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
-	bool  wifi_cfg = (pregistrypriv->wifi_spec) ? true : false;
-	bool result = true;
 
-	switch (numoutpipe) {
+	BOOLEAN	 bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE;
-	case 2:
+	
-		two_out_pipe(adapter, wifi_cfg);
+	BOOLEAN result = _TRUE;
-		break;
+
-	case 3:
+	switch(NumOutPipe)
-		three_out_pipe(adapter, wifi_cfg);
+	{
-		break;
+		case 2:
-	case 1:
+			_TwoOutPipeMapping(pAdapter, bWIFICfg);
-		one_out_pipe(adapter);
+			break;
-		break;
+		case 3:
-	default:
+			_ThreeOutPipeMapping(pAdapter, bWIFICfg);
-		result = false;
+			break;
-		break;
+		case 1:
+			_OneOutPipeMapping(pAdapter);
+			break;
+		default:
+			result = _FALSE;
+			break;
 	}
+
 	return result;
+	
 }
 
-void hal_init_macaddr(struct adapter *adapter)
+void hal_init_macaddr(_adapter *adapter)
 {
-	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR,
+	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
-			  adapter->eeprompriv.mac_addr);
+#ifdef  CONFIG_CONCURRENT_MODE
+	if (adapter->pbuddy_adapter)
+		rtw_hal_set_hwreg(adapter->pbuddy_adapter, HW_VAR_MAC_ADDR, adapter->pbuddy_adapter->eeprompriv.mac_addr);
+#endif
 }
 
 /* 
 * C2H event format:
-* Field	 TRIGGER		CONTENT	   CMD_SEQ	CMD_LEN		 CMD_ID
+* Field	 TRIGGER		CONTENT	   CMD_SEQ 	CMD_LEN		 CMD_ID
-* BITS	 [127:120]	[119:16]      [15:8]		  [7:4]		   [3:0]
+* BITS	 [127:120]	[119:16]      [15:8]		  [7:4]	 	   [3:0]
 */
 
-void c2h_evt_clear(struct adapter *adapter)
+void c2h_evt_clear(_adapter *adapter)
 {
 	rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
 }
 
-s32 c2h_evt_read(struct adapter *adapter, u8 *buf)
+s32 c2h_evt_read(_adapter *adapter, u8 *buf)
 {
 	s32 ret = _FAIL;
 	struct c2h_evt_hdr *c2h_evt;
@@ -343,10 +356,11 @@ s32 c2h_evt_read(struct adapter *adapter, u8 *buf)
 
 	trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
 
-	if (trigger == C2H_EVT_HOST_CLOSE)
+	if (trigger == C2H_EVT_HOST_CLOSE) {
 		goto exit; /* Not ready */
-	else if (trigger != C2H_EVT_FW_CLOSE)
+	} else if (trigger != C2H_EVT_FW_CLOSE) {
 		goto clear_evt; /* Not a valid value */
+	}
 
 	c2h_evt = (struct c2h_evt_hdr *)buf;
 
@@ -356,26 +370,84 @@ s32 c2h_evt_read(struct adapter *adapter, u8 *buf)
 	*(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);	
 
 	RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ",
-		      &c2h_evt , sizeof(c2h_evt));
+		&c2h_evt , sizeof(c2h_evt));
+
+	if (0) {
+		DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
+			, c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
+	}
 
 	/* Read the content */
 	for (i = 0; i < c2h_evt->plen; i++)
-		c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL +
+		c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + sizeof(*c2h_evt) + i);
-						sizeof(*c2h_evt) + i);
 
-	RT_PRINT_DATA(_module_hal_init_c_, _drv_info_,
+	RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
-		      "c2h_evt_read(): Command Content:\n",
+		c2h_evt->payload, c2h_evt->plen);
-		      c2h_evt->payload, c2h_evt->plen);
 
 	ret = _SUCCESS;
 
 clear_evt:
 	/* 
 	* Clear event to notify FW we have read the command.
-	* If this field isn't clear, the FW won't update the next
+	* If this field isn't clear, the FW won't update the next command message.
-	* command message.
 	*/
 	c2h_evt_clear(adapter);
 exit:
 	return ret;
 }
+
+u8
+SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+	u8 bResult = _SUCCESS;
+
+	switch(variable) {
+	case HW_DEF_FA_CNT_DUMP:
+		if(*((u8*)value))
+			pDM_Odm->DebugComponents |= (ODM_COMP_DIG |ODM_COMP_FA_CNT);
+		else
+			pDM_Odm->DebugComponents &= ~(ODM_COMP_DIG |ODM_COMP_FA_CNT);
+		break;
+	case HW_DEF_ODM_DBG_FLAG:
+		ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_COMP, *((u8Byte*)value));
+		break;
+	case HW_DEF_ODM_DBG_LEVEL:
+		ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_LEVEL, *((u4Byte*)value));
+		break;
+	default:
+		DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
+		bResult = _FAIL;
+		break;
+	}
+
+	return bResult;
+}
+
+u8
+GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+	u8 bResult = _SUCCESS;
+
+	switch(variable) {
+	case HW_DEF_ODM_DBG_FLAG:
+		*((u8Byte*)value) = pDM_Odm->DebugComponents;
+		break;
+	case HW_DEF_ODM_DBG_LEVEL:
+		*((u4Byte*)value) = pDM_Odm->DebugLevel;
+		break;
+	case HAL_DEF_DBG_DM_FUNC:
+		*((u32*)value) = pHalData->odmpriv.SupportAbility;
+		break;
+	default:
+		DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
+		bResult = _FAIL;
+		break;
+	}
+
+	return bResult;
+}
+

hal/hal_intf.c

@@ -19,450 +19,573 @@
  ******************************************************************************/
 
 #define _HAL_INTF_C_
+#include <drv_conf.h>
 #include <osdep_service.h>
 #include <drv_types.h>
+#include <rtw_byteorder.h>
+
 #include <hal_intf.h>
-#include <usb_hal.h>
 
-void rtw_hal_chip_configure(struct adapter *adapt)
+#ifdef CONFIG_SDIO_HCI
+	#include <sdio_hal.h>
+#elif defined(CONFIG_USB_HCI)
+	#include <usb_hal.h>
+#elif defined(CONFIG_GSPI_HCI)
+	#include <gspi_hal.h>
+#endif
+
+void rtw_hal_chip_configure(_adapter *padapter)
 {
-	if (adapt->HalFunc.intf_chip_configure)
+	if(padapter->HalFunc.intf_chip_configure)
-		adapt->HalFunc.intf_chip_configure(adapt);
+		padapter->HalFunc.intf_chip_configure(padapter);
 }
 
-void rtw_hal_read_chip_info(struct adapter *adapt)
+void rtw_hal_read_chip_info(_adapter *padapter)
 {
-	if (adapt->HalFunc.read_adapter_info)
+	if(padapter->HalFunc.read_adapter_info)
-		adapt->HalFunc.read_adapter_info(adapt);
+		padapter->HalFunc.read_adapter_info(padapter);
 }
 
-void rtw_hal_read_chip_version(struct adapter *adapt)
+void rtw_hal_read_chip_version(_adapter *padapter)
 {
-	if (adapt->HalFunc.read_chip_version)
+	if(padapter->HalFunc.read_chip_version)
-		adapt->HalFunc.read_chip_version(adapt);
+		padapter->HalFunc.read_chip_version(padapter);
 }
 
-void rtw_hal_def_value_init(struct adapter *adapt)
+void rtw_hal_def_value_init(_adapter *padapter)
 {
-	if (adapt->HalFunc.init_default_value)
+	if (is_primary_adapter(padapter))
-		adapt->HalFunc.init_default_value(adapt);
+		if(padapter->HalFunc.init_default_value)
+			padapter->HalFunc.init_default_value(padapter);
+}
+void	rtw_hal_free_data(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter))
+		if(padapter->HalFunc.free_hal_data)
+			padapter->HalFunc.free_hal_data(padapter);
+}
+void	rtw_hal_dm_init(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter))
+		if(padapter->HalFunc.dm_init)
+			padapter->HalFunc.dm_init(padapter);
+}
+void rtw_hal_dm_deinit(_adapter *padapter)
+{
+	// cancel dm  timer
+	if (is_primary_adapter(padapter))
+		if(padapter->HalFunc.dm_deinit)
+			padapter->HalFunc.dm_deinit(padapter);
+}
+void	rtw_hal_sw_led_init(_adapter *padapter)
+{
+	if(padapter->HalFunc.InitSwLeds)
+		padapter->HalFunc.InitSwLeds(padapter);
 }
 
-void rtw_hal_free_data(struct adapter *adapt)
+void rtw_hal_sw_led_deinit(_adapter *padapter)
 {
-	if (adapt->HalFunc.free_hal_data)
+	if(padapter->HalFunc.DeInitSwLeds)
-		adapt->HalFunc.free_hal_data(adapt);
+		padapter->HalFunc.DeInitSwLeds(padapter);
 }
 
-void rtw_hal_dm_init(struct adapter *adapt)
+u32 rtw_hal_power_on(_adapter *padapter)
 {
-	if (adapt->HalFunc.dm_init)
+	if(padapter->HalFunc.hal_power_on)
-		adapt->HalFunc.dm_init(adapt);
+		return padapter->HalFunc.hal_power_on(padapter);
-}
-
-void rtw_hal_dm_deinit(struct adapter *adapt)
-{
-	/*  cancel dm  timer */
-	if (adapt->HalFunc.dm_deinit)
-		adapt->HalFunc.dm_deinit(adapt);
-}
-
-void rtw_hal_sw_led_init(struct adapter *adapt)
-{
-	if (adapt->HalFunc.InitSwLeds)
-		adapt->HalFunc.InitSwLeds(adapt);
-}
-
-void rtw_hal_sw_led_deinit(struct adapter *adapt)
-{
-	if (adapt->HalFunc.DeInitSwLeds)
-		adapt->HalFunc.DeInitSwLeds(adapt);
-}
-
-u32 rtw_hal_power_on(struct adapter *adapt)
-{
-	if (adapt->HalFunc.hal_power_on)
-		return adapt->HalFunc.hal_power_on(adapt);
 	return _FAIL;
 }
+void rtw_hal_power_off(_adapter *padapter)
+{
+	if(padapter->HalFunc.hal_power_off)
+		padapter->HalFunc.hal_power_off(padapter);	
+}
 
-uint	 rtw_hal_init(struct adapter *adapt)
+
+uint	 rtw_hal_init(_adapter *padapter) 
 {
 	uint	status = _SUCCESS;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	int i;
 
-	adapt->hw_init_completed = false;
+#ifdef CONFIG_DUALMAC_CONCURRENT
-
+	if(padapter->hw_init_completed == _TRUE)
-	status = adapt->HalFunc.hal_init(adapt);
+	{
-
+		DBG_871X("rtw_hal_init: hw_init_completed == _TRUE\n");
-	if (status == _SUCCESS) {
+		return status;
-		adapt->hw_init_completed = true;
-
-		if (adapt->registrypriv.notch_filter == 1)
-			rtw_hal_notch_filter(adapt, 1);
-
-		rtw_hal_reset_security_engine(adapt);
-	} else {
-		adapt->hw_init_completed = false;
-		DBG_88E("rtw_hal_init: hal__init fail\n");
 	}
 
-	RT_TRACE(_module_hal_init_c_, _drv_err_,
+	// before init mac0, driver must init mac1 first to avoid usb rx error.
-		 ("-rtl871x_hal_init:status=0x%x\n", status));
+	if((padapter->pbuddy_adapter != NULL) && (padapter->DualMacConcurrent == _TRUE)
+		&& (padapter->adapter_type == PRIMARY_ADAPTER))
+	{
+		if(padapter->pbuddy_adapter->hw_init_completed == _TRUE)
+		{
+			DBG_871X("rtw_hal_init: pbuddy_adapter hw_init_completed == _TRUE\n");
+		}
+		else
+		{
+			status = 	padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
+			if(status == _SUCCESS){
+				padapter->pbuddy_adapter->hw_init_completed = _TRUE;
+			}
+			else{
+			 	padapter->pbuddy_adapter->hw_init_completed = _FALSE;
+				RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail(pbuddy_adapter)\n"));
+				DBG_871X("rtw_hal_init: hal__init fail(pbuddy_adapter)\n");
+				return status;
+			}
+		}
+	}
+#endif
+
+	status = padapter->HalFunc.hal_init(padapter);
+
+	if(status == _SUCCESS){
+		for (i = 0; i<dvobj->iface_nums; i++) {
+			padapter = dvobj->padapters[i];
+			padapter->hw_init_completed = _TRUE;
+		}
+			
+		if (padapter->registrypriv.notch_filter == 1)
+			rtw_hal_notch_filter(padapter, 1);
+
+		rtw_hal_reset_security_engine(padapter);
+		rtw_sec_restore_wep_key(padapter);
+
+		init_hw_mlme_ext(padapter);
+	}
+	else{
+		for (i = 0; i<dvobj->iface_nums; i++) {
+			padapter = dvobj->padapters[i];
+			padapter->hw_init_completed = _FALSE;
+		}
+		DBG_871X("rtw_hal_init: hal__init fail\n");
+	}
+
+	RT_TRACE(_module_hal_init_c_,_drv_err_,("-rtl871x_hal_init:status=0x%x\n",status));
 
 	return status;
+
 }	
 
-uint rtw_hal_deinit(struct adapter *adapt)
+uint rtw_hal_deinit(_adapter *padapter)
 {
 	uint	status = _SUCCESS;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	int i;
 
-	status = adapt->HalFunc.hal_deinit(adapt);
+_func_enter_;
+	if (!is_primary_adapter(padapter)){
+		DBG_871X(" rtw_hal_deinit: Secondary adapter return l\n");
+		return status;
+	}
 
-	if (status == _SUCCESS)
+	status = padapter->HalFunc.hal_deinit(padapter);
-		adapt->hw_init_completed = false;
+
+	if(status == _SUCCESS){
+		for (i = 0; i<dvobj->iface_nums; i++) {
+			padapter = dvobj->padapters[i];
+			padapter->hw_init_completed = _FALSE;
+		}
+	}
 	else
-		DBG_88E("\n rtw_hal_deinit: hal_init fail\n");
+	{
+		DBG_871X("\n rtw_hal_deinit: hal_init fail\n");
+	}
+	
+_func_exit_;
 	
 	return status;
 }
 
-void rtw_hal_set_hwreg(struct adapter *adapt, u8 variable, u8 *val)
+void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
 {
-	if (adapt->HalFunc.SetHwRegHandler)
+	if (padapter->HalFunc.SetHwRegHandler)
-		adapt->HalFunc.SetHwRegHandler(adapt, variable, val);
+		padapter->HalFunc.SetHwRegHandler(padapter, variable, val);
 }
 
-void rtw_hal_get_hwreg(struct adapter *adapt, u8 variable, u8 *val)
+void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
 {
-	if (adapt->HalFunc.GetHwRegHandler)
+	if (padapter->HalFunc.GetHwRegHandler)
-		adapt->HalFunc.GetHwRegHandler(adapt, variable, val);
+		padapter->HalFunc.GetHwRegHandler(padapter, variable, val);
 }
 
-u8 rtw_hal_set_def_var(struct adapter *adapt, enum hal_def_variable var,
+u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
-		      void *val)
 {	
-	if (adapt->HalFunc.SetHalDefVarHandler)
+	if(padapter->HalFunc.SetHalDefVarHandler)
-		return adapt->HalFunc.SetHalDefVarHandler(adapt, var, val);
+		return padapter->HalFunc.SetHalDefVarHandler(padapter,eVariable,pValue);
+	return _FAIL;
+}
+u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
+{	
+	if(padapter->HalFunc.GetHalDefVarHandler)
+		return padapter->HalFunc.GetHalDefVarHandler(padapter,eVariable,pValue);
 	return _FAIL;	
 }	
 
-u8 rtw_hal_get_def_var(struct adapter *adapt,
+void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet)
-		       enum hal_def_variable var, void *val)
 {
-	if (adapt->HalFunc.GetHalDefVarHandler)
+	if(padapter->HalFunc.SetHalODMVarHandler)
-		return adapt->HalFunc.GetHalDefVarHandler(adapt, var, val);
+		padapter->HalFunc.SetHalODMVarHandler(padapter,eVariable,pValue1,bSet);
-	return _FAIL;
+}
+void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet)
+{
+	if(padapter->HalFunc.GetHalODMVarHandler)
+		padapter->HalFunc.GetHalODMVarHandler(padapter,eVariable,pValue1,bSet);
 }
 
-void rtw_hal_set_odm_var(struct adapter *adapt,
+void rtw_hal_enable_interrupt(_adapter *padapter)
-			 enum hal_odm_variable var, void *val1,
-			 bool set)
 {
-	if (adapt->HalFunc.SetHalODMVarHandler)
+	if (!is_primary_adapter(padapter)){
-		adapt->HalFunc.SetHalODMVarHandler(adapt, var,
+		DBG_871X(" rtw_hal_enable_interrupt: Secondary adapter return l\n");
-						      val1, set);
+		return;
-}
+	}
 	
-void rtw_hal_get_odm_var(struct adapter *adapt,
+	if (padapter->HalFunc.enable_interrupt)
-			 enum hal_odm_variable var, void *val1,
+		padapter->HalFunc.enable_interrupt(padapter);
-			 bool set)
-{
-	if (adapt->HalFunc.GetHalODMVarHandler)
-		adapt->HalFunc.GetHalODMVarHandler(adapt, var,
-						      val1, set);
-}
-
-void rtw_hal_enable_interrupt(struct adapter *adapt)
-{
-	if (adapt->HalFunc.enable_interrupt)
-		adapt->HalFunc.enable_interrupt(adapt);
 	else 
-		DBG_88E("%s: HalFunc.enable_interrupt is NULL!\n", __func__);
+		DBG_871X("%s: HalFunc.enable_interrupt is NULL!\n", __FUNCTION__);
-}
 	
-void rtw_hal_disable_interrupt(struct adapter *adapt)
+}
+void rtw_hal_disable_interrupt(_adapter *padapter)
 {
-	if (adapt->HalFunc.disable_interrupt)
+	if (!is_primary_adapter(padapter)){
-		adapt->HalFunc.disable_interrupt(adapt);
+		DBG_871X(" rtw_hal_disable_interrupt: Secondary adapter return l\n");
+		return;
+	}
+	
+	if (padapter->HalFunc.disable_interrupt)
+		padapter->HalFunc.disable_interrupt(padapter);
 	else 
-		DBG_88E("%s: HalFunc.disable_interrupt is NULL!\n", __func__);
+		DBG_871X("%s: HalFunc.disable_interrupt is NULL!\n", __FUNCTION__);
+	
 }
 
-u32 rtw_hal_inirp_init(struct adapter *adapt)
+
+u32	rtw_hal_inirp_init(_adapter *padapter)
 {
 	u32 rst = _FAIL;
-
+	if(padapter->HalFunc.inirp_init)	
-	if (adapt->HalFunc.inirp_init)
+		rst = padapter->HalFunc.inirp_init(padapter);	
-		rst = adapt->HalFunc.inirp_init(adapt);
 	else		
-		DBG_88E(" %s HalFunc.inirp_init is NULL!!!\n", __func__);
+		DBG_871X(" %s HalFunc.inirp_init is NULL!!!\n",__FUNCTION__);		
 	return rst;
 }
 	
-u32 rtw_hal_inirp_deinit(struct adapter *adapt)
+u32	rtw_hal_inirp_deinit(_adapter *padapter)
 {
-	if (adapt->HalFunc.inirp_deinit)
-		return adapt->HalFunc.inirp_deinit(adapt);
 	
+	if(padapter->HalFunc.inirp_deinit)
+		return padapter->HalFunc.inirp_deinit(padapter);
+
+	return _FAIL;
+		
+}
+
+u8	rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val)
+{	
+	if(padapter->HalFunc.interface_ps_func)	
+		return padapter->HalFunc.interface_ps_func(padapter,efunc_id,val);
 	return _FAIL;
 }
 
-u8 rtw_hal_intf_ps_func(struct adapter *adapt,
+s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
-			enum hal_intf_ps_func efunc_id, u8 *val)
-{
-	if (adapt->HalFunc.interface_ps_func)
-		return adapt->HalFunc.interface_ps_func(adapt, efunc_id,
-							   val);
-	return _FAIL;
-}
-
-s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter,
-			      struct xmit_frame *pxmitframe)
 {
 	if(padapter->HalFunc.hal_xmitframe_enqueue)
 		return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
-	return false;
+
+	return _FALSE;	
 }
 
-s32 rtw_hal_xmit(struct adapter *adapt, struct xmit_frame *pxmitframe)
+s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
 {
-	if (adapt->HalFunc.hal_xmit)
+	if(padapter->HalFunc.hal_xmit)
-		return adapt->HalFunc.hal_xmit(adapt, pxmitframe);
+		return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
 
-	return false;
+	return _FALSE;	
 }
 
-s32 rtw_hal_mgnt_xmit(struct adapter *adapt, struct xmit_frame *pmgntframe)
+s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
 {
 	s32 ret = _FAIL;
-	if (adapt->HalFunc.mgnt_xmit)
+	unsigned char	*pframe;
-		ret = adapt->HalFunc.mgnt_xmit(adapt, pmgntframe);
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+	_rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN);
+
+#ifdef CONFIG_IEEE80211W
+	if(padapter->securitypriv.binstallBIPkey == _TRUE)
+	{
+		if(IS_MCAST(pmgntframe->attrib.ra))
+		{
+			pmgntframe->attrib.encrypt = _BIP_;
+			//pmgntframe->attrib.bswenc = _TRUE;
+		}	
+		else
+		{
+			pmgntframe->attrib.encrypt = _AES_;
+			pmgntframe->attrib.bswenc = _TRUE;
+		}
+		rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
+	}
+#endif //CONFIG_IEEE80211W
+	
+	if(padapter->HalFunc.mgnt_xmit)
+		ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
 	return ret;
 }
 
-s32 rtw_hal_init_xmit_priv(struct adapter *adapt)
+s32	rtw_hal_init_xmit_priv(_adapter *padapter)
 {	
-	if (adapt->HalFunc.init_xmit_priv != NULL)
+	if(padapter->HalFunc.init_xmit_priv != NULL)
-		return adapt->HalFunc.init_xmit_priv(adapt);
+		return padapter->HalFunc.init_xmit_priv(padapter);
 	return _FAIL;
 }
-
+void	rtw_hal_free_xmit_priv(_adapter *padapter)
-void rtw_hal_free_xmit_priv(struct adapter *adapt)
 {
-	if (adapt->HalFunc.free_xmit_priv != NULL)
+	if(padapter->HalFunc.free_xmit_priv != NULL)
-		adapt->HalFunc.free_xmit_priv(adapt);
+		padapter->HalFunc.free_xmit_priv(padapter);
 }
 
-s32 rtw_hal_init_recv_priv(struct adapter *adapt)
+s32	rtw_hal_init_recv_priv(_adapter *padapter)
 {	
-	if (adapt->HalFunc.init_recv_priv)
+	if(padapter->HalFunc.init_recv_priv)
-		return adapt->HalFunc.init_recv_priv(adapt);
+		return padapter->HalFunc.init_recv_priv(padapter);
 
 	return _FAIL;
 }
-
+void	rtw_hal_free_recv_priv(_adapter *padapter)
-void rtw_hal_free_recv_priv(struct adapter *adapt)
 {
	
-	if (adapt->HalFunc.free_recv_priv)
+	if(padapter->HalFunc.free_recv_priv)
-		adapt->HalFunc.free_recv_priv(adapt);
+		padapter->HalFunc.free_recv_priv(padapter);
 }
 
-void rtw_hal_update_ra_mask(struct adapter *adapt, u32 mac_id, u8 rssi_level)
+void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level)
 {
-	struct mlme_priv *pmlmepriv = &(adapt->mlmepriv);
+	_adapter *padapter;
+	struct mlme_priv *pmlmepriv;
 
-	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == true) {
+	if(!psta)
-#ifdef CONFIG_88EU_AP_MODE
+		return;
-		struct sta_info *psta = NULL;
+
-		struct sta_priv *pstapriv = &adapt->stapriv;
+	padapter = psta->padapter;
-		if ((mac_id-1) > 0)
+
-			psta = pstapriv->sta_aid[(mac_id-1) - 1];
+	pmlmepriv = &(padapter->mlmepriv);
-		if (psta)
+
-			add_RATid(adapt, psta, 0);/* todo: based on rssi_level*/
+	if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
-#endif
+	{
-	} else {
+		add_RATid(padapter, psta, rssi_level);
-		if (adapt->HalFunc.UpdateRAMaskHandler)
+	}
-			adapt->HalFunc.UpdateRAMaskHandler(adapt, mac_id,
+	else
-							      rssi_level);
+	{	
+		if(padapter->HalFunc.UpdateRAMaskHandler)
+			padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level);
 	}	
 }
 
-void rtw_hal_add_ra_tid(struct adapter *adapt, u32 bitmap, u8 arg,
+void	rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level)
-			u8 rssi_level)
 {
-	if (adapt->HalFunc.Add_RateATid)
+	if(padapter->HalFunc.Add_RateATid)
-		adapt->HalFunc.Add_RateATid(adapt, bitmap, arg,
+		padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level);
-					       rssi_level);
 }
 
 /*	Start specifical interface thread		*/
-void rtw_hal_start_thread(struct adapter *adapt)
+void	rtw_hal_start_thread(_adapter *padapter)
 {
-	if (adapt->HalFunc.run_thread)
+	if(padapter->HalFunc.run_thread)
-		adapt->HalFunc.run_thread(adapt);
+		padapter->HalFunc.run_thread(padapter);
 }
-
 /*	Start specifical interface thread		*/
-void rtw_hal_stop_thread(struct adapter *adapt)
+void	rtw_hal_stop_thread(_adapter *padapter)
 {
-	if (adapt->HalFunc.cancel_thread)
+	if(padapter->HalFunc.cancel_thread)
-		adapt->HalFunc.cancel_thread(adapt);
+		padapter->HalFunc.cancel_thread(padapter);
 }
 
-u32 rtw_hal_read_bbreg(struct adapter *adapt, u32 regaddr, u32 bitmask)
+u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
 {
 	u32 data = 0;
-
+	if(padapter->HalFunc.read_bbreg)
-	if (adapt->HalFunc.read_bbreg)
+		 data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
-		data = adapt->HalFunc.read_bbreg(adapt, regaddr, bitmask);
 	return data;
 }
-
+void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
-void rtw_hal_write_bbreg(struct adapter *adapt, u32 regaddr, u32 bitmask,
-			 u32 data)
 {
-	if (adapt->HalFunc.write_bbreg)
+	if(padapter->HalFunc.write_bbreg)
-		adapt->HalFunc.write_bbreg(adapt, regaddr, bitmask, data);
+		padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
 }
 
-u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rfpath,
+u32	rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
-		       u32 regaddr, u32 bitmask)
 {
 	u32 data = 0;
-
+	if( padapter->HalFunc.read_rfreg)
-	if (adapt->HalFunc.read_rfreg)
+		data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
-		data = adapt->HalFunc.read_rfreg(adapt, rfpath, regaddr,
-						    bitmask);
 	return data;
 }
-
+void	rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
-void rtw_hal_write_rfreg(struct adapter *adapt, enum rf_radio_path rfpath,
-			 u32 regaddr, u32 bitmask, u32 data)
 {
-	if (adapt->HalFunc.write_rfreg)
+	if(padapter->HalFunc.write_rfreg)
-		adapt->HalFunc.write_rfreg(adapt, rfpath, regaddr,
+		padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);	
-					      bitmask, data);
 }
 
-s32 rtw_hal_interrupt_handler(struct adapter *adapt)
+s32	rtw_hal_interrupt_handler(_adapter *padapter)
 {
-	if (adapt->HalFunc.interrupt_handler)
+	if(padapter->HalFunc.interrupt_handler)
-		return adapt->HalFunc.interrupt_handler(adapt);
+		return padapter->HalFunc.interrupt_handler(padapter);
 	return _FAIL;
 }
 
-void rtw_hal_set_bwmode(struct adapter *adapt,
+void	rtw_hal_set_bwmode(_adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset)
-			enum ht_channel_width bandwidth, u8 offset)
 {
-	if (adapt->HalFunc.set_bwmode_handler)
+	if(padapter->HalFunc.set_bwmode_handler)
-		adapt->HalFunc.set_bwmode_handler(adapt, bandwidth,
+		padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset);
-						     offset);
 }
 
-void rtw_hal_set_chan(struct adapter *adapt, u8 channel)
+void	rtw_hal_set_chan(_adapter *padapter, u8 channel)
 {
-	if (adapt->HalFunc.set_channel_handler)
+	if(padapter->HalFunc.set_channel_handler)
-		adapt->HalFunc.set_channel_handler(adapt, channel);
+		padapter->HalFunc.set_channel_handler(padapter, channel);
 }
 
-void rtw_hal_dm_watchdog(struct adapter *adapt)
+void	rtw_hal_dm_watchdog(_adapter *padapter)
 {
-	if (adapt->HalFunc.hal_dm_watchdog)
+#if defined(CONFIG_CONCURRENT_MODE)
-		adapt->HalFunc.hal_dm_watchdog(adapt);
+	if (padapter->adapter_type != PRIMARY_ADAPTER)
+		return;
+#endif	
+	if(padapter->HalFunc.hal_dm_watchdog)
+		padapter->HalFunc.hal_dm_watchdog(padapter);
 }
 
-void rtw_hal_bcn_related_reg_setting(struct adapter *adapt)
+void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
 {
-	if (adapt->HalFunc.SetBeaconRelatedRegistersHandler)
+	if(padapter->HalFunc.SetBeaconRelatedRegistersHandler)
-		adapt->HalFunc.SetBeaconRelatedRegistersHandler(adapt);
+		padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);	
 }
 
-u8 rtw_hal_antdiv_before_linked(struct adapter *adapt)
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+u8	rtw_hal_antdiv_before_linked(_adapter *padapter)
 {	
-	if (adapt->HalFunc.AntDivBeforeLinkHandler)
+	if(padapter->HalFunc.AntDivBeforeLinkHandler)
-		return adapt->HalFunc.AntDivBeforeLinkHandler(adapt);
+		return padapter->HalFunc.AntDivBeforeLinkHandler(padapter);
-	return false;
+	return _FALSE;		
+}
+void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
+{
+	if(padapter->HalFunc.AntDivCompareHandler)
+		padapter->HalFunc.AntDivCompareHandler(padapter, dst, src);
+}
+#endif
+
+#ifdef CONFIG_HOSTAPD_MLME
+s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
+{
+	if(padapter->HalFunc.hostap_mgnt_xmit_entry)
+		return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
+	return _FAIL;
+}
+#endif //CONFIG_HOSTAPD_MLME
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+void	rtw_hal_sreset_init(_adapter *padapter)
+{
+	if(padapter->HalFunc.sreset_init_value)
+		padapter->HalFunc.sreset_init_value(padapter); 
+}
+void rtw_hal_sreset_reset(_adapter *padapter)
+{
+	padapter = GET_PRIMARY_ADAPTER(padapter);
+
+	if(padapter->HalFunc.silentreset)
+		padapter->HalFunc.silentreset(padapter);
 }
 
-void rtw_hal_antdiv_rssi_compared(struct adapter *adapt,
+void rtw_hal_sreset_reset_value(_adapter *padapter)
-				  struct wlan_bssid_ex *dst,
-				  struct wlan_bssid_ex *src)
 {
-	if (adapt->HalFunc.AntDivCompareHandler)
+	if(padapter->HalFunc.sreset_reset_value)
-		adapt->HalFunc.AntDivCompareHandler(adapt, dst, src);
+		padapter->HalFunc.sreset_reset_value(padapter);
 }
 
-void rtw_hal_sreset_init(struct adapter *adapt)
+void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
 {
-	if (adapt->HalFunc.sreset_init_value)
+	if (!is_primary_adapter(padapter))
-		adapt->HalFunc.sreset_init_value(adapt);
+		return;
-}
 
-void rtw_hal_sreset_reset(struct adapter *adapt)
+	if(padapter->HalFunc.sreset_xmit_status_check)
+		padapter->HalFunc.sreset_xmit_status_check(padapter);		
+}
+void rtw_hal_sreset_linked_status_check(_adapter *padapter)
 {
-	if (adapt->HalFunc.silentreset)
+	if (!is_primary_adapter(padapter))
-		adapt->HalFunc.silentreset(adapt);
+		return;
-}
 
-void rtw_hal_sreset_reset_value(struct adapter *adapt)
+	if(padapter->HalFunc.sreset_linked_status_check)
-{
+		padapter->HalFunc.sreset_linked_status_check(padapter);	
-	if (adapt->HalFunc.sreset_reset_value)
-		adapt->HalFunc.sreset_reset_value(adapt);
 }
-
+u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter)
-void rtw_hal_sreset_xmit_status_check(struct adapter *adapt)
-{
-	if (adapt->HalFunc.sreset_xmit_status_check)
-		adapt->HalFunc.sreset_xmit_status_check(adapt);
-}
-
-void rtw_hal_sreset_linked_status_check(struct adapter *adapt)
-{
-	if (adapt->HalFunc.sreset_linked_status_check)
-		adapt->HalFunc.sreset_linked_status_check(adapt);
-}
-
-u8   rtw_hal_sreset_get_wifi_status(struct adapter *adapt)
 {
 	u8 status = 0;
-
+	if(padapter->HalFunc.sreset_get_wifi_status)				
-	if (adapt->HalFunc.sreset_get_wifi_status)
+		status = padapter->HalFunc.sreset_get_wifi_status(padapter);       
-		status = adapt->HalFunc.sreset_get_wifi_status(adapt);
 	return status;
 }
 
-int rtw_hal_iol_cmd(struct adapter  *adapter, struct xmit_frame *xmit_frame,
+bool rtw_hal_sreset_inprogress(_adapter *padapter)
-		    u32 max_wating_ms, u32 bndy_cnt)
 {
-	if (adapter->HalFunc.IOL_exec_cmds_sync)
+	bool inprogress = _FALSE;
-		return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame,
+
-							   max_wating_ms,
+	padapter = GET_PRIMARY_ADAPTER(padapter);
-							   bndy_cnt);
+
+	if(padapter->HalFunc.sreset_inprogress)
+		inprogress = padapter->HalFunc.sreset_inprogress(padapter);
+	return inprogress;
+}
+#endif	//DBG_CONFIG_ERROR_DETECT
+
+#ifdef CONFIG_IOL
+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+{
+	if(adapter->HalFunc.IOL_exec_cmds_sync)
+		return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,bndy_cnt);
 	return _FAIL;
 }
+#endif
 
-void rtw_hal_notch_filter(struct adapter *adapter, bool enable)
+#ifdef CONFIG_XMIT_THREAD_MODE
+s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
 {
-	if (adapter->HalFunc.hal_notch_filter)
+	if(padapter->HalFunc.xmit_thread_handler)
-		adapter->HalFunc.hal_notch_filter(adapter, enable);
+		return padapter->HalFunc.xmit_thread_handler(padapter);
+	return _FAIL;
+}
+#endif
+
+void rtw_hal_notch_filter(_adapter *adapter, bool enable)
+{
+	if(adapter->HalFunc.hal_notch_filter)
+		adapter->HalFunc.hal_notch_filter(adapter,enable);		
 }
 
-void rtw_hal_reset_security_engine(struct adapter *adapter)
+void rtw_hal_reset_security_engine(_adapter * adapter)
 {
-	if (adapter->HalFunc.hal_reset_security_engine)
+	if(adapter->HalFunc.hal_reset_security_engine)
 		adapter->HalFunc.hal_reset_security_engine(adapter);
 }
 
-s32 rtw_hal_c2h_handler(struct adapter *adapter, struct c2h_evt_hdr *c2h_evt)
+s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt)
 {
 	s32 ret = _FAIL;
-
 	if (adapter->HalFunc.c2h_handler)
 		ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt);
 	return ret;
 }
 
-c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter)
+c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter)
 {
 	return adapter->HalFunc.c2h_id_filter_ccx;
 }
+

hal/rtl8188e/Hal8188EPwrSeq.c

@@ -0,0 +1,97 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "Hal8188EPwrSeq.h"
+#include <rtl8188e_hal.h>
+
+/* 
+    drivers should parse below arrays and do the corresponding actions
+*/
+//3 Power on  Array
+WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_CARDEMU_TO_ACT
+	RTL8188E_TRANS_END
+};
+
+//3Radio off Array
+WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_ACT_TO_CARDEMU
+	RTL8188E_TRANS_END
+};
+
+//3Card Disable Array
+WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_ACT_TO_CARDEMU
+	RTL8188E_TRANS_CARDEMU_TO_CARDDIS
+	RTL8188E_TRANS_END
+};
+
+//3 Card Enable Array
+WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_CARDDIS_TO_CARDEMU
+	RTL8188E_TRANS_CARDEMU_TO_ACT
+	RTL8188E_TRANS_END
+};
+
+//3Suspend Array
+WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_ACT_TO_CARDEMU
+	RTL8188E_TRANS_CARDEMU_TO_SUS
+	RTL8188E_TRANS_END
+};
+
+//3 Resume Array
+WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_SUS_TO_CARDEMU
+	RTL8188E_TRANS_CARDEMU_TO_ACT
+	RTL8188E_TRANS_END
+};
+
+
+//3HWPDN Array
+WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	RTL8188E_TRANS_ACT_TO_CARDEMU
+	RTL8188E_TRANS_CARDEMU_TO_PDN	
+	RTL8188E_TRANS_END
+};
+
+//3 Enter LPS 
+WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	//FW behavior
+	RTL8188E_TRANS_ACT_TO_LPS	
+	RTL8188E_TRANS_END
+};
+
+//3 Leave LPS 
+WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
+{
+	//FW behavior
+	RTL8188E_TRANS_LPS_TO_ACT
+	RTL8188E_TRANS_END
+};
+

hal/rtl8188e/rtl8188e_dm.c

@@ -0,0 +1,650 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//============================================================
+// Description:
+//
+// This file is for 92CE/92CU dynamic mechanism only
+//
+//
+//============================================================
+#define _RTL8188E_DM_C_
+
+//============================================================
+// include files
+//============================================================
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_byteorder.h>
+
+#include <rtl8188e_hal.h>
+
+//============================================================
+// Global var
+//============================================================
+
+
+static VOID
+dm_CheckProtection(
+	IN	PADAPTER	Adapter
+	)
+{
+#if 0
+	PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo);
+	u1Byte			CurRate, RateThreshold;
+
+	if(pMgntInfo->pHTInfo->bCurBW40MHz)
+		RateThreshold = MGN_MCS1;
+	else
+		RateThreshold = MGN_MCS3;
+
+	if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
+	{
+		pMgntInfo->bDmDisableProtect = TRUE;
+		DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
+	}
+	else
+	{
+		pMgntInfo->bDmDisableProtect = FALSE;
+		DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
+	}
+#endif
+}
+
+static VOID
+dm_CheckStatistics(
+	IN	PADAPTER	Adapter
+	)
+{
+#if 0
+	if(!Adapter->MgntInfo.bMediaConnect)
+		return;
+
+	//2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.
+	rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );
+
+	// Calculate current Tx Rate(Successful transmited!!)
+
+	// Calculate current Rx Rate(Successful received!!)
+
+	//for tx tx retry count
+	rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );
+#endif
+}
+
+static void dm_CheckPbcGPIO(_adapter *padapter)
+{
+	u8	tmp1byte;
+	u8	bPbcPressed = _FALSE;
+
+	if(!padapter->registrypriv.hw_wps_pbc)
+		return;
+
+#ifdef CONFIG_USB_HCI
+	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
+	tmp1byte |= (HAL_8188E_HW_GPIO_WPS_BIT);
+	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	//enable GPIO[2] as output mode
+
+	tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT);
+	rtw_write8(padapter,  GPIO_IN, tmp1byte);		//reset the floating voltage level
+
+	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
+	tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT);
+	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	//enable GPIO[2] as input mode
+
+	tmp1byte =rtw_read8(padapter, GPIO_IN);
+
+	if (tmp1byte == 0xff)
+		return ;
+
+	if (tmp1byte&HAL_8188E_HW_GPIO_WPS_BIT)
+	{
+		bPbcPressed = _TRUE;
+	}
+#else
+	tmp1byte = rtw_read8(padapter, GPIO_IN);
+	//RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte));
+
+	if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
+		return ;
+
+	if((tmp1byte&HAL_8188E_HW_GPIO_WPS_BIT)==0)
+	{
+		bPbcPressed = _TRUE;
+	}
+#endif
+
+	if( _TRUE == bPbcPressed)
+	{
+		// Here we only set bPbcPressed to true
+		// After trigger PBC, the variable will be set to false
+		DBG_8192C("CheckPbcGPIO - PBC is pressed\n");
+
+#ifdef RTK_DMP_PLATFORM
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
+		kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);
+#else
+		kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);
+#endif
+#else
+
+		if ( padapter->pid[0] == 0 )
+		{	//	0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver.
+			return;
+		}
+
+#ifdef PLATFORM_LINUX
+		rtw_signal_process(padapter->pid[0], SIGUSR1);
+#endif
+#endif
+	}
+}
+
+#ifdef CONFIG_PCI_HCI
+//
+//	Description:
+//		Perform interrupt migration dynamically to reduce CPU utilization.
+//
+//	Assumption:
+//		1. Do not enable migration under WIFI test.
+//
+//	Created by Roger, 2010.03.05.
+//
+VOID
+dm_InterruptMigration(
+	IN	PADAPTER	Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN			bCurrentIntMt, bCurrentACIntDisable;
+	BOOLEAN			IntMtToSet = _FALSE;
+	BOOLEAN			ACIntToSet = _FALSE;
+
+
+	// Retrieve current interrupt migration and Tx four ACs IMR settings first.
+	bCurrentIntMt = pHalData->bInterruptMigration;
+	bCurrentACIntDisable = pHalData->bDisableTxInt;
+
+	//
+	// <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
+	// when interrupt migration is set before. 2010.03.05.
+	//
+	if(!Adapter->registrypriv.wifi_spec &&
+		(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) &&
+		pmlmepriv->LinkDetectInfo.bHigherBusyTraffic)
+	{
+		IntMtToSet = _TRUE;
+
+		// To check whether we should disable Tx interrupt or not.
+		if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic )
+			ACIntToSet = _TRUE;
+	}
+
+	//Update current settings.
+	if( bCurrentIntMt != IntMtToSet ){
+		DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet);
+		if(IntMtToSet)
+		{
+			//
+			// <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.
+			// timer 25ns*0xfa0=100us for 0xf packets.
+			// 2010.03.05.
+			//
+			rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx
+			pHalData->bInterruptMigration = IntMtToSet;
+		}
+		else
+		{
+			// Reset all interrupt migration settings.
+			rtw_write32(Adapter, REG_INT_MIG, 0);
+			pHalData->bInterruptMigration = IntMtToSet;
+		}
+	}
+
+	/*if( bCurrentACIntDisable != ACIntToSet ){
+		DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet);
+		if(ACIntToSet) // Disable four ACs interrupts.
+		{
+			//
+			// <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization.
+			// When extremely highly Rx OK occurs, we will disable Tx interrupts.
+			// 2010.03.05.
+			//
+			UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );
+			pHalData->bDisableTxInt = ACIntToSet;
+		}
+		else// Enable four ACs interrupts.
+		{
+			UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );
+			pHalData->bDisableTxInt = ACIntToSet;
+		}
+	}*/
+
+}
+
+#endif
+
+//
+// Initialize GPIO setting registers
+//
+static void
+dm_InitGPIOSetting(
+	IN	PADAPTER	Adapter
+	)
+{
+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(Adapter);
+
+	u8	tmp1byte;
+
+	tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
+	tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
+
+#ifdef CONFIG_BT_COEXIST
+	// UMB-B cut bug. We need to support the modification.
+	if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
+		pHalData->bt_coexist.BT_Coexist)
+	{
+		tmp1byte |= (BIT5);
+	}
+#endif
+	rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
+
+}
+
+//============================================================
+// functions
+//============================================================
+static void Init_ODM_ComInfo_88E(PADAPTER	Adapter)
+{
+
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);
+	u8	cut_ver,fab_ver;
+	
+	//
+	// Init Value
+	//
+	_rtw_memset(pDM_Odm,0,sizeof(pDM_Odm));
+	
+	pDM_Odm->Adapter = Adapter;	
+	
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE);
+
+	if(Adapter->interface_type == RTW_GSPI )
+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);
+	else
+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE
+	
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8188E);
+
+	fab_ver = ODM_TSMC;
+	cut_ver = ODM_CUT_A;	
+
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver);		
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver);
+
+	ODM_CmnInfoInit(pDM_Odm,	ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
+	
+#if 0	
+//#ifdef CONFIG_USB_HCI	
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType);
+
+	if(pHalData->BoardType == BOARD_USB_High_PA){
+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE);
+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE);
+	}
+#endif	
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);
+	//	ODM_CMNINFO_BINHCT_TEST only for MP Team
+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
+		
+	
+	if(pHalData->rf_type == RF_1T1R){
+		ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R);		
+	}
+	else if(pHalData->rf_type == RF_2T2R){
+		ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R);		
+	}
+	else if(pHalData->rf_type == RF_1T2R){		
+		ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);		
+	}	
+
+ 	ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
+	
+	#ifdef CONFIG_DISABLE_ODM
+	pdmpriv->InitODMFlag = 0;
+	#else
+	pdmpriv->InitODMFlag =	ODM_RF_CALIBRATION		|
+							ODM_RF_TX_PWR_TRACK	//|
+							;	
+	//if(pHalData->AntDivCfg)
+	//	pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
+	#endif	
+
+	ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
+	
+}
+static void Update_ODM_ComInfo_88E(PADAPTER	Adapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;	
+	int i;	
+
+	pdmpriv->InitODMFlag = 0
+		| ODM_BB_DIG
+#ifdef CONFIG_ODM_REFRESH_RAMASK
+		| ODM_BB_RA_MASK
+#endif
+		| ODM_BB_DYNAMIC_TXPWR
+		| ODM_BB_FA_CNT
+		| ODM_BB_RSSI_MONITOR
+		| ODM_BB_CCK_PD
+		| ODM_BB_PWR_SAVE
+		| ODM_RF_CALIBRATION
+		| ODM_RF_TX_PWR_TRACK
+#ifdef CONFIG_ODM_ADAPTIVITY
+		| ODM_BB_ADAPTIVITY
+#endif
+		;
+
+	if (!Adapter->registrypriv.qos_opt_enable) {
+		pdmpriv->InitODMFlag |= ODM_MAC_EDCA_TURBO;
+	}
+
+	if(pHalData->AntDivCfg)
+		pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
+
+#if (MP_DRIVER==1)
+	if (Adapter->registrypriv.mp_mode == 1) {
+		pdmpriv->InitODMFlag = 0
+			| ODM_RF_CALIBRATION
+			| ODM_RF_TX_PWR_TRACK
+			;
+	}
+#endif//(MP_DRIVER==1)
+
+#ifdef CONFIG_DISABLE_ODM
+	pdmpriv->InitODMFlag = 0;
+#endif//CONFIG_DISABLE_ODM
+
+	ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
+	
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_RX_UNI,&(Adapter->recvpriv.rx_bytes));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_WM_MODE,&(pmlmeext->cur_wireless_mode));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_CHNL_OFFSET,&(pHalData->nCur40MhzPrimeSC));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_MODE,&(Adapter->securitypriv.dot11PrivacyAlgrthm));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BW,&(pHalData->CurrentChannelBW ));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel));	
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));
+
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
+	//================= only for 8192D   =================
+	/*
+	//pHalData->CurrentBandType92D
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));
+	//================= only for 8192D   =================
+	// driver havn't those variable now
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));
+	*/
+	
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));
+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));
+	ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
+
+	for(i=0; i< NUM_STA; i++)
+	{
+		//pDM_Odm->pODM_StaInfo[i] = NULL;
+		ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);
+	}	
+}
+
+void
+rtl8188e_InitHalDm(
+	IN	PADAPTER	Adapter
+	)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);
+	u8	i;
+
+#ifdef CONFIG_USB_HCI
+	dm_InitGPIOSetting(Adapter);
+#endif
+
+	pdmpriv->DM_Type = DM_Type_ByDriver;
+	pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
+	
+	Update_ODM_ComInfo_88E(Adapter);
+	ODM_DMInit(pDM_Odm);
+
+	Adapter->fix_rate = 0xFF;
+
+}
+
+
+VOID
+rtl8188e_HalDmWatchDog(
+	IN	PADAPTER	Adapter
+	)
+{
+	BOOLEAN		bFwCurrentInPSMode = _FALSE;
+	BOOLEAN		bFwPSAwake = _TRUE;
+	u8 hw_init_completed = _FALSE;
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);
+#ifdef CONFIG_CONCURRENT_MODE
+	PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
+#endif //CONFIG_CONCURRENT_MODE
+
+	_func_enter_;
+
+	hw_init_completed = Adapter->hw_init_completed;
+
+	if (hw_init_completed == _FALSE)
+		goto skip_dm;
+
+#ifdef CONFIG_LPS
+	bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode;
+	rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));
+#endif
+
+#ifdef CONFIG_P2P_PS
+	// Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
+	// modifed by thomas. 2011.06.11.
+	if(Adapter->wdinfo.p2p_ps_mode)
+		bFwPSAwake = _FALSE;
+#endif //CONFIG_P2P_PS
+
+	if( (hw_init_completed == _TRUE)
+		&& ((!bFwCurrentInPSMode) && bFwPSAwake))
+	{
+		//
+		// Calculate Tx/Rx statistics.
+		//
+		dm_CheckStatistics(Adapter);
+	
+		//
+		// Dynamically switch RTS/CTS protection.
+		//
+		//dm_CheckProtection(Adapter);
+
+#ifdef CONFIG_PCI_HCI
+		// 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput.
+		// Tx Migration settings.
+		//dm_InterruptMigration(Adapter);
+
+		//if(Adapter->HalFunc.TxCheckStuckHandler(Adapter))
+		//	PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem));
+#endif
+	
+	}
+
+
+	//ODM
+	if (hw_init_completed == _TRUE)
+	{
+		u8	bLinked=_FALSE;
+		u8   bsta_state = _FALSE;
+
+		#ifdef CONFIG_DISABLE_ODM
+		pHalData->odmpriv.SupportAbility = 0;
+		#endif
+			
+		if(rtw_linked_check(Adapter))
+			bLinked = _TRUE;
+		
+#ifdef CONFIG_CONCURRENT_MODE
+		if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter))
+			bLinked = _TRUE;
+#endif //CONFIG_CONCURRENT_MODE
+		ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked);
+
+
+		if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE))
+			bsta_state = _TRUE;
+#ifdef CONFIG_CONCURRENT_MODE
+		if(pbuddy_adapter && check_fwstate(&pbuddy_adapter->mlmepriv, WIFI_STATION_STATE))
+			bsta_state = _TRUE;
+#endif //CONFIG_CONCURRENT_MODE	
+		ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_STATION_STATE, bsta_state);
+		
+		ODM_DMWatchdog(&pHalData->odmpriv);
+			
+	}
+
+skip_dm:
+
+	// Check GPIO to determine current RF on/off and Pbc status.
+	// Check Hardware Radio ON/OFF or not
+#ifdef CONFIG_PCI_HCI
+	if(pHalData->bGpioHwWpsPbc)
+#endif
+	{
+		//temp removed
+		//dm_CheckPbcGPIO(Adapter);				
+	}
+	return;
+}
+
+void rtl8188e_init_dm_priv(IN PADAPTER Adapter)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	PDM_ODM_T 		podmpriv = &pHalData->odmpriv;
+	_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
+	//_rtw_spinlock_init(&(pHalData->odm_stainfo_lock));
+	Init_ODM_ComInfo_88E(Adapter);
+#ifdef CONFIG_SW_ANTENNA_DIVERSITY
+	//_init_timer(&(pdmpriv->SwAntennaSwitchTimer),  Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter);	
+	ODM_InitAllTimers(podmpriv );	
+#endif
+	ODM_InitDebugSetting(podmpriv);	
+}
+
+void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	PDM_ODM_T 		podmpriv = &pHalData->odmpriv;
+	//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);
+#ifdef CONFIG_SW_ANTENNA_DIVERSITY
+	//_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);	
+	ODM_CancelAllTimers(podmpriv);	
+#endif
+}
+
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+// Add new function to reset the state of antenna diversity before link.
+//
+// Compare RSSI for deciding antenna
+void	AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
+{
+	//PADAPTER Adapter = pDM_Odm->Adapter ;
+	
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	if(0 != pHalData->AntDivCfg )
+	{
+		//DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
+		//	src->Rssi,query_rx_pwr_percentage(src->Rssi));
+		//select optimum_antenna for before linked =>For antenna diversity
+		if(dst->Rssi >=  src->Rssi )//keep org parameter
+		{
+			src->Rssi = dst->Rssi;
+			src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;						
+		}
+	}
+}
+
+// Add new function to reset the state of antenna diversity before link.
+u8 AntDivBeforeLink8188E(PADAPTER Adapter )
+{
+	
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);	
+	PDM_ODM_T 	pDM_Odm =&pHalData->odmpriv;
+	SWAT_T		*pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	
+	// Condition that does not need to use antenna diversity.
+	if(pHalData->AntDivCfg==0)
+	{
+		//DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
+		return _FALSE;
+	}
+
+	if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)	
+	{		
+		return _FALSE;
+	}
+
+
+	if(pDM_SWAT_Table->SWAS_NoLink_State == 0){
+		//switch channel
+		pDM_SWAT_Table->SWAS_NoLink_State = 1;
+		pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
+
+		//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
+		rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE);
+		//DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B");
+		return _TRUE;
+	}
+	else
+	{
+		pDM_SWAT_Table->SWAS_NoLink_State = 0;
+		return _FALSE;
+	}	
+
+}
+#endif
+

hal/rtl8188e/rtl8188e_rxdesc.c

@@ -0,0 +1,350 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188E_REDESC_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtl8188e_hal.h>
+
+static s32  translate2dbm(u8 signal_strength_idx)
+{
+	s32	signal_power; // in dBm.
+
+
+	// Translate to dBm (x=0.5y-95).
+	signal_power = (s32)((signal_strength_idx + 1) >> 1);
+	signal_power -= 95;
+
+	return signal_power;
+}
+
+
+static void process_rssi(_adapter *padapter,union recv_frame *prframe)
+{
+	u32	last_rssi, tmp_val;
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+	//DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength);
+	//if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
+	{
+	
+	#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+		if(signal_stat->update_req) {
+			signal_stat->total_num = 0;
+			signal_stat->total_val = 0;
+			signal_stat->update_req = 0;
+		}
+
+		signal_stat->total_num++;
+		signal_stat->total_val  += pattrib->phy_info.SignalStrength;
+		signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;		
+	#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	
+		//Adapter->RxStats.RssiCalculateCnt++;	//For antenna Test
+		if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX)
+		{
+			padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
+			last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
+			padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
+		}
+		padapter->recvpriv.signal_strength_data.total_val  +=pattrib->phy_info.SignalStrength;
+
+		padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength;
+		if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
+			padapter->recvpriv.signal_strength_data.index = 0;
+
+
+		tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num;
+		
+		if(padapter->recvpriv.is_signal_dbg) {
+			padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg;
+			padapter->recvpriv.rssi=(s8)translate2dbm((u8)padapter->recvpriv.signal_strength_dbg);
+		} else {
+			padapter->recvpriv.signal_strength= tmp_val;
+			padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val);
+		}
+
+		RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
+	#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	}
+
+}// Process_UI_RSSI_8192C
+
+
+
+static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
+{
+	u32	last_evm=0, tmpVal;
+ 	struct rx_pkt_attrib *pattrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct signal_stat * signal_stat;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+	if(prframe == NULL || padapter==NULL){
+		return;
+	}
+
+	pattrib = &prframe->u.hdr.attrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	signal_stat = &padapter->recvpriv.signal_qual_data;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+	//DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual);
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	if(signal_stat->update_req) {
+		signal_stat->total_num = 0;
+		signal_stat->total_val = 0;
+		signal_stat->update_req = 0;
+	}
+
+	signal_stat->total_num++;
+	signal_stat->total_val  += pattrib->phy_info.SignalQuality;
+	signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
+	
+#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	if(pattrib->phy_info.SignalQuality != 0)
+	{
+			//
+			// 1. Record the general EVM to the sliding window.
+			//
+			if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
+			{
+				padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
+				last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
+				padapter->recvpriv.signal_qual_data.total_val -= last_evm;
+			}
+			padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality;
+
+			padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality;
+			if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
+				padapter->recvpriv.signal_qual_data.index = 0;
+
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d  pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality));
+
+			// <1> Showed on UI for user, in percentage.
+			tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
+			padapter->recvpriv.signal_qual=(u8)tmpVal;
+
+	}
+	else
+	{
+		RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality));
+	}
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+}
+
+//void rtl8188e_process_phy_info(_adapter *padapter, union recv_frame *prframe)
+void rtl8188e_process_phy_info(_adapter *padapter, void *prframe)
+{
+	union recv_frame *precvframe = (union recv_frame *)prframe;
+
+	//
+	// Check RSSI
+	//
+	process_rssi(padapter, precvframe);
+	//
+	// Check PWDB.
+	//
+	//process_PWDB(padapter, precvframe); 
+
+	//UpdateRxSignalStatistics8192C(Adapter, pRfd);
+	//
+	// Check EVM
+	//
+	process_link_qual(padapter,  precvframe);
+
+}
+
+
+void update_recvframe_attrib_88e(
+	union recv_frame *precvframe,
+	struct recv_stat *prxstat)
+{
+	struct rx_pkt_attrib	*pattrib;
+	struct recv_stat	report;
+	PRXREPORT		prxreport;
+	//struct recv_frame_hdr	*phdr;
+
+	//phdr = &precvframe->u.hdr;
+
+	report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
+	report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
+	report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
+	report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
+	report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
+	report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
+
+	prxreport = (PRXREPORT)&report;
+
+	pattrib = &precvframe->u.hdr.attrib;
+	_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
+
+	pattrib->crc_err = (u8)((report.rxdw0 >> 14) & 0x1);;//(u8)prxreport->crc32;	
+	
+	// update rx report to recv_frame attribute
+	pattrib->pkt_rpt_type = (u8)((report.rxdw3 >> 14) & 0x3);//prxreport->rpt_sel;
+	
+	if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet	
+	{
+		pattrib->pkt_len = (u16)(report.rxdw0 &0x00003fff);//(u16)prxreport->pktlen;
+		pattrib->drvinfo_sz = (u8)((report.rxdw0 >> 16) & 0xf) * 8;//(u8)(prxreport->drvinfosize << 3);
+			
+		pattrib->physt =  (u8)((report.rxdw0 >> 26) & 0x1);//(u8)prxreport->physt;	
+
+		pattrib->bdecrypted = (report.rxdw0 & BIT(27))? 0:1;//(u8)(prxreport->swdec ? 0 : 1);
+		pattrib->encrypt = (u8)((report.rxdw0 >> 20) & 0x7);//(u8)prxreport->security;
+
+		pattrib->qos = (u8)((report.rxdw0 >> 23) & 0x1);//(u8)prxreport->qos;
+		pattrib->priority = (u8)((report.rxdw1 >> 8) & 0xf);//(u8)prxreport->tid;
+
+		pattrib->amsdu = (u8)((report.rxdw1 >> 13) & 0x1);//(u8)prxreport->amsdu;
+
+		pattrib->seq_num = (u16)(report.rxdw2 & 0x00000fff);//(u16)prxreport->seq;
+		pattrib->frag_num = (u8)((report.rxdw2 >> 12) & 0xf);//(u8)prxreport->frag;
+		pattrib->mfrag = (u8)((report.rxdw1 >> 27) & 0x1);//(u8)prxreport->mf;
+		pattrib->mdata = (u8)((report.rxdw1 >> 26) & 0x1);//(u8)prxreport->md;
+
+		pattrib->mcs_rate = (u8)(report.rxdw3 & 0x3f);//(u8)prxreport->rxmcs;
+		pattrib->rxht = (u8)((report.rxdw3 >> 6) & 0x1);//(u8)prxreport->rxht;
+		
+		pattrib->icv_err = (u8)((report.rxdw0 >> 15) & 0x1);//(u8)prxreport->icverr;
+		pattrib->shift_sz = (u8)((report.rxdw0 >> 24) & 0x3);
+	
+	}
+	else if(pattrib->pkt_rpt_type == TX_REPORT1)//CCX
+	{
+		pattrib->pkt_len = TX_RPT1_PKT_LEN;
+		pattrib->drvinfo_sz = 0;
+	}
+	else if(pattrib->pkt_rpt_type == TX_REPORT2)// TX RPT
+	{
+		pattrib->pkt_len =(u16)(report.rxdw0 & 0x3FF);//Rx length[9:0]
+		pattrib->drvinfo_sz = 0;
+
+		//
+		// Get TX report MAC ID valid.
+		//
+		pattrib->MacIDValidEntry[0] = report.rxdw4;
+		pattrib->MacIDValidEntry[1] = report.rxdw5;
+		
+	}
+	else if(pattrib->pkt_rpt_type == HIS_REPORT)// USB HISR RPT
+	{
+		pattrib->pkt_len = (u16)(report.rxdw0 &0x00003fff);//(u16)prxreport->pktlen;
+	}	
+	
+}
+
+/*
+ * Notice:
+ *	Before calling this function,
+ *	precvframe->u.hdr.rx_data should be ready!
+ */
+void update_recvframe_phyinfo_88e(
+	union recv_frame	*precvframe,
+	struct phy_stat *pphy_status)
+{
+	PADAPTER 			padapter = precvframe->u.hdr.adapter;
+	struct rx_pkt_attrib	*pattrib = &precvframe->u.hdr.attrib;
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);	
+	PODM_PHY_INFO_T 	pPHYInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
+	u8					*wlanhdr;
+	ODM_PACKET_INFO_T	pkt_info;
+	u8 *sa;
+	struct sta_priv *pstapriv;
+	struct sta_info *psta;
+	//_irqL		irqL;
+	
+	pkt_info.bPacketMatchBSSID =_FALSE;
+	pkt_info.bPacketToSelf = _FALSE;
+	pkt_info.bPacketBeacon = _FALSE;
+	
+	wlanhdr = get_recvframe_data(precvframe);
+
+	pkt_info.bPacketMatchBSSID = ((!IsFrameTypeCtrl(wlanhdr)) &&
+		!pattrib->icv_err && !pattrib->crc_err &&
+		_rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN));
+
+	pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID && (_rtw_memcmp(get_da(wlanhdr), myid(&padapter->eeprompriv), ETH_ALEN));
+
+	pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
+
+	if(pkt_info.bPacketBeacon){
+		if(check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){				
+			sa = padapter->mlmepriv.cur_network.network.MacAddress;
+			#if 0
+			{					
+				DBG_8192C("==> rx beacon from AP[%02x:%02x:%02x:%02x:%02x:%02x]\n",
+					sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]);					
+			}
+			#endif
+		}
+		else
+			sa = get_sa(wlanhdr);
+	}
+	else{
+		sa = get_sa(wlanhdr);
+	}	
+	
+	pstapriv = &padapter->stapriv;
+	pkt_info.StationID = 0xFF;
+	psta = rtw_get_stainfo(pstapriv, sa);
+	if (psta)
+	{
+		pkt_info.StationID = psta->mac_id;		
+		//DBG_8192C("%s ==> StationID(%d)\n",__FUNCTION__,pkt_info.StationID);
+	}			
+	pkt_info.Rate = pattrib->mcs_rate;	
+	//rtl8188e_query_rx_phy_status(precvframe, pphy_status);
+
+	//_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);	
+	ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info));
+	//_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
+
+	precvframe->u.hdr.psta = NULL;
+	if (pkt_info.bPacketMatchBSSID &&
+		(check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
+	{		
+		if (psta)
+		{			
+			precvframe->u.hdr.psta = psta;
+			rtl8188e_process_phy_info(padapter, precvframe);
+			
+		}		
+	}
+	else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon)
+	{
+		if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
+		{		
+			if (psta)
+			{				
+				precvframe->u.hdr.psta = psta;
+			}
+		}
+		rtl8188e_process_phy_info(padapter, precvframe);		
+	}
+}
+

hal/rtl8188e/rtl8188e_sreset.c

@@ -0,0 +1,125 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188E_SRESET_C_
+
+#include <rtl8188e_sreset.h>
+#include <rtl8188e_hal.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+
+void rtl8188e_sreset_xmit_status_check(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+
+	unsigned long current_time;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	unsigned int diff_time;
+	u32 txdma_status;
+	
+	if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
+		DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);	
+		rtw_hal_sreset_reset(padapter);
+	}
+#ifdef CONFIG_USB_HCI
+	//total xmit irp = 4
+	//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
+	//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
+	current_time = rtw_get_current_time();
+
+	if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
+
+		diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
+
+		if (diff_time > 2000) {
+			if (psrtpriv->last_tx_complete_time == 0) {
+				psrtpriv->last_tx_complete_time = current_time;
+			}
+			else{
+				diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
+				if (diff_time > 4000) {
+					u32 ability;
+
+					//padapter->Wifi_Error_Status = WIFI_TX_HANG;
+					rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &ability);
+
+					DBG_871X("%s tx hang %s\n", __FUNCTION__,
+						(ability & ODM_BB_ADAPTIVITY)? "ODM_BB_ADAPTIVITY" : "");
+
+					if (!(ability & ODM_BB_ADAPTIVITY))
+						rtw_hal_sreset_reset(padapter);
+				}
+			}
+		}
+	}
+#endif //CONFIG_USB_HCI
+
+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
+		rtw_hal_sreset_reset(padapter);
+		return;
+	}
+}
+
+void rtl8188e_sreset_linked_status_check(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+
+	u32 rx_dma_status = 0;
+	u8 fw_status=0;
+	rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
+	if(rx_dma_status!= 0x00){
+		DBG_8192C("%s REG_RXDMA_STATUS:0x%08x \n",__FUNCTION__,rx_dma_status);
+		rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);
+	}	
+	fw_status = rtw_read8(padapter,REG_FMETHR);
+	if(fw_status != 0x00)
+	{		
+		if(fw_status == 1)
+			DBG_8192C("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !!   \n",__FUNCTION__,fw_status);
+		else if(fw_status == 2)
+			DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !!   \n",__FUNCTION__,fw_status);
+	}
+#if 0
+	u32 regc50,regc58,reg824,reg800;
+	regc50 = rtw_read32(padapter,0xc50);
+	regc58 = rtw_read32(padapter,0xc58);
+	reg824 = rtw_read32(padapter,0x824);
+	reg800 = rtw_read32(padapter,0x800);
+	if(	((regc50&0xFFFFFF00)!= 0x69543400)||
+		((regc58&0xFFFFFF00)!= 0x69543400)||
+		(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
+		( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
+	{
+		DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
+			regc50, regc58, reg824, reg800);
+		rtw_hal_sreset_reset(padapter);
+	}
+#endif
+
+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
+		rtw_hal_sreset_reset(padapter);
+		return;
+	}
+}
+#endif
+

hal/rtl8188e/rtl8188e_xmit.c

@@ -0,0 +1,292 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188E_XMIT_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtl8188e_hal.h>
+
+#ifdef CONFIG_XMIT_ACK
+void dump_txrpt_ccx_88e(void *buf)
+{
+	struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf;
+
+	DBG_871X("%s:\n"
+		"tag1:%u, pkt_num:%u, txdma_underflow:%u, int_bt:%u, int_tri:%u, int_ccx:%u\n"
+		"mac_id:%u, pkt_ok:%u, bmc:%u\n"
+		"retry_cnt:%u, lifetime_over:%u, retry_over:%u\n"
+		"ccx_qtime:%u\n"
+		"final_data_rate:0x%02x\n"
+		"qsel:%u, sw:0x%03x\n"
+		, __func__
+		, txrpt_ccx->tag1, txrpt_ccx->pkt_num, txrpt_ccx->txdma_underflow, txrpt_ccx->int_bt, txrpt_ccx->int_tri, txrpt_ccx->int_ccx
+		, txrpt_ccx->mac_id, txrpt_ccx->pkt_ok, txrpt_ccx->bmc
+		, txrpt_ccx->retry_cnt, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over 
+		, txrpt_ccx_qtime_88e(txrpt_ccx)
+		, txrpt_ccx->final_data_rate
+		, txrpt_ccx->qsel, txrpt_ccx_sw_88e(txrpt_ccx)
+	);
+}
+
+void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf)
+{
+	struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf;
+
+	#ifdef DBG_CCX
+	dump_txrpt_ccx_88e(buf);
+	#endif
+
+	if (txrpt_ccx->int_ccx) {
+		if (txrpt_ccx->pkt_ok)
+			rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
+		else
+			rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
+	}
+}
+#endif //CONFIG_XMIT_ACK
+
+void _dbg_dump_tx_info(_adapter	*padapter,int frame_tag,struct tx_desc *ptxdesc)
+{
+	u8 bDumpTxPkt;
+	u8 bDumpTxDesc = _FALSE;
+	rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
+
+	if(bDumpTxPkt ==1){//dump txdesc for data frame
+		DBG_871X("dump tx_desc for data frame\n");
+		if((frame_tag&0x0f) == DATA_FRAMETAG){	
+			bDumpTxDesc = _TRUE;		
+		}
+	}	
+	else if(bDumpTxPkt ==2){//dump txdesc for mgnt frame
+		DBG_871X("dump tx_desc for mgnt frame\n");
+		if((frame_tag&0x0f) == MGNT_FRAMETAG){	
+			bDumpTxDesc = _TRUE;		
+		}
+	}	
+	else if(bDumpTxPkt ==3){//dump early info
+	}
+
+	if(bDumpTxDesc){
+		//	ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M
+		//	ptxdesc->txdw6 = 0x6666f800;
+		DBG_8192C("=====================================\n");
+		DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0);
+		DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1);
+		DBG_8192C("txdw2(0x%08x)\n",ptxdesc->txdw2);
+		DBG_8192C("txdw3(0x%08x)\n",ptxdesc->txdw3);
+		DBG_8192C("txdw4(0x%08x)\n",ptxdesc->txdw4);
+		DBG_8192C("txdw5(0x%08x)\n",ptxdesc->txdw5);
+		DBG_8192C("txdw6(0x%08x)\n",ptxdesc->txdw6);
+		DBG_8192C("txdw7(0x%08x)\n",ptxdesc->txdw7);
+		DBG_8192C("=====================================\n");
+	}
+
+}
+
+/*
+ * Description:
+ *	Aggregation packets and send to hardware
+ *
+ * Return:
+ *	0	Success
+ *	-1	Hardware resource(TX FIFO) not ready
+ *	-2	Software resource(xmitbuf) not ready
+ */
+#ifdef CONFIG_TX_EARLY_MODE
+
+//#define DBG_EMINFO
+
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1	
+	#define EARLY_MODE_MAX_PKT_NUM	10
+#else
+	#define EARLY_MODE_MAX_PKT_NUM	5
+#endif
+
+
+struct EMInfo{
+	u8 	EMPktNum;
+	u16  EMPktLen[EARLY_MODE_MAX_PKT_NUM];
+};
+
+
+void
+InsertEMContent_8188E(
+	struct EMInfo *pEMInfo,
+	IN pu1Byte	VirtualAddress)
+{
+
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+	u1Byte index=0;
+	u4Byte	dwtmp=0;
+#endif
+
+	_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);
+	if(pEMInfo->EMPktNum==0)
+		return;
+
+	#ifdef DBG_EMINFO
+	{
+		int i;
+		DBG_8192C("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum);
+		for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){
+			DBG_8192C("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]);
+		}
+
+	}
+	#endif
+	
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+	SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
+
+	if(pEMInfo->EMPktNum == 1){
+		dwtmp = pEMInfo->EMPktLen[0];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[0];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[1];
+	}
+	SET_EARLYMODE_LEN0(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 3){
+		dwtmp = pEMInfo->EMPktLen[2];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[2];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[3];
+	}
+	SET_EARLYMODE_LEN1(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 5){
+		dwtmp = pEMInfo->EMPktLen[4];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[4];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[5];
+	}
+	SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF);
+	SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4);
+	if(pEMInfo->EMPktNum <= 7){
+		dwtmp = pEMInfo->EMPktLen[6];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[6];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[7];
+	}
+	SET_EARLYMODE_LEN3(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 9){
+		dwtmp = pEMInfo->EMPktLen[8];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[8];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[9];
+	}
+	SET_EARLYMODE_LEN4(VirtualAddress, dwtmp);
+#else	
+	SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
+	SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]);
+	SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]);
+	SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF);
+	SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4);
+	SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
+	SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
+#endif	
+	//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
+
+}
+
+
+
+void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
+{
+	//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq	*ptxservq
+	int index,j;
+	u16 offset,pktlen;
+	PTXDESC ptxdesc;
+	
+	u8 *pmem,*pEMInfo_mem;
+	s8 node_num_0=0,node_num_1=0;
+	struct EMInfo eminfo;
+	struct agg_pkt_info *paggpkt;
+	struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data;	
+	pmem= pframe->buf_addr;	
+	
+	#ifdef DBG_EMINFO			
+	DBG_8192C("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num);
+	for(index=0;index<pframe->agg_num;index++){
+		offset = 	pxmitpriv->agg_pkt[index].offset;
+		pktlen = pxmitpriv->agg_pkt[index].pkt_len;
+		DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset);
+		DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen);
+	}
+	#endif
+	
+	if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM)
+	{	
+		node_num_0 = pframe->agg_num;
+		node_num_1= EARLY_MODE_MAX_PKT_NUM-1;
+	}
+	
+	for(index=0;index<pframe->agg_num;index++){
+
+		offset = pxmitpriv->agg_pkt[index].offset;
+		pktlen = pxmitpriv->agg_pkt[index].pkt_len;		
+
+		_rtw_memset(&eminfo,0,sizeof(struct EMInfo));
+		if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){
+			if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){
+				eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM;
+				node_num_0--;
+			}
+			else{
+				eminfo.EMPktNum = node_num_1;
+				node_num_1--;				
+			}			
+		}
+		else{
+			eminfo.EMPktNum = pframe->agg_num-(index+1);	
+		}				
+		for(j=0;j< eminfo.EMPktNum ;j++){
+			eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
+		}
+			
+		if(pmem){
+			if(index==0){
+				ptxdesc = (PTXDESC)(pmem);
+				pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;				
+			}
+			else{
+				pmem = pmem + pxmitpriv->agg_pkt[index-1].offset;
+				ptxdesc = (PTXDESC)(pmem);
+				pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;					
+			}
+			
+			#ifdef DBG_EMINFO
+			DBG_8192C("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen);
+			#endif
+			InsertEMContent_8188E(&eminfo,pEMInfo_mem);
+		}	
+		
+		
+	} 
+	_rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM);
+
+}
+#endif
+
+

hal/rtl8188e/sdio/rtl8189es_led.c

@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8189ES_LED_C_
+
+#include "drv_types.h"
+#include "rtl8188e_hal.h"
+
+//================================================================================
+// LED object.
+//================================================================================
+
+
+//================================================================================
+//	Prototype of protected function.
+//================================================================================
+
+//================================================================================
+// LED_819xUsb routines.
+//================================================================================
+
+//
+//	Description:
+//		Turn on LED according to LedPin specified.
+//
+void
+SwLedOn(
+	_adapter			*padapter,
+	PLED_871x		pLed
+)
+{
+	u8	LedCfg;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
+	{
+		return;
+	}
+
+	pLed->bLedOn = _TRUE;
+}
+
+
+//
+//	Description:
+//		Turn off LED according to LedPin specified.
+//
+void
+SwLedOff(
+	_adapter			*padapter,
+	PLED_871x		pLed
+)
+{
+	u8	LedCfg;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
+	{
+		goto exit;
+	}
+
+exit:
+	pLed->bLedOn = _FALSE;
+
+}
+
+//================================================================================
+// Default LED behavior.
+//================================================================================
+
+//
+//	Description:
+//		Initialize all LED_871x objects.
+//
+void
+rtl8188es_InitSwLeds(
+	_adapter	*padapter
+	)
+{
+	struct led_priv *pledpriv = &(padapter->ledpriv);
+
+#if 0
+	pledpriv->LedControlHandler = LedControl871x;
+
+	InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
+
+	InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1);
+#endif
+}
+
+
+//
+//	Description:
+//		DeInitialize all LED_819xUsb objects.
+//
+void
+rtl8188es_DeInitSwLeds(
+	_adapter	*padapter
+	)
+{
+#if 0
+	struct led_priv	*ledpriv = &(padapter->ledpriv);
+
+	DeInitLed871x( &(ledpriv->SwLed0) );
+	DeInitLed871x( &(ledpriv->SwLed1) );
+#endif
+}
+

hal/rtl8188e/sdio/rtl8189es_recv.c

@@ -0,0 +1,861 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8189ES_RECV_C_
+
+#include <drv_conf.h>
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+#error "Shall be Linux or Windows, but not both!\n"
+#endif
+
+#include <drv_types.h>
+#include <recv_osdep.h>
+#include <rtl8188e_hal.h>
+
+static void rtl8188es_recv_tasklet(void *priv);
+
+static s32 initrecvbuf(struct recv_buf *precvbuf, PADAPTER padapter)
+{
+	_rtw_init_listhead(&precvbuf->list);
+	_rtw_spinlock_init(&precvbuf->recvbuf_lock);
+
+	precvbuf->adapter = padapter;
+
+	return _SUCCESS;
+}
+
+static void freerecvbuf(struct recv_buf *precvbuf)
+{
+	_rtw_spinlock_free(&precvbuf->recvbuf_lock);
+}
+
+/*
+ * Initialize recv private variable for hardware dependent
+ * 1. recv buf
+ * 2. recv tasklet
+ *
+ */
+s32 rtl8188es_init_recv_priv(PADAPTER padapter)
+{
+	s32			res;
+	u32			i, n;
+	struct recv_priv	*precvpriv;
+	struct recv_buf		*precvbuf;
+
+
+	res = _SUCCESS;
+	precvpriv = &padapter->recvpriv;
+
+	//3 1. init recv buffer
+	_rtw_init_queue(&precvpriv->free_recv_buf_queue);
+	_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
+
+	n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
+	precvpriv->pallocated_recv_buf = rtw_zmalloc(n);
+	if (precvpriv->pallocated_recv_buf == NULL) {
+		res = _FAIL;
+		RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n"));
+		goto exit;
+	}
+
+	precvpriv->precv_buf = (u8*)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
+
+	// init each recv buffer
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+	for (i = 0; i < NR_RECVBUFF; i++)
+	{
+		res = initrecvbuf(precvbuf, padapter);
+		if (res == _FAIL)
+			break;
+
+		res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
+		if (res == _FAIL) {
+			freerecvbuf(precvbuf);
+			break;
+		}
+
+#ifdef CONFIG_SDIO_RX_COPY
+		if (precvbuf->pskb == NULL) {
+			SIZE_PTR tmpaddr=0;
+			SIZE_PTR alignment=0;
+
+			precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
+
+			if(precvbuf->pskb)
+			{
+				precvbuf->pskb->dev = padapter->pnetdev;
+
+				tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
+				alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
+				skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+				precvbuf->phead = precvbuf->pskb->head;
+				precvbuf->pdata = precvbuf->pskb->data;
+				precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
+				precvbuf->pend = skb_end_pointer(precvbuf->pskb);
+				precvbuf->len = 0;
+			}
+
+			if (precvbuf->pskb == NULL) {
+				DBG_871X("%s: alloc_skb fail!\n", __FUNCTION__);
+			}
+		}
+#endif
+
+		rtw_list_insert_tail(&precvbuf->list, &precvpriv->free_recv_buf_queue.queue);
+
+		precvbuf++;
+	}
+	precvpriv->free_recv_buf_queue_cnt = i;
+
+	if (res == _FAIL)
+		goto initbuferror;
+
+	//3 2. init tasklet
+#ifdef PLATFORM_LINUX
+	tasklet_init(&precvpriv->recv_tasklet,
+	     (void(*)(unsigned long))rtl8188es_recv_tasklet,
+	     (unsigned long)padapter);
+#endif
+
+	goto exit;
+
+initbuferror:
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+	if (precvbuf) {
+		n = precvpriv->free_recv_buf_queue_cnt;
+		precvpriv->free_recv_buf_queue_cnt = 0;
+		for (i = 0; i < n ; i++)
+		{
+			rtw_list_delete(&precvbuf->list);
+			rtw_os_recvbuf_resource_free(padapter, precvbuf);
+			freerecvbuf(precvbuf);
+			precvbuf++;
+		}
+		precvpriv->precv_buf = NULL;
+	}
+
+	if (precvpriv->pallocated_recv_buf) {
+		n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
+		rtw_mfree(precvpriv->pallocated_recv_buf, n);
+		precvpriv->pallocated_recv_buf = NULL;
+	}
+
+exit:
+	return res;
+}
+
+/*
+ * Free recv private variable of hardware dependent
+ * 1. recv buf
+ * 2. recv tasklet
+ *
+ */
+void rtl8188es_free_recv_priv(PADAPTER padapter)
+{
+	u32			i, n;
+	struct recv_priv	*precvpriv;
+	struct recv_buf		*precvbuf;
+
+
+	precvpriv = &padapter->recvpriv;
+
+	//3 1. kill tasklet
+#ifdef PLATFORM_LINUX
+	tasklet_kill(&precvpriv->recv_tasklet);
+#endif
+
+	//3 2. free all recv buffers
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+	if (precvbuf) {
+		n = NR_RECVBUFF;
+		precvpriv->free_recv_buf_queue_cnt = 0;
+		for (i = 0; i < n ; i++)
+		{
+			rtw_list_delete(&precvbuf->list);
+			rtw_os_recvbuf_resource_free(padapter, precvbuf);
+			freerecvbuf(precvbuf);
+			precvbuf++;
+		}
+		precvpriv->precv_buf = NULL;
+	}
+
+	if (precvpriv->pallocated_recv_buf) {
+		n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
+		rtw_mfree(precvpriv->pallocated_recv_buf, n);
+		precvpriv->pallocated_recv_buf = NULL;
+	}
+}
+
+#ifdef CONFIG_SDIO_RX_COPY
+static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf	*precvbuf, struct phy_stat *pphy_status)
+{	
+	s32 ret=_SUCCESS;
+#ifdef CONFIG_CONCURRENT_MODE	
+	u8 *primary_myid, *secondary_myid, *paddr1;
+	union recv_frame	*precvframe_if2 = NULL;
+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
+	_adapter *secondary_padapter = primary_padapter->pbuddy_adapter;
+	struct recv_priv *precvpriv = &primary_padapter->recvpriv;
+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(primary_padapter);
+
+	if(!secondary_padapter)
+		return ret;
+
+	paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);
+
+	if(IS_MCAST(paddr1) == _FALSE)//unicast packets
+	{
+		//primary_myid = myid(&primary_padapter->eeprompriv);
+		secondary_myid = myid(&secondary_padapter->eeprompriv);
+
+		if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
+		{			
+			//change to secondary interface
+			precvframe->u.hdr.adapter = secondary_padapter;
+		}	
+
+		//ret = recv_entry(precvframe);
+
+	}
+	else // Handle BC/MC Packets	
+	{
+		//clone/copy to if2
+		_pkt	 *pkt_copy = NULL;
+		struct rx_pkt_attrib *pattrib = NULL;
+		
+		precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue);
+
+		if(!precvframe_if2)
+			return _FAIL;
+		
+		precvframe_if2->u.hdr.adapter = secondary_padapter;
+		_rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
+		pattrib = &precvframe_if2->u.hdr.attrib;
+
+		//driver need to set skb len for rtw_skb_copy().
+		//If skb->len is zero, rtw_skb_copy() will not copy data from original skb.
+		skb_put(precvframe->u.hdr.pkt, pattrib->pkt_len);
+
+		pkt_copy = rtw_skb_copy( precvframe->u.hdr.pkt);
+		if (pkt_copy == NULL)
+		{
+			if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0))
+			{				
+				DBG_8192C("pre_recv_entry(): rtw_skb_copy fail , drop frag frame \n");
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				return ret;
+			}
+
+			pkt_copy = rtw_skb_clone(precvframe->u.hdr.pkt);
+			if(pkt_copy == NULL)
+			{
+				DBG_8192C("pre_recv_entry(): rtw_skb_clone fail , drop frame\n");
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				return ret;
+			}
+		}
+		
+		pkt_copy->dev = secondary_padapter->pnetdev;
+
+		precvframe_if2->u.hdr.pkt = pkt_copy;
+		precvframe_if2->u.hdr.rx_head = pkt_copy->head;
+		precvframe_if2->u.hdr.rx_data = pkt_copy->data;
+		precvframe_if2->u.hdr.rx_tail = skb_tail_pointer(pkt_copy);
+		precvframe_if2->u.hdr.rx_end = skb_end_pointer(pkt_copy);
+		precvframe_if2->u.hdr.len = pkt_copy->len;
+
+		//recvframe_put(precvframe_if2, pattrib->pkt_len);
+
+		if ( pHalData->ReceiveConfig & RCR_APPFCS)
+			recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN);
+
+		if (pattrib->physt) 
+			update_recvframe_phyinfo_88e(precvframe_if2, pphy_status);
+
+		if(rtw_recv_entry(precvframe_if2) != _SUCCESS)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+				("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+		}
+	}
+	
+	if (precvframe->u.hdr.attrib.physt)
+		update_recvframe_phyinfo_88e(precvframe, pphy_status);
+	ret = rtw_recv_entry(precvframe);
+
+#endif
+
+	return ret;
+
+}
+
+static void rtl8188es_recv_tasklet(void *priv)
+{
+	PADAPTER			padapter;
+	PHAL_DATA_TYPE		pHalData;
+	struct recv_priv		*precvpriv;
+	struct recv_buf		*precvbuf;
+	union recv_frame		*precvframe;
+	struct recv_frame_hdr	*phdr;
+	struct rx_pkt_attrib	*pattrib;
+	_irqL	irql;
+	u8		*ptr;
+	u32		pkt_offset, skb_len, alloc_sz;
+	s32		transfer_len;
+	_pkt		*pkt_copy = NULL;
+	struct phy_stat	*pphy_status = NULL;
+	u8		shift_sz = 0, rx_report_sz = 0;
+
+
+	padapter = (PADAPTER)priv;
+	pHalData = GET_HAL_DATA(padapter);
+	precvpriv = &padapter->recvpriv;
+	
+	do {
+		if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
+		{
+			DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
+			break;
+		}
+		
+		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
+		if (NULL == precvbuf) break;
+
+		transfer_len = (s32)precvbuf->len;
+		ptr = precvbuf->pdata;
+
+		do {
+			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
+			if (precvframe == NULL) {
+				RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: no enough recv frame!\n",__FUNCTION__));
+				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+				// The case of can't allocte recvframe should be temporary,
+				// schedule again and hope recvframe is available next time.
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+				return;
+			}
+
+			//rx desc parsing
+			update_recvframe_attrib_88e(precvframe, (struct recv_stat*)ptr);
+
+			pattrib = &precvframe->u.hdr.attrib;
+
+			// fix Hardware RX data error, drop whole recv_buffer
+			if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err)
+			{
+				DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			if (pHalData->ReceiveConfig & RCR_APP_BA_SSN)
+				rx_report_sz = RXDESC_SIZE + 4 + pattrib->drvinfo_sz;
+			else
+				rx_report_sz = RXDESC_SIZE + pattrib->drvinfo_sz;
+
+			pkt_offset = rx_report_sz + pattrib->shift_sz + pattrib->pkt_len;
+
+			if ((pattrib->pkt_len==0) || (pkt_offset>transfer_len)) {
+				DBG_8192C("%s()-%d: RX Warning!,pkt_len==0 or pkt_offset(%d)> transfoer_len(%d) \n", __FUNCTION__, __LINE__, pkt_offset, transfer_len);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			if ((pattrib->crc_err) || (pattrib->icv_err))
+			{
+				#ifdef CONFIG_MP_INCLUDED
+				if (padapter->registrypriv.mp_mode == 1)
+				{
+					if ((check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE))//&&(padapter->mppriv.check_mp_pkt == 0))
+					{
+						if (pattrib->crc_err == 1)
+							padapter->mppriv.rx_crcerrpktcount++;
+					}
+				}
+				#endif
+				DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+			}
+			else
+			{
+				//	Modified by Albert 20101213
+				//	For 8 bytes IP header alignment.
+				if (pattrib->qos)	//	Qos data, wireless lan header length is 26
+				{
+					shift_sz = 6;
+				}
+				else
+				{
+					shift_sz = 0;
+				}
+
+				skb_len = pattrib->pkt_len;
+
+				// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
+				// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
+				if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+					//alloc_sz = 1664;	//1664 is 128 alignment.
+					if(skb_len <= 1650)
+						alloc_sz = 1664;
+					else
+						alloc_sz = skb_len + 14;
+				}
+				else {
+					alloc_sz = skb_len;
+					//	6 is for IP header 8 bytes alignment in QoS packet case.
+					//	8 is for skb->data 4 bytes alignment.
+					alloc_sz += 14;
+				}
+
+				pkt_copy = rtw_skb_alloc(alloc_sz);
+
+				if(pkt_copy)
+				{
+					pkt_copy->dev = padapter->pnetdev;
+					precvframe->u.hdr.pkt = pkt_copy;
+					skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
+					skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
+					_rtw_memcpy(pkt_copy->data, (ptr + rx_report_sz + pattrib->shift_sz), skb_len);
+					precvframe->u.hdr.rx_head = pkt_copy->head;
+					precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
+					precvframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);
+				}
+				else
+				{
+					if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0))
+					{				
+						DBG_8192C("rtl8188es_recv_tasklet: alloc_skb fail , drop frag frame \n");
+						rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+						break;
+					}
+					
+					precvframe->u.hdr.pkt = rtw_skb_clone(precvbuf->pskb);
+					if(precvframe->u.hdr.pkt)
+					{
+						_pkt	*pkt_clone = precvframe->u.hdr.pkt;
+
+						pkt_clone->data = ptr + rx_report_sz + pattrib->shift_sz;
+						skb_reset_tail_pointer(pkt_clone);
+						precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail 
+							= pkt_clone->data;
+						precvframe->u.hdr.rx_end =  pkt_clone->data + skb_len;
+					}
+					else
+					{
+						DBG_8192C("rtl8188es_recv_tasklet: rtw_skb_clone fail\n");
+						rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+						break;
+					}
+				}
+
+				recvframe_put(precvframe, skb_len);
+				//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
+
+				if (pHalData->ReceiveConfig & RCR_APPFCS)
+					recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
+
+				// update drv info
+				if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) {
+					//rtl8723s_update_bassn(padapter, (ptr + RXDESC_SIZE));
+				}
+
+				if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
+				{
+					pphy_status = (struct phy_stat *)(ptr + (rx_report_sz - pattrib->drvinfo_sz));
+				
+#ifdef CONFIG_CONCURRENT_MODE
+					if(rtw_buddy_adapter_up(padapter))
+					{
+						if(pre_recv_entry(precvframe, precvbuf, (struct phy_stat*)pphy_status) != _SUCCESS)
+						{
+							RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+								("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
+						}
+					}
+					else
+#endif
+					{
+						if (pattrib->physt)
+							update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);
+
+						if (rtw_recv_entry(precvframe) != _SUCCESS)
+						{
+							RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: rtw_recv_entry(precvframe) != _SUCCESS\n",__FUNCTION__));
+						}
+					}
+				}
+				else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
+
+					//enqueue recvframe to txrtp queue
+					if(pattrib->pkt_rpt_type == TX_REPORT1){
+						//DBG_8192C("rx CCX \n");
+						//CCX-TXRPT ack for xmit mgmt frames.
+						handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
+					}
+					else if(pattrib->pkt_rpt_type == TX_REPORT2){
+						//printk("rx TX RPT \n");
+						ODM_RA_TxRPT2Handle_8188E(
+									&pHalData->odmpriv,
+									precvframe->u.hdr.rx_data,
+									pattrib->pkt_len,
+									pattrib->MacIDValidEntry[0],
+									pattrib->MacIDValidEntry[1]
+									);
+
+					}
+					/*
+					else if(pattrib->pkt_rpt_type == HIS_REPORT){
+						printk("rx USB HISR \n");						
+					}*/
+
+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);					
+
+				}
+			}
+
+			// Page size of receive package is 128 bytes alignment =>DMA AGG
+			// refer to _InitTransferPageSize()
+			pkt_offset = _RND128(pkt_offset);
+			transfer_len -= pkt_offset;
+			ptr += pkt_offset;	
+			precvframe = NULL;
+			pkt_copy = NULL;
+		}while(transfer_len>0);
+
+		precvbuf->len = 0;
+
+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
+	} while (1);
+
+}
+#else
+static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf	*precvbuf, struct phy_stat *pphy_status)
+{	
+	s32 ret=_SUCCESS;
+#ifdef CONFIG_CONCURRENT_MODE	
+	u8 *primary_myid, *secondary_myid, *paddr1;
+	union recv_frame	*precvframe_if2 = NULL;
+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
+	_adapter *secondary_padapter = primary_padapter->pbuddy_adapter;
+	struct recv_priv *precvpriv = &primary_padapter->recvpriv;
+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
+	u8	*pbuf = precvframe->u.hdr.rx_head;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(primary_padapter);
+
+	if(!secondary_padapter)
+		return ret;
+
+	paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);
+
+	if(IS_MCAST(paddr1) == _FALSE)//unicast packets
+	{
+		//primary_myid = myid(&primary_padapter->eeprompriv);
+		secondary_myid = myid(&secondary_padapter->eeprompriv);
+
+		if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
+		{			
+			//change to secondary interface
+			precvframe->u.hdr.adapter = secondary_padapter;
+		}	
+
+		//ret = recv_entry(precvframe);
+
+	}
+	else // Handle BC/MC Packets	
+	{
+		//clone/copy to if2
+		u8 shift_sz = 0;
+		u32 alloc_sz, skb_len;		
+		_pkt	 *pkt_copy = NULL;
+		struct rx_pkt_attrib *pattrib = NULL;
+		
+		precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue);
+
+		if(!precvframe_if2)
+			return _FAIL;
+		
+		precvframe_if2->u.hdr.adapter = secondary_padapter;
+		_rtw_init_listhead(&precvframe_if2->u.hdr.list);	
+		precvframe_if2->u.hdr.precvbuf = NULL;	//can't access the precvbuf for new arch.
+		precvframe_if2->u.hdr.len=0;
+		_rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
+		pattrib = &precvframe_if2->u.hdr.attrib;
+
+		pkt_copy = rtw_skb_copy( precvframe->u.hdr.pkt);
+		if (pkt_copy == NULL)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n",__FUNCTION__));
+			rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue);
+			rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+			// The case of can't allocte skb is serious and may never be recovered,
+			// once bDriverStopped is enable, this task should be stopped.
+			if (secondary_padapter->bDriverStopped == _FALSE)
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+			return ret;
+		}
+		pkt_copy->dev = secondary_padapter->pnetdev;
+
+
+
+		if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+			//alloc_sz = 1664;	//1664 is 128 alignment.
+			if(skb_len <= 1650)
+				alloc_sz = 1664;
+			else
+				alloc_sz = skb_len + 14;
+		}
+		else {
+			alloc_sz = skb_len;
+			//	6 is for IP header 8 bytes alignment in QoS packet case.
+			//	8 is for skb->data 4 bytes alignment.
+			alloc_sz += 14;
+		}
+
+#if 1
+		precvframe_if2->u.hdr.pkt = pkt_copy;
+		precvframe_if2->u.hdr.rx_head = pkt_copy->head;
+		precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data; 
+		precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz;
+#endif
+		recvframe_put(precvframe_if2, pkt_offset);
+		recvframe_pull(precvframe_if2, RXDESC_SIZE + pattrib->drvinfo_sz);
+
+		if ( pHalData->ReceiveConfig & RCR_APPFCS)
+			recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN);
+
+		if (pattrib->physt) 
+			update_recvframe_phyinfo_88e(precvframe_if2, pphy_status);
+
+		if(rtw_recv_entry(precvframe_if2) != _SUCCESS)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+				("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+		}
+	}
+	
+	if (precvframe->u.hdr.attrib.physt)
+		update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);	
+	ret = rtw_recv_entry(precvframe);
+
+#endif
+
+	return ret;
+
+}
+
+static void rtl8188es_recv_tasklet(void *priv)
+{
+	PADAPTER				padapter;
+	PHAL_DATA_TYPE			pHalData;
+	struct recv_priv		*precvpriv;
+	struct recv_buf			*precvbuf;
+	union recv_frame		*precvframe;
+	struct recv_frame_hdr	*phdr;
+	struct rx_pkt_attrib	*pattrib;
+	u8			*ptr;
+	_pkt		*ppkt;
+	u32			pkt_offset;
+	_irqL		irql;
+#ifdef CONFIG_CONCURRENT_MODE	
+	struct recv_stat	*prxstat;
+#endif
+
+	padapter = (PADAPTER)priv;
+	pHalData = GET_HAL_DATA(padapter);
+	precvpriv = &padapter->recvpriv;
+	
+	do {
+		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
+		if (NULL == precvbuf) break;
+
+		ptr = precvbuf->pdata;
+
+		while (ptr < precvbuf->ptail)
+		{
+			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
+			if (precvframe == NULL) {
+				RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: no enough recv frame!\n",__FUNCTION__));
+				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+				// The case of can't allocte recvframe should be temporary,
+				// schedule again and hope recvframe is available next time.
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+				return;
+			}
+
+			phdr = &precvframe->u.hdr;
+			pattrib = &phdr->attrib;
+
+			//rx desc parsing
+			update_recvframe_attrib_88e(precvframe, (struct recv_stat*)ptr);
+#ifdef CONFIG_CONCURRENT_MODE
+			prxstat = (struct recv_stat*)ptr;
+#endif
+			// fix Hardware RX data error, drop whole recv_buffer
+			if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err)
+			{	
+				DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->pkt_len;
+
+			if ((ptr + pkt_offset) > precvbuf->ptail) {
+				DBG_8192C("%s()-%d: : next pkt len(%p,%d) exceed ptail(%p)!\n", __FUNCTION__, __LINE__, ptr, pkt_offset, precvbuf->ptail);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			if ((pattrib->crc_err) || (pattrib->icv_err))
+			{
+				#ifdef CONFIG_MP_INCLUDED
+				if (padapter->registrypriv.mp_mode == 1)
+				{
+					if ((check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE))//&&(padapter->mppriv.check_mp_pkt == 0))
+					{
+						if (pattrib->crc_err == 1)
+							padapter->mppriv.rx_crcerrpktcount++;
+					}
+				}
+				#endif
+
+				DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+			}
+			else
+			{
+				ppkt = rtw_skb_clone(precvbuf->pskb);
+				if (ppkt == NULL)
+				{
+					RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n",__FUNCTION__));
+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+					rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+					// The case of can't allocte skb is serious and may never be recovered,
+					// once bDriverStopped is enable, this task should be stopped.
+					if (padapter->bDriverStopped == _FALSE) {
+#ifdef PLATFORM_LINUX
+						tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+					}
+
+					return;
+				}
+
+				phdr->pkt = ppkt;
+				phdr->len = 0;
+				phdr->rx_head = precvbuf->phead;
+				phdr->rx_data = phdr->rx_tail = precvbuf->pdata;
+				phdr->rx_end = precvbuf->pend;
+
+				recvframe_put(precvframe, pkt_offset);
+				recvframe_pull(precvframe, RXDESC_SIZE + pattrib->drvinfo_sz);
+
+				if (pHalData->ReceiveConfig & RCR_APPFCS)
+					recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
+
+				// move to drv info position
+				ptr += RXDESC_SIZE;
+
+				// update drv info
+				if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) {
+//					rtl8723s_update_bassn(padapter, pdrvinfo);
+					ptr += 4;
+				}
+
+				if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
+				{
+#ifdef CONFIG_CONCURRENT_MODE
+					if(rtw_buddy_adapter_up(padapter))
+					{
+						if(pre_recv_entry(precvframe, precvbuf, (struct phy_stat*)ptr) != _SUCCESS)
+						{
+							RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+								("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
+						}
+					}
+					else
+#endif
+					{
+						if (pattrib->physt) 
+					update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)ptr);
+
+					if (rtw_recv_entry(precvframe) != _SUCCESS)
+					{
+							RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+								("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+						}
+					}
+				}
+				else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
+
+					//enqueue recvframe to txrtp queue
+					if(pattrib->pkt_rpt_type == TX_REPORT1){
+						DBG_8192C("rx CCX \n");
+					}
+					else if(pattrib->pkt_rpt_type == TX_REPORT2){
+						//DBG_8192C("rx TX RPT \n");
+						ODM_RA_TxRPT2Handle_8188E(
+									&pHalData->odmpriv,
+									precvframe->u.hdr.rx_data,
+									pattrib->pkt_len,
+									pattrib->MacIDValidEntry[0],
+									pattrib->MacIDValidEntry[1]
+									);
+
+					}
+					/*
+					else if(pattrib->pkt_rpt_type == HIS_REPORT){
+						DBG_8192C("rx USB HISR \n");
+					}*/
+
+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);					
+
+				}
+			}
+
+			// Page size of receive package is 128 bytes alignment =>DMA AGG
+			// refer to _InitTransferPageSize()
+			pkt_offset = _RND128(pkt_offset);
+			precvbuf->pdata += pkt_offset;
+			ptr = precvbuf->pdata;
+
+		}
+
+		rtw_skb_free(precvbuf->pskb);
+		precvbuf->pskb = NULL;
+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
+
+	} while (1);
+
+}
+#endif
+

hal/rtl8188e/usb/rtl8188eu_led.c

@@ -0,0 +1,170 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtl8188e_hal.h>
+
+//================================================================================
+// LED object.
+//================================================================================
+
+
+//================================================================================
+//	Prototype of protected function.
+//================================================================================
+
+
+//================================================================================
+// LED_819xUsb routines. 
+//================================================================================
+
+//
+//	Description:
+//		Turn on LED according to LedPin specified.
+//
+void
+SwLedOn(
+	_adapter			*padapter, 
+	PLED_871x		pLed
+)
+{
+	u8	LedCfg;
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
+	{
+		return;
+	}
+
+	LedCfg = rtw_read8(padapter, REG_LEDCFG2);
+	switch(pLed->LedPin)
+	{	
+		case LED_PIN_LED0:
+			rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on.
+			break;
+
+		case LED_PIN_LED1:
+			rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on.
+			break;
+
+		default:
+			break;
+	}
+	
+	pLed->bLedOn = _TRUE;
+}
+
+
+//
+//	Description:
+//		Turn off LED according to LedPin specified.
+//
+void
+SwLedOff(
+	_adapter			*padapter, 
+	PLED_871x		pLed
+)
+{
+	u8	LedCfg;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))	
+	{
+		goto exit;
+	}
+
+
+	LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E
+
+	switch(pLed->LedPin)
+	{
+		case LED_PIN_LED0:
+			if(pHalData->bLedOpenDrain == _TRUE) // Open-drain arrangement for controlling the LED)
+			{
+				LedCfg &= 0x90; // Set to software control.				
+				rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));				
+				LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG);
+				LedCfg &= 0xFE;
+				rtw_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg);									
+			}
+			else
+			{
+				rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6));
+			}
+			break;
+
+		case LED_PIN_LED1:
+			LedCfg &= 0x0f; // Set to software control.
+			rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
+			break;
+
+		default:
+			break;
+	}
+exit:
+	pLed->bLedOn = _FALSE;
+	
+}
+
+//================================================================================
+// Interface to manipulate LED objects.
+//================================================================================
+
+
+//================================================================================
+// Default LED behavior.
+//================================================================================
+
+//
+//	Description:
+//		Initialize all LED_871x objects.
+//
+void
+rtl8188eu_InitSwLeds(
+	_adapter	*padapter
+	)
+{
+	struct led_priv *pledpriv = &(padapter->ledpriv);
+
+	pledpriv->LedControlHandler = LedControl871x;
+
+	InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
+
+	InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1);
+}
+
+
+//
+//	Description:
+//		DeInitialize all LED_819xUsb objects.
+//
+void
+rtl8188eu_DeInitSwLeds(
+	_adapter	*padapter
+	)
+{
+	struct led_priv	*ledpriv = &(padapter->ledpriv);
+
+	DeInitLed871x( &(ledpriv->SwLed0) );
+	DeInitLed871x( &(ledpriv->SwLed1) );
+}
+

hal/rtl8188e/usb/rtl8188eu_recv.c

@@ -0,0 +1,234 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188EU_RECV_C_
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <recv_osdep.h>
+#include <mlme_osdep.h>
+#include <ip.h>
+#include <if_ether.h>
+#include <ethernet.h>
+
+#include <usb_ops.h>
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+#include <wifi.h>
+#include <circ_buf.h>
+
+#include <rtl8188e_hal.h>
+
+
+void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf)
+{
+
+	precvbuf->transfer_len = 0;
+
+	precvbuf->len = 0;
+
+	precvbuf->ref_cnt = 0;
+
+	if(precvbuf->pbuf)
+	{
+		precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf;
+		precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ;
+	}
+
+}
+
+int	rtl8188eu_init_recv_priv(_adapter *padapter)
+{
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	int	i, res = _SUCCESS;
+	struct recv_buf *precvbuf;
+
+#ifdef CONFIG_RECV_THREAD_MODE	
+	_rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed
+	_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed
+#endif
+
+#ifdef PLATFORM_LINUX
+	tasklet_init(&precvpriv->recv_tasklet,
+	     (void(*)(unsigned long))rtl8188eu_recv_tasklet,
+	     (unsigned long)padapter);
+#endif
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+#ifdef PLATFORM_LINUX
+	precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
+	if(precvpriv->int_in_urb == NULL){
+		res= _FAIL;
+		DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n");
+		goto exit;
+	}
+#endif
+	precvpriv->int_in_buf = rtw_zmalloc(INTERRUPT_MSG_FORMAT_LEN);
+	if(precvpriv->int_in_buf == NULL){
+		res= _FAIL;
+		DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n");
+		goto exit;
+	}
+#endif
+
+	//init recv_buf
+	_rtw_init_queue(&precvpriv->free_recv_buf_queue);
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
+#endif	// CONFIG_USE_USB_BUFFER_ALLOC_RX
+
+	precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
+	if(precvpriv->pallocated_recv_buf==NULL){
+		res= _FAIL;
+		RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n"));
+		goto exit;
+	}
+	_rtw_memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
+
+	precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
+	//precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 -
+	//						((uint) (precvpriv->pallocated_recv_buf) &(4-1));
+
+
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+
+	for(i=0; i < NR_RECVBUFF ; i++)
+	{
+		_rtw_init_listhead(&precvbuf->list);
+
+		_rtw_spinlock_init(&precvbuf->recvbuf_lock);
+
+		precvbuf->alloc_sz = MAX_RECVBUF_SZ;
+
+		res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
+		if(res==_FAIL)
+			break;
+
+		precvbuf->ref_cnt = 0;
+		precvbuf->adapter =padapter;
+
+
+		//rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue));
+
+		precvbuf++;
+
+	}
+
+	precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF;
+
+#ifdef PLATFORM_LINUX
+
+	skb_queue_head_init(&precvpriv->rx_skb_queue);
+
+#ifdef CONFIG_PREALLOC_RECV_SKB
+	{
+		int i;
+		SIZE_PTR tmpaddr=0;
+		SIZE_PTR alignment=0;
+		struct sk_buff *pskb=NULL;
+
+		skb_queue_head_init(&precvpriv->free_recv_skb_queue);
+
+		for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
+		{
+			pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
+
+			if(pskb)
+			{
+				pskb->dev = padapter->pnetdev;
+
+				tmpaddr = (SIZE_PTR)pskb->data;
+				alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
+				skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+				skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
+			}
+
+			pskb=NULL;
+
+		}
+	}
+#endif
+
+#endif
+
+exit:
+
+	return res;
+
+}
+
+void rtl8188eu_free_recv_priv (_adapter *padapter)
+{
+	int	i;
+	struct recv_buf	*precvbuf;
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+
+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
+
+	for(i=0; i < NR_RECVBUFF ; i++)
+	{
+		rtw_os_recvbuf_resource_free(padapter, precvbuf);
+		precvbuf++;
+	}
+
+	if(precvpriv->pallocated_recv_buf)
+		rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+#ifdef PLATFORM_LINUX
+	if(precvpriv->int_in_urb)
+	{
+		usb_free_urb(precvpriv->int_in_urb);
+	}
+#endif//PLATFORM_LINUX
+
+	if(precvpriv->int_in_buf)
+		rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN);
+#endif//CONFIG_USB_INTERRUPT_IN_PIPE
+
+#ifdef PLATFORM_LINUX
+
+	if (skb_queue_len(&precvpriv->rx_skb_queue)) {
+		DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n");
+	}
+
+	rtw_skb_queue_purge(&precvpriv->rx_skb_queue);
+
+#ifdef CONFIG_PREALLOC_RECV_SKB
+
+	if (skb_queue_len(&precvpriv->free_recv_skb_queue)) {
+		DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue));
+	}
+
+	rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue);
+
+#endif
+
+#endif
+
+}
+
+

include/Hal8188EPhyCfg.h

@@ -20,24 +20,31 @@
 #ifndef __INC_HAL8188EPHYCFG_H__
 #define __INC_HAL8188EPHYCFG_H__
 
+
 /*--------------------------Define Parameters-------------------------------*/
-#define LOOP_LIMIT			5
+#define LOOP_LIMIT				5
-#define MAX_STALL_TIME			50		/* us */
+#define MAX_STALL_TIME			50		//us
-#define AntennaDiversityValue		0x80
+#define AntennaDiversityValue	0x80	//(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
-#define MAX_TXPWR_IDX_NMODE_92S		63
+#define MAX_TXPWR_IDX_NMODE_92S	63
 #define Reset_Cnt_Limit			3
 
-#define IQK_MAC_REG_NUM			4
+#define IQK_MAC_REG_NUM		4
 #define IQK_ADDA_REG_NUM		16
 #define IQK_BB_REG_NUM			9
-#define HP_THERMAL_NUM			8
+#define HP_THERMAL_NUM		8
+
+#ifdef CONFIG_PCI_HCI
+#define MAX_AGGR_NUM	0x0B
+#else
+#define MAX_AGGR_NUM	0x07
+#endif // CONFIG_PCI_HCI
 
-#define MAX_AGGR_NUM			0x07
 
 /*--------------------------Define Parameters-------------------------------*/
 
+
 /*------------------------------Define structure----------------------------*/ 
-enum sw_chnl_cmd_id {
+typedef enum _SwChnlCmdID{
 	CmdID_End,
 	CmdID_SetTxPowerLevel,
 	CmdID_BBRegWrite10,
@@ -45,55 +52,57 @@ enum sw_chnl_cmd_id {
 	CmdID_WritePortUshort,
 	CmdID_WritePortUchar,
 	CmdID_RF_WriteReg,
-};
+}SwChnlCmdID;
+
 
 /* 1. Switch channel related */
-struct sw_chnl_cmd {
+typedef struct _SwChnlCmd{
-	enum sw_chnl_cmd_id CmdID;
+	SwChnlCmdID	CmdID;
-	u32 Para1;
+	u32			Para1;
-	u32 Para2;
+	u32			Para2;
-	u32 msDelay;
+	u32			msDelay;
-};
+}SwChnlCmd;
 
-enum hw90_block {
+typedef enum _HW90_BLOCK{
 	HW90_BLOCK_MAC = 0,
 	HW90_BLOCK_PHY0 = 1,
 	HW90_BLOCK_PHY1 = 2,
 	HW90_BLOCK_RF = 3,
-	HW90_BLOCK_MAXIMUM = 4, /*  Never use this */
+	HW90_BLOCK_MAXIMUM = 4, // Never use this
-};
+}HW90_BLOCK_E, *PHW90_BLOCK_E;
 
-enum rf_radio_path {
+typedef enum _RF_RADIO_PATH{
-	RF_PATH_A = 0,			/* Radio Path A */
+	RF_PATH_A = 0,			//Radio Path A
-	RF_PATH_B = 1,			/* Radio Path B */
+	RF_PATH_B = 1,			//Radio Path B
-	RF_PATH_C = 2,			/* Radio Path C */
+	RF_PATH_C = 2,			//Radio Path C
-	RF_PATH_D = 3,			/* Radio Path D */
+	RF_PATH_D = 3,			//Radio Path D
-};
+	//RF_PATH_MAX				//Max RF number 90 support 
+}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
 
 #define MAX_PG_GROUP 13
 
-#define	RF_PATH_MAX			3
+#define	RF_PATH_MAX		2
-#define		MAX_RF_PATH		RF_PATH_MAX
+#define 	MAX_RF_PATH		RF_PATH_MAX
-#define		MAX_TX_COUNT		4 /* path numbers */
+#define	MAX_TX_COUNT_88E			1
+#define 	MAX_TX_COUNT				MAX_TX_COUNT_88E  // 4 //path numbers
 
-#define CHANNEL_MAX_NUMBER		14	/*  14 is the max chnl number */
+#define CHANNEL_MAX_NUMBER		14	// 14 is the max channel number
-#define MAX_CHNL_GROUP_24G		6	/*  ch1~2, ch3~5, ch6~8,
+#define MAX_CHNL_GROUP_24G		6	// ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total six groups
-						 *ch9~11, ch12~13, CH 14
+#define CHANNEL_GROUP_MAX_88E    	6
-						 * total three groups */
-#define CHANNEL_GROUP_MAX_88E		6
 
-enum wireless_mode {
+typedef enum _WIRELESS_MODE {
 	WIRELESS_MODE_UNKNOWN = 0x00,
-	WIRELESS_MODE_A			= BIT2,
+	WIRELESS_MODE_A 		= BIT2,
-	WIRELESS_MODE_B			= BIT0,
+	WIRELESS_MODE_B 		= BIT0,
-	WIRELESS_MODE_G			= BIT1,
+	WIRELESS_MODE_G 		= BIT1,
-	WIRELESS_MODE_AUTO		= BIT5,
+	WIRELESS_MODE_AUTO 	= BIT5,
-	WIRELESS_MODE_N_24G		= BIT3,
+	WIRELESS_MODE_N_24G 	= BIT3,
-	WIRELESS_MODE_N_5G		= BIT4,
+	WIRELESS_MODE_N_5G 	= BIT4,
 	WIRELESS_MODE_AC		= BIT6
-};
+} WIRELESS_MODE;
 
-enum phy_rate_tx_offset_area {
+
+typedef enum _PHY_Rate_Tx_Power_Offset_Area{
 	RA_OFFSET_LEGACY_OFDM1,
 	RA_OFFSET_LEGACY_OFDM2,
 	RA_OFFSET_HT_OFDM1,
@@ -101,170 +110,320 @@ enum phy_rate_tx_offset_area {
 	RA_OFFSET_HT_OFDM3,
 	RA_OFFSET_HT_OFDM4,
 	RA_OFFSET_HT_CCK,
-};
+}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
+
 
 /* BB/RF related */
-enum RF_TYPE_8190P {
+typedef	enum _RF_TYPE_8190P{
-	RF_TYPE_MIN,		/*  0 */
+	RF_TYPE_MIN,	// 0
-	RF_8225 = 1,		/*  1 11b/g RF for verification only */
+	RF_8225=1,			// 1 11b/g RF for verification only
-	RF_8256 = 2,		/*  2 11b/g/n */
+	RF_8256=2,			// 2 11b/g/n 
-	RF_8258 = 3,		/*  3 11a/b/g/n RF */
+	RF_8258=3,			// 3 11a/b/g/n RF
-	RF_6052 = 4,		/*  4 11b/g/n RF */
+	RF_6052=4,		// 4 11b/g/n RF
-	/*  TODO: We should remove this psudo PHY RF after we get new RF. */
+	//RF_6052=5,		// 4 11b/g/n RF
-	RF_PSEUDO_11N = 5,	/*  5, It is a temporality RF. */
+	// TODO: We sholud remove this psudo PHY RF after we get new RF.
-};
+	RF_PSEUDO_11N=5,	// 5, It is a temporality RF. 
+}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
 
-struct bb_reg_def {
-	u32 rfintfs;		/*  set software control: */
-				/*	0x870~0x877[8 bytes] */
-	u32 rfintfi;		/*  readback data: */
-				/*	0x8e0~0x8e7[8 bytes] */
-	u32 rfintfo;		/*  output data: */
-				/*	0x860~0x86f [16 bytes] */
-	u32 rfintfe;		/*  output enable: */
-				/*	0x860~0x86f [16 bytes] */
-	u32 rf3wireOffset;	/*  LSSI data: */
-				/*	0x840~0x84f [16 bytes] */
-	u32 rfLSSI_Select;	/*  BB Band Select: */
-				/*	0x878~0x87f [8 bytes] */
-	u32 rfTxGainStage;	/*  Tx gain stage: */
-				/*	0x80c~0x80f [4 bytes] */
-	u32 rfHSSIPara1;	/*  wire parameter control1 : */
-				/*	0x820~0x823,0x828~0x82b,
-				 *	0x830~0x833, 0x838~0x83b [16 bytes] */
-	u32 rfHSSIPara2;	/*  wire parameter control2 : */
-				/*	0x824~0x827,0x82c~0x82f, 0x834~0x837,
-				 *	0x83c~0x83f [16 bytes] */
-	u32 rfSwitchControl;	/* Tx Rx antenna control : */
-				/*	0x858~0x85f [16 bytes] */
-	u32 rfAGCControl1;	/* AGC parameter control1 : */
-				/*	0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
-				 * 0xc68~0xc6b [16 bytes] */
-	u32 rfAGCControl2;	/* AGC parameter control2 : */
-				/*	0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
-				 *	0xc6c~0xc6f [16 bytes] */
-	u32 rfRxIQImbalance;	/* OFDM Rx IQ imbalance matrix : */
-				/*	0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
-				 *	0xc2c~0xc2f [16 bytes] */
-	u32 rfRxAFE;		/* Rx IQ DC ofset and Rx digital filter,
-				 * Rx DC notch filter : */
-				/*	0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
-				 *	0xc28~0xc2b [16 bytes] */
-	u32 rfTxIQImbalance;	/* OFDM Tx IQ imbalance matrix */
-				/*	0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
-				 *	 0xc98~0xc9b [16 bytes] */
-	u32 rfTxAFE;		/* Tx IQ DC Offset and Tx DFIR type */
-				/*	0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
-				 *	0xc9c~0xc9f [16 bytes] */
-	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */
-				/*	0x8a0~0x8af [16 bytes] */
-	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for
-				 * Path A and B */
-};
 
-struct ant_sel_ofdm {
+typedef struct _BB_REGISTER_DEFINITION{
-	u32 r_tx_antenna:4;
+	u32 rfintfs;			// set software control: 
-	u32 r_ant_l:4;
+							//		0x870~0x877[8 bytes]
-	u32 r_ant_non_ht:4;
-	u32 r_ant_ht1:4;
-	u32 r_ant_ht2:4;
-	u32 r_ant_ht_s1:4;
-	u32 r_ant_non_ht_s1:4;
-	u32 OFDM_TXSC:2;
-	u32 reserved:2;
-};
 							
-struct ant_sel_cck {
+	u32 rfintfi;			// readback data: 
-	u8 r_cckrx_enable_2:2;
+							//		0x8e0~0x8e7[8 bytes]
-	u8 r_cckrx_enable:2;
+							
-	u8 r_ccktx_enable:4;
+	u32 rfintfo; 		// output data: 
-};
+							//		0x860~0x86f [16 bytes]
+							
+	u32 rfintfe; 		// output enable: 
+							//		0x860~0x86f [16 bytes]
+							
+	u32 rf3wireOffset;	// LSSI data:
+							//		0x840~0x84f [16 bytes]
+							
+	u32 rfLSSI_Select;	// BB Band Select: 
+							//		0x878~0x87f [8 bytes]
+							
+	u32 rfTxGainStage;	// Tx gain stage: 
+							//		0x80c~0x80f [4 bytes]
+							
+	u32 rfHSSIPara1; 	// wire parameter control1 : 
+							//		0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
+							
+	u32 rfHSSIPara2; 	// wire parameter control2 : 
+							//		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
+								
+	u32 rfSwitchControl; //Tx Rx antenna control : 
+							//		0x858~0x85f [16 bytes]
+								
+	u32 rfAGCControl1; 	//AGC parameter control1 : 
+							//		0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] 
+								
+	u32 rfAGCControl2; 	//AGC parameter control2 : 
+							//		0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] 
+							
+	u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : 
+							//		0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
+							
+	u32 rfRxAFE;  		//Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : 
+							//		0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
+							
+	u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
+							//		0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
+							
+	u32 rfTxAFE; 		//Tx IQ DC Offset and Tx DFIR type
+							//		0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
+								
+	u32 rfLSSIReadBack; 	//LSSI RF readback data SI mode
+								//		0x8a0~0x8af [16 bytes]
+
+	u32 rfLSSIReadBackPi; 	//LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
+
+}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
+
+typedef struct _R_ANTENNA_SELECT_OFDM{	
+	u32			r_tx_antenna:4;	
+	u32			r_ant_l:4;
+	u32			r_ant_non_ht:4;	
+	u32			r_ant_ht1:4;
+	u32			r_ant_ht2:4;
+	u32			r_ant_ht_s1:4;
+	u32			r_ant_non_ht_s1:4;
+	u32			OFDM_TXSC:2;
+	u32			Reserved:2;
+}R_ANTENNA_SELECT_OFDM;
+
+typedef struct _R_ANTENNA_SELECT_CCK{
+	u8			r_cckrx_enable_2:2;	
+	u8			r_cckrx_enable:2;
+	u8			r_ccktx_enable:4;
+}R_ANTENNA_SELECT_CCK;
 
 /*------------------------------Define structure----------------------------*/ 
 
+
 /*------------------------Export global variable----------------------------*/
 /*------------------------Export global variable----------------------------*/
 
+
 /*------------------------Export Marco Definition---------------------------*/
 /*------------------------Export Marco Definition---------------------------*/
 
+
 /*--------------------------Exported Function prototype---------------------*/
-/*  */
+//
-/*  BB and RF register read/write */
+// BB and RF register read/write
-/*  */
+//
-u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
+u32	rtl8188e_PHY_QueryBBReg(	IN	PADAPTER	Adapter,
-void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
+								IN	u32		RegAddr,
-			   u32 mask, u32 data);
+								IN	u32		BitMask	);
-u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
+void	rtl8188e_PHY_SetBBReg(	IN	PADAPTER	Adapter,
-			    u32 regaddr, u32 mask);
+								IN	u32		RegAddr,
-void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
+								IN	u32		BitMask,
-			   u32 regaddr, u32 mask, u32 data);
+								IN	u32		Data	);
+u32	rtl8188e_PHY_QueryRFReg(	IN	PADAPTER			Adapter,
+								IN	RF_RADIO_PATH_E	eRFPath,
+								IN	u32				RegAddr,
+								IN	u32				BitMask	);
+void	rtl8188e_PHY_SetRFReg(	IN	PADAPTER			Adapter,
+								IN	RF_RADIO_PATH_E	eRFPath,
+								IN	u32				RegAddr,
+								IN	u32				BitMask,
+								IN	u32				Data	);
 
-/*  Initialization related function */
+//
+// Initialization related function
+//
 /* MAC/BB/RF HAL config */
-int PHY_MACConfig8188E(struct adapter *adapter);
+int	PHY_MACConfig8188E(IN	PADAPTER	Adapter	);
-int PHY_BBConfig8188E(struct adapter *adapter);
+int	PHY_BBConfig8188E(IN	PADAPTER	Adapter	);
-int PHY_RFConfig8188E(struct adapter *adapter);
+int	PHY_RFConfig8188E(IN	PADAPTER	Adapter	);
 
 /* RF config */
-int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *adapter, u8 *filename,
+int	rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath);
-				      enum rf_radio_path rfpath);
+int	rtl8188e_PHY_ConfigRFWithHeaderFile(	IN	PADAPTER			Adapter,
-int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *adapter,
+													IN	RF_RADIO_PATH_E		eRFPath);
-					enum rf_radio_path rfpath);
 
 /* Read initi reg value for tx power setting. */
-void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
+void	rtl8192c_PHY_GetHWRegOriginalValue(	IN	PADAPTER		Adapter	);
 
-/*  BB TX Power R/W */
+//
-void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
+// RF Power setting
-void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
+//
-bool PHY_UpdateTxPowerDbm8188E(struct adapter *adapter, int power);
+//extern	BOOLEAN	PHY_SetRFPowerState(IN	PADAPTER			Adapter, 
+//									IN	RT_RF_POWER_STATE	eRFPowerState);
 
-void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
+//
+// BB TX Power R/W
+//
+void	PHY_GetTxPowerLevel8188E(	IN	PADAPTER		Adapter,
+											OUT u32*    		powerlevel	);
+void	PHY_SetTxPowerLevel8188E(	IN	PADAPTER		Adapter,
+											IN	u8			channel	);
+BOOLEAN	PHY_UpdateTxPowerDbm8188E(	IN	PADAPTER	Adapter,
+											IN	int		powerInDbm	);
 
-/*  Switch bandwidth for 8192S */
+//
-void PHY_SetBWMode8188E(struct adapter *adapter,
+VOID 
-			enum ht_channel_width chnlwidth, unsigned char offset);
+PHY_ScanOperationBackup8188E(IN	PADAPTER	Adapter,
+										IN	u8		Operation	);
 
-/*  channel switch related funciton */
+//
-void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
+// Switch bandwidth for 8192S
-/*  Call after initialization */
+//
-void ChkFwCmdIoDone(struct adapter *adapter);
+//extern	void	PHY_SetBWModeCallback8192C(	IN	PRT_TIMER		pTimer	);
+void	PHY_SetBWMode8188E(	IN	PADAPTER			pAdapter,
+									IN	HT_CHANNEL_WIDTH	ChnlWidth,
+									IN	unsigned char	Offset	);
 
-/*  BB/MAC/RF other monitor API */
+//
-void PHY_SetRFPathSwitch_8188E(struct adapter *adapter,	bool main);
+// Set FW CMD IO for 8192S.
+//
+//extern	BOOLEAN HalSetIO8192C(	IN	PADAPTER			Adapter,
+//									IN	IO_TYPE				IOType);
 
-void PHY_SwitchEphyParameter(struct adapter *adapter);
+//
+// Set A2 entry to fw for 8192S
+//
+extern	void FillA2Entry8192C(		IN	PADAPTER			Adapter,
+										IN	u8				index,
+										IN	u8*				val);
 
-void PHY_EnableHostClkReq(struct adapter *adapter);
 
-bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
+//
+// channel switch related funciton
+//
+//extern	void	PHY_SwChnlCallback8192C(	IN	PRT_TIMER		pTimer	);
+void	PHY_SwChnl8188E(	IN	PADAPTER		pAdapter,
+									IN	u8			channel	);
+				// Call after initialization
+void	PHY_SwChnlPhy8192C(	IN	PADAPTER		pAdapter,
+									IN	u8			channel	);
 
-void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
+void ChkFwCmdIoDone(	IN	PADAPTER	Adapter);
-				 u32 mask, u32 data);
+
+//
+// BB/MAC/RF other monitor API
+//
+void	PHY_SetMonitorMode8192C(IN	PADAPTER	pAdapter,
+										IN	BOOLEAN		bEnableMonitorMode	);
+
+BOOLEAN	PHY_CheckIsLegalRfPath8192C(IN	PADAPTER	pAdapter,
+											IN	u32		eRFPath	);
+
+VOID PHY_SetRFPathSwitch_8188E(IN	PADAPTER	pAdapter, IN	BOOLEAN		bMain);
+
+extern	VOID
+PHY_SwitchEphyParameter(
+	IN	PADAPTER			Adapter
+	);
+
+extern	VOID
+PHY_EnableHostClkReq(
+	IN	PADAPTER			Adapter
+	);
+
+BOOLEAN
+SetAntennaConfig92C(
+	IN	PADAPTER	Adapter,
+	IN	u8		DefaultAnt	
+	);
+
+#ifdef CONFIG_PHY_SETTING_WITH_ODM
+VOID
+storePwrIndexDiffRateOffset(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+	);
+#endif //CONFIG_PHY_SETTING_WITH_ODM
 /*--------------------------Exported Function prototype---------------------*/
 
-#define PHY_QueryBBReg(adapt, regaddr, mask)			\
+#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8188e_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
-	 rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask))
+#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8188e_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
-#define PHY_SetBBReg(adapt, regaddr, bitmask, data)		\
+#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8188e_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
-	 rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data))
+#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8188e_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
-#define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask)	\
-	rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask))
-#define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data)	\
-	rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data))
 
 #define PHY_SetMacReg	PHY_SetBBReg
+#define PHY_QueryMacReg PHY_QueryBBReg
+
+
+//
+// Initialization related function
+//
+/* MAC/BB/RF HAL config */
+//extern s32 PHY_MACConfig8723(PADAPTER padapter);
+//s32 PHY_BBConfig8723(PADAPTER padapter);
+//s32 PHY_RFConfig8723(PADAPTER padapter);
+
+
+
+//==================================================================
+// Note: If SIC_ENABLE under PCIE, because of the slow operation
+//	you should 
+//	2) "#define RTL8723_FPGA_VERIFICATION	1"				in Precomp.h.WlanE.Windows
+//	3) "#define RTL8190_Download_Firmware_From_Header	0"	in Precomp.h.WlanE.Windows if needed.
+//
+#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
+#define	SIC_ENABLE				1
+#define	SIC_HW_SUPPORT		1
+#else
+#define	SIC_ENABLE				0
+#define	SIC_HW_SUPPORT		0
+#endif
+//==================================================================
 
-#define	SIC_HW_SUPPORT			0
 
 #define	SIC_MAX_POLL_CNT		5
 
+#if(SIC_HW_SUPPORT == 1)
+#define	SIC_CMD_READY			0
+#define	SIC_CMD_PREWRITE		0x1
+#if(RTL8188E_SUPPORT == 1)
+#define	SIC_CMD_WRITE			0x40
+#define	SIC_CMD_PREREAD		0x2
+#define	SIC_CMD_READ			0x80
+#define	SIC_CMD_INIT			0xf0
+#define	SIC_INIT_VAL			0xff
+
+#define	SIC_INIT_REG			0x1b7
+#define	SIC_CMD_REG			0x1EB		// 1byte
+#define	SIC_ADDR_REG			0x1E8		// 1b4~1b5, 2 bytes
+#define	SIC_DATA_REG			0x1EC		// 1b0~1b3
+#else
+#define	SIC_CMD_WRITE			0x11
+#define	SIC_CMD_PREREAD		0x2
+#define	SIC_CMD_READ			0x12
+#define	SIC_CMD_INIT			0x1f
+#define	SIC_INIT_VAL			0xff
+
+#define	SIC_INIT_REG			0x1b7
+#define	SIC_CMD_REG			0x1b6		// 1byte
+#define	SIC_ADDR_REG			0x1b4		// 1b4~1b5, 2 bytes
+#define	SIC_DATA_REG			0x1b0		// 1b0~1b3
+#endif
+#else
 #define	SIC_CMD_READY			0
 #define	SIC_CMD_WRITE			1
 #define	SIC_CMD_READ			2
 
-#define	SIC_CMD_REG			0x1EB		/*  1byte */
+#if(RTL8188E_SUPPORT == 1)
-#define	SIC_ADDR_REG			0x1E8		/*  1b9~1ba, 2 bytes */
+#define	SIC_CMD_REG			0x1EB		// 1byte
-#define	SIC_DATA_REG			0x1EC		/*  1bc~1bf */
+#define	SIC_ADDR_REG			0x1E8		// 1b9~1ba, 2 bytes
+#define	SIC_DATA_REG			0x1EC		// 1bc~1bf
+#else
+#define	SIC_CMD_REG			0x1b8		// 1byte
+#define	SIC_ADDR_REG			0x1b9		// 1b9~1ba, 2 bytes
+#define	SIC_DATA_REG			0x1bc		// 1bc~1bf
+#endif
+#endif
+
+#if(SIC_ENABLE == 1)
+VOID SIC_Init(IN PADAPTER Adapter);
+#endif
+
+
+#endif	// __INC_HAL8192CPHYCFG_H
 
-#endif	/*  __INC_HAL8192CPHYCFG_H */

include/Hal8188EPwrSeq.h

@@ -53,121 +53,125 @@
 #define	RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS	10
 #define	RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS	10
 #define	RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS	10
-#define	RTL8188E_TRANS_ACT_TO_LPS_STEPS		15
+#define	RTL8188E_TRANS_ACT_TO_LPS_STEPS	15
-#define	RTL8188E_TRANS_LPS_TO_ACT_STEPS		15
+#define	RTL8188E_TRANS_LPS_TO_ACT_STEPS	15	
-#define	RTL8188E_TRANS_END_STEPS		1
+#define	RTL8188E_TRANS_END_STEPS	1
 
-#define RTL8188E_TRANS_CARDEMU_TO_ACT														\
+
+#define RTL8188E_TRANS_CARDEMU_TO_ACT 														\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0	reset BB*/			\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0	reset BB*/			\
-	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
+	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/	\
-	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/	\
-	{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/	\
+	{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/	\
 
 #define RTL8188E_TRANS_ACT_TO_CARDEMU													\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
 
 #define RTL8188E_TRANS_CARDEMU_TO_SUS													\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/				\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/	\
-	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
-	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
-	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
+	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
 
 #define RTL8188E_TRANS_SUS_TO_CARDEMU													\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/							\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
 
 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS													\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },  comments here*/							\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
+	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
-	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
-	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
+	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
 
 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU													\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
 
 #define RTL8188E_TRANS_CARDEMU_TO_PDN												\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/							\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
 
 #define RTL8188E_TRANS_PDN_TO_CARDEMU												\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },  comments here					 */ \
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
 
-/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
+//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step
 #define RTL8188E_TRANS_ACT_TO_LPS														\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here				*/   \
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\
-	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
-	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
 
 #define RTL8188E_TRANS_LPS_TO_ACT															\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here				 */ \
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
  
 #define RTL8188E_TRANS_END															\
 	/* format */																\
-	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },  comments here*/					\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0, PWR_CMD_END, 0, 0}, /*  */
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
 
-extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
-extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
 
-#endif /* __HAL8188EPWRSEQ_H__ */
+extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
+
+#endif //__HAL8188EPWRSEQ_H__
+

include/Hal8192CPhyCfg.h

@@ -0,0 +1,396 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+/*****************************************************************************
+ * Module:	__INC_HAL8192CPHYCFG_H
+ *
+ *
+ * Note:	
+ *			
+ *
+ * Export:	Constants, macro, functions(API), global variables(None).
+ *
+ * Abbrev:	
+ *
+ * History:
+ *		Data		Who		Remark 
+ *      08/07/2007  MHC    	1. Porting from 9x series PHYCFG.h.
+ *							2. Reorganize code architecture.
+ * 
+ *****************************************************************************/
+ /* Check to see if the file has been included already.  */
+#ifndef __INC_HAL8192CPHYCFG_H
+#define __INC_HAL8192CPHYCFG_H
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		//us
+#define AntennaDiversityValue	0x80	//(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+
+#ifdef CONFIG_PCI_HCI
+#define MAX_AGGR_NUM	0x0A0A
+#else
+#define MAX_AGGR_NUM	0x0909
+#endif
+
+#ifdef CONFIG_PCI_HCI
+#define	SET_RTL8192SE_RF_SLEEP(_pAdapter)							\
+{																	\
+	u1Byte		u1bTmp;												\
+	u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL);		\
+	u1bTmp |= BIT0;													\
+	PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp);		\
+	PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0);				\
+	PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF);				\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);				\
+	delay_us(100);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);				\
+	PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0);				\
+	delay_us(10);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC);				\
+	delay_us(10);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);				\
+	delay_us(10);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);				\
+}
+#endif
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/ 
+typedef enum _SwChnlCmdID{
+	CmdID_End,
+	CmdID_SetTxPowerLevel,
+	CmdID_BBRegWrite10,
+	CmdID_WritePortUlong,
+	CmdID_WritePortUshort,
+	CmdID_WritePortUchar,
+	CmdID_RF_WriteReg,
+}SwChnlCmdID;
+
+
+/* 1. Switch channel related */
+typedef struct _SwChnlCmd{
+	SwChnlCmdID	CmdID;
+	u32			Para1;
+	u32			Para2;
+	u32			msDelay;
+}SwChnlCmd;
+
+typedef enum _HW90_BLOCK{
+	HW90_BLOCK_MAC = 0,
+	HW90_BLOCK_PHY0 = 1,
+	HW90_BLOCK_PHY1 = 2,
+	HW90_BLOCK_RF = 3,
+	HW90_BLOCK_MAXIMUM = 4, // Never use this
+}HW90_BLOCK_E, *PHW90_BLOCK_E;
+
+typedef enum _RF_RADIO_PATH{
+	RF_PATH_A = 0,			//Radio Path A
+	RF_PATH_B = 1,			//Radio Path B
+	RF_PATH_C = 2,			//Radio Path C
+	RF_PATH_D = 3,			//Radio Path D
+	//RF_PATH_MAX				//Max RF number 90 support 
+}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
+
+#define	RF_PATH_MAX			2
+
+#define CHANNEL_MAX_NUMBER		14	// 14 is the max channel number
+#define CHANNEL_GROUP_MAX		3	// ch1~3, ch4~9, ch10~14 total three groups
+
+typedef enum _WIRELESS_MODE {
+	WIRELESS_MODE_UNKNOWN = 0x00,
+	WIRELESS_MODE_A 		= BIT2,
+	WIRELESS_MODE_B 		= BIT0,
+	WIRELESS_MODE_G 		= BIT1,
+	WIRELESS_MODE_AUTO 	= BIT5,
+	WIRELESS_MODE_N_24G 	= BIT3,
+	WIRELESS_MODE_N_5G 	= BIT4,
+	WIRELESS_MODE_AC		= BIT6
+} WIRELESS_MODE;
+
+typedef enum _BaseBand_Config_Type{
+	BaseBand_Config_PHY_REG = 0,			//Radio Path A
+	BaseBand_Config_AGC_TAB = 1,			//Radio Path B
+}BaseBand_Config_Type, *PBaseBand_Config_Type;
+
+
+typedef enum _PHY_Rate_Tx_Power_Offset_Area{
+	RA_OFFSET_LEGACY_OFDM1,
+	RA_OFFSET_LEGACY_OFDM2,
+	RA_OFFSET_HT_OFDM1,
+	RA_OFFSET_HT_OFDM2,
+	RA_OFFSET_HT_OFDM3,
+	RA_OFFSET_HT_OFDM4,
+	RA_OFFSET_HT_CCK,
+}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
+
+
+/* BB/RF related */
+typedef	enum _RF_TYPE_8190P{
+	RF_TYPE_MIN,	// 0
+	RF_8225=1,			// 1 11b/g RF for verification only
+	RF_8256=2,			// 2 11b/g/n 
+	RF_8258=3,			// 3 11a/b/g/n RF
+	RF_6052=4,		// 4 11b/g/n RF
+	//RF_6052=5,		// 4 11b/g/n RF
+	// TODO: We sholud remove this psudo PHY RF after we get new RF.
+	RF_PSEUDO_11N=5,	// 5, It is a temporality RF. 
+}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
+
+
+typedef struct _BB_REGISTER_DEFINITION{
+	u32 rfintfs;			// set software control: 
+							//		0x870~0x877[8 bytes]
+							
+	u32 rfintfi;			// readback data: 
+							//		0x8e0~0x8e7[8 bytes]
+							
+	u32 rfintfo; 		// output data: 
+							//		0x860~0x86f [16 bytes]
+							
+	u32 rfintfe; 		// output enable: 
+							//		0x860~0x86f [16 bytes]
+							
+	u32 rf3wireOffset;	// LSSI data:
+							//		0x840~0x84f [16 bytes]
+							
+	u32 rfLSSI_Select;	// BB Band Select: 
+							//		0x878~0x87f [8 bytes]
+							
+	u32 rfTxGainStage;	// Tx gain stage: 
+							//		0x80c~0x80f [4 bytes]
+							
+	u32 rfHSSIPara1; 	// wire parameter control1 : 
+							//		0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
+							
+	u32 rfHSSIPara2; 	// wire parameter control2 : 
+							//		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
+								
+	u32 rfSwitchControl; //Tx Rx antenna control : 
+							//		0x858~0x85f [16 bytes]
+								
+	u32 rfAGCControl1; 	//AGC parameter control1 : 
+							//		0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] 
+								
+	u32 rfAGCControl2; 	//AGC parameter control2 : 
+							//		0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] 
+							
+	u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : 
+							//		0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
+							
+	u32 rfRxAFE;  		//Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : 
+							//		0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
+							
+	u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
+							//		0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
+							
+	u32 rfTxAFE; 		//Tx IQ DC Offset and Tx DFIR type
+							//		0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
+								
+	u32 rfLSSIReadBack; 	//LSSI RF readback data SI mode
+								//		0x8a0~0x8af [16 bytes]
+
+	u32 rfLSSIReadBackPi; 	//LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
+
+}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
+
+typedef struct _R_ANTENNA_SELECT_OFDM{	
+	u32			r_tx_antenna:4;	
+	u32			r_ant_l:4;
+	u32			r_ant_non_ht:4;	
+	u32			r_ant_ht1:4;
+	u32			r_ant_ht2:4;
+	u32			r_ant_ht_s1:4;
+	u32			r_ant_non_ht_s1:4;
+	u32			OFDM_TXSC:2;
+	u32			Reserved:2;
+}R_ANTENNA_SELECT_OFDM;
+
+typedef struct _R_ANTENNA_SELECT_CCK{
+	u8			r_cckrx_enable_2:2;	
+	u8			r_cckrx_enable:2;
+	u8			r_ccktx_enable:4;
+}R_ANTENNA_SELECT_CCK;
+
+/*------------------------------Define structure----------------------------*/ 
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+//
+// BB and RF register read/write
+//
+u32	rtl8192c_PHY_QueryBBReg(	IN	PADAPTER	Adapter,
+								IN	u32		RegAddr,
+								IN	u32		BitMask	);
+void	rtl8192c_PHY_SetBBReg(	IN	PADAPTER	Adapter,
+								IN	u32		RegAddr,
+								IN	u32		BitMask,
+								IN	u32		Data	);
+u32	rtl8192c_PHY_QueryRFReg(	IN	PADAPTER			Adapter,
+								IN	RF_RADIO_PATH_E	eRFPath,
+								IN	u32				RegAddr,
+								IN	u32				BitMask	);
+void	rtl8192c_PHY_SetRFReg(	IN	PADAPTER			Adapter,
+								IN	RF_RADIO_PATH_E	eRFPath,
+								IN	u32				RegAddr,
+								IN	u32				BitMask,
+								IN	u32				Data	);
+
+//
+// Initialization related function
+//
+/* MAC/BB/RF HAL config */
+int	PHY_MACConfig8192C(	IN	PADAPTER	Adapter	);
+int	PHY_BBConfig8192C(	IN	PADAPTER	Adapter	);
+int	PHY_RFConfig8192C(	IN	PADAPTER	Adapter	);
+/* RF config */
+int	rtl8192c_PHY_ConfigRFWithParaFile(	IN	PADAPTER	Adapter,
+												IN	u8* 	pFileName,
+												IN	RF_RADIO_PATH_E	eRFPath);
+int	rtl8192c_PHY_ConfigRFWithHeaderFile(	IN	PADAPTER			Adapter,
+												IN	RF_RADIO_PATH_E	eRFPath);
+
+/* BB/RF readback check for making sure init OK */
+int	rtl8192c_PHY_CheckBBAndRFOK(	IN	PADAPTER			Adapter,
+										IN	HW90_BLOCK_E		CheckBlock,
+										IN	RF_RADIO_PATH_E	eRFPath	  );
+/* Read initi reg value for tx power setting. */
+void	rtl8192c_PHY_GetHWRegOriginalValue(	IN	PADAPTER		Adapter	);
+
+//
+// RF Power setting
+//
+//extern	BOOLEAN	PHY_SetRFPowerState(IN	PADAPTER			Adapter, 
+//									IN	RT_RF_POWER_STATE	eRFPowerState);
+
+//
+// BB TX Power R/W
+//
+void	PHY_GetTxPowerLevel8192C(	IN	PADAPTER		Adapter,
+											OUT u32*    		powerlevel	);
+void	PHY_SetTxPowerLevel8192C(	IN	PADAPTER		Adapter,
+											IN	u8			channel	);
+BOOLEAN	PHY_UpdateTxPowerDbm8192C(	IN	PADAPTER	Adapter,
+											IN	int		powerInDbm	);
+
+//
+VOID 
+PHY_ScanOperationBackup8192C(IN	PADAPTER	Adapter,
+										IN	u8		Operation	);
+
+//
+// Switch bandwidth for 8192S
+//
+//extern	void	PHY_SetBWModeCallback8192C(	IN	PRT_TIMER		pTimer	);
+void	PHY_SetBWMode8192C(	IN	PADAPTER			pAdapter,
+									IN	HT_CHANNEL_WIDTH	ChnlWidth,
+									IN	unsigned char	Offset	);
+
+//
+// Set FW CMD IO for 8192S.
+//
+//extern	BOOLEAN HalSetIO8192C(	IN	PADAPTER			Adapter,
+//									IN	IO_TYPE				IOType);
+
+//
+// Set A2 entry to fw for 8192S
+//
+extern	void FillA2Entry8192C(		IN	PADAPTER			Adapter,
+										IN	u8				index,
+										IN	u8*				val);
+
+
+//
+// channel switch related funciton
+//
+//extern	void	PHY_SwChnlCallback8192C(	IN	PRT_TIMER		pTimer	);
+void	PHY_SwChnl8192C(	IN	PADAPTER		pAdapter,
+									IN	u8			channel	);
+				// Call after initialization
+void	PHY_SwChnlPhy8192C(	IN	PADAPTER		pAdapter,
+									IN	u8			channel	);
+
+void ChkFwCmdIoDone(	IN	PADAPTER	Adapter);
+				
+//
+// BB/MAC/RF other monitor API
+//
+void	PHY_SetMonitorMode8192C(IN	PADAPTER	pAdapter,
+										IN	BOOLEAN		bEnableMonitorMode	);
+
+BOOLEAN	PHY_CheckIsLegalRfPath8192C(IN	PADAPTER	pAdapter,
+											IN	u32		eRFPath	);
+
+
+VOID rtl8192c_PHY_SetRFPathSwitch(IN	PADAPTER	pAdapter, IN	BOOLEAN		bMain);
+
+//
+// Modify the value of the hw register when beacon interval be changed.
+//
+void	
+rtl8192c_PHY_SetBeaconHwReg(	IN	PADAPTER		Adapter,
+					IN	u16			BeaconInterval	);
+
+
+extern	VOID
+PHY_SwitchEphyParameter(
+	IN	PADAPTER			Adapter
+	);
+
+extern	VOID
+PHY_EnableHostClkReq(
+	IN	PADAPTER			Adapter
+	);
+
+BOOLEAN
+SetAntennaConfig92C(
+	IN	PADAPTER	Adapter,
+	IN	u8		DefaultAnt	
+	);
+
+#ifdef RTL8192C_RECONFIG_TO_1T1R
+extern void	PHY_Reconfig_To_1T1R(_adapter *padapter);
+#endif
+/*--------------------------Exported Function prototype---------------------*/
+
+#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
+#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
+#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
+#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
+
+#define PHY_SetMacReg	PHY_SetBBReg
+#define PHY_QueryMacReg	PHY_QueryBBReg
+
+#endif	// __INC_HAL8192CPHYCFG_H
+

include/Hal8192DPhyCfg.h

@@ -0,0 +1,487 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+/*****************************************************************************
+ *
+ * Module:	__INC_HAL8192DPHYCFG_H
+ *
+ *
+ * Note:	
+ *			
+ *
+ * Export:	Constants, macro, functions(API), global variables(None).
+ *
+ * Abbrev:	
+ *
+ * History:
+ *		Data		Who		Remark 
+ *      08/07/2007  MHC    	1. Porting from 9x series PHYCFG.h.
+ *							2. Reorganize code architecture.
+ * 
+ *****************************************************************************/
+ /* Check to see if the file has been included already.  */
+#ifndef __INC_HAL8192DPHYCFG_H
+#define __INC_HAL8192DPHYCFG_H
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		//us
+#define AntennaDiversityValue	0x80	//(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+
+#ifdef CONFIG_PCI_HCI
+#define	SET_RTL8192SE_RF_SLEEP(_pAdapter)							\
+{																	\
+	u1Byte		u1bTmp;												\
+	u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL);		\
+	u1bTmp |= BIT0;													\
+	PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp);		\
+	PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0);				\
+	PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF);				\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);				\
+	delay_us(100);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);				\
+	PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0);				\
+	delay_us(10);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC);				\
+	delay_us(10);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);				\
+	delay_us(10);													\
+	PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);				\
+}
+#endif
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/ 
+typedef enum _SwChnlCmdID{
+	CmdID_End,
+	CmdID_SetTxPowerLevel,
+	CmdID_BBRegWrite10,
+	CmdID_WritePortUlong,
+	CmdID_WritePortUshort,
+	CmdID_WritePortUchar,
+	CmdID_RF_WriteReg,
+}SwChnlCmdID;
+
+
+/* 1. Switch channel related */
+typedef struct _SwChnlCmd{
+	SwChnlCmdID	CmdID;
+	u32			Para1;
+	u32			Para2;
+	u32			msDelay;
+}SwChnlCmd;
+
+typedef enum _HW90_BLOCK{
+	HW90_BLOCK_MAC = 0,
+	HW90_BLOCK_PHY0 = 1,
+	HW90_BLOCK_PHY1 = 2,
+	HW90_BLOCK_RF = 3,
+	HW90_BLOCK_MAXIMUM = 4, // Never use this
+}HW90_BLOCK_E, *PHW90_BLOCK_E;
+
+//vivi added this for read parameter from header, 20100908
+typedef enum _RF_CONTENT{
+	radioa_txt = 0x1000,
+	radiob_txt = 0x1001,
+	radioc_txt = 0x1002,
+	radiod_txt = 0x1003
+} RF_CONTENT;
+
+typedef enum _RF_RADIO_PATH{
+	RF_PATH_A = 0,			//Radio Path A
+	RF_PATH_B = 1,			//Radio Path B
+	RF_PATH_C = 2,			//Radio Path C
+	RF_PATH_D = 3,			//Radio Path D
+	//RF_PATH_MAX				//Max RF number 90 support 
+}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
+
+#define	RF_PATH_MAX			2
+
+
+typedef enum _WIRELESS_MODE {
+	WIRELESS_MODE_UNKNOWN = 0x00,
+	WIRELESS_MODE_A = 0x01,
+	WIRELESS_MODE_B = 0x02,
+	WIRELESS_MODE_G = 0x04,
+	WIRELESS_MODE_AUTO = 0x08,
+	WIRELESS_MODE_N_24G = 0x10,
+	WIRELESS_MODE_N_5G = 0x20
+} WIRELESS_MODE;
+
+
+#if(TX_POWER_FOR_5G_BAND == 1)
+#define CHANNEL_MAX_NUMBER		14+24+21	// 14 is the max channel number
+#define CHANNEL_GROUP_MAX		3+9	// ch1~3, ch4~9, ch10~14 total three groups
+#define MAX_PG_GROUP 13
+#else
+#define CHANNEL_MAX_NUMBER		14	// 14 is the max channel number
+#define CHANNEL_GROUP_MAX		3	// ch1~3, ch4~9, ch10~14 total three groups
+#define MAX_PG_GROUP 7
+#endif
+#define	CHANNEL_GROUP_MAX_2G		3
+#define	CHANNEL_GROUP_IDX_5GL		3
+#define	CHANNEL_GROUP_IDX_5GM		6
+#define	CHANNEL_GROUP_IDX_5GH		9
+#define	CHANNEL_GROUP_MAX_5G		9
+#define	CHANNEL_MAX_NUMBER_2G		14
+
+#if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1)
+typedef enum _BaseBand_Config_Type{
+	BaseBand_Config_PHY_REG = 0,			
+	BaseBand_Config_AGC_TAB = 1,			
+	BaseBand_Config_AGC_TAB_2G = 2,
+	BaseBand_Config_AGC_TAB_5G = 3,
+}BaseBand_Config_Type, *PBaseBand_Config_Type;
+#else
+typedef enum _BaseBand_Config_Type{
+	BaseBand_Config_PHY_REG = 0,			//Radio Path A
+	BaseBand_Config_AGC_TAB = 1,			//Radio Path B
+}BaseBand_Config_Type, *PBaseBand_Config_Type;
+#endif
+
+
+typedef enum _MACPHY_MODE_8192D{
+	SINGLEMAC_SINGLEPHY,	//SMSP
+	DUALMAC_DUALPHY,		//DMDP
+	DUALMAC_SINGLEPHY,	//DMSP	
+}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
+
+typedef enum _MACPHY_MODE_CHANGE_ACTION{
+	DMDP2DMSP = 0,
+	DMSP2DMDP = 1,
+	DMDP2SMSP = 2,
+	SMSP2DMDP = 3,
+	DMSP2SMSP = 4,
+	SMSP2DMSP = 5,
+	MAXACTION
+}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
+
+typedef enum _BAND_TYPE{
+	BAND_ON_2_4G 	= 1,
+	BAND_ON_5G	= 2,
+	BAND_ON_BOTH,
+	BANDMAX
+}BAND_TYPE,*PBAND_TYPE;
+
+typedef enum _PHY_Rate_Tx_Power_Offset_Area{
+	RA_OFFSET_LEGACY_OFDM1,
+	RA_OFFSET_LEGACY_OFDM2,
+	RA_OFFSET_HT_OFDM1,
+	RA_OFFSET_HT_OFDM2,
+	RA_OFFSET_HT_OFDM3,
+	RA_OFFSET_HT_OFDM4,
+	RA_OFFSET_HT_CCK,
+}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
+
+
+/* BB/RF related */
+typedef	enum _RF_TYPE_8190P{
+	RF_TYPE_MIN,	// 0
+	RF_8225=1,			// 1 11b/g RF for verification only
+	RF_8256=2,			// 2 11b/g/n 
+	RF_8258=3,			// 3 11a/b/g/n RF
+	RF_6052=4,		// 4 11b/g/n RF
+	//RF_6052=5,		// 4 11b/g/n RF
+	// TODO: We sholud remove this psudo PHY RF after we get new RF.
+	RF_PSEUDO_11N=5,	// 5, It is a temporality RF. 
+}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
+
+
+
+typedef struct _BB_REGISTER_DEFINITION{
+	u32 rfintfs;			// set software control: 
+							//		0x870~0x877[8 bytes]
+							
+	u32 rfintfi;			// readback data: 
+							//		0x8e0~0x8e7[8 bytes]
+							
+	u32 rfintfo; 		// output data: 
+							//		0x860~0x86f [16 bytes]
+							
+	u32 rfintfe; 		// output enable: 
+							//		0x860~0x86f [16 bytes]
+							
+	u32 rf3wireOffset;	// LSSI data:
+							//		0x840~0x84f [16 bytes]
+							
+	u32 rfLSSI_Select;	// BB Band Select: 
+							//		0x878~0x87f [8 bytes]
+							
+	u32 rfTxGainStage;	// Tx gain stage: 
+							//		0x80c~0x80f [4 bytes]
+							
+	u32 rfHSSIPara1; 	// wire parameter control1 : 
+							//		0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
+							
+	u32 rfHSSIPara2; 	// wire parameter control2 : 
+							//		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
+								
+	u32 rfSwitchControl; //Tx Rx antenna control : 
+							//		0x858~0x85f [16 bytes]
+								
+	u32 rfAGCControl1; 	//AGC parameter control1 : 
+							//		0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] 
+								
+	u32 rfAGCControl2; 	//AGC parameter control2 : 
+							//		0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] 
+							
+	u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : 
+							//		0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
+							
+	u32 rfRxAFE;  		//Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : 
+							//		0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
+							
+	u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
+							//		0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
+							
+	u32 rfTxAFE; 		//Tx IQ DC Offset and Tx DFIR type
+							//		0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
+								
+	u32 rfLSSIReadBack; 	//LSSI RF readback data SI mode
+								//		0x8a0~0x8af [16 bytes]
+
+	u32 rfLSSIReadBackPi; 	//LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
+
+}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
+
+
+typedef struct _R_ANTENNA_SELECT_OFDM{	
+	u32			r_tx_antenna:4;	
+	u32			r_ant_l:4;
+	u32			r_ant_non_ht:4;	
+	u32			r_ant_ht1:4;
+	u32			r_ant_ht2:4;
+	u32			r_ant_ht_s1:4;
+	u32			r_ant_non_ht_s1:4;
+	u32			OFDM_TXSC:2;
+	u32			Reserved:2;
+}R_ANTENNA_SELECT_OFDM;
+
+typedef struct _R_ANTENNA_SELECT_CCK{
+	u8			r_cckrx_enable_2:2;	
+	u8			r_cckrx_enable:2;
+	u8			r_ccktx_enable:4;
+}R_ANTENNA_SELECT_CCK;
+
+/*------------------------------Define structure----------------------------*/ 
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+//
+// BB and RF register read/write
+//
+void	rtl8192d_PHY_SetBBReg1Byte(	IN	PADAPTER	Adapter,
+								IN	u32		RegAddr,
+								IN	u32		BitMask,
+								IN	u32		Data	);
+u32	rtl8192d_PHY_QueryBBReg(	IN	PADAPTER	Adapter,
+								IN	u32		RegAddr,
+								IN	u32		BitMask	);
+void	rtl8192d_PHY_SetBBReg(	IN	PADAPTER	Adapter,
+								IN	u32		RegAddr,
+								IN	u32		BitMask,
+								IN	u32		Data	);
+u32	rtl8192d_PHY_QueryRFReg(	IN	PADAPTER			Adapter,
+								IN	RF_RADIO_PATH_E	eRFPath,
+								IN	u32				RegAddr,
+								IN	u32				BitMask	);
+void	rtl8192d_PHY_SetRFReg(	IN	PADAPTER			Adapter,
+								IN	RF_RADIO_PATH_E	eRFPath,
+								IN	u32				RegAddr,
+								IN	u32				BitMask,
+								IN	u32				Data	);
+
+//
+// Initialization related function
+//
+/* MAC/BB/RF HAL config */
+extern	int	PHY_MACConfig8192D(	IN	PADAPTER	Adapter	);
+extern	int	PHY_BBConfig8192D(	IN	PADAPTER	Adapter	);
+extern	int	PHY_RFConfig8192D(	IN	PADAPTER	Adapter	);
+/* RF config */
+int	rtl8192d_PHY_ConfigRFWithParaFile(	IN	PADAPTER	Adapter,
+												IN	u8* 	pFileName,
+												IN	RF_RADIO_PATH_E	eRFPath);
+int	rtl8192d_PHY_ConfigRFWithHeaderFile(	IN	PADAPTER			Adapter,
+												IN	RF_CONTENT			Content,
+												IN	RF_RADIO_PATH_E	eRFPath);
+/* BB/RF readback check for making sure init OK */
+int	rtl8192d_PHY_CheckBBAndRFOK(	IN	PADAPTER			Adapter,
+										IN	HW90_BLOCK_E		CheckBlock,
+										IN	RF_RADIO_PATH_E	eRFPath	  );
+/* Read initi reg value for tx power setting. */
+void	rtl8192d_PHY_GetHWRegOriginalValue(	IN	PADAPTER		Adapter	);
+
+//
+// RF Power setting
+//
+//extern	BOOLEAN	PHY_SetRFPowerState(IN	PADAPTER			Adapter, 
+//									IN	RT_RF_POWER_STATE	eRFPowerState);
+
+//
+// BB TX Power R/W
+//
+void	PHY_GetTxPowerLevel8192D(	IN	PADAPTER		Adapter,
+											OUT u32*    		powerlevel	);
+void	PHY_SetTxPowerLevel8192D(	IN	PADAPTER		Adapter,
+											IN	u8			channel	);
+BOOLEAN	PHY_UpdateTxPowerDbm8192D(	IN	PADAPTER	Adapter,
+											IN	int		powerInDbm	);
+
+//
+VOID 
+PHY_ScanOperationBackup8192D(IN	PADAPTER	Adapter,
+										IN	u8		Operation	);
+
+//
+// Switch bandwidth for 8192S
+//
+//void	PHY_SetBWModeCallback8192C(	IN	PRT_TIMER		pTimer	);
+void	PHY_SetBWMode8192D(	IN	PADAPTER			pAdapter,
+									IN	HT_CHANNEL_WIDTH	ChnlWidth,
+									IN	unsigned char	Offset	);
+
+//
+// Set FW CMD IO for 8192S.
+//
+//extern	BOOLEAN HalSetIO8192C(	IN	PADAPTER			Adapter,
+//									IN	IO_TYPE				IOType);
+
+//
+// Set A2 entry to fw for 8192S
+//
+extern	void FillA2Entry8192C(		IN	PADAPTER			Adapter,
+										IN	u8				index,
+										IN	u8*				val);
+
+
+//
+// channel switch related funciton
+//
+//extern	void	PHY_SwChnlCallback8192C(	IN	PRT_TIMER		pTimer	);
+void	PHY_SwChnl8192D(	IN	PADAPTER		pAdapter,
+									IN	u8			channel	);
+				// Call after initialization
+void	PHY_SwChnlPhy8192D(	IN	PADAPTER		pAdapter,
+									IN	u8			channel	);
+
+extern void ChkFwCmdIoDone(	IN	PADAPTER	Adapter);
+
+	
+//
+// BB/MAC/RF other monitor API
+//
+void	PHY_SetMonitorMode8192D(IN	PADAPTER	pAdapter,
+										IN	BOOLEAN		bEnableMonitorMode	);
+
+BOOLEAN	PHY_CheckIsLegalRfPath8192D(IN	PADAPTER	pAdapter,
+											IN	u32		eRFPath	);
+
+
+//
+// Modify the value of the hw register when beacon interval be changed.
+//
+void	
+rtl8192d_PHY_SetBeaconHwReg(	IN	PADAPTER		Adapter,
+					IN	u16			BeaconInterval	);
+
+
+extern	VOID
+PHY_SwitchEphyParameter(
+	IN	PADAPTER			Adapter
+	);
+
+extern	VOID
+PHY_EnableHostClkReq(
+	IN	PADAPTER			Adapter
+	);
+
+BOOLEAN
+SetAntennaConfig92C(
+	IN	PADAPTER	Adapter,
+	IN	u8		DefaultAnt	
+	);
+
+VOID
+PHY_UpdateBBRFConfiguration8192D(
+	IN PADAPTER Adapter,
+	IN BOOLEAN bisBandSwitch
+);
+
+VOID PHY_ReadMacPhyMode92D(
+	IN PADAPTER	Adapter,
+	IN BOOLEAN 	AutoloadFail	
+);
+
+VOID PHY_ConfigMacPhyMode92D(
+	IN PADAPTER	Adapter
+);
+
+VOID PHY_ConfigMacPhyModeInfo92D(
+	IN PADAPTER	Adapter
+);
+
+VOID PHY_ConfigMacCoexist_RFPage92D(
+	IN PADAPTER	Adapter
+);
+
+VOID
+rtl8192d_PHY_InitRxSetting(
+	IN	PADAPTER Adapter
+);
+
+
+VOID 
+rtl8192d_PHY_SetRFPathSwitch(IN	PADAPTER	pAdapter, IN	BOOLEAN		bMain);
+
+VOID
+HalChangeCCKStatus8192D(
+	IN	PADAPTER	Adapter,
+	IN	BOOLEAN		bCCKDisable
+);
+
+VOID 
+PHY_InitPABias92D(IN	PADAPTER Adapter);
+
+/*--------------------------Exported Function prototype---------------------*/
+
+#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data))
+#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
+#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
+#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
+#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
+
+#define PHY_SetMacReg	PHY_SetBBReg
+#define PHY_QueryMacReg PHY_QueryBBReg
+
+#endif	// __INC_HAL8192SPHYCFG_H
+

include/Hal8723APhyCfg.h

@@ -0,0 +1,30 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __INC_HAL8723PHYCFG_H__
+#define __INC_HAL8723PHYCFG_H__
+
+#include <Hal8192CPhyCfg.h>
+/* MAC/BB/RF HAL config */
+int	PHY_BBConfig8723A(	IN	PADAPTER	Adapter	);
+int	PHY_RFConfig8723A(	IN	PADAPTER	Adapter	);
+s32 PHY_MACConfig8723A(PADAPTER padapter);
+
+#endif
+

include/Hal8723APhyReg.h

@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __INC_HAL8723APHYREG_H__
+#define __INC_HAL8723APHYREG_H__
+
+#include <Hal8192CPhyReg.h>
+
+//
+// PageB(0xB00)
+//
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA 				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+
+#endif
+

include/Hal8723PwrSeq.h

@@ -0,0 +1,171 @@
+#ifndef __HAL8723PWRSEQ_H__
+#define __HAL8723PWRSEQ_H__
+/*
+	Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#include "HalPwrSeqCmd.h"
+#include "rtl8723a_spec.h"
+
+#define	RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS	15
+#define	RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS	15
+#define	RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8723A_TRANS_ACT_TO_LPS_STEPS	15
+#define	RTL8723A_TRANS_LPS_TO_ACT_STEPS	15
+#define	RTL8723A_TRANS_END_STEPS	1
+
+
+#define RTL8723A_TRANS_CARDEMU_TO_ACT 														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/	\
+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
+
+#define RTL8723A_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
+
+
+#define RTL8723A_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8723A_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8723A_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8723A_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8723A_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8723A_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8723A_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
+
+
+extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
+
+#endif
+

include/HalPwrSeqCmd.h

@@ -23,51 +23,51 @@
 #include <drv_types.h>
 
 /*---------------------------------------------*/
-/* 3 The value of cmd: 4 bits */
+//3 The value of cmd: 4 bits
 /*---------------------------------------------*/
 #define PWR_CMD_READ			0x00
-     /*  offset: the read register offset */
+     // offset: the read register offset
-     /*  msk: the mask of the read value */
+     // msk: the mask of the read value
-     /*  value: N/A, left by 0 */
+     // value: N/A, left by 0
-     /*  note: dirver shall implement this function by read & msk */
+     // note: dirver shall implement this function by read & msk
 
 #define PWR_CMD_WRITE			0x01
-     /*  offset: the read register offset */
+     // offset: the read register offset
-     /*  msk: the mask of the write bits */
+     // msk: the mask of the write bits
-     /*  value: write value */
+     // value: write value
-     /*  note: driver shall implement this cmd by read & msk after write */
+     // note: driver shall implement this cmd by read & msk after write
 
 #define PWR_CMD_POLLING			0x02
-     /*  offset: the read register offset */
+     // offset: the read register offset
-     /*  msk: the mask of the polled value */
+     // msk: the mask of the polled value
-     /*  value: the value to be polled, masked by the msd field. */
+     // value: the value to be polled, masked by the msd field.
-     /*  note: driver shall implement this cmd by */
+     // note: driver shall implement this cmd by
-     /*  do{ */
+     // do{
-     /*  if ( (Read(offset) & msk) == (value & msk) ) */
+     // if( (Read(offset) & msk) == (value & msk) )
-     /*  break; */
+     // break;
-     /*  } while (not timeout); */
+     // } while(not timeout);
 
 #define PWR_CMD_DELAY			0x03
-     /*  offset: the value to delay */
+     // offset: the value to delay
-     /*  msk: N/A */
+     // msk: N/A
-     /*  value: the unit of delay, 0: us, 1: ms */
+     // value: the unit of delay, 0: us, 1: ms
 
-#define PWR_CMD_END			0x04
+#define PWR_CMD_END				0x04
-     /*  offset: N/A */
+     // offset: N/A
-     /*  msk: N/A */
+     // msk: N/A
-     /*  value: N/A */
+     // value: N/A
 
 /*---------------------------------------------*/
-/* 3 The value of base: 4 bits */
+//3 The value of base: 4 bits
 /*---------------------------------------------*/
-   /*  define the base address of each block */
+   // define the base address of each block
 #define PWR_BASEADDR_MAC		0x00
 #define PWR_BASEADDR_USB		0x01
 #define PWR_BASEADDR_PCIE		0x02
 #define PWR_BASEADDR_SDIO		0x03
 
 /*---------------------------------------------*/
-/* 3 The value of interface_msk: 4 bits */
+//3 The value of interface_msk: 4 bits
 /*---------------------------------------------*/
 #define	PWR_INTF_SDIO_MSK		BIT(0)
 #define	PWR_INTF_USB_MSK		BIT(1)
@@ -75,16 +75,16 @@
 #define	PWR_INTF_ALL_MSK		(BIT(0)|BIT(1)|BIT(2)|BIT(3))
 
 /*---------------------------------------------*/
-/* 3 The value of fab_msk: 4 bits */
+//3 The value of fab_msk: 4 bits
 /*---------------------------------------------*/
 #define	PWR_FAB_TSMC_MSK		BIT(0)
 #define	PWR_FAB_UMC_MSK			BIT(1)
 #define	PWR_FAB_ALL_MSK			(BIT(0)|BIT(1)|BIT(2)|BIT(3))
 
 /*---------------------------------------------*/
-/* 3 The value of cut_msk: 8 bits */
+//3 The value of cut_msk: 8 bits
 /*---------------------------------------------*/
-#define	PWR_CUT_TESTCHIP_MSK		BIT(0)
+#define	PWR_CUT_TESTCHIP_MSK	BIT(0)
 #define	PWR_CUT_A_MSK			BIT(1)
 #define	PWR_CUT_B_MSK			BIT(2)
 #define	PWR_CUT_C_MSK			BIT(3)
@@ -94,12 +94,15 @@
 #define	PWR_CUT_G_MSK			BIT(7)
 #define	PWR_CUT_ALL_MSK			0xFF
 
-enum pwrseq_cmd_delat_unit {
+
+typedef enum _PWRSEQ_CMD_DELAY_UNIT_
+{
 	PWRSEQ_DELAY_US,
 	PWRSEQ_DELAY_MS,
-};
+} PWRSEQ_DELAY_UNIT;
 
-struct wl_pwr_cfg {
+typedef struct _WL_PWR_CFG_
+{
 	u16 offset;
 	u8 cut_msk;
 	u8 fab_msk:4;
@@ -108,19 +111,28 @@ struct wl_pwr_cfg {
 	u8 cmd:4;
 	u8 msk;
 	u8 value;
-};
+} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
+
 
 #define GET_PWR_CFG_OFFSET(__PWR_CMD)		__PWR_CMD.offset
 #define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		__PWR_CMD.cut_msk
 #define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		__PWR_CMD.fab_msk
 #define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	__PWR_CMD.interface_msk
-#define GET_PWR_CFG_BASE(__PWR_CMD)		__PWR_CMD.base
+#define GET_PWR_CFG_BASE(__PWR_CMD)			__PWR_CMD.base
-#define GET_PWR_CFG_CMD(__PWR_CMD)		__PWR_CMD.cmd
+#define GET_PWR_CFG_CMD(__PWR_CMD)			__PWR_CMD.cmd
-#define GET_PWR_CFG_MASK(__PWR_CMD)		__PWR_CMD.msk
+#define GET_PWR_CFG_MASK(__PWR_CMD)			__PWR_CMD.msk
 #define GET_PWR_CFG_VALUE(__PWR_CMD)		__PWR_CMD.value
 
-/*	Prototype of protected function. */
+
-u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 CutVersion, u8 FabVersion,
+//================================================================================
-		       u8 InterfaceType, struct wl_pwr_cfg PwrCfgCmd[]);
+//	Prototype of protected function.
+//================================================================================
+u8 HalPwrSeqCmdParsing(
+	PADAPTER		padapter,
+	u8				CutVersion,
+	u8				FabVersion,
+	u8				InterfaceType,
+	WLAN_PWR_CFG	PwrCfgCmd[]);
 
 #endif
+