mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Convert C90 comments
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
54abf571c4
commit
592c85f4e2
47 changed files with 4098 additions and 4374 deletions
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@ -18,9 +18,9 @@
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*
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******************************************************************************/
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//============================================================
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// include files
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//============================================================
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/* */
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/* include files */
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/* */
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#include "odm_precomp.h"
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@ -36,7 +36,7 @@ ODM_DIG_LowerBound_88E(
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pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
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}
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//If only one Entry connected
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/* If only one Entry connected */
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@ -54,31 +54,31 @@ odm_RX_HWAntDivInit(
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if (*(pDM_Odm->mp_mode) == 1)
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{
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pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* 1:CG, 0:CS */
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return;
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}
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#endif
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n"));
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//MAC Setting
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/* MAC Setting */
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value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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//Pin Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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//OFDM Settings
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ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
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/* Pin Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0antsel antselb by HW */
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
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/* OFDM Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
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//CCK Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
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/* CCK Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
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ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); /* antenna mapping table */
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//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
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//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
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/* ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); Enable HW AntDiv */
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/* ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); Enable CCK AntDiv */
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}
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static void
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@ -93,8 +93,8 @@ odm_TRX_HWAntDivInit(
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if (*(pDM_Odm->mp_mode) == 1)
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{
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pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */
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return;
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}
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@ -102,34 +102,34 @@ odm_TRX_HWAntDivInit(
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n"));
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//MAC Setting
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/* MAC Setting */
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value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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//Pin Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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//OFDM Settings
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ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
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/* Pin Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
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/* OFDM Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
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//CCK Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
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//Tx Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
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/* CCK Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
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/* Tx Settings */
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ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
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ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
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//antenna mapping table
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if(!pDM_Odm->bIsMPChip) //testchip
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/* antenna mapping table */
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if(!pDM_Odm->bIsMPChip) /* testchip */
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{
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
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}
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else //MPchip
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001
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else /* MPchip */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
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//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
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//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
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/* ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); Enable HW AntDiv */
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/* ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); Enable CCK AntDiv */
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}
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void
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@ -161,33 +161,33 @@ odm_FastAntTrainingInit(
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pDM_FatTable->TrainIdx = 0;
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pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
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//MAC Setting
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/* MAC Setting */
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value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
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value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
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//value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
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//PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
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ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
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/* value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); */
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/* PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); append MACID in reponse packet */
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//Match MAC ADDR
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/* Match MAC ADDR */
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ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
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ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
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ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
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ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
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ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
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ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
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ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
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//antenna mapping table
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/* antenna mapping table */
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if(AntCombination == 2)
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{
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if(!pDM_Odm->bIsMPChip) //testchip
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if(!pDM_Odm->bIsMPChip) /* testchip */
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{
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
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}
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else //MPchip
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else /* MPchip */
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{
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
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@ -195,19 +195,19 @@ odm_FastAntTrainingInit(
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}
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else if(AntCombination == 7)
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{
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if(!pDM_Odm->bIsMPChip) //testchip
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if(!pDM_Odm->bIsMPChip) /* testchip */
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{
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */
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}
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else //MPchip
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else /* MPchip */
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{
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
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@ -220,27 +220,22 @@ odm_FastAntTrainingInit(
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}
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}
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//Default Ant Setting when no fast training
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ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
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//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX
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/* Default Ant Setting when no fast training */
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ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); /* Default RX */
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); /* Optional RX */
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//Enter Traing state
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
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//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
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//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
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//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
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ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
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/* Enter Traing state */
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */
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ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
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//SW Control
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//PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
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//PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
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//PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
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//PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
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//PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
|
||||
//PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
|
||||
/* SW Control */
|
||||
/* PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); */
|
||||
/* PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); */
|
||||
/* PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); */
|
||||
/* PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); */
|
||||
/* PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); */
|
||||
/* PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); */
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -248,20 +243,11 @@ ODM_AntennaDiversityInit_88E(
|
|||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
/*
|
||||
//2012.03.27 LukeLee: For temp use, should be removed later
|
||||
//pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
|
||||
//{
|
||||
struct adapter * Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
|
||||
//pHalData->AntDivCfg = 1;
|
||||
//}
|
||||
*/
|
||||
if(pDM_Odm->SupportICType != ODM_RTL8188E)
|
||||
return;
|
||||
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n",
|
||||
// pDM_Odm->AntDivType, pHalData->AntDivCfg));
|
||||
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", */
|
||||
/* pDM_Odm->AntDivType, pHalData->AntDivCfg)); */
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE")));
|
||||
|
||||
|
|
@ -296,16 +282,16 @@ ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u8 Ant)
|
|||
|
||||
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX
|
||||
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */
|
||||
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); /* Resp Tx */
|
||||
|
||||
}
|
||||
else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
|
||||
}
|
||||
}
|
||||
pDM_FatTable->RxIdleAnt = Ant;
|
||||
|
|
@ -349,8 +335,8 @@ ODM_SetTxAntByTxInfo_88E(
|
|||
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
|
||||
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
|
||||
SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
|
||||
// macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
|
||||
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n", */
|
||||
/* macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId])); */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -415,7 +401,7 @@ odm_HWAntDiv(
|
|||
pEntry = pDM_Odm->pODM_StaInfo[i];
|
||||
if(IS_STA_VALID(pEntry))
|
||||
{
|
||||
//2 Caculate RSSI per Antenna
|
||||
/* 2 Caculate RSSI per Antenna */
|
||||
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
|
||||
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
|
||||
TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT;
|
||||
|
|
@ -423,14 +409,14 @@ odm_HWAntDiv(
|
|||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
|
||||
|
||||
//2 Select MaxRSSI for DIG
|
||||
/* 2 Select MaxRSSI for DIG */
|
||||
LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
|
||||
if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
|
||||
AntDivMaxRSSI = LocalMaxRSSI;
|
||||
if(LocalMaxRSSI > MaxRSSI)
|
||||
MaxRSSI = LocalMaxRSSI;
|
||||
|
||||
//2 Select RX Idle Antenna
|
||||
/* 2 Select RX Idle Antenna */
|
||||
if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
|
||||
Main_RSSI = Aux_RSSI;
|
||||
else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
|
||||
|
|
@ -445,7 +431,7 @@ odm_HWAntDiv(
|
|||
#if TX_BY_REG
|
||||
|
||||
#else
|
||||
//2 Select TRX Antenna
|
||||
/* 2 Select TRX Antenna */
|
||||
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
||||
odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i);
|
||||
#endif
|
||||
|
|
@ -456,7 +442,7 @@ odm_HWAntDiv(
|
|||
pDM_FatTable->AuxAnt_Cnt[i] = 0;
|
||||
}
|
||||
|
||||
//2 Set RX Idle Antenna
|
||||
/* 2 Set RX Idle Antenna */
|
||||
ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt);
|
||||
|
||||
pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
|
||||
|
|
@ -471,7 +457,7 @@ ODM_AntennaDiversity_88E(
|
|||
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
||||
if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
|
||||
{
|
||||
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n"));
|
||||
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); */
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
|
||||
|
|
@ -512,29 +498,24 @@ ODM_AntennaDiversity_88E(
|
|||
if(pDM_FatTable->bBecomeLinked == TRUE)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); /* Enable CCK AntDiv */
|
||||
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
|
||||
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
|
||||
}
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(pDM_FatTable->bBecomeLinked ==FALSE)
|
||||
{
|
||||
} else {
|
||||
if(pDM_FatTable->bBecomeLinked ==FALSE) {
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
|
||||
//Because HW AntDiv is disabled before Link, we enable HW AntDiv after link
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv
|
||||
//ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv
|
||||
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
||||
{
|
||||
/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); /* Enable CCK AntDiv */
|
||||
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
|
||||
#if TX_BY_REG
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from Reg */
|
||||
#else
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
|
||||
#endif
|
||||
}
|
||||
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
|
||||
|
|
@ -548,7 +529,7 @@ ODM_AntennaDiversity_88E(
|
|||
}
|
||||
|
||||
|
||||
#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
|
||||
#else /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
|
||||
void
|
||||
ODM_SetTxAntByTxInfo_88E(
|
||||
IN PDM_ODM_T pDM_Odm,
|
||||
|
|
@ -557,10 +538,10 @@ ODM_SetTxAntByTxInfo_88E(
|
|||
)
|
||||
{
|
||||
}
|
||||
#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
|
||||
//3============================================================
|
||||
//3 Dynamic Primary CCA
|
||||
//3============================================================
|
||||
#endif /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
|
||||
/* 3============================================================ */
|
||||
/* 3 Dynamic Primary CCA */
|
||||
/* 3============================================================ */
|
||||
|
||||
void
|
||||
odm_PrimaryCCA_Init(
|
||||
|
|
@ -589,14 +570,14 @@ odm_DynamicPrimaryCCA(
|
|||
IN PDM_ODM_T pDM_Odm
|
||||
)
|
||||
{
|
||||
struct adapter *Adapter = pDM_Odm->Adapter; // for NIC
|
||||
prtl8192cd_priv priv = pDM_Odm->priv; // for AP
|
||||
struct adapter *Adapter = pDM_Odm->Adapter; /* for NIC */
|
||||
prtl8192cd_priv priv = pDM_Odm->priv; /* for AP */
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
|
||||
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
|
||||
BOOLEAN Is40MHz;
|
||||
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW
|
||||
BOOLEAN bConnected = FALSE; // connected or not
|
||||
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; /* connected client BW */
|
||||
BOOLEAN bConnected = FALSE; /* connected or not */
|
||||
static u8 Client_40MHz_pre = 0;
|
||||
static u64 lastTxOkCnt = 0;
|
||||
static u64 lastRxOkCnt = 0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue