skyfall/rtl8188eu
1
0
Fork 0
mirror of https://github.com/lwfinger/rtl8188eu.git synced 2024-11-10 15:39:38 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

rtl8188eu: Convert C90 comments

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-02-19 18:51:33 -06:00
parent 54abf571c4
commit 592c85f4e2
47 changed files with 4098 additions and 4374 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
hal/Hal8188EFWImg_CE.h
View file

@ -20,10 +20,10 @@
#ifndef __INC_HAL8188E_FW_IMG_H
#define __INC_HAL8188E_FW_IMG_H
//V10(1641)
/* V10(1641) */
#define Rtl8188EFWImgArrayLength 13904
extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
#endif //__INC_HAL8188E_FW_IMG_H
#endif /* __INC_HAL8188E_FW_IMG_H */

22
hal/Hal8188EPwrSeq.c
View file

@ -24,21 +24,21 @@
/*
drivers should parse below arrays and do the corresponding actions
*/
//3 Power on Array
/* 3 Power on Array */
WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_CARDEMU_TO_ACT
RTL8188E_TRANS_END
};
//3Radio off Array
/* 3Radio off Array */
WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_END
};
//3Card Disable Array
/* 3Card Disable Array */
WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
@ -46,7 +46,7 @@ WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8
RTL8188E_TRANS_END
};
//3 Card Enable Array
/* 3 Card Enable Array */
WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_CARDDIS_TO_CARDEMU
@ -54,7 +54,7 @@ WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL81
RTL8188E_TRANS_END
};
//3Suspend Array
/* 3Suspend Array */
WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
@ -62,7 +62,7 @@ WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_
RTL8188E_TRANS_END
};
//3 Resume Array
/* 3 Resume Array */
WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_SUS_TO_CARDEMU
@ -71,7 +71,7 @@ WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_T
};
//3HWPDN Array
/* 3HWPDN Array */
WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
@ -79,18 +79,18 @@ WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TR
RTL8188E_TRANS_END
};
//3 Enter LPS
/* 3 Enter LPS */
WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
//FW behavior
/* FW behavior */
RTL8188E_TRANS_ACT_TO_LPS
RTL8188E_TRANS_END
};
//3 Leave LPS
/* 3 Leave LPS */
WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
{
//FW behavior
/* FW behavior */
RTL8188E_TRANS_LPS_TO_ACT
RTL8188E_TRANS_END
};

152
hal/Hal8188ERateAdaptive.c
View file

@ -16,47 +16,47 @@ Major Change History:
#include "odm_precomp.h"
#if (RATE_ADAPTIVE_SUPPORT == 1)
// Rate adaptive parameters
/* Rate adaptive parameters */
static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0
{6,5,4,3,0,4},//86 , idx=1
{6,5,4,2,0,4},//81 , idx=2
{8,7,6,4,0,6},//75 , idx=3
{10,9,8,6,0,8},//71 , idx=4
{10,9,8,4,0,8},//66 , idx=5
{10,9,8,2,0,8},//62 , idx=6
{10,9,8,0,0,8},//59 , idx=7
{18,17,16,8,0,16},//53 , idx=8
{26,25,24,16,0,24},//50 , idx=9
{34,33,32,24,0,32},//47 , idx=0x0a
{34,31,28,20,0,32},//43 , idx=0x0b
{34,31,27,18,0,32},//40 , idx=0x0c
{34,31,26,16,0,32},//37 , idx=0x0d
{34,30,22,16,0,32},//32 , idx=0x0e
{34,30,24,16,0,32},//26 , idx=0x0f
{49,46,40,16,0,48},//20 , idx=0x10
{49,45,32,0,0,48},//17 , idx=0x11
{49,45,22,18,0,48},//15 , idx=0x12
{49,40,24,16,0,48},//12 , idx=0x13
{49,32,18,12,0,48},//9 , idx=0x14
{49,22,18,14,0,48},//6 , idx=0x15
{49,16,16,0,0,48}};//3 //3, idx=0x16
static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},/* 92 , idx=0 */
{6,5,4,3,0,4},/* 86 , idx=1 */
{6,5,4,2,0,4},/* 81 , idx=2 */
{8,7,6,4,0,6},/* 75 , idx=3 */
{10,9,8,6,0,8},/* 71 , idx=4 */
{10,9,8,4,0,8},/* 66 , idx=5 */
{10,9,8,2,0,8},/* 62 , idx=6 */
{10,9,8,0,0,8},/* 59 , idx=7 */
{18,17,16,8,0,16},/* 53 , idx=8 */
{26,25,24,16,0,24},/* 50 , idx=9 */
{34,33,32,24,0,32},/* 47 , idx=0x0a */
{34,31,28,20,0,32},/* 43 , idx=0x0b */
{34,31,27,18,0,32},/* 40 , idx=0x0c */
{34,31,26,16,0,32},/* 37 , idx=0x0d */
{34,30,22,16,0,32},/* 32 , idx=0x0e */
{34,30,24,16,0,32},/* 26 , idx=0x0f */
{49,46,40,16,0,48},/* 20 , idx=0x10 */
{49,45,32,0,0,48},/* 17 , idx=0x11 */
{49,45,22,18,0,48},/* 15 , idx=0x12 */
{49,40,24,16,0,48},/* 12 , idx=0x13 */
{49,32,18,12,0,48},/* 9 , idx=0x14 */
{49,22,18,14,0,48},/* 6 , idx=0x15 */
{49,16,16,0,0,48}};/* 3 idx=0x16 */
static u8 RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up
static u8 RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; /* 12% for rate up */
static u8 PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
// wilson modify
static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
/* wilson modify */
static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, /* SS>TH */
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SS<TH
5,5,7,7,8,0x0b,0x0d,0x0f}, /* 0329 R01 */
{0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, /* SS<TH */
0x0b,0x0c,0x0d,0x0e,0x0f,0x11,0x13,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, // SS>TH
static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, /* SS>TH */
0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
@ -76,32 +76,32 @@ static u16 N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8,
static u8 TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
2,2,3,3,4,4,5,7,
4,4,7,10,10,12,12,18,
5,7,7,8,11,18,36,60}; // 0329 // 1207
5,7,7,8,11,18,36,60}; /* 0329 */
static u8 DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
1,2,3,4,5,6,7,8,
1,2,3,4,5,6,7,8,
5,6,7,8,9,10,11,12};
static u32 INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode
0x0f8ff010, // 1: 40M GN mode
0x0f8ff005, // 2: BN mode/ 40M BGN mode
0x0f8ff000, // 3: N mode
0x00000ff5, // 4: BG mode
0x00000ff0, // 5: G mode
0x0000000d, // 6: B mode
0, // 7:
0, // 8:
0, // 9:
0, // 10:
0, // 11:
0, // 12:
0, // 13:
0, // 14:
0, // 15:
static u32 INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, /* 0: 40M BGN mode */
0x0f8ff010, /* 1: 40M GN mode */
0x0f8ff005, /* 2: BN mode/ 40M BGN mode */
0x0f8ff000, /* 3: N mode */
0x00000ff5, /* 4: BG mode */
0x00000ff0, /* 5: G mode */
0x0000000d, /* 6: B mode */
0, /* 7: */
0, /* 8: */
0, /* 9: */
0, /* 10: */
0, /* 11: */
0, /* 12: */
0, /* 13: */
0, /* 14: */
0, /* 15: */
};
static u8 PendingForRateUpFail[5]={2,10,24,40,60};
static u16 DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms
static u16 DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; /* 200ms-1200ms */
// End Rate adaptive parameters
/* End Rate adaptive parameters */
static void
odm_SetTxRPTTiming_8188E(
@ -116,14 +116,14 @@ odm_SetTxRPTTiming_8188E(
if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
break;
if (extend==0) // back to default timing
idx=0; //200ms
else if (extend==1) {// increase the timing
if (extend==0) /* back to default timing */
idx=0; /* 200ms */
else if (extend==1) {/* increase the timing */
idx+=1;
if (idx>5)
idx=5;
}
else if (extend==2) {// decrease the timing
else if (extend==2) {/* decrease the timing */
if(idx!=0)
idx-=1;
}
@ -254,13 +254,13 @@ odm_RateUp_8188E(
else if((pRaInfo->SGIEnable) !=1 )
pRaInfo->RateSGI = 0;
}
else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate))
else /* if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */
{
RateID = HighestRate;
}
RateUpfinish:
//if(pRaInfo->RAWaitingCounter==10)
/* if(pRaInfo->RAWaitingCounter==10) */
if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter]))
pRaInfo->RAWaitingCounter=0;
else
@ -287,18 +287,18 @@ odm_RateDecision_8188E(
)
{
u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
//u32 pool_retry;
/* u32 pool_retry; */
static u8 DynamicTxRPTTimingCounter=0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n"));
if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits
if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) /* STA used and data packet exits */
{
if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
// Start RA decision
/* Start RA decision */
if (pRaInfo->PreRate > pRaInfo->HighestRate)
RateID = pRaInfo->HighestRate;
else
@ -307,11 +307,11 @@ odm_RateDecision_8188E(
RtyPtID=0;
else
RtyPtID=1;
PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page
PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" NscDown init is %d\n", pRaInfo->NscDown));
//pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP;
/* pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; */
pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0];
pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1];
pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2];
@ -325,7 +325,7 @@ odm_RateDecision_8188E(
else
pRaInfo->NscDown=0;
// rate up
/* rate up */
PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" NscUp init is %d\n", pRaInfo->NscUp));
@ -347,7 +347,7 @@ odm_RateDecision_8188E(
pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI));
if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID]))
odm_RateDown_8188E(pDM_Odm,pRaInfo);
//else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retry<POOL_RETRY_TH[RateID]))
/* else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retry<POOL_RETRY_TH[RateID])) */
else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])
odm_RateUp_8188E(pDM_Odm,pRaInfo);
@ -365,7 +365,7 @@ odm_RateDecision_8188E(
DynamicTxRPTTimingCounter=0;
}
pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120
pRaInfo->PreRate = pRaInfo->DecisionRate; /* YJ,add,120120 */
odm_ResetRaCounter_8188E( pRaInfo);
}
@ -377,7 +377,7 @@ odm_ARFBRefresh_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
)
{ // Wilson 2011/10/26
{ /* Wilson 2011/10/26 */
u32 MaskFromReg;
s8 i;
@ -424,7 +424,7 @@ odm_ARFBRefresh_8188E(
pRaInfo->RAUseRate=(pRaInfo->RateMask);
break;
}
// Highest rate
/* Highest rate */
if (pRaInfo->RAUseRate){
for (i=RATESIZE;i>=0;i--)
{
@ -437,7 +437,7 @@ odm_ARFBRefresh_8188E(
else{
pRaInfo->HighestRate=0;
}
// Lowest rate
/* Lowest rate */
if (pRaInfo->RAUseRate){
for (i=0;i<RATESIZE;i++)
{
@ -605,7 +605,7 @@ ODM_RASupport_Init(
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n"));
// 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!!
/* 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! */
if (pDM_Odm->SupportICType == ODM_RTL8188E)
pDM_Odm->RaSupport88E = TRUE;
@ -621,8 +621,8 @@ ODM_RAInfo_Init(
{
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
#if 1
u8 WirelessMode=0xFF; //invalid value
u8 max_rate_idx = 0x13; //MCS7
u8 WirelessMode=0xFF; /* invalid value */
u8 max_rate_idx = 0x13; /* MCS7 */
if(pDM_Odm->pWirelessMode!=NULL){
WirelessMode=*(pDM_Odm->pWirelessMode);
}
@ -636,7 +636,7 @@ ODM_RAInfo_Init(
max_rate_idx = 0x03;
}
//printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx);
/* printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n",
WirelessMode,max_rate_idx));
@ -659,7 +659,7 @@ ODM_RAInfo_Init(
pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2;
pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2;
pRaInfo->RateSGI=0;
pRaInfo->Active=1; //Active is not used at present. by page, 110819
pRaInfo->Active=1; /* Active is not used at present. by page, 110819 */
pRaInfo->RptTime = 0x927c;
pRaInfo->DROP=0;
pRaInfo->DROP1=0;
@ -672,9 +672,9 @@ ODM_RAInfo_Init(
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
#if POWER_TRAINING_ACTIVE == 1
pRaInfo->PTActive=1; // Active when this STA is use
pRaInfo->PTActive=1; /* Active when this STA is use */
pRaInfo->PTTryState=0;
pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS
pRaInfo->PTStage=5; /* Need to fill into HW_PWR_STATUS */
pRaInfo->PTSmoothFactor=192;
pRaInfo->PTStopCount=0;
pRaInfo->PTPreRate=0;
@ -864,14 +864,14 @@ ODM_RA_TxRPT2Handle_8188E(
if(pRAInfo->RAstage<5){
odm_RateDecision_8188E(pDM_Odm,pRAInfo);
}
else if(pRAInfo->RAstage==5){ // Power training try state
else if(pRAInfo->RAstage==5){ /* Power training try state */
odm_PTTryState_8188E(pRAInfo);
}
else {// RAstage==6
else {/* RAstage==6 */
odm_PTDecision_8188E(pRAInfo);
}
// Stage_RA counter
/* Stage_RA counter */
if (pRAInfo->RAstage<=5)
pRAInfo->RAstage++;
else

10
hal/Hal8188ERateAdaptive.h
View file

@ -15,15 +15,15 @@ Major Change History:
2011-08-12 Page Create.
--*/
// Rate adaptive define
/* Rate adaptive define */
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
//
// TX report 2 format in Rx desc
//
/* */
/* TX report 2 format in Rx desc */
/* */
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
@ -36,7 +36,7 @@ Major Change History:
#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8)
// End rate adaptive define
/* End rate adaptive define */
void
ODM_RASupport_Init(

30
hal/Hal8188EReg.h
View file

@ -17,29 +17,29 @@
*
*
******************************************************************************/
//============================================================
// File Name: Hal8188EReg.h
//
// Description:
//
// This file is for RTL8188E register definition.
//
//
//============================================================
/* */
/* File Name: Hal8188EReg.h */
/* */
/* Description: */
/* */
/* This file is for RTL8188E register definition. */
/* */
/* */
/* */
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
//
// Register Definition
//
/* */
/* Register Definition */
/* */
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
//
// Bitmap Definition
//
/* */
/* Bitmap Definition */
/* */
#define BIT_FA_RESET_8188E BIT0

90
hal/HalHWImg8188E_BB.c
View file

@ -348,7 +348,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
PADAPTER Adapter = pDM_Odm->Adapter;
struct xmit_frame *pxmit_frame;
u8 bndy_cnt=1;
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
@ -364,14 +364,14 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
return HAL_STATUS_FAILURE;
}
}
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -381,16 +381,16 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
rtw_IOL_append_WD_cmd(pxmit_frame,(u16)v1, v2,bMaskDWord);
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -398,9 +398,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
@ -414,7 +414,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
rtw_IOL_append_WD_cmd(pxmit_frame,(u16)v1, v2,bMaskDWord);
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
@ -431,31 +431,31 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
}
#ifdef CONFIG_IOL_IOREG_CFG
if(biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
/* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */
if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
printk("~~~ %s Success !!! \n",__FUNCTION__);
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
printk("~~~ %s IOL_exec_cmds Failed !!! \n",__FUNCTION__);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
rst = HAL_STATUS_FAILURE;
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
@ -626,16 +626,16 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -643,9 +643,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
@ -914,7 +914,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
struct cmd_cmp cmpdata[ArrayLen];
u32 cmpdata_idx=0;
#endif
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
hex += interfaceValue << 8;
@ -930,7 +930,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
return HAL_STATUS_FAILURE;
}
}
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
@ -938,7 +938,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -978,16 +978,16 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -995,9 +995,9 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
@ -1039,7 +1039,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
@ -1056,7 +1056,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
#ifdef CONFIG_IOL_IOREG_CFG
if(biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
/* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */
if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
@ -1076,13 +1076,13 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
}
}
printk("### %s data compared !!###\n",__FUNCTION__);
//if(rst == HAL_STATUS_FAILURE)
{//dump data from TX packet buffer
/* if(rst == HAL_STATUS_FAILURE) */
{/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
@ -1090,13 +1090,13 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
/******************************************************************************
@ -1327,16 +1327,16 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -1344,9 +1344,9 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
@ -1412,7 +1412,7 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
u32 v5 = Array[i+4];
u32 v6 = Array[i+5];
// this line is a line of pure_body
/* this line is a line of pure_body */
if ( v1 < 0xCDCDCDCD )
{
@ -1421,10 +1421,10 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
continue;
}
else
{ // this line is the start of branch
{ /* this line is the start of branch */
if ( !CheckCondition(Array[i], hex) )
{ // don't need the hw_body
i += 2; // skip the pair of expression
{ /* don't need the hw_body */
i += 2; /* skip the pair of expression */
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+2];

8
hal/HalHWImg8188E_BB.h
View file

@ -21,7 +21,7 @@
#ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex);
/* static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); */
/******************************************************************************
* AGC_TAB_1T.TXT
@ -36,7 +36,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
******************************************************************************/
void
ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */
IN PDM_ODM_T pDM_Odm
);
/******************************************************************************
@ -52,7 +52,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
******************************************************************************/
void
ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */
IN PDM_ODM_T pDM_Odm
);
@ -65,4 +65,4 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif // end of HWIMG_SUPPORT
#endif /* end of HWIMG_SUPPORT */

48
hal/HalHWImg8188E_MAC.c
View file

@ -181,7 +181,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
struct cmd_cmp cmpdata[ArrayLen];
u32 cmpdata_idx=0;
#endif
#endif //CONFIG_IOL_IOREG_CFG
#endif /* CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
hex += interfaceValue << 8;
@ -199,14 +199,14 @@ ODM_ReadAndConfig_MAC_REG_8188E(
}
}
#endif //CONFIG_IOL_IOREG_CFG
#endif /* CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -223,16 +223,16 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#endif
}
else
#endif //endif CONFIG_IOL_IOREG_CFG
#endif /* endif CONFIG_IOL_IOREG_CFG */
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -240,9 +240,9 @@ ODM_ReadAndConfig_MAC_REG_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
@ -261,7 +261,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#endif
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
}
@ -280,17 +280,17 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#ifdef CONFIG_IOL_IOREG_CFG
if(biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
/* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */
if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
printk("~~~ IOL Config MAC Success !!! \n");
//compare writed data
/* compare writed data */
{
u32 idx;
u8 cdata;
// HAL_STATUS_FAILURE;
/* HAL_STATUS_FAILURE; */
printk(" MAC data compare => array_len:%d \n",cmpdata_idx);
for(idx=0;idx< cmpdata_idx;idx++)
{
@ -298,34 +298,34 @@ ODM_ReadAndConfig_MAC_REG_8188E(
if(cdata != cmpdata[idx].value){
printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n",
cmpdata[idx].addr,cmpdata[idx].value,cdata);
//rst = HAL_STATUS_FAILURE;
/* rst = HAL_STATUS_FAILURE; */
}
}
//dump data from TX packet buffer
//if(rst == HAL_STATUS_FAILURE)
/* dump data from TX packet buffer */
/* if(rst == HAL_STATUS_FAILURE) */
{
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
printk("~~~ MAC IOL_exec_cmds Failed !!! \n");
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
rst = HAL_STATUS_FAILURE;
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
@ -456,16 +456,16 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -473,9 +473,9 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&

4
hal/HalHWImg8188E_MAC.h
View file

@ -21,7 +21,7 @@
#ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex);
/* static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); */
/******************************************************************************
* MAC_REG.TXT
@ -37,7 +37,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
******************************************************************************/
void
ODM_ReadAndConfig_MAC_REG_ICUT_8188E( // TC: Test Chip, MP: MP Chip
ODM_ReadAndConfig_MAC_REG_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */
IN PDM_ODM_T pDM_Odm
);

42
hal/HalHWImg8188E_RF.c
View file

@ -201,7 +201,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
struct cmd_cmp cmpdata[ArrayLen];
u32 cmpdata_idx=0;
#endif
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
HAL_STATUS rst =HAL_STATUS_SUCCESS;
hex += board;
@ -218,14 +218,14 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
return HAL_STATUS_FAILURE;
}
}
#endif//#ifdef CONFIG_IOL_IOREG_CFG
#endif/* ifdef CONFIG_IOL_IOREG_CFG */
for (i = 0; i < ArrayLen; i += 2 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
@ -263,16 +263,16 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -280,9 +280,9 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
@ -325,7 +325,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
@ -342,7 +342,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
}
#ifdef CONFIG_IOL_IOREG_CFG
if(biol){
//printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
/* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */
if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
{
#ifdef CONFIG_IOL_IOREG_CFG_DBG
@ -362,12 +362,12 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
}
}
printk("### %s data compared !!###\n",__FUNCTION__);
//if(rst == HAL_STATUS_FAILURE)
{//dump data from TX packet buffer
/* if(rst == HAL_STATUS_FAILURE) */
{/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
else{
@ -375,15 +375,15 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
{
//dump data from TX packet buffer
/* dump data from TX packet buffer */
rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
}
#endif //CONFIG_IOL_IOREG_CFG_DBG
#endif /* CONFIG_IOL_IOREG_CFG_DBG */
}
}
#endif //#ifdef CONFIG_IOL_IOREG_CFG
#endif /* ifdef CONFIG_IOL_IOREG_CFG */
return rst;
}
/******************************************************************************
@ -522,16 +522,16 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
continue;
}
else
{ // This line is the start line of branch.
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
@ -539,9 +539,9 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
i -= 2; /* prevent from for-loop += 2 */
}
else // Configure matched pairs and skip to end of if-else.
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&

4
hal/HalHWImg8188E_RF.h
View file

@ -21,7 +21,7 @@
#ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex);
/* static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); */
/******************************************************************************
* RadioA_1T.TXT
@ -36,7 +36,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
******************************************************************************/
void
ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip
ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */
IN PDM_ODM_T pDM_Odm
);

8
hal/HalPhyRf.c
View file

@ -20,9 +20,9 @@
#include "odm_precomp.h"
//3============================================================
//3 IQ Calibration
//3============================================================
/* 3============================================================ */
/* 3 IQ Calibration */
/* 3============================================================ */
void
ODM_ResetIQKResult(
@ -35,7 +35,7 @@ ODM_ResetIQKResult(
if (!IS_HARDWARE_TYPE_8192D(Adapter))
return;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
//0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc
/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
for(i = 0; i < IQK_Matrix_Settings_NUM; i++)
{

2
hal/HalPhyRf.h
View file

@ -26,5 +26,5 @@
void ODM_ResetIQKResult(PDM_ODM_T pDM_Odm );
u8 ODM_GetRightChnlPlaceforIQK(u8 chnl);
#endif // #ifndef __HAL_PHY_RF_H__
#endif /* #ifndef __HAL_PHY_RF_H__ */

448
hal/HalPhyRf_8188e.c
View file

File diff suppressed because it is too large Load diff

24
hal/HalPhyRf_8188e.h
View file

@ -23,7 +23,7 @@
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 //ms
#define IQK_DELAY_TIME_88E 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
@ -36,9 +36,9 @@ typedef enum _PWRTRACK_CONTROL_METHOD {
void
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u8 Type, // 0 = OFDM, 1 = CCK
u8 * pDirection, // 1 = +(increase) 2 = -(decrease)
u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
u8 Type, /* 0 = OFDM, 1 = CCK */
u8 * pDirection, /* 1 = +(increase) 2 = -(decrease) */
u32 * pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */
);
@ -48,7 +48,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
);
//1 7. IQK
/* 1 7. IQK */
void
PHY_IQCalibrate_8188E(
@ -56,17 +56,17 @@ PHY_IQCalibrate_8188E(
IN BOOLEAN bReCovery);
//
// LC calibrate
//
/* */
/* LC calibrate */
/* */
void
PHY_LCCalibrate_8188E(
IN struct adapter * pAdapter
);
//
// AP calibrate
//
/* */
/* AP calibrate */
/* */
void
PHY_APCalibrate_8188E(
IN struct adapter * pAdapter,
@ -106,5 +106,5 @@ _PHY_PathAStandBy(
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

30
hal/HalPwrSeqCmd.c
View file

@ -35,15 +35,15 @@ Major Change History:
--*/
#include <HalPwrSeqCmd.h>
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
/* */
/* Description: */
/* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
/* */
/* Assumption: */
/* We should follow specific format which was released from HW SD. */
/* */
/* 2011.07.07, added by Roger. */
/* */
u8 HalPwrSeqCmdParsing(
struct adapter * padapter,
u8 CutVersion,
@ -56,7 +56,7 @@ u8 HalPwrSeqCmdParsing(
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 pollingCount = 0; /* polling autoload done. */
u32 maxPollingCnt = 5000;
do {
@ -73,7 +73,7 @@ u8 HalPwrSeqCmdParsing(
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
@ -88,13 +88,13 @@ u8 HalPwrSeqCmdParsing(
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
// Read the value from system register
/* Read the value from system register */
value = rtw_read8(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
/* Write the value back to sytem register */
rtw_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
@ -128,7 +128,7 @@ u8 HalPwrSeqCmdParsing(
break;
case PWR_CMD_END:
// When this command is parsed, end the process
/* When this command is parsed, end the process */
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return true;
break;
@ -139,7 +139,7 @@ u8 HalPwrSeqCmdParsing(
}
}
AryIdx++;//Add Array Index
AryIdx++;/* Add Array Index */
}while(1);
return true;

140
hal/hal_com.c
View file

@ -71,12 +71,12 @@ void dump_chip_info(HAL_VERSION ChipVersion)
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
u8 //return the final channel plan decision
u8 /* return the final channel plan decision */
hal_com_get_channel_plan(
IN struct adapter *padapter,
IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
IN u8 sw_channel_plan, //channel plan from SW (registry/module param)
IN u8 def_channel_plan, //channel plan used when the former two is invalid
IN u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */
IN u8 sw_channel_plan, /* channel plan from SW (registry/module param) */
IN u8 def_channel_plan, /* channel plan used when the former two is invalid */
IN BOOLEAN AutoLoadFail
)
{
@ -109,7 +109,7 @@ u8 MRateToHwRate(u8 rate)
switch(rate)
{
// CCK and OFDM non-HT rates
/* CCK and OFDM non-HT rates */
case IEEE80211_CCK_RATE_1MB: ret = DESC_RATE1M; break;
case IEEE80211_CCK_RATE_2MB: ret = DESC_RATE2M; break;
case IEEE80211_CCK_RATE_5MB: ret = DESC_RATE5_5M; break;
@ -123,15 +123,15 @@ u8 MRateToHwRate(u8 rate)
case IEEE80211_OFDM_RATE_48MB: ret = DESC_RATE48M; break;
case IEEE80211_OFDM_RATE_54MB: ret = DESC_RATE54M; break;
// HT rates since here
//case MGN_MCS0: ret = DESC_RATEMCS0; break;
//case MGN_MCS1: ret = DESC_RATEMCS1; break;
//case MGN_MCS2: ret = DESC_RATEMCS2; break;
//case MGN_MCS3: ret = DESC_RATEMCS3; break;
//case MGN_MCS4: ret = DESC_RATEMCS4; break;
//case MGN_MCS5: ret = DESC_RATEMCS5; break;
//case MGN_MCS6: ret = DESC_RATEMCS6; break;
//case MGN_MCS7: ret = DESC_RATEMCS7; break;
/* HT rates since here */
/* case MGN_MCS0: ret = DESC_RATEMCS0; break; */
/* case MGN_MCS1: ret = DESC_RATEMCS1; break; */
/* case MGN_MCS2: ret = DESC_RATEMCS2; break; */
/* case MGN_MCS3: ret = DESC_RATEMCS3; break; */
/* case MGN_MCS4: ret = DESC_RATEMCS4; break; */
/* case MGN_MCS5: ret = DESC_RATEMCS5; break; */
/* case MGN_MCS6: ret = DESC_RATEMCS6; break; */
/* case MGN_MCS7: ret = DESC_RATEMCS7; break; */
default: break;
}
@ -179,15 +179,15 @@ _OneOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
static void
@ -198,39 +198,39 @@ _TwoOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if(bWIFICfg){ //WMM
if(bWIFICfg){ /* WMM */
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 0, 1, 0, 1, 0, 0, 0, 0, 0 };
//0:H, 1:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
else{//typical setting
else{/* typical setting */
//BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 1, 0, 0, 0, 0, 0, 0, 0 };
//0:H, 1:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
@ -243,39 +243,39 @@ static void _ThreeOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if(bWIFICfg){//for WMM
if(bWIFICfg){/* for WMM */
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H, 1:N, 2:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:N, 2:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
else{//typical setting
else{/* typical setting */
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 2, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H, 1:N, 2:L
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
/* 0:H, 1:N, 2:L */
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
}
}

10
hal/hal_intf.c
View file

@ -63,7 +63,7 @@ void rtw_hal_dm_init(struct adapter *padapter)
}
void rtw_hal_dm_deinit(struct adapter *padapter)
{
// cancel dm timer
/* cancel dm timer */
if (is_primary_adapter(padapter))
if(padapter->HalFunc.dm_deinit)
padapter->HalFunc.dm_deinit(padapter);
@ -282,7 +282,7 @@ s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe)
if(IS_MCAST(pmgntframe->attrib.ra))
{
pmgntframe->attrib.encrypt = _BIP_;
//pmgntframe->attrib.bswenc = true;
/* pmgntframe->attrib.bswenc = true; */
}
else
{
@ -291,7 +291,7 @@ s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe)
}
rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
}
#endif //CONFIG_IEEE80211W
#endif /* CONFIG_IEEE80211W */
if(padapter->HalFunc.mgnt_xmit)
ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
@ -444,7 +444,7 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
return _FAIL;
}
#endif //CONFIG_HOSTAPD_MLME
#endif /* CONFIG_HOSTAPD_MLME */
#ifdef DBG_CONFIG_ERROR_DETECT
void rtw_hal_sreset_init(struct adapter *padapter)
@ -500,7 +500,7 @@ bool rtw_hal_sreset_inprogress(struct adapter *padapter)
inprogress = padapter->HalFunc.sreset_inprogress(padapter);
return inprogress;
}
#endif //DBG_CONFIG_ERROR_DETECT
#endif /* DBG_CONFIG_ERROR_DETECT */
#ifdef CONFIG_IOL
int rtw_hal_iol_cmd(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)

1278
hal/odm.c
View file

File diff suppressed because it is too large Load diff

767
hal/odm.h
View file

File diff suppressed because it is too large Load diff

237
hal/odm_HWConfig.c
View file

@ -18,9 +18,9 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
@ -60,10 +60,10 @@ odm_QueryRxPwrPercentage(
}
//
// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
// IF other SW team do not support the feature, remove this section.??
//
/* */
/* 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. */
/* IF other SW team do not support the feature, remove this section.?? */
/* */
static s32
odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
IN OUT PDM_ODM_T pDM_Odm,
@ -95,7 +95,7 @@ odm_SignalScaleMapping_92CSeries(
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE)
{
// Step 1. Scale mapping.
/* Step 1. Scale mapping. */
if(CurrSig >= 61 && CurrSig <= 100)
{
RetSig = 90 + ((CurrSig - 60) / 4);
@ -185,14 +185,14 @@ odm_SignalScaleMapping(
)
{
if( (pDM_Odm->SupportPlatform == ODM_MP) &&
(pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO
(pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore
(pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && /* USB & SDIO */
(pDM_Odm->PatchID==10))/* pMgntInfo->CustomerID == RT_CID_819x_Netcore */
{
return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig);
}
else if( (pDM_Odm->SupportPlatform == ODM_MP) &&
(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) &&
(pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo)
(pDM_Odm->PatchID==19))/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo) */
{
return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig);
}
@ -202,7 +202,7 @@ odm_SignalScaleMapping(
}
//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
static u8 odm_SQ_process_patch_RT_CID_819x_Lenovo(
IN PDM_ODM_T pDM_Odm,
IN u8 isCCKrate,
@ -220,15 +220,15 @@ odm_EVMdbToPercentage(
IN s8 Value
)
{
//
// -33dB~0dB to 0%~99%
//
/* */
/* -33dB~0dB to 0%~99% */
/* */
s8 ret_val;
ret_val = Value;
//ret_val /= 2;
/* ret_val /= 2; */
//ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x \n", ret_val, ret_val));
/* ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x \n", ret_val, ret_val)); */
if(ret_val >= 0)
ret_val = 0;
@ -278,21 +278,21 @@ odm_RxPhyStatus92CSeries_Parsing(
u8 cck_agc_rpt;
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
//
// (1)Hardware does not provide RSSI for CCK
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
/* */
/* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
/* */
//if(pHalData->eRFPowerState == eRfOn)
/* if(pHalData->eRFPowerState == eRfOn) */
cck_highpwr = pDM_Odm->bCckHighPower;
//else
// cck_highpwr = FALSE;
/* else */
/* cck_highpwr = FALSE; */
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ;
//2011.11.28 LukeLee: 88E use different LNA & VGA gain table
//The RSSI formula should be modified according to the gain table
//In 88E, cck_highpwr is always set to 1
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
/* The RSSI formula should be modified according to the gain table */
/* In 88E, cck_highpwr is always set to 1 */
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812))
{
LNA_idx = ((cck_agc_rpt & 0xE0) >>5);
@ -301,37 +301,35 @@ odm_RxPhyStatus92CSeries_Parsing(
{
case 7:
if(VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2
rx_pwr_all = -100 + 2*(27-VGA_idx); /* VGA_idx = 27~2 */
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0
rx_pwr_all = -48 + 2*(2-VGA_idx); /* VGA_idx = 2~0 */
break;
case 5:
rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5
rx_pwr_all = -42 + 2*(7-VGA_idx); /* VGA_idx = 7~5 */
break;
case 4:
rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4
rx_pwr_all = -36 + 2*(7-VGA_idx); /* VGA_idx = 7~4 */
break;
case 3:
//rx_pwr_all = -28 + 2*(7-VGA_idx); //VGA_idx = 7~0
rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0
rx_pwr_all = -24 + 2*(7-VGA_idx); /* VGA_idx = 7~0 */
break;
case 2:
if(cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0
rx_pwr_all = -12 + 2*(5-VGA_idx); /* VGA_idx = 5~0 */
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
break;
case 1:
rx_pwr_all = 8-2*VGA_idx;
rx_pwr_all = 8-2*VGA_idx;
break;
case 0:
rx_pwr_all = 14-2*VGA_idx;
rx_pwr_all = 14-2*VGA_idx;
break;
default:
//DbgPrint("CCK Exception default\n");
break;
}
rx_pwr_all += 6;
@ -353,9 +351,9 @@ odm_RxPhyStatus92CSeries_Parsing(
report =( cck_agc_rpt & 0xc0 )>>6;
switch(report)
{
// 03312009 modified by cosa
// Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion
// Note: different RF with the different RNA gain.
/* 03312009 modified by cosa */
/* Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion */
/* Note: different RF with the different RNA gain. */
case 0x3:
rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
break;
@ -372,8 +370,8 @@ odm_RxPhyStatus92CSeries_Parsing(
}
else
{
//report = pDrvInfo->cfosho[0] & 0x60;
//report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60;
/* report = pDrvInfo->cfosho[0] & 0x60; */
/* report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; */
report = (cck_agc_rpt & 0x60)>>5;
switch(report)
@ -395,7 +393,7 @@ odm_RxPhyStatus92CSeries_Parsing(
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
//Modification for ext-LNA board
/* Modification for ext-LNA board */
if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
{
if((cck_agc_rpt>>7) == 0){
@ -409,13 +407,13 @@ odm_RxPhyStatus92CSeries_Parsing(
PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12);
}
//CCK modification
/* CCK modification */
if(PWDB_ALL > 25 && PWDB_ALL <= 60)
PWDB_ALL += 6;
//else if (PWDB_ALL <= 25)
// PWDB_ALL += 8;
/* else if (PWDB_ALL <= 25) */
/* PWDB_ALL += 8; */
}
else//Modification for int-LNA board
else/* Modification for int-LNA board */
{
if(PWDB_ALL > 99)
PWDB_ALL -= 8;
@ -427,14 +425,14 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxPWDBAll = PWDB_ALL;
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL;
pPhyInfo->RecvSignalPower = rx_pwr_all;
//
// (3) Get Signal Quality (EVM)
//
/* */
/* (3) Get Signal Quality (EVM) */
/* */
if(pPktinfo->bPacketMatchBSSID)
{
u8 SQ,SQ_rpt;
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0);
}
else if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){
@ -452,27 +450,27 @@ odm_RxPhyStatus92CSeries_Parsing(
}
//DbgPrint("cck SQ = %d\n", SQ);
/* DbgPrint("cck SQ = %d\n", SQ); */
pPhyInfo->SignalQuality = SQ;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
}
}
else //is OFDM rate
else /* is OFDM rate */
{
pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++;
//
// (1)Get RSSI for HT rate
//
/* */
/* (1)Get RSSI for HT rate */
/* */
for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
{
// 2008/01/30 MH we will judge RF RX path now.
/* 2008/01/30 MH we will judge RF RX path now. */
if (pDM_Odm->RFPathRxEnable & BIT(i))
rf_rx_num++;
//else
//continue;
/* else */
/* continue; */
rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110;
@ -481,9 +479,9 @@ odm_RxPhyStatus92CSeries_Parsing(
/* Translate DBM to percentage. */
RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]);
total_rssi += RSSI;
//RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));
/* RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */
//Modification for ext-LNA board
/* Modification for ext-LNA board */
if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
{
if((pPhyStaRpt->path_agc[i].trsw) == 1)
@ -497,7 +495,7 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxMIMOSignalStrength[i] =(u8) RSSI;
//Get Rx snr value in DB
/* Get Rx snr value in DB */
pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2);
/* Record Signal Strength for next packet */
@ -514,9 +512,9 @@ odm_RxPhyStatus92CSeries_Parsing(
}
//
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
/* */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
/* */
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110;
PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
@ -527,28 +525,28 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RecvSignalPower = rx_pwr_all;
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){
//do nothing
} else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo
//
// (3)EVM of HT rate
//
/* do nothing */
} else{/* pMgntInfo->CustomerID != RT_CID_819x_Lenovo */
/* */
/* (3)EVM of HT rate */
/* */
if(pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15)
Max_spatial_stream = 2; //both spatial stream make sense
Max_spatial_stream = 2; /* both spatial stream make sense */
else
Max_spatial_stream = 1; //only spatial stream 1 makes sense
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
for(i=0; i<Max_spatial_stream; i++) {
// Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
// fill most significant bit to "zero" when doing shifting operation which may change a negative
// value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm
/* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
/* fill most significant bit to "zero" when doing shifting operation which may change a negative */
/* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); /* dbm */
//RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",
//GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM));
/* RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", */
/* GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); */
if(pPktinfo->bPacketMatchBSSID)
{
if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only
if(i==ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
{
pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
}
@ -558,11 +556,11 @@ odm_RxPhyStatus92CSeries_Parsing(
}
}
//UI BSS List signal strength(in percentage), make it good looking, from 0~100.
//It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
/* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
/* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
if(isCCKrate)
{
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL;
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/* PWDB_ALL; */
}
else
{
@ -572,10 +570,10 @@ odm_RxPhyStatus92CSeries_Parsing(
}
}
//For 92C/92D HW (Hybrid) Antenna Diversity
/* For 92C/92D HW (Hybrid) Antenna Diversity */
#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
pDM_SWAT_Table->antsel = pPhyStaRpt->ant_sel;
//For 88E HW Antenna Diversity
/* For 88E HW Antenna Diversity */
pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel;
pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b;
pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2;
@ -609,8 +607,8 @@ odm_Process_RSSIForDM(
if(pPktinfo->StationID == 0xFF)
return;
// 2011/11/17 MH Need to debug
//if (pDM_Odm->SupportPlatform == ODM_MP)
/* 2011/11/17 MH Need to debug */
/* if (pDM_Odm->SupportPlatform == ODM_MP) */
{
}
@ -630,7 +628,7 @@ odm_Process_RSSIForDM(
pDM_Odm->RxRate = pPktinfo->Rate;
#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
//-----------------Smart Antenna Debug Message------------------//
/* Smart Antenna Debug Message------------------ */
if(pDM_Odm->SupportICType == ODM_RTL8188E)
{
u8 antsel_tr_mux;
@ -640,33 +638,23 @@ odm_Process_RSSIForDM(
{
if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
{
if(pPktinfo->bPacketToSelf) //(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))
if(pPktinfo->bPacketToSelf) /* pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) */
{
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
pDM_FatTable->antSumRSSI[antsel_tr_mux] += pPhyInfo->RxPWDBAll;
pDM_FatTable->antRSSIcnt[antsel_tr_mux]++;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll));
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",
//pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));
}
}
}
else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV))
{
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
} else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) {
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",
// pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));
ODM_AntselStatistics_88E(pDM_Odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll);
}
}
}
#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
//-----------------Smart Antenna Debug Message------------------//
#endif /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
/* Smart Antenna Debug Message------------------ */
UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK;
UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM;
@ -675,7 +663,7 @@ odm_Process_RSSIForDM(
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
if(!isCCKrate)//ofdm rate
if(!isCCKrate)/* ofdm rate */
{
if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
@ -684,8 +672,8 @@ odm_Process_RSSIForDM(
}
else
{
//DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d \n",
//pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]);
/* DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d \n", */
/* pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); */
pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
@ -709,8 +697,8 @@ odm_Process_RSSIForDM(
RSSI_Ave = RSSI_max - 3;
}
//1 Process OFDM RSSI
if(UndecoratedSmoothedOFDM <= 0) // initialize
/* 1 Process OFDM RSSI */
if(UndecoratedSmoothedOFDM <= 0) /* initialize */
{
UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll;
}
@ -740,8 +728,8 @@ odm_Process_RSSIForDM(
pDM_Odm->RSSI_A = (u8) pPhyInfo->RxPWDBAll;
pDM_Odm->RSSI_B = 0xFF;
//1 Process CCK RSSI
if(UndecoratedSmoothedCCK <= 0) // initialize
/* 1 Process CCK RSSI */
if(UndecoratedSmoothedCCK <= 0) /* initialize */
{
UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll;
}
@ -764,9 +752,9 @@ odm_Process_RSSIForDM(
pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1;
}
//if(pEntry)
/* if(pEntry) */
{
//2011.07.28 LukeLee: modified to prevent unstable CCK RSSI
/* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
if(pEntry->rssi_stat.ValidBit >= 64)
pEntry->rssi_stat.ValidBit = 64;
else
@ -792,18 +780,18 @@ odm_Process_RSSIForDM(
pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM;
pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
//DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting);
//DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n",
// UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK);
/* DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); */
/* DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", */
/* UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); */
}
}
}
//
// Endianness before calling this API
//
/* */
/* Endianness before calling this API */
/* */
static void
ODM_PhyStatusQuery_92CSeries(
IN OUT PDM_ODM_T pDM_Odm,
@ -820,7 +808,7 @@ ODM_PhyStatusQuery_92CSeries(
pPktinfo);
if( pDM_Odm->RSSI_test == TRUE) {
// Select the packets to do RSSI checking for antenna switching.
/* Select the packets to do RSSI checking for antenna switching. */
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon )
ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo);
} else {
@ -829,9 +817,9 @@ ODM_PhyStatusQuery_92CSeries(
}
//
// Endianness before calling this API
//
/* */
/* Endianness before calling this API */
/* */
static void
ODM_PhyStatusQuery_JaguarSeries(
IN OUT PDM_ODM_T pDM_Odm,
@ -855,7 +843,7 @@ ODM_PhyStatusQuery(
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
// For future use.
/* For future use. */
void
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
@ -866,7 +854,7 @@ ODM_MacStatusQuery(
IN BOOLEAN bPacketBeacon
)
{
// 2011/10/19 Driver team will handle in the future.
/* 2011/10/19 Driver team will handle in the future. */
}
@ -877,7 +865,7 @@ ODM_ConfigRFWithHeaderFile(
IN ODM_RF_RADIO_PATH_E eRFPath
)
{
//RT_STATUS rtStatus = RT_STATUS_SUCCESS;
/* RT_STATUS rtStatus = RT_STATUS_SUCCESS; */
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
@ -894,7 +882,6 @@ ODM_ConfigRFWithHeaderFile(
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath));
//rtStatus = RT_STATUS_SUCCESS;
return HAL_STATUS_SUCCESS;
}

34
hal/odm_HWConfig.h
View file

@ -22,18 +22,18 @@
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
//============================================================
// Definition
//============================================================
//
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
/* */
/* Definition */
/* */
/* */
/* */
/* CCK Rates, TxHT = 0 */
#define DESC92C_RATE1M 0x00
#define DESC92C_RATE2M 0x01
#define DESC92C_RATE5_5M 0x02
#define DESC92C_RATE11M 0x03
// OFDM Rates, TxHT = 0
/* OFDM Rates, TxHT = 0 */
#define DESC92C_RATE6M 0x04
#define DESC92C_RATE9M 0x05
#define DESC92C_RATE12M 0x06
@ -43,7 +43,7 @@
#define DESC92C_RATE48M 0x0a
#define DESC92C_RATE54M 0x0b
// MCS Rates, TxHT = 1
/* MCS Rates, TxHT = 1 */
#define DESC92C_RATEMCS0 0x0c
#define DESC92C_RATEMCS1 0x0d
#define DESC92C_RATEMCS2 0x0e
@ -64,9 +64,9 @@
#define DESC92C_RATEMCS32 0x20
//============================================================
// structure and define
//============================================================
/* */
/* structure and define */
/* */
typedef struct _Phy_Rx_AGC_Info
{
@ -84,7 +84,7 @@ typedef struct _Phy_Status_Rpt_8192cd
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;//ch_corr_msb;
u8 rsvd_1;/* ch_corr_msb; */
u8 noise_power_db_msb;
u8 path_cfotail[2];
u8 pcts_mask[2];
@ -98,21 +98,21 @@ typedef struct _Phy_Status_Rpt_8192cd
u8 rsvd_3;
#ifdef __LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; //ex_intf_flg:1;
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 ant_sel_b:1;
u8 ant_sel:1;
#else // _BIG_ENDIAN_
#else /* _BIG_ENDIAN_ */
u8 ant_sel:1;
u8 ant_sel_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; //ex_intf_flg:1;
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
@ -124,7 +124,7 @@ typedef struct _Phy_Status_Rpt_8195
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_bb_pwr_ofdm_cfosho_b;
u8 cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u8 cck_rx_path; /* CCK_RX_PATH [3:0] (with regA07[3:0] definition) */
u8 rsvd_1;
u8 path_cfotail[2];
u8 pcts_mask[2];
@ -140,7 +140,7 @@ typedef struct _Phy_Status_Rpt_8195
u8 antidx_anta:3;
u8 antidx_antb:3;
u8 rsvd_5:2;
#else // _BIG_ENDIAN_
#else /* _BIG_ENDIAN_ */
u8 rsvd_5:2;
u8 antidx_antb:3;
u8 antidx_anta:3;

255
hal/odm_RTL8188E.c
View file

@ -18,9 +18,9 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
@ -36,7 +36,7 @@ ODM_DIG_LowerBound_88E(
pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
}
//If only one Entry connected
/* If only one Entry connected */
@ -54,31 +54,31 @@ odm_RX_HWAntDivInit(
if (*(pDM_Odm->mp_mode) == 1)
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* 1:CG, 0:CS */
return;
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n"));
//MAC Setting
/* MAC Setting */
value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
//Pin Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
//OFDM Settings
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0antsel antselb by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
//CCK Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
/* CCK Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); /* antenna mapping table */
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
/* ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); Enable HW AntDiv */
/* ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); Enable CCK AntDiv */
}
static void
@ -93,8 +93,8 @@ odm_TRX_HWAntDivInit(
if (*(pDM_Odm->mp_mode) == 1)
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */
return;
}
@ -102,34 +102,34 @@ odm_TRX_HWAntDivInit(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n"));
//MAC Setting
/* MAC Setting */
value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
//Pin Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
//OFDM Settings
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
//CCK Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
//Tx Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
/* CCK Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
/* Tx Settings */
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
//antenna mapping table
if(!pDM_Odm->bIsMPChip) //testchip
/* antenna mapping table */
if(!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
}
else //MPchip
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001
else /* MPchip */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
/* ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); Enable HW AntDiv */
/* ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); Enable CCK AntDiv */
}
void
@ -161,33 +161,33 @@ odm_FastAntTrainingInit(
pDM_FatTable->TrainIdx = 0;
pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
//MAC Setting
/* MAC Setting */
value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
//value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
//PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
/* value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); */
/* PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); append MACID in reponse packet */
//Match MAC ADDR
/* Match MAC ADDR */
ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
//antenna mapping table
/* antenna mapping table */
if(AntCombination == 2)
{
if(!pDM_Odm->bIsMPChip) //testchip
if(!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
}
else //MPchip
else /* MPchip */
{
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
@ -195,19 +195,19 @@ odm_FastAntTrainingInit(
}
else if(AntCombination == 7)
{
if(!pDM_Odm->bIsMPChip) //testchip
if(!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */
ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */
}
else //MPchip
else /* MPchip */
{
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
@ -220,27 +220,22 @@ odm_FastAntTrainingInit(
}
}
//Default Ant Setting when no fast training
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX
/* Default Ant Setting when no fast training */
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); /* Default RX */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); /* Optional RX */
//Enter Traing state
ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
/* Enter Traing state */
ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
//SW Control
//PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
//PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
//PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
//PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
//PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
//PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
/* SW Control */
/* PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); */
/* PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); */
/* PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); */
/* PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); */
/* PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); */
/* PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); */
}
void
@ -248,20 +243,11 @@ ODM_AntennaDiversityInit_88E(
IN PDM_ODM_T pDM_Odm
)
{
/*
//2012.03.27 LukeLee: For temp use, should be removed later
//pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
//{
struct adapter * Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
//pHalData->AntDivCfg = 1;
//}
*/
if(pDM_Odm->SupportICType != ODM_RTL8188E)
return;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n",
// pDM_Odm->AntDivType, pHalData->AntDivCfg));
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", */
/* pDM_Odm->AntDivType, pHalData->AntDivCfg)); */
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE")));
@ -296,16 +282,16 @@ ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u8 Ant)
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); /* Resp Tx */
}
else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
}
}
pDM_FatTable->RxIdleAnt = Ant;
@ -349,8 +335,8 @@ ODM_SetTxAntByTxInfo_88E(
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
// macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n", */
/* macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId])); */
}
}
@ -415,7 +401,7 @@ odm_HWAntDiv(
pEntry = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pEntry))
{
//2 Caculate RSSI per Antenna
/* 2 Caculate RSSI per Antenna */
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT;
@ -423,14 +409,14 @@ odm_HWAntDiv(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
//2 Select MaxRSSI for DIG
/* 2 Select MaxRSSI for DIG */
LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
AntDivMaxRSSI = LocalMaxRSSI;
if(LocalMaxRSSI > MaxRSSI)
MaxRSSI = LocalMaxRSSI;
//2 Select RX Idle Antenna
/* 2 Select RX Idle Antenna */
if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
Main_RSSI = Aux_RSSI;
else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
@ -445,7 +431,7 @@ odm_HWAntDiv(
#if TX_BY_REG
#else
//2 Select TRX Antenna
/* 2 Select TRX Antenna */
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i);
#endif
@ -456,7 +442,7 @@ odm_HWAntDiv(
pDM_FatTable->AuxAnt_Cnt[i] = 0;
}
//2 Set RX Idle Antenna
/* 2 Set RX Idle Antenna */
ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt);
pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
@ -471,7 +457,7 @@ ODM_AntennaDiversity_88E(
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
{
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n"));
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); */
return;
}
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
@ -512,29 +498,24 @@ ODM_AntennaDiversity_88E(
if(pDM_FatTable->bBecomeLinked == TRUE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); /* Enable CCK AntDiv */
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
}
return;
}
else
{
if(pDM_FatTable->bBecomeLinked ==FALSE)
{
} else {
if(pDM_FatTable->bBecomeLinked ==FALSE) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
//Because HW AntDiv is disabled before Link, we enable HW AntDiv after link
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv
//ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); /* Enable CCK AntDiv */
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
#if TX_BY_REG
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from Reg */
#else
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
#endif
}
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
@ -548,7 +529,7 @@ ODM_AntennaDiversity_88E(
}
#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
#else /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
void
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
@ -557,10 +538,10 @@ ODM_SetTxAntByTxInfo_88E(
)
{
}
#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
//3============================================================
//3 Dynamic Primary CCA
//3============================================================
#endif /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */
/* 3============================================================ */
/* 3 Dynamic Primary CCA */
/* 3============================================================ */
void
odm_PrimaryCCA_Init(
@ -589,14 +570,14 @@ odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm
)
{
struct adapter *Adapter = pDM_Odm->Adapter; // for NIC
prtl8192cd_priv priv = pDM_Odm->priv; // for AP
struct adapter *Adapter = pDM_Odm->Adapter; /* for NIC */
prtl8192cd_priv priv = pDM_Odm->priv; /* for AP */
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
BOOLEAN Is40MHz;
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW
BOOLEAN bConnected = FALSE; // connected or not
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; /* connected client BW */
BOOLEAN bConnected = FALSE; /* connected or not */
static u8 Client_40MHz_pre = 0;
static u64 lastTxOkCnt = 0;
static u64 lastRxOkCnt = 0;

10
hal/odm_RegConfig8188E.c
View file

@ -60,7 +60,7 @@ odm_ConfigRFReg_8188E(
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
@ -73,7 +73,7 @@ odm_ConfigRF_RadioA_8188E(
IN u32 Data
)
{
u32 content = 0x1000; // RF_Content: radioa_txt
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskforPhySet= (u32)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
@ -88,7 +88,7 @@ odm_ConfigRF_RadioB_8188E(
IN u32 Data
)
{
u32 content = 0x1001; // RF_Content: radiob_txt
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskforPhySet= (u32)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
@ -117,7 +117,7 @@ odm_ConfigBB_AGC_8188E(
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
@ -190,7 +190,7 @@ odm_ConfigBB_PHY_8188E(
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}

2
hal/odm_RegConfig8188E.h
View file

@ -74,5 +74,5 @@ odm_ConfigBB_PHY_8188E(
IN u32 Data
);
#endif // end of SUPPORT
#endif /* end of SUPPORT */

20
hal/odm_RegDefine11AC.h
View file

@ -21,32 +21,32 @@
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
/* 2 RF REG LIST */
//2 BB REG LIST
//PAGE 8
//PAGE 9
/* 2 BB REG LIST */
/* PAGE 8 */
/* PAGE 9 */
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
//PAGE A
/* PAGE A */
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE C
/* PAGE C */
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
/* PAGE E */
#define ODM_REG_IGI_B_11AC 0xE50
//PAGE F
/* PAGE F */
#define ODM_REG_OFDM_FA_11AC 0xF48
//2 MAC REG LIST
/* 2 MAC REG LIST */
//DIG Related
/* DIG Related */
#define ODM_BIT_IGI_11AC 0xFFFFFFFF

22
hal/odm_RegDefine11N.h
View file

@ -22,7 +22,7 @@
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
/* 2 RF REG LIST */
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
@ -38,8 +38,8 @@
//2 BB REG LIST
//PAGE 8
/* 2 BB REG LIST */
/* PAGE 8 */
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
@ -57,10 +57,10 @@
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
//PAGE 9
/* PAGE 9 */
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
//PAGE A
/* PAGE A */
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
@ -79,13 +79,13 @@
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
/* PAGE B */
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
/* PAGE C */
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
@ -105,12 +105,12 @@
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
/* PAGE D */
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
//PAGE E
/* PAGE E */
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
@ -149,7 +149,7 @@
//2 MAC REG LIST
/* 2 MAC REG LIST */
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
@ -164,7 +164,7 @@
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
/* DIG Related */
#define ODM_BIT_IGI_11N 0x0000007F

54
hal/odm_debug.c
View file

@ -18,9 +18,9 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
@ -34,31 +34,31 @@ pDM_Odm->DebugLevel = ODM_DBG_TRACE;
pDM_Odm->DebugComponents =
\
#if DBG
//BB Functions
// ODM_COMP_DIG |
// ODM_COMP_RA_MASK |
// ODM_COMP_DYNAMIC_TXPWR |
// ODM_COMP_FA_CNT |
// ODM_COMP_RSSI_MONITOR |
// ODM_COMP_CCK_PD |
// ODM_COMP_ANT_DIV |
// ODM_COMP_PWR_SAVE |
// ODM_COMP_PWR_TRAIN |
// ODM_COMP_RATE_ADAPTIVE |
// ODM_COMP_PATH_DIV |
// ODM_COMP_DYNAMIC_PRICCA |
// ODM_COMP_RXHP |
/* BB Functions */
/* ODM_COMP_DIG | */
/* ODM_COMP_RA_MASK | */
/* ODM_COMP_DYNAMIC_TXPWR | */
/* ODM_COMP_FA_CNT | */
/* ODM_COMP_RSSI_MONITOR | */
/* ODM_COMP_CCK_PD | */
/* ODM_COMP_ANT_DIV | */
/* ODM_COMP_PWR_SAVE | */
/* ODM_COMP_PWR_TRAIN | */
/* ODM_COMP_RATE_ADAPTIVE | */
/* ODM_COMP_PATH_DIV | */
/* ODM_COMP_DYNAMIC_PRICCA | */
/* ODM_COMP_RXHP | */
//MAC Functions
// ODM_COMP_EDCA_TURBO |
// ODM_COMP_EARLY_MODE |
//RF Functions
// ODM_COMP_TX_PWR_TRACK |
// ODM_COMP_RX_GAIN_TRACK |
// ODM_COMP_CALIBRATION |
//Common
// ODM_COMP_COMMON |
// ODM_COMP_INIT |
/* MAC Functions */
/* ODM_COMP_EDCA_TURBO | */
/* ODM_COMP_EARLY_MODE | */
/* RF Functions */
/* ODM_COMP_TX_PWR_TRACK | */
/* ODM_COMP_RX_GAIN_TRACK | */
/* ODM_COMP_CALIBRATION | */
/* Common */
/* ODM_COMP_COMMON | */
/* ODM_COMP_INIT | */
#endif
0;
}

82
hal/odm_debug.h
View file

@ -23,53 +23,53 @@
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
/* */
/* Define the debug levels */
/* */
/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */
/* So that, they can help SW engineer to develope or trace states changed */
/* and also help HW enginner to trace every operation to and from HW, */
/* e.g IO, Tx, Rx. */
/* */
/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */
/* which help us to debug SW or HW. */
/* */
/* */
/* */
/* Never used in a call to ODM_RT_TRACE()! */
/* */
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
/* */
/* Fatal bug. */
/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */
/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */
/* */
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
/* */
/* Abnormal, rare, or unexpeted cases. */
/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */
/* */
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
/* */
/* Normal case with useful information about current SW or HW state. */
/* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, */
/* SW protocol state change, dynamic mechanism state change and so on. */
/* */
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
/* */
/* Normal case with detail execution flow or information. */
/* */
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
/* */
/* Define the tracing components */
/* */
/* */
/* BB Functions */
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
@ -84,14 +84,14 @@
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
//MAC Functions
/* MAC Functions */
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
//RF Functions
/* RF Functions */
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
/* Common Functions */
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
@ -166,5 +166,5 @@ ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
);
#endif // __ODM_DBG_H__
#endif /* __ODM_DBG_H__ */

46
hal/odm_interface.c
View file

@ -18,14 +18,14 @@
*
******************************************************************************/
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include "odm_precomp.h"
//
// ODM IO Relative API.
//
/* */
/* ODM IO Relative API. */
/* */
u8
ODM_Read1Byte(
@ -165,9 +165,9 @@ ODM_GetRFReg(
RegAddr, BitMask);
}
//
// ODM Memory relative API.
//
/* */
/* ODM Memory relative API. */
/* */
void
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
@ -178,7 +178,7 @@ ODM_AllocateMemory(
*pPtr = rtw_zvmalloc(length);
}
// length could be ignored, used to detect memory leakage.
/* length could be ignored, used to detect memory leakage. */
void
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
@ -199,9 +199,9 @@ s32 ODM_CompareMemory(
return _rtw_memcmp(pBuf1,pBuf2,length);
}
//
// ODM MISC relative API.
//
/* */
/* ODM MISC relative API. */
/* */
void
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
@ -218,9 +218,9 @@ ODM_ReleaseSpinLock(
{
}
//
// Work item relative API. FOr MP driver only~!
//
/* */
/* Work item relative API. FOr MP driver only~! */
/* */
void
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
@ -267,9 +267,9 @@ ODM_IsWorkItemScheduled(
{
}
//
// ODM Timer relative API.
//
/* */
/* ODM Timer relative API. */
/* */
void
ODM_StallExecution(
IN u32 usDelay
@ -309,7 +309,7 @@ ODM_SetTimer(
IN u32 msDelay
)
{
_set_timer(pTimer,msDelay ); //ms
_set_timer(pTimer,msDelay ); /* ms */
}
void
@ -342,9 +342,9 @@ ODM_ReleaseTimer(
{
}
//
// ODM FW relative API.
//
/* */
/* ODM FW relative API. */
/* */
u32
ODM_FillH2CCmd(
IN u8 * pH2CBuffer,

70
hal/odm_interface.h
View file

@ -24,15 +24,15 @@
//
// =========== Constant/Structure/Enum/... Define
//
/* */
/* =========== Constant/Structure/Enum/... Define */
/* */
//
// =========== Macro Define
//
/* */
/* =========== Macro Define */
/* */
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
@ -58,9 +58,9 @@ ODM_REG(DIG,_pDM_Odm)
_func##_11AC(_name) \
)
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
/* _name: name of register or bit. */
/* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */
/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. */
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
@ -73,22 +73,22 @@ typedef enum _ODM_H2C_CMD
}ODM_H2C_CMD;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
/* */
/* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */
/* Suggest HW team to use thread instead of workitem. Windows also support the feature. */
/* */
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext);
//
// =========== Extern Variable ??? It should be forbidden.
//
/* */
/* =========== Extern Variable ??? It should be forbidden. */
/* */
//
// =========== EXtern Function Prototype
//
/* */
/* =========== EXtern Function Prototype */
/* */
u8
@ -178,9 +178,9 @@ ODM_GetRFReg(
);
//
// Memory Relative Function.
//
/* */
/* Memory Relative Function. */
/* */
void
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
@ -201,9 +201,9 @@ s32 ODM_CompareMemory(
IN u32 length
);
//
// ODM MISC-spin lock relative API.
//
/* */
/* ODM MISC-spin lock relative API. */
/* */
void
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
@ -217,9 +217,9 @@ ODM_ReleaseSpinLock(
);
//
// ODM MISC-workitem relative API.
//
/* */
/* ODM MISC-workitem relative API. */
/* */
void
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
@ -254,9 +254,9 @@ ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
/* */
/* ODM Timer relative API. */
/* */
void
ODM_StallExecution(
IN u32 usDelay
@ -304,9 +304,9 @@ ODM_ReleaseTimer(
);
//
// ODM FW relative API.
//
/* */
/* ODM FW relative API. */
/* */
u32
ODM_FillH2CCmd(
IN u8 * pH2CBuffer,
@ -318,4 +318,4 @@ ODM_FillH2CCmd(
IN u8 * CmdStartSeq
);
#endif // __ODM_INTERFACE_H__
#endif /* __ODM_INTERFACE_H__ */

14
hal/odm_precomp.h
View file

@ -25,7 +25,7 @@
#define TEST_FALG___ 1
//2 Config Flags and Structs - defined by each ODM Type
/* 2 Config Flags and Structs - defined by each ODM Type */
#include <drv_conf.h>
#include <osdep_service.h>
@ -33,11 +33,11 @@
#include <hal_intf.h>
//2 Hardware Parameter Files
/* 2 Hardware Parameter Files */
#include "Hal8188EFWImg_CE.h"
//2 OutSrc Header Files
/* 2 OutSrc Header Files */
#include "odm.h"
#include "odm_HWConfig.h"
@ -46,8 +46,8 @@
#include "odm_RegDefine11N.h"
#include "HalPhyRf.h"
#include "HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "Hal8188ERateAdaptive.h"//for RA,Power training
#include "HalPhyRf_8188e.h"/* for IQK,LCK,Power-tracking */
#include "Hal8188ERateAdaptive.h"/* for RA,Power training */
#include "rtl8188e_hal.h"
#include "odm_interface.h"
@ -66,10 +66,10 @@
#ifdef CONFIG_WOWLAN
#include "HalHWImg8188E_FW.h"
#endif //CONFIG_WOWLAN
#endif /* CONFIG_WOWLAN */
#include "odm_RegConfig8188E.h"
#include "odm_RTL8188E.h"
#endif // __ODM_PRECOMP_H__
#endif /* __ODM_PRECOMP_H__ */

42
hal/odm_reg.h
View file

@ -17,23 +17,23 @@
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
/* */
/* File Name: odm_reg.h */
/* */
/* Description: */
/* */
/* This file is for general register definition. */
/* */
/* */
/* */
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
/* */
/* Register Definition */
/* */
//MAC REG
/* MAC REG */
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define ODM_EDCA_VO_PARAM 0x500
@ -42,7 +42,7 @@
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
/* BB REG */
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
@ -93,24 +93,24 @@
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
/* RF REG */
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
//Ant Detect Reg
/* Ant Detect Reg */
#define ODM_DPDT 0x300
//PSD Init
/* PSD Init */
#define ODM_PSDREG 0x808
//92D Path Div
/* 92D Path Div */
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
/* */
/* Bitmap Definition */
/* */
#define BIT_FA_RESET BIT0

20
hal/odm_types.h
View file

@ -20,15 +20,15 @@
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
//
// Define Different SW team support
//
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_MP 0x08 //BIT3
/* */
/* Define Different SW team support */
/* */
#define ODM_AP 0x01 /* BIT0 */
#define ODM_ADSL 0x02 /* BIT1 */
#define ODM_CE 0x04 /* BIT2 */
#define ODM_MP 0x08 /* BIT3 */
// Deifne HW endian support
/* Deifne HW endian support */
#define ODM_ENDIAN_BIG 0
#define ODM_ENDIAN_LITTLE 1
@ -79,11 +79,11 @@ typedef void * RT_TIMER_CALL_BACK;
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
//define useless flag to avoid compile warning
/* define useless flag to avoid compile warning */
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define BT_30_SUPPORT 0
#define FPGA_TWO_MAC_VERIFICATION 0
#endif // __ODM_TYPES_H__
#endif /* __ODM_TYPES_H__ */

345
hal/rtl8188e_cmd.c
View file

@ -46,7 +46,7 @@ static u8 _is_fw_read_cmd_down(struct adapter* padapter, u8 msgbox_num)
u8 valid;
//DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num);
/* DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); */
do{
valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
@ -108,7 +108,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
if (padapter->bSurpriseRemoved == true)
goto exit;
//pay attention to if race condition happened in H2C cmd setting.
/* pay attention to if race condition happened in H2C cmd setting. */
do{
h2c_box_num = pHalData->LastHMEBoxNum;
@ -128,7 +128,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
ext_cmd_len = CmdLen-3;
memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer+3,ext_cmd_len );
//Write Ext command
/* Write Ext command */
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for(cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){
@ -139,7 +139,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
#endif
}
// Write command
/* Write command */
msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *RTL88E_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for(cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){
@ -152,11 +152,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
bcmd_down = true;
// DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n"
// ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);
pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS;
}while((!bcmd_down) && (retry_cnts--));
ret = _SUCCESS;
@ -205,15 +201,13 @@ u8 rtl8188e_set_raid_cmd(struct adapter*padapter, u32 mask)
return res;
}
//bitmap[0:27] = tx_rate_bitmap
//bitmap[28:31]= Rate Adaptive id
//arg[0:4] = macid
//arg[5] = Short GI
/* bitmap[0:27] = tx_rate_bitmap */
/* bitmap[28:31]= Rate Adaptive id */
/* arg[0:4] = macid */
/* arg[5] = Short GI */
void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
//struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 macid, init_rate, raid, shortGIrate=false;
macid = arg&0x1f;
@ -226,7 +220,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi
bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level);
bitmap |= ((raid<<28)&0xf0000000);
#endif //CONFIG_ODM_REFRESH_RAMASK
#endif /* CONFIG_ODM_REFRESH_RAMASK */
init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f;
@ -237,7 +231,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi
init_rate |= BIT(6);
//rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
/* rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate); */
raid = (bitmap>>28) & 0x0f;
@ -263,13 +257,13 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode)
{
SETPWRMODE_PARM H2CSetPwrMode;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
u8 RLBM = 0; // 0:Min, 1:Max , 2:User define
u8 RLBM = 0; /* 0:Min, 1:Max , 2:User define */
;
DBG_871X("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __FUNCTION__,
Mode, pwrpriv->smart_ps, padapter->registrypriv.uapsd_enable);
H2CSetPwrMode.AwakeInterval = 2; //DTIM =1
H2CSetPwrMode.AwakeInterval = 2; /* DTIM =1 */
switch(Mode)
{
@ -295,7 +289,7 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode)
break;
}
//H2CSetPwrMode.Mode = Mode;
/* H2CSetPwrMode.Mode = Mode; */
H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps<<4)&0xf0) | (RLBM & 0x0f));
@ -303,13 +297,13 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode)
if(Mode > 0)
{
H2CSetPwrMode.PwrState = 0x00;// AllON(0x0C), RFON(0x04), RFOFF(0x00)
H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
#ifdef CONFIG_EXT_CLK
H2CSetPwrMode.Mode |= BIT(7);//supporting 26M XTAL CLK_Request feature.
#endif //CONFIG_EXT_CLK
H2CSetPwrMode.Mode |= BIT(7);/* supporting 26M XTAL CLK_Request feature. */
#endif /* CONFIG_EXT_CLK */
}
else
H2CSetPwrMode.PwrState = 0x0C;// AllON(0x0C), RFON(0x04), RFOFF(0x00)
H2CSetPwrMode.PwrState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
FillH2CCmd_88E(padapter, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);
@ -332,12 +326,12 @@ void rtl8188e_set_FwMediaStatus_cmd(struct adapter *padapter, __le16 mstatus_rpt
reg_macid_no_link = REG_MACID_NO_LINK_1;
}
//Delete select macid (MACID 0~63) from queue list.
if(opmode == 1)// 1:connect
/* Delete select macid (MACID 0~63) from queue list. */
if(opmode == 1)/* 1:connect */
{
rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link) & (~BIT(macid))));
}
else//0: disconnect
else/* 0: disconnect */
{
rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link)|BIT(macid)));
}
@ -357,7 +351,7 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength)
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
//DBG_871X("%s\n", __FUNCTION__);
/* DBG_871X("%s\n", __FUNCTION__); */
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
@ -369,23 +363,23 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength)
memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
//pmlmeext->mgnt_seq++;
/* pmlmeext->mgnt_seq++; */
SetFrameSubType(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
//timestamp will be inserted by hardware
/* timestamp will be inserted by hardware */
pframe += 8;
pktlen += 8;
// beacon interval: 2 bytes
/* beacon interval: 2 bytes */
memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
pframe += 2;
pktlen += 2;
// capability info: 2 bytes
/* capability info: 2 bytes */
memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
pframe += 2;
@ -393,46 +387,46 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength)
if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
{
//DBG_871X("ie len=%d\n", cur_network->IELength);
/* DBG_871X("ie len=%d\n", cur_network->IELength); */
pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen);
goto _ConstructBeacon;
}
//below for ad-hoc mode
/* below for ad-hoc mode */
// SSID
/* SSID */
pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
// supported rates...
/* supported rates... */
rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen);
// DS parameter set
/* DS parameter set */
pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
{
u32 ATIMWindow;
// IBSS Parameter Set...
//ATIMWindow = cur->Configuration.ATIMWindow;
/* IBSS Parameter Set... */
/* ATIMWindow = cur->Configuration.ATIMWindow; */
ATIMWindow = 0;
pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
}
//todo: ERP IE
/* todo: ERP IE */
// EXTERNDED SUPPORTED RATE
/* EXTERNDED SUPPORTED RATE */
if (rate_len > 8)
{
pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
}
//todo:HT for adhoc
/* todo:HT for adhoc */
_ConstructBeacon:
@ -444,7 +438,7 @@ _ConstructBeacon:
*pLength = pktlen;
//DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen);
/* DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */
}
@ -456,23 +450,23 @@ static void ConstructPSPoll(struct adapter *padapter, u8 *pframe, u32 *pLength)
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//DBG_871X("%s\n", __FUNCTION__);
/* DBG_871X("%s\n", __FUNCTION__); */
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
// Frame control.
/* Frame control. */
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
SetPwrMgt(fctrl);
SetFrameSubType(pframe, WIFI_PSPOLL);
// AID.
/* AID. */
SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
// BSSID.
/* BSSID. */
memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
// TA.
/* TA. */
memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
*pLength = 16;
@ -497,7 +491,7 @@ static void ConstructNullFunctionData(
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave);
/* DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); */
pwlanhdr = (struct rtw_ieee80211_hdr*)pframe;
@ -552,10 +546,10 @@ static void ConstructNullFunctionData(
}
#ifdef CONFIG_WOWLAN
//
// Description:
// Construct the ARP response packet to support ARP offload.
//
/* */
/* Description: */
/* Construct the ARP response packet to support ARP offload. */
/* */
static void ConstructARPResponse(
struct adapter *padapter,
u8 *pframe,
@ -574,7 +568,7 @@ static void ConstructARPResponse(
__le16 *fctrl;
u32 pktlen;
u8 *pARPRspPkt = pframe;
//for TKIP Cal MIC
/* for TKIP Cal MIC */
u8 *payload = pframe;
u8 EncryptionHeadOverhead = 0;
@ -583,11 +577,11 @@ static void ConstructARPResponse(
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
//-------------------------------------------------------------------------
// MAC Header.
//-------------------------------------------------------------------------
/* */
/* MAC Header. */
/* */
SetFrameType(fctrl, WIFI_DATA);
//SetFrameSubType(fctrl, 0);
/* SetFrameSubType(fctrl, 0); */
SetToDs(fctrl);
memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
@ -595,21 +589,21 @@ static void ConstructARPResponse(
SetSeqNum(pwlanhdr, 0);
SetDuration(pwlanhdr, 0);
//SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0);
//SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data);
//SET_80211_HDR_TO_DS(pARPRspPkt, 1);
//SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid);
//SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress);
//SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid);
/* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */
/* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */
/* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */
/* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */
/* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */
/* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */
//SET_80211_HDR_DURATION(pARPRspPkt, 0);
//SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0);
/* SET_80211_HDR_DURATION(pARPRspPkt, 0); */
/* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */
*pLength = 24;
//YJ,del,120503
//-------------------------------------------------------------------------
// Security Header: leave space for it if necessary.
//-------------------------------------------------------------------------
/* YJ,del,120503 */
/* */
/* Security Header: leave space for it if necessary. */
/* */
switch (psecuritypriv->dot11PrivacyAlgrthm)
{
@ -636,25 +630,24 @@ static void ConstructARPResponse(
{
memset(&(pframe[*pLength]), 0,EncryptionHeadOverhead);
*pLength += EncryptionHeadOverhead;
//SET_80211_HDR_WEP(pARPRspPkt, 1); //Suggested by CCW.
SetPrivacy(fctrl);
}
//-------------------------------------------------------------------------
// Frame Body.
//-------------------------------------------------------------------------
/* */
/* Frame Body. */
/* */
pARPRspPkt = (u8*)(pframe+ *pLength);
// LLC header
/* LLC header */
memcpy(pARPRspPkt, ARPLLCHeader, 8);
*pLength += 8;
// ARP element
/* ARP element */
pARPRspPkt += 8;
SET_ARP_PKT_HW(pARPRspPkt, 0x0100);
SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); // IP protocol
SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); /* IP protocol */
SET_ARP_PKT_HW_ADDR_LEN(pARPRspPkt, 6);
SET_ARP_PKT_PROTOCOL_ADDR_LEN(pARPRspPkt, 4);
SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); // ARP response
SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); /* ARP response */
SET_ARP_PKT_SENDER_MAC_ADDR(pARPRspPkt, myid(&(padapter->eeprompriv)));
SET_ARP_PKT_SENDER_IP_ADDR(pARPRspPkt, pIPAddress);
#ifdef CONFIG_ARP_KEEP_ALIVE
@ -686,18 +679,18 @@ static void ConstructARPResponse(
if(_rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],null_key, 16)==true){
DBG_871X("%s(): STA dot11tkiptxmickey==0\n",__FUNCTION__);
}
//start to calculate the mic code
/* start to calculate the mic code */
rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);
}
rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); //DA
rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */
rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); //SA
rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
priority[0]=0;
rtw_secmicappend(&micdata, &priority[0], 4);
rtw_secmicappend(&micdata, payload, 36); //payload length = 8 + 28
rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
rtw_secgetmic(&micdata,&(mic[0]));
@ -714,8 +707,8 @@ static void rtl8188e_set_FwRsvdPage_cmd(struct adapter *padapter, PRSVDPAGE_LOC
u8 u1H2CRsvdPageParm[H2C_8188E_RSVDPAGE_LOC_LEN]={0};
u8 u1H2CAoacRsvdPageParm[H2C_8188E_AOAC_RSVDPAGE_LOC_LEN]={0};
//DBG_871X("8188RsvdPageLoc: PsPoll=%d Null=%d QoSNull=%d\n",
// rsvdpageloc->LocPsPoll, rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull);
/* DBG_871X("8188RsvdPageLoc: PsPoll=%d Null=%d QoSNull=%d\n", */
/* rsvdpageloc->LocPsPoll, rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull); */
SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll);
SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData);
@ -724,7 +717,7 @@ static void rtl8188e_set_FwRsvdPage_cmd(struct adapter *padapter, PRSVDPAGE_LOC
FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, H2C_8188E_RSVDPAGE_LOC_LEN, u1H2CRsvdPageParm);
#ifdef CONFIG_WOWLAN
//DBG_871X("8188E_AOACRsvdPageLoc: RWC=%d ArpRsp=%d\n", rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp);
/* DBG_871X("8188E_AOACRsvdPageLoc: RWC=%d ArpRsp=%d\n", rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp); */
SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);
SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);
@ -732,8 +725,8 @@ static void rtl8188e_set_FwRsvdPage_cmd(struct adapter *padapter, PRSVDPAGE_LOC
#endif
}
// To check if reserved page content is destroyed by beacon beacuse beacon is too large.
// 2010.06.23. Added by tynli.
/* To check if reserved page content is destroyed by beacon beacuse beacon is too large. */
/* 2010.06.23. Added by tynli. */
void
CheckFwRsvdPageContent(
IN struct adapter * Adapter
@ -752,16 +745,16 @@ CheckFwRsvdPageContent(
}
}
//
// Description: Fill the reserved packets that FW will use to RSVD page.
// Now we just send 4 types packet to rsvd page.
// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
// Input:
// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw,
// so we need to set the packet length to total lengh.
// TRUE: At the second time, we should send the first packet (default:beacon)
// to Hw again and set the lengh in descriptor to the real beacon lengh.
// 2009.10.15 by tynli.
/* */
/* Description: Fill the reserved packets that FW will use to RSVD page. */
/* Now we just send 4 types packet to rsvd page. */
/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */
/* Input: */
/* bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw, */
/* so we need to set the packet length to total lengh. */
/* TRUE: At the second time, we should send the first packet (default:beacon) */
/* to Hw again and set the lengh in descriptor to the real beacon lengh. */
/* 2009.10.15 by tynli. */
static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
{
PHAL_DATA_TYPE pHalData;
@ -800,14 +793,14 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
TxDescLen = TXDESC_SIZE;
PageNum = 0;
//3 (1) beacon * 2 pages
/* 3 (1) beacon * 2 pages */
BufIndex = TXDESC_OFFSET;
ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength);
// When we count the first page size, we need to reserve description size for the RSVD
// packet, it will be filled in front of the packet in TXPKTBUF.
/* When we count the first page size, we need to reserve description size for the RSVD */
/* packet, it will be filled in front of the packet in TXPKTBUF. */
PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);
// To reserved 2 pages for beacon buffer. 2010.06.24.
/* To reserved 2 pages for beacon buffer. 2010.06.24. */
if (PageNeed == 1)
PageNeed += 1;
PageNum += PageNeed;
@ -815,7 +808,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
BufIndex += PageNeed*128;
//3 (2) ps-poll *1 page
/* 3 (2) ps-poll *1 page */
RsvdPageLoc.LocPsPoll = PageNum;
ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength);
rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, true, false);
@ -825,7 +818,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
BufIndex += PageNeed*128;
//3 (3) null data * 1 page
/* 3 (3) null data * 1 page */
RsvdPageLoc.LocNullData = PageNum;
ConstructNullFunctionData(
padapter,
@ -840,7 +833,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
BufIndex += PageNeed*128;
//3 (5) Qos null data
/* 3 (5) Qos null data */
RsvdPageLoc.LocQosNull = PageNum;
ConstructNullFunctionData(
padapter,
@ -856,7 +849,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
BufIndex += PageNeed*128;
#ifdef CONFIG_WOWLAN
//3(7) ARP
/* 3(7) ARP */
rtw_get_current_ip_address(padapter, currentip);
RsvdPageLoc.LocArpRsp = PageNum;
ConstructARPResponse(
@ -891,12 +884,12 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
BufIndex += PageNeed*128;
//3(8) sec IV
/* 3(8) sec IV */
rtw_get_sec_iv(padapter, cur_dot11txpn, get_my_bssid(&pmlmeinfo->network));
RsvdPageLoc.LocRemoteCtrlInfo = PageNum;
memcpy(ReservedPagePacket+BufIndex-TxDescLen, cur_dot11txpn, 8);
TotalPacketLen = BufIndex-TxDescLen + sizeof (union pn48); //IV len
TotalPacketLen = BufIndex-TxDescLen + sizeof (union pn48); /* IV len */
#else
TotalPacketLen = BufIndex + QosNullLength;
#endif
@ -905,7 +898,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
if (pmgntframe == NULL)
goto exit;
// update attribute
/* update attribute */
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(padapter, pattrib);
pattrib->qsel = 0x10;
@ -920,7 +913,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished)
DBG_871X("%s: Set RSVD page location to Fw\n", __FUNCTION__);
rtl8188e_set_FwRsvdPage_cmd(padapter, &RsvdPageLoc);
//FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc);
/* FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc); */
exit:
rtw_mfree(ReservedPagePacket, RTL88E_RSVDPAGE_SIZE);
@ -947,24 +940,24 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
if(mstatus == 1)
{
// We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.
// Suggested by filen. Added by tynli.
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
// Do not set TSF again here or vWiFi beacon DMA INT will not work.
//correct_TSF(padapter, pmlmeext);
// Hw sequende enable by dedault. 2010.06.23. by tynli.
//rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF));
//rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
/* correct_TSF(padapter, pmlmeext); */
/* Hw sequende enable by dedault. 2010.06.23. by tynli. */
/* rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */
/* rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */
//Set REG_CR bit 8. DMA beacon by SW.
/* Set REG_CR bit 8. DMA beacon by SW. */
pHalData->RegCR_1 |= BIT0;
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
// Disable Hw protection for a time which revserd for Hw sending beacon.
// Fix download reserved page packet fail that access collision with the protection time.
// 2010.05.11. Added by tynli.
//SetBcnCtrlReg(padapter, 0, BIT3);
//SetBcnCtrlReg(padapter, BIT4, 0);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
/* 2010.05.11. Added by tynli. */
/* SetBcnCtrlReg(padapter, 0, BIT3); */
/* SetBcnCtrlReg(padapter, BIT4, 0); */
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
@ -974,31 +967,31 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
bSendBeacon = true;
}
// Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6)));
pHalData->RegFwHwTxQCtrl &= (~BIT6);
// Clear beacon valid check bit.
/* Clear beacon valid check bit. */
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DLBcnCount = 0;
poll = 0;
do
{
// download rsvd page.
/* download rsvd page. */
SetFwRsvdPagePkt(padapter, false);
DLBcnCount++;
do
{
rtw_yield_os();
//rtw_mdelay_os(10);
// check rsvd page download OK.
/* rtw_mdelay_os(10); */
/* check rsvd page download OK. */
rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));
poll++;
} while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n"));
/* RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n")); */
if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
@ -1006,13 +999,13 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
DBG_871X("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll);
else
DBG_871X("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll);
//
// We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower)
// becuase we need to free the Tx BCN Desc which is used by the first reserved page packet.
// At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return
// the beacon TCB in the following code. 2011.11.23. by tynli.
//
//if(bcn_valid && padapter->bEnterPnpSleep)
/* */
/* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */
/* becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. */
/* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */
/* the beacon TCB in the following code. 2011.11.23. by tynli. */
/* */
/* if(bcn_valid && padapter->bEnterPnpSleep) */
if(0)
{
if(bSendBeacon)
@ -1028,14 +1021,14 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
do
{
rtw_yield_os();
//rtw_mdelay_os(10);
// check rsvd page download OK.
/* rtw_mdelay_os(10); */
/* check rsvd page download OK. */
rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));
poll++;
} while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n"));
/* RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n")); */
if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
@ -1046,37 +1039,37 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
}
}
// Enable Bcn
//SetBcnCtrlReg(padapter, BIT3, 0);
//SetBcnCtrlReg(padapter, 0, BIT4);
/* Enable Bcn */
/* SetBcnCtrlReg(padapter, BIT3, 0); */
/* SetBcnCtrlReg(padapter, 0, BIT4); */
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4)));
// To make sure that if there exists an adapter which would like to send beacon.
// If exists, the origianl value of 0x422[6] will be 1, we should check this to
// prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
// the beacon cannot be sent by HW.
// 2010.06.23. Added by tynli.
/* To make sure that if there exists an adapter which would like to send beacon. */
/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if(bSendBeacon)
{
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));
pHalData->RegFwHwTxQCtrl |= BIT6;
}
//
// Update RSVD page location H2C to Fw.
//
/* */
/* Update RSVD page location H2C to Fw. */
/* */
if(bcn_valid)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DBG_871X("Set RSVD page location to Fw.\n");
//FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc);
/* FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc); */
}
// Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.
//if(!padapter->bEnterPnpSleep)
/* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */
/* if(!padapter->bEnterPnpSleep) */
{
// Clear CR[8] or beacon packet will not be send to TxBuf anymore.
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
pHalData->RegCR_1 &= (~BIT0);
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
}
@ -1095,7 +1088,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
} else {
DBG_871X_LEVEL(_drv_info_, "%s wowlan_mode is off\n", __func__);
}
#endif //CONFIG_WOWLAN
#endif /* CONFIG_WOWLAN */
;
}
@ -1119,40 +1112,40 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state)
break;
case P2P_PS_ENABLE:
DBG_8192C("P2P_PS_ENABLE \n");
// update CTWindow value.
/* update CTWindow value. */
if( pwdinfo->ctwindow > 0 )
{
p2p_ps_offload->CTWindow_En = 1;
rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
}
// hw only support 2 set of NoA
/* hw only support 2 set of NoA */
for( i=0 ; i<pwdinfo->noa_num ; i++)
{
// To control the register setting for which NOA
/* To control the register setting for which NOA */
rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
if(i == 0)
p2p_ps_offload->NoA0_En = 1;
else
p2p_ps_offload->NoA1_En = 1;
// config P2P NoA Descriptor Register
//DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]);
/* config P2P NoA Descriptor Register */
/* DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); */
rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
//DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]);
/* DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); */
rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
//DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]);
/* DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); */
rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
//DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]);
/* DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); */
rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
}
if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )
{
// rst p2p circuit
/* rst p2p circuit */
rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->Offload_En = 1;
@ -1189,7 +1182,7 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state)
;
}
#endif //CONFIG_P2P_PS
#endif /* CONFIG_P2P_PS */
#ifdef CONFIG_TSF_RESET_OFFLOAD
/*
@ -1237,7 +1230,7 @@ int reset_tsf(struct adapter *Adapter, u8 reset_port )
}
#endif // CONFIG_TSF_RESET_OFFLOAD
#endif /* CONFIG_TSF_RESET_OFFLOAD */
#ifdef CONFIG_WOWLAN
#ifdef CONFIG_GPIO_WAKEUP
@ -1281,7 +1274,7 @@ void rtl8188es_set_output_gpio(struct adapter* padapter, u8 index, u8 outputval)
}
}
}
#endif //CONFIG_GPIO_WAKEUP
#endif /* CONFIG_GPIO_WAKEUP */
void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
{
@ -1294,7 +1287,7 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
struct security_priv *psecpriv = &padapter->securitypriv;
#ifdef CONFIG_GPIO_WAKEUP
u8 gpio_wake_pin = 7;
u8 gpio_high_active = 0; //default low active
u8 gpio_high_active = 0; /* default low active */
#endif
;
@ -1329,16 +1322,16 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP;
pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP;
//DataPinWakeUp
/* DataPinWakeUp */
pwowlan_parm.gpio_index=0x0;
#ifdef CONFIG_GPIO_WAKEUP
pwowlan_parm.gpio_index = gpio_wake_pin;
//WOWLAN_GPIO_ACTIVE means GPIO high active
//pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE;
/* WOWLAN_GPIO_ACTIVE means GPIO high active */
/* pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; */
if (gpio_high_active)
pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE;
#endif //CONFIG_GPIO_WAKEUP
#endif /* CONFIG_GPIO_WAKEUP */
DBG_871X_LEVEL(_drv_info_, "%s 5.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode);
DBG_871X_LEVEL(_drv_info_, "%s 6.pwowlan_parm.index=0x%x \n",__FUNCTION__,pwowlan_parm.gpio_index);
@ -1346,19 +1339,19 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
rtw_msleep_os(2);
//disconnect decision
/* disconnect decision */
pwowlan_parm.mode =1;
pwowlan_parm.gpio_index=0;
pwowlan_parm.gpio_duration=0;
FillH2CCmd_88E(padapter, H2C_COM_DISCNT_DECISION, 3, (u8 *)&pwowlan_parm);
//keep alive period = 10 * 10 BCN interval
/* keep alive period = 10 * 10 BCN interval */
pwowlan_parm.mode = FW_WOWLAN_KEEP_ALIVE_EN | FW_ADOPT_USER | FW_WOWLAN_KEEP_ALIVE_PKT_TYPE;
pwowlan_parm.gpio_index=10;
res = FillH2CCmd_88E(padapter, H2C_COM_KEEP_ALIVE, 2, (u8 *)&pwowlan_parm);
rtw_msleep_os(2);
//Configure STA security information for GTK rekey wakeup event.
/* Configure STA security information for GTK rekey wakeup event. */
paoac_global_info_parm.pairwiseEncAlg=
padapter->securitypriv.dot11PrivacyAlgrthm;
paoac_global_info_parm.groupEncAlg=
@ -1366,7 +1359,7 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
res = FillH2CCmd_88E(padapter, H2C_COM_AOAC_GLOBAL_INFO, 2, (u8 *)&paoac_global_info_parm);
rtw_msleep_os(2);
//enable Remote wake ctrl
/* enable Remote wake ctrl */
pwowlan_parm.mode = FW_REMOTE_WAKE_CTRL_EN | FW_WOW_FW_UNICAST_EN | FW_ARP_EN;
if (psecpriv->dot11PrivacyAlgrthm == _AES_ || psecpriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)
{
@ -1381,7 +1374,7 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
pwrpriv->wowlan_magic =false;
#ifdef CONFIG_GPIO_WAKEUP
rtl8188es_set_output_gpio(padapter, gpio_wake_pin, !gpio_high_active);
#endif //CONFIG_GPIO_WAKEUP
#endif /* CONFIG_GPIO_WAKEUP */
res = FillH2CCmd_88E(padapter, H2C_COM_WWLAN, 2, (u8 *)&pwowlan_parm);
rtw_msleep_os(2);
res = FillH2CCmd_88E(padapter, H2C_COM_REMOTE_WAKE_CTRL, 3, (u8 *)&pwowlan_parm);
@ -1390,4 +1383,4 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable)
DBG_871X_LEVEL(_drv_always_, "-%s res:%d-\n", __func__, res);
return ;
}
#endif //CONFIG_WOWLAN
#endif /* CONFIG_WOWLAN */

141
hal/rtl8188e_dm.c
View file

@ -17,27 +17,27 @@
*
*
******************************************************************************/
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
/* */
/* Description: */
/* */
/* This file is for 92CE/92CU dynamic mechanism only */
/* */
/* */
/* */
#define _RTL8188E_DM_C_
//============================================================
// include files
//============================================================
/* */
/* include files */
/* */
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtl8188e_hal.h>
//============================================================
// Global var
//============================================================
/* */
/* Global var */
/* */
static void
@ -64,14 +64,14 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte |= (HAL_8188E_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level
rtw_write8(padapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
tmp1byte =rtw_read8(padapter, GPIO_IN);
@ -84,8 +84,8 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
}
if( true == bPbcPressed)
{
// Here we only set bPbcPressed to true
// After trigger PBC, the variable will be set to false
/* Here we only set bPbcPressed to true */
/* After trigger PBC, the variable will be set to false */
DBG_8192C("CheckPbcGPIO - PBC is pressed\n");
#ifdef RTK_DMP_PLATFORM
@ -97,7 +97,7 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
#else
if ( padapter->pid[0] == 0 )
{ // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver.
{ /* 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */
return;
}
rtw_signal_process(padapter->pid[0], SIGUSR1);
@ -105,9 +105,9 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
}
}
//
// Initialize GPIO setting registers
//
/* */
/* Initialize GPIO setting registers */
/* */
static void
dm_InitGPIOSetting(
IN struct adapter *Adapter
@ -121,7 +121,7 @@ dm_InitGPIOSetting(
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
#ifdef CONFIG_BT_COEXIST
// UMB-B cut bug. We need to support the modification.
/* UMB-B cut bug. We need to support the modification. */
if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
pHalData->bt_coexist.BT_Coexist)
{
@ -132,9 +132,9 @@ dm_InitGPIOSetting(
}
//============================================================
// functions
//============================================================
/* */
/* functions */
/* */
static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
{
@ -143,9 +143,9 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
u8 cut_ver,fab_ver;
//
// Init Value
//
/* */
/* Init Value */
/* */
memset(pDM_Odm, 0, sizeof(*pDM_Odm));
pDM_Odm->Adapter = Adapter;
@ -155,7 +155,7 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
if(Adapter->interface_type == RTW_GSPI )
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);
else
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);/* RTL871X_HCI_TYPE */
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8188E);
@ -168,7 +168,7 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);
// ODM_CMNINFO_BINHCT_TEST only for MP Team
/* ODM_CMNINFO_BINHCT_TEST only for MP Team */
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
@ -188,10 +188,10 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
pdmpriv->InitODMFlag = 0;
#else
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |
ODM_RF_TX_PWR_TRACK //|
ODM_RF_TX_PWR_TRACK /* */
;
//if(pHalData->AntDivCfg)
// pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
/* if(pHalData->AntDivCfg) */
/* pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; */
#endif
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
@ -238,11 +238,11 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
| ODM_RF_TX_PWR_TRACK
;
}
#endif//(MP_DRIVER==1)
#endif/* MP_DRIVER==1) */
#ifdef CONFIG_DISABLE_ODM
pdmpriv->InitODMFlag = 0;
#endif//CONFIG_DISABLE_ODM
#endif/* CONFIG_DISABLE_ODM */
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
@ -257,18 +257,7 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp));
//================= only for 8192D =================
/*
//pHalData->CurrentBandType92D
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u8_temp));
//================= only for 8192D =================
// driver havn't those variable now
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u8_temp));
*/
/* only for 8192D ================= */
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));
@ -276,7 +265,7 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
for(i=0; i< NUM_STA; i++)
{
//pDM_Odm->pODM_StaInfo[i] = NULL;
/* pDM_Odm->pODM_StaInfo[i] = NULL; */
ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);
}
}
@ -327,23 +316,23 @@ rtl8188e_HalDmWatchDog(
#endif
#ifdef CONFIG_P2P_PS
// Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
// modifed by thomas. 2011.06.11.
/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
/* modifed by thomas. 2011.06.11. */
if(Adapter->wdinfo.p2p_ps_mode)
bFwPSAwake = false;
#endif //CONFIG_P2P_PS
#endif /* CONFIG_P2P_PS */
if( (hw_init_completed == true)
&& ((!bFwCurrentInPSMode) && bFwPSAwake))
{
//
// Calculate Tx/Rx statistics.
//
/* */
/* Calculate Tx/Rx statistics. */
/* */
dm_CheckStatistics(Adapter);
}
//ODM
/* ODM */
if (hw_init_completed == true)
{
u8 bLinked=false;
@ -369,8 +358,8 @@ rtl8188e_HalDmWatchDog(
skip_dm:
// Check GPIO to determine current RF on/off and Pbc status.
// Check Hardware Radio ON/OFF or not
/* Check GPIO to determine current RF on/off and Pbc status. */
/* Check Hardware Radio ON/OFF or not */
return;
}
@ -380,10 +369,10 @@ void rtl8188e_init_dm_priv(IN struct adapter *Adapter)
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
memset(pdmpriv, 0, sizeof(struct dm_priv));
//_rtw_spinlock_init(&(pHalData->odm_stainfo_lock));
/* _rtw_spinlock_init(&(pHalData->odm_stainfo_lock)); */
Init_ODM_ComInfo_88E(Adapter);
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter);
/* _init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter); */
ODM_InitAllTimers(podmpriv );
#endif
ODM_InitDebugSetting(podmpriv);
@ -394,29 +383,29 @@ void rtl8188e_deinit_dm_priv(IN struct adapter *Adapter)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);
/* _rtw_spinlock_free(&pHalData->odm_stainfo_lock); */
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);
/* _cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer); */
ODM_CancelAllTimers(podmpriv);
#endif
}
#ifdef CONFIG_ANTENNA_DIVERSITY
// Add new function to reset the state of antenna diversity before link.
//
// Compare RSSI for deciding antenna
/* Add new function to reset the state of antenna diversity before link. */
/* */
/* Compare RSSI for deciding antenna */
void AntDivCompare8188E(struct adapter *Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
{
//struct adapter *Adapter = pDM_Odm->Adapter ;
/* struct adapter *Adapter = pDM_Odm->Adapter ; */
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(0 != pHalData->AntDivCfg )
{
//DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
// src->Rssi,query_rx_pwr_percentage(src->Rssi));
//select optimum_antenna for before linked =>For antenna diversity
if(dst->Rssi >= src->Rssi )//keep org parameter
/* DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi), */
/* src->Rssi,query_rx_pwr_percentage(src->Rssi)); */
/* select optimum_antenna for before linked =>For antenna diversity */
if(dst->Rssi >= src->Rssi )/* keep org parameter */
{
src->Rssi = dst->Rssi;
src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
@ -424,7 +413,7 @@ void AntDivCompare8188E(struct adapter *Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_
}
}
// Add new function to reset the state of antenna diversity before link.
/* Add new function to reset the state of antenna diversity before link. */
u8 AntDivBeforeLink8188E(struct adapter *Adapter )
{
@ -433,10 +422,10 @@ u8 AntDivBeforeLink8188E(struct adapter *Adapter )
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
// Condition that does not need to use antenna diversity.
/* Condition that does not need to use antenna diversity. */
if(pHalData->AntDivCfg==0)
{
//DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
/* DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n"); */
return false;
}
@ -447,13 +436,13 @@ u8 AntDivBeforeLink8188E(struct adapter *Adapter )
if(pDM_SWAT_Table->SWAS_NoLink_State == 0){
//switch channel
/* switch channel */
pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
/* PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna); */
rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, false);
//DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B");
/* DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"); */
return true;
}
else

677
hal/rtl8188e_hal_init.c
View file

File diff suppressed because it is too large Load diff

1136
hal/rtl8188e_phycfg.c
View file

File diff suppressed because it is too large Load diff

259
hal/rtl8188e_rf6052.c
View file

@ -48,17 +48,17 @@
#include <rtl8188e_hal.h>
/*---------------------------Define Local Constant---------------------------*/
// Define local structure for debug!!!!!
/* Define local structure for debug!!!!! */
typedef struct RF_Shadow_Compare_Map {
// Shadow register value
/* Shadow register value */
u32 Value;
// Compare or not flag
/* Compare or not flag */
u8 Compare;
// Record If it had ever modified unpredicted
/* Record If it had ever modified unpredicted */
u8 ErrorOrNot;
// Recorver Flag
/* Recorver Flag */
u8 Recorver;
//
/* */
u8 Driver_Write;
}RF_SHADOW_T;
/*---------------------------Define Local Constant---------------------------*/
@ -69,8 +69,8 @@ typedef struct RF_Shadow_Compare_Map {
/*------------------------Define local variable------------------------------*/
// 2008/11/20 MH For Debug only, RF
//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
/* 2008/11/20 MH For Debug only, RF */
/* static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */
static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
/*------------------------Define local variable------------------------------*/
@ -80,7 +80,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
*
* Overview: For RL6052, we must change some RF settign for 1T or 2T.
*
* Input: u16 DataRate // 0x80-8f, 0x90-9f
* Input: u16 DataRate 0x80-8f, 0x90-9f
*
* Output: NONE
*
@ -95,7 +95,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
/* We do not support gain table change inACUT now !!!! Delete later !!! */
} /* RF_ChangeTxPath */
@ -105,7 +105,7 @@ void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: struct adapter * Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
*
@ -116,7 +116,7 @@ void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
void
rtl8188e_PHY_RF6052SetBandwidth(
IN struct adapter * Adapter,
IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
IN HT_CHANNEL_WIDTH Bandwidth) /* 20M or 40M */
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -133,7 +133,6 @@ rtl8188e_PHY_RF6052SetBandwidth(
break;
default:
//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
@ -166,13 +165,11 @@ rtl8188e_PHY_RF6052SetCckTxPower(
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
//PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
BOOLEAN TurboScanOff = false;
u8 idx1, idx2;
u8* ptr;
u8 direction;
//FOR CE ,must disable turbo scan
TurboScanOff = true;
@ -181,7 +178,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;//disable turbo scan
TurboScanOff = true;/* disable turbo scan */
if(TurboScanOff)
{
@ -190,7 +187,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
// 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
TxAGC[idx1] = 0x20;
}
@ -198,9 +195,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
}
else
{
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
{
TxAGC[RF_PATH_A] = 0x10101010;
@ -235,16 +232,16 @@ rtl8188e_PHY_RF6052SetCckTxPower(
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
//printk("ODM_TxPwrTrackAdjust88E => direction:%02x, pwrtrac_value:%d \n", direction, pwrtrac_value);
//printk(" ==> TxAGC:0x%08x \n",TxAGC[0] );
/* printk("ODM_TxPwrTrackAdjust88E => direction:%02x, pwrtrac_value:%d \n", direction, pwrtrac_value); */
/* printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); */
if (direction == 1) // Increase TX pwoer
if (direction == 1) /* Increase TX pwoer */
{
TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value;
}
else if (direction == 2) // Decrease TX pwoer
else if (direction == 2) /* Decrease TX pwoer */
{
TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value;
@ -260,31 +257,22 @@ rtl8188e_PHY_RF6052SetCckTxPower(
ptr++;
}
}
//printk(" ==> TxAGC:0x%08x \n",TxAGC[0] );
/* printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); */
// rf-A cck tx power
/* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A]&0xff;
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
//printk("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32);
/* printk("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32); */
tmpval = TxAGC[RF_PATH_A]>>8;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
//printk("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11);
/* printk("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11); */
/*
// rf-B cck tx power
tmpval = TxAGC[RF_PATH_B]>>24;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
//printk("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11);
tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
//printk("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",tmpval, rTxAGC_B_CCK1_55_Mcs32);
*/
} /* PHY_RF6052SetCckTxPower */
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
/* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */
static void getPowerBase88E(
IN struct adapter *Adapter,
IN u8* pPowerLevelOFDM,
@ -307,12 +295,12 @@ static void getPowerBase88E(
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
*(OfdmBase+i) = powerBase0;
//DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i));
/* DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)); */
}
for(i=0; i<pHalData->NumTotalRFPath; i++)
{
//Check HT20 to HT40 diff
/* Check HT20 to HT40 diff */
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
powerlevel[i] = pPowerLevelBW20[i];
@ -324,7 +312,7 @@ static void getPowerBase88E(
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
*(MCSBase+i) = powerBase1;
//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
/* DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)); */
}
}
@ -345,38 +333,38 @@ static void getTxPowerWriteValByRegulatory88E(
u32 writeVal, customer_limit, rf;
u8 Regulatory = pHalData->EEPROMRegulatory;
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
/* */
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
/* */
for(rf=0; rf<2; rf++) {
switch(Regulatory) {
case 0: // Realtek better performance
// increase power diff defined by Realtek for large power
case 0: /* Realtek better performance */
/* increase power diff defined by Realtek for large power */
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
/* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */
/* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
/* RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
break;
case 1: // Realtek regulatory
// increase power diff defined by Realtek for regulatory
case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */
{
if(pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
//if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
/* if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) */
{
if (Channel < 3) // Chanel 1-2
if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0;
else if (Channel < 6) // Channel 3-5
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if(Channel <9) // Channel 6-8
else if(Channel <9) /* Channel 6-8 */
chnlGroup = 2;
else if(Channel <12) // Channel 9-11
else if(Channel <12) /* Channel 9-11 */
chnlGroup = 3;
else if(Channel <14) // Channel 12-13
else if(Channel <14) /* Channel 12-13 */
chnlGroup = 4;
else if(Channel ==14) // Channel 14
else if(Channel ==14) /* Channel 14 */
chnlGroup = 4;
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
@ -399,23 +387,23 @@ static void getTxPowerWriteValByRegulatory88E(
chnlGroup+=4;
*/
}
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
/* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */
/* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
/* RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
}
break;
case 2: // Better regulatory
// don't increase any power diff
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
/* RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
break;
case 3: // Customer defined power diff.
// increase power diff defined by customer.
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
/* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */
/* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */
/*
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
@ -434,14 +422,14 @@ static void getTxPowerWriteValByRegulatory88E(
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
//RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff));
/* RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff)); */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
else
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
//RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit));
/* RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit)); */
if(pwr_diff >= customer_pwr_limit)
pwr_diff = 0;
@ -457,46 +445,39 @@ static void getTxPowerWriteValByRegulatory88E(
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
/* RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); */
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
/* RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
/* RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
break;
}
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
//92d do not need this
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
/* 92d do not need this */
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
// 20100628 Joseph: High power mode for BT-Coexist mechanism.
// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
/* RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); */
writeVal = writeVal - 0x06060606;
}
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
/* RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); */
writeVal = writeVal ;
}
/*
if(pMgntInfo->bDisableTXPowerByRate)
{
// add for OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate
writeVal = 0x2c2c2c2c;
}
*/
*(pOutWriteVal+rf) = writeVal;
}
}
@ -535,9 +516,9 @@ static void writeOFDMPowerReg88E(
RegOffset = RegOffset_B[index];
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
//printk("Set OFDM tx pwr- 0x%x = %08x\n", RegOffset, writeVal);
/* printk("Set OFDM tx pwr- 0x%x = %08x\n", RegOffset, writeVal); */
// 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if(((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
((pHalData->rf_type != RF_2T2R) &&
@ -598,14 +579,14 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
u8 index = 0;
//DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel);
/* DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel); */
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
//
// 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power.
// This is ued to fix unstable power tracking mode.
//
/* */
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
/* This is ued to fix unstable power tracking mode. */
/* */
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
for(index=0; index<6; index++)
@ -635,10 +616,10 @@ phy_RF6052_Config_HardCode(
)
{
// Set Default Bandwidth to 20M
//Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
/* Set Default Bandwidth to 20M */
/* Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); */
// TODO: Set Default Channel to channel one for RTL8225
/* TODO: Set Default Channel to channel one for RTL8225 */
}
@ -664,10 +645,10 @@ phy_RF6052_Config_ParaFile(
pszRadioBFile = sz88eRadioBFile;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
/* for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
@ -688,18 +669,18 @@ phy_RF6052_Config_ParaFile(
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
@ -711,10 +692,10 @@ phy_RF6052_Config_ParaFile(
rtStatus= _FAIL;
#else
rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
#endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */
#else
rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
#endif//#ifdef CONFIG_EMBEDDED_FWIMG
#endif/* ifdef CONFIG_EMBEDDED_FWIMG */
break;
case RF_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
@ -723,7 +704,7 @@ phy_RF6052_Config_ParaFile(
rtStatus= _FAIL;
#else
rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
#endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM
#endif /* ifdef CONFIG_PHY_SETTING_WITH_ODM */
#else
rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
#endif
@ -748,13 +729,13 @@ phy_RF6052_Config_ParaFile(
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
/* RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
@ -769,26 +750,26 @@ PHY_RF6052_Config8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
//
// Initialize general global value
//
// TODO: Extend RF_PATH_C and RF_PATH_D in the future
/* */
/* Initialize general global value */
/* */
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
if(pHalData->rf_type == RF_1T1R)
pHalData->NumTotalRFPath = 1;
else
pHalData->NumTotalRFPath = 2;
//
// Config BB and RF
//
/* */
/* Config BB and RF */
/* */
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
return rtStatus;
}
//
// ==> RF shadow Operation API Code Section!!!
//
/* */
/* ==> RF shadow Operation API Code Section!!! */
/* */
/*-----------------------------------------------------------------------------
* Function: PHY_RFShadowRead
* PHY_RFShadowWrite
@ -845,18 +826,18 @@ PHY_RFShadowCompare(
IN u32 Offset)
{
u32 reg;
// Check if we need to check the register
/* Check if we need to check the register */
if (RF_Shadow[eRFPath][Offset].Compare == true)
{
reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
// Compare shadow and real rf register for 20bits!!
/* Compare shadow and real rf register for 20bits!! */
if (RF_Shadow[eRFPath][Offset].Value != reg)
{
// Locate error position.
/* Locate error position. */
RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
//RT_TRACE(COMP_INIT, DBG_LOUD,
//("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",
//eRFPath, Offset, reg));
/* RT_TRACE(COMP_INIT, DBG_LOUD, */
/* PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", */
/* eRFPath, Offset, reg)); */
}
return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
}
@ -870,17 +851,17 @@ PHY_RFShadowRecorver(
IN RF_RADIO_PATH_E eRFPath,
IN u32 Offset)
{
// Check if the address is error
/* Check if the address is error */
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
{
// Check if we need to recorver the register.
/* Check if we need to recorver the register. */
if (RF_Shadow[eRFPath][Offset].Recorver == true)
{
PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
RF_Shadow[eRFPath][Offset].Value);
//RT_TRACE(COMP_INIT, DBG_LOUD,
//("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
//eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
/* RT_TRACE(COMP_INIT, DBG_LOUD, */
/* PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", */
/* eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); */
}
}
@ -930,7 +911,7 @@ PHY_RFShadowCompareFlagSet(
IN u32 Offset,
IN u8 Type)
{
// Set True or False!!!
/* Set True or False!!! */
RF_Shadow[eRFPath][Offset].Compare = Type;
} /* PHY_RFShadowCompareFlagSet */
@ -943,7 +924,7 @@ PHY_RFShadowRecorverFlagSet(
IN u32 Offset,
IN u8 Type)
{
// Set True or False!!!
/* Set True or False!!! */
RF_Shadow[eRFPath][Offset].Recorver= Type;
} /* PHY_RFShadowRecorverFlagSet */
@ -960,7 +941,7 @@ PHY_RFShadowCompareFlagSetAll(
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
if (Offset != 0x26 && Offset != 0x27)
PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, false);
else
@ -982,7 +963,7 @@ PHY_RFShadowRecorverFlagSetAll(
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
if (Offset != 0x26 && Offset != 0x27)
PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, false);
else

125
hal/rtl8188e_rxdesc.c
View file

@ -26,10 +26,10 @@
static s32 translate2dbm(u8 signal_strength_idx)
{
s32 signal_power; // in dBm.
s32 signal_power; /* in dBm. */
// Translate to dBm (x=0.5y-95).
/* Translate to dBm (x=0.5y-95). */
signal_power = (s32)((signal_strength_idx + 1) >> 1);
signal_power -= 95;
@ -43,10 +43,10 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe)
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
//DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength);
//if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
/* DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); */
/* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */
{
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
@ -59,9 +59,8 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe)
signal_stat->total_num++;
signal_stat->total_val += pattrib->phy_info.SignalStrength;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
//Adapter->RxStats.RssiCalculateCnt++; //For antenna Test
if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX)
{
padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
@ -86,10 +85,10 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe)
}
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
}
}// Process_UI_RSSI_8192C
}/* Process_UI_RSSI_8192C */
@ -99,7 +98,7 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
struct rx_pkt_attrib *pattrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
if(prframe == NULL || padapter==NULL){
return;
@ -108,9 +107,9 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
pattrib = &prframe->u.hdr.attrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
signal_stat = &padapter->recvpriv.signal_qual_data;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
//DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual);
/* DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
if(signal_stat->update_req) {
@ -123,12 +122,12 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
signal_stat->total_val += pattrib->phy_info.SignalQuality;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
if(pattrib->phy_info.SignalQuality != 0)
{
//
// 1. Record the general EVM to the sliding window.
//
/* */
/* 1. Record the general EVM to the sliding window. */
/* */
if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
{
padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
@ -143,7 +142,7 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality));
// <1> Showed on UI for user, in percentage.
/* <1> Showed on UI for user, in percentage. */
tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
padapter->recvpriv.signal_qual=(u8)tmpVal;
@ -152,28 +151,28 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality));
}
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
}
//void rtl8188e_process_phy_info(struct adapter *padapter, union recv_frame *prframe)
/* void rtl8188e_process_phy_info(struct adapter *padapter, union recv_frame *prframe) */
void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe)
{
union recv_frame *precvframe = (union recv_frame *)prframe;
//
// Check RSSI
//
/* */
/* Check RSSI */
/* */
process_rssi(padapter, precvframe);
//
// Check PWDB.
//
//process_PWDB(padapter, precvframe);
/* */
/* Check PWDB. */
/* */
/* process_PWDB(padapter, precvframe); */
//UpdateRxSignalStatistics8192C(Adapter, pRfd);
//
// Check EVM
//
/* UpdateRxSignalStatistics8192C(Adapter, pRfd); */
/* */
/* Check EVM */
/* */
process_link_qual(padapter, precvframe);
}
@ -186,9 +185,9 @@ void update_recvframe_attrib_88e(
struct rx_pkt_attrib *pattrib;
struct recv_stat report;
PRXREPORT prxreport;
//struct recv_frame_hdr *phdr;
/* struct recv_frame_hdr *phdr; */
//phdr = &precvframe->u.hdr;
/* phdr = &precvframe->u.hdr; */
report.rxdw0 = prxstat->rxdw0;
report.rxdw1 = prxstat->rxdw1;
@ -202,54 +201,54 @@ void update_recvframe_attrib_88e(
pattrib = &precvframe->u.hdr.attrib;
memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
pattrib->crc_err = (u8)((le32_to_cpu(report.rxdw0) >> 14) & 0x1);;//(u8)prxreport->crc32;
pattrib->crc_err = (u8)((le32_to_cpu(report.rxdw0) >> 14) & 0x1);;/* u8)prxreport->crc32; */
// update rx report to recv_frame attribute
pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);//prxreport->rpt_sel;
/* update rx report to recv_frame attribute */
pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);/* prxreport->rpt_sel; */
if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
if(pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
{
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);//(u16)prxreport->pktlen;
pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;//(u8)(prxreport->drvinfosize << 3);
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */
pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;/* u8)(prxreport->drvinfosize << 3); */
pattrib->physt = (u8)((le32_to_cpu(report.rxdw0) >> 26) & 0x1);//(u8)prxreport->physt;
pattrib->physt = (u8)((le32_to_cpu(report.rxdw0) >> 26) & 0x1);/* u8)prxreport->physt; */
pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27))? 0:1;//(u8)(prxreport->swdec ? 0 : 1);
pattrib->encrypt = (u8)((le32_to_cpu(report.rxdw0) >> 20) & 0x7);//(u8)prxreport->security;
pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27))? 0:1;/* u8)(prxreport->swdec ? 0 : 1); */
pattrib->encrypt = (u8)((le32_to_cpu(report.rxdw0) >> 20) & 0x7);/* u8)prxreport->security; */
pattrib->qos = (u8)((le32_to_cpu(report.rxdw0) >> 23) & 0x1);//(u8)prxreport->qos;
pattrib->priority = (u8)((le32_to_cpu(report.rxdw1) >> 8) & 0xf);//(u8)prxreport->tid;
pattrib->qos = (u8)((le32_to_cpu(report.rxdw0) >> 23) & 0x1);/* u8)prxreport->qos; */
pattrib->priority = (u8)((le32_to_cpu(report.rxdw1) >> 8) & 0xf);/* u8)prxreport->tid; */
pattrib->amsdu = (u8)((le32_to_cpu(report.rxdw1) >> 13) & 0x1);//(u8)prxreport->amsdu;
pattrib->amsdu = (u8)((le32_to_cpu(report.rxdw1) >> 13) & 0x1);/* u8)prxreport->amsdu; */
pattrib->seq_num = (u16)(le32_to_cpu(report.rxdw2) & 0x00000fff);//(u16)prxreport->seq;
pattrib->frag_num = (u8)((le32_to_cpu(report.rxdw2) >> 12) & 0xf);//(u8)prxreport->frag;
pattrib->mfrag = (u8)((le32_to_cpu(report.rxdw1) >> 27) & 0x1);//(u8)prxreport->mf;
pattrib->mdata = (u8)((le32_to_cpu(report.rxdw1) >> 26) & 0x1);//(u8)prxreport->md;
pattrib->seq_num = (u16)(le32_to_cpu(report.rxdw2) & 0x00000fff);/* u16)prxreport->seq; */
pattrib->frag_num = (u8)((le32_to_cpu(report.rxdw2) >> 12) & 0xf);/* u8)prxreport->frag; */
pattrib->mfrag = (u8)((le32_to_cpu(report.rxdw1) >> 27) & 0x1);/* u8)prxreport->mf; */
pattrib->mdata = (u8)((le32_to_cpu(report.rxdw1) >> 26) & 0x1);/* u8)prxreport->md; */
pattrib->mcs_rate = (u8)(le32_to_cpu(report.rxdw3) & 0x3f);//(u8)prxreport->rxmcs;
pattrib->rxht = (u8)((le32_to_cpu(report.rxdw3) >> 6) & 0x1);//(u8)prxreport->rxht;
pattrib->mcs_rate = (u8)(le32_to_cpu(report.rxdw3) & 0x3f);/* u8)prxreport->rxmcs; */
pattrib->rxht = (u8)((le32_to_cpu(report.rxdw3) >> 6) & 0x1);/* u8)prxreport->rxht; */
pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);//(u8)prxreport->icverr;
pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);/* u8)prxreport->icverr; */
pattrib->shift_sz = (u8)((le32_to_cpu(report.rxdw0) >> 24) & 0x3);
} else if(pattrib->pkt_rpt_type == TX_REPORT1) {//CCX
} else if(pattrib->pkt_rpt_type == TX_REPORT1) {/* CCX */
pattrib->pkt_len = TX_RPT1_PKT_LEN;
pattrib->drvinfo_sz = 0;
} else if(pattrib->pkt_rpt_type == TX_REPORT2) { // TX RPT
pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);//Rx length[9:0]
} else if(pattrib->pkt_rpt_type == TX_REPORT2) { /* TX RPT */
pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);/* Rx length[9:0] */
pattrib->drvinfo_sz = 0;
//
// Get TX report MAC ID valid.
//
/* */
/* Get TX report MAC ID valid. */
/* */
pattrib->MacIDValidEntry[0] = le32_to_cpu(report.rxdw4);
pattrib->MacIDValidEntry[1] = le32_to_cpu(report.rxdw5);
}
else if(pattrib->pkt_rpt_type == HIS_REPORT)// USB HISR RPT
else if(pattrib->pkt_rpt_type == HIS_REPORT)/* USB HISR RPT */
{
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);//(u16)prxreport->pktlen;
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */
}
}
@ -272,7 +271,7 @@ void update_recvframe_phyinfo_88e(
u8 *sa;
struct sta_priv *pstapriv;
struct sta_info *psta;
//_irqL irqL;
/* _irqL irqL; */
pkt_info.bPacketMatchBSSID =false;
pkt_info.bPacketToSelf = false;
@ -302,16 +301,10 @@ void update_recvframe_phyinfo_88e(
pkt_info.StationID = 0xFF;
psta = rtw_get_stainfo(pstapriv, sa);
if (psta)
{
pkt_info.StationID = psta->mac_id;
//DBG_8192C("%s ==> StationID(%d)\n",__FUNCTION__,pkt_info.StationID);
}
pkt_info.Rate = pattrib->mcs_rate;
//rtl8188e_query_rx_phy_status(precvframe, pphy_status);
//_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info));
//_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
precvframe->u.hdr.psta = NULL;
if (pkt_info.bPacketMatchBSSID &&

8
hal/rtl8188e_sreset.c
View file

@ -38,9 +38,9 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
//total xmit irp = 4
//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
/* total xmit irp = 4 */
/* DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); */
/* if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) */
current_time = rtw_get_current_time();
if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
@ -56,7 +56,7 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
if (diff_time > 4000) {
u32 ability;
//padapter->Wifi_Error_Status = WIFI_TX_HANG;
/* padapter->Wifi_Error_Status = WIFI_TX_HANG; */
rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &ability);
DBG_871X("%s tx hang %s\n", __FUNCTION__,

18
hal/rtl8188e_xmit.c
View file

@ -61,7 +61,7 @@ void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf)
rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
}
}
#endif //CONFIG_XMIT_ACK
#endif /* CONFIG_XMIT_ACK */
void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc)
{
@ -69,24 +69,22 @@ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *pt
u8 bDumpTxDesc = false;
rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
if(bDumpTxPkt ==1){//dump txdesc for data frame
if(bDumpTxPkt ==1){/* dump txdesc for data frame */
DBG_871X("dump tx_desc for data frame\n");
if((frame_tag&0x0f) == DATA_FRAMETAG){
bDumpTxDesc = true;
}
}
else if(bDumpTxPkt ==2){//dump txdesc for mgnt frame
else if(bDumpTxPkt ==2){/* dump txdesc for mgnt frame */
DBG_871X("dump tx_desc for mgnt frame\n");
if((frame_tag&0x0f) == MGNT_FRAMETAG){
bDumpTxDesc = true;
}
}
else if(bDumpTxPkt ==3){//dump early info
else if(bDumpTxPkt ==3){/* dump early info */
}
if(bDumpTxDesc){
// ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M
// ptxdesc->txdw6 = 0x6666f800;
DBG_8192C("=====================================\n");
DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0);
DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1);
@ -112,7 +110,7 @@ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *pt
*/
#ifdef CONFIG_TX_EARLY_MODE
//#define DBG_EMINFO
/* define DBG_EMINFO */
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
#define EARLY_MODE_MAX_PKT_NUM 10
@ -206,7 +204,7 @@ InsertEMContent_8188E(
SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
#endif
//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
/* RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8); */
}
@ -214,7 +212,7 @@ InsertEMContent_8188E(
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
{
//struct adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq
/* struct adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq */
int index,j;
u16 offset,pktlen;
PTXDESC ptxdesc;
@ -262,7 +260,7 @@ void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmit
eminfo.EMPktNum = pframe->agg_num-(index+1);
}
for(j=0;j< eminfo.EMPktNum ;j++){
eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;/* 4 bytes CRC */
}
if(pmem){

76
hal/rtl8188eu_led.c
View file

@ -25,24 +25,24 @@
#include <rtw_led.h>
#include <rtl8188e_led.h>
//================================================================================
// LED object.
//================================================================================
/* */
/* LED object. */
/* */
//================================================================================
// Prototype of protected function.
//================================================================================
/* */
/* Prototype of protected function. */
/* */
//================================================================================
// LED_819xUsb routines.
//================================================================================
/* */
/* LED_819xUsb routines. */
/* */
//
// Description:
// Turn on LED according to LedPin specified.
//
/* */
/* Description: */
/* Turn on LED according to LedPin specified. */
/* */
void
SwLedOn(
struct adapter *padapter,
@ -50,7 +50,7 @@ SwLedOn(
)
{
u8 LedCfg;
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
/* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */
if( (padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true))
{
@ -61,11 +61,11 @@ SwLedOn(
switch(pLed->LedPin)
{
case LED_PIN_LED0:
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on.
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
break;
case LED_PIN_LED1:
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on.
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); /* SW control led1 on. */
break;
default:
@ -76,10 +76,10 @@ SwLedOn(
}
//
// Description:
// Turn off LED according to LedPin specified.
//
/* */
/* Description: */
/* Turn off LED according to LedPin specified. */
/* */
void
SwLedOff(
struct adapter *padapter,
@ -95,14 +95,14 @@ SwLedOff(
}
LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E
LedCfg = rtw_read8(padapter, REG_LEDCFG2);/* 0x4E */
switch(pLed->LedPin)
{
case LED_PIN_LED0:
if(pHalData->bLedOpenDrain == true) // Open-drain arrangement for controlling the LED)
if(pHalData->bLedOpenDrain == true) /* Open-drain arrangement for controlling the LED) */
{
LedCfg &= 0x90; // Set to software control.
LedCfg &= 0x90; /* Set to software control. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG);
LedCfg &= 0xFE;
@ -115,7 +115,7 @@ SwLedOff(
break;
case LED_PIN_LED1:
LedCfg &= 0x0f; // Set to software control.
LedCfg &= 0x0f; /* Set to software control. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
break;
@ -127,19 +127,19 @@ exit:
}
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
/* */
/* Interface to manipulate LED objects. */
/* */
//================================================================================
// Default LED behavior.
//================================================================================
/* */
/* Default LED behavior. */
/* */
//
// Description:
// Initialize all LED_871x objects.
//
/* */
/* Description: */
/* Initialize all LED_871x objects. */
/* */
void
rtl8188eu_InitSwLeds(
struct adapter *padapter
@ -155,10 +155,10 @@ rtl8188eu_InitSwLeds(
}
//
// Description:
// DeInitialize all LED_819xUsb objects.
//
/* */
/* Description: */
/* DeInitialize all LED_819xUsb objects. */
/* */
void
rtl8188eu_DeInitSwLeds(
struct adapter *padapter

16
hal/rtl8188eu_recv.c
View file

@ -59,8 +59,8 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
struct recv_buf *precvbuf;
#ifdef CONFIG_RECV_THREAD_MODE
_rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed
_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed
_rtw_init_sema(&precvpriv->recv_sema, 0);/* will be removed */
_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);/* will be removed */
#endif
tasklet_init(&precvpriv->recv_tasklet,
@ -82,12 +82,12 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
}
#endif
//init recv_buf
/* init recv_buf */
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
if(precvpriv->pallocated_recv_buf==NULL){
@ -98,8 +98,8 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
//precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 -
// ((uint) (precvpriv->pallocated_recv_buf) &(4-1));
/* precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 - */
/* ((uint) (precvpriv->pallocated_recv_buf) &(4-1)); */
precvbuf = (struct recv_buf*)precvpriv->precv_buf;
@ -120,7 +120,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
precvbuf->adapter =padapter;
//rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue));
/* rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue)); */
precvbuf++;
@ -189,7 +189,7 @@ void rtl8188eu_free_recv_priv (struct adapter *padapter)
if(precvpriv->int_in_buf)
rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN);
#endif//CONFIG_USB_INTERRUPT_IN_PIPE
#endif/* CONFIG_USB_INTERRUPT_IN_PIPE */
if (skb_queue_len(&precvpriv->rx_skb_queue)) {
DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n");

379
hal/rtl8188eu_xmit.c
View file

@ -58,11 +58,11 @@ static u8 urb_zero_packet_chk(struct adapter *padapter, int sz)
static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
{
u16 *usPtr = (u16*)ptxdesc;
u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times
u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
u32 index;
u16 checksum = 0;
//Clear first
/* Clear first */
ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
for(index = 0 ; index < count ; index++){
@ -72,11 +72,11 @@ static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum);
}
//
// Description: In normal chip, we should send some packet to Hw which will be used by Fw
// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
// Fw can tell Hw to send these packet derectly.
//
/* */
/* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
/* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
/* Fw can tell Hw to send these packet derectly. */
/* */
void rtl8188e_fill_fake_txdesc(
struct adapter *padapter,
u8* pDesc,
@ -87,41 +87,41 @@ void rtl8188e_fill_fake_txdesc(
struct tx_desc *ptxdesc;
// Clear all status
/* Clear all status */
ptxdesc = (struct tx_desc*)pDesc;
memset(pDesc, 0, TXDESC_SIZE);
//offset 0
ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg;
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); //32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); /* 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header
ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); /* Buffer size + command header */
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); // Fixed queue of Mgnt queue
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); /* Fixed queue of Mgnt queue */
//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
if (IsPsPoll)
{
ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
}
else
{
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
}
if (true == IsBTQosNull)
{
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
}
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
// USB interface drop packet if the checksum of descriptor isn't correct.
// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
/* USB interface drop packet if the checksum of descriptor isn't correct. */
/* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
rtl8188eu_cal_txdesc_chksum(ptxdesc);
}
@ -129,7 +129,7 @@ static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxd
{
if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
switch (pattrib->encrypt) {
//SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES
/* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
case _WEP40_:
case _WEP104_:
ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
@ -159,7 +159,7 @@ static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxd
static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
{
//DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode);
/* DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); */
switch(pattrib->vcs_mode)
{
@ -177,7 +177,7 @@ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
if(pattrib->vcs_mode) {
*pdw |= cpu_to_le32(HW_RTS_EN);
// Set RTS BW
/* Set RTS BW */
if(pattrib->ht_en)
{
*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(27)):0;
@ -196,7 +196,7 @@ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw)
{
//DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
/* DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */
if(pattrib->ht_en)
{
@ -223,7 +223,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
//struct dm_priv *pdmpriv = &pHalData->dmpriv;
/* struct dm_priv *pdmpriv = &pHalData->dmpriv; */
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -231,37 +231,37 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
#ifdef CONFIG_P2P
struct wifidirect_info* pwdinfo = &padapter->wdinfo;
#endif //CONFIG_P2P
#endif /* CONFIG_P2P */
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
if (padapter->registrypriv.mp_mode == 0)
{
if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))//(sz %512) != 0
//if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==false))
if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))/* sz %512) != 0 */
/* if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==false)) */
{
ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
//DBG_8192C("==> non-agg-pkt,shift pointer...\n");
/* DBG_8192C("==> non-agg-pkt,shift pointer...\n"); */
pull = 1;
}
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
memset(ptxdesc, 0, sizeof(struct tx_desc));
//4 offset 0
/* 4 offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
//DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt);
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);//update TXPKTSIZE
/* DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt); */
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */
offset = TXDESC_SIZE + OFFSET_SZ;
#ifdef CONFIG_TX_EARLY_MODE
if(bagg_pkt){
offset += EARLY_MODE_INFO_SIZE ;//0x28
offset += EARLY_MODE_INFO_SIZE ;/* 0x28 */
}
#endif
//DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset);
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc
/* DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset); */
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */
if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC);
@ -275,24 +275,24 @@ if (padapter->registrypriv.mp_mode == 0)
}
}
#endif
//DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset);
/* DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset); */
// pkt_offset, unit:8 bytes padding
/* pkt_offset, unit:8 bytes padding */
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
//driver uses rate
ptxdesc->txdw4 |= cpu_to_le32(USERATE);//rate control always by driver
/* driver uses rate */
ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
//DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n");
/* DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); */
//offset 4
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3F);
qsel = (uint)(pattrib->qsel & 0x0000001f);
//DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel);
/* DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel); */
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000F0000);
@ -300,27 +300,27 @@ if (padapter->registrypriv.mp_mode == 0)
fill_txdesc_sectype(pattrib, ptxdesc);
if(pattrib->ampdu_en==true){
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);//AGG EN
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
} else{
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
}
//offset 8
/* offset 8 */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<< SEQ_SHT)&0x0FFF0000);
//offset 16 , offset 20
/* offset 16 , offset 20 */
if (pattrib->qos_en)
ptxdesc->txdw4 |= cpu_to_le32(QOS);//QoS
ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
//offset 20
/* offset 20 */
#ifdef CONFIG_USB_TX_AGGREGATION
if (pxmitframe->agg_num > 1){
//DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num );
/* DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num ); */
ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
}
#endif
@ -330,28 +330,28 @@ if (padapter->registrypriv.mp_mode == 0)
(pattrib->ether_type != 0x88b4) &&
(pattrib->dhcp_pkt != 1))
{
//Non EAP & ARP & DHCP type data packet
/* Non EAP & ARP & DHCP type data packet */
fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//DATA/RTS Rate FB LMT
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
#if (RATE_ADAPTIVE_SUPPORT == 1)
if(pattrib->ht_en){
if( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
}
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
//for debug
/* for debug */
#if 1
if(padapter->fix_rate!= 0xFF){
data_rate = padapter->fix_rate;
ptxdesc->txdw4 |= cpu_to_le32(DISDATAFB);
//printk("==> fix data_rate:0x%02x\n",data_rate);
/* printk("==> fix data_rate:0x%02x\n",data_rate); */
}
#endif
@ -360,40 +360,39 @@ if (padapter->registrypriv.mp_mode == 0)
#if (POWER_TRAINING_ACTIVE==1)
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT);
#endif //(POWER_TRAINING_ACTIVE==1)
#else//if (RATE_ADAPTIVE_SUPPORT == 1)
#endif /* POWER_TRAINING_ACTIVE==1) */
#else/* if (RATE_ADAPTIVE_SUPPORT == 1) */
if(pattrib->ht_en)
ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
data_rate = 0x13; //default rate: MCS7
if(padapter->fix_rate!= 0xFF){//rate control by iwpriv
data_rate = 0x13; /* default rate: MCS7 */
if(padapter->fix_rate!= 0xFF){/* rate control by iwpriv */
data_rate = padapter->fix_rate;
ptxdesc->txdw4 | cpu_to_le32(DISDATAFB);
}
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
#endif//if (RATE_ADAPTIVE_SUPPORT == 1)
#endif/* if (RATE_ADAPTIVE_SUPPORT == 1) */
}
else
{
// EAP data packet and ARP packet and DHCP.
// Use the 1M data rate to send the EAP/ARP packet.
// This will maybe make the handshake smooth.
/* EAP data packet and ARP packet and DHCP. */
/* Use the 1M data rate to send the EAP/ARP packet. */
/* This will maybe make the handshake smooth. */
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
//offset 24
/* offset 24 */
if ( pattrib->hw_tcp_csum == 1 ) {
// ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!!
u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8;
ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16);
DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7);
@ -402,9 +401,9 @@ if (padapter->registrypriv.mp_mode == 0)
}
else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG)
{
//DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n");
/* DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); */
//offset 4
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f);
qsel = (uint)(pattrib->qsel&0x0000001f);
@ -412,11 +411,11 @@ if (padapter->registrypriv.mp_mode == 0)
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000f0000);
//fill_txdesc_sectype(pattrib, ptxdesc);
/* fill_txdesc_sectype(pattrib, ptxdesc); */
//offset 8
/* offset 8 */
#ifdef CONFIG_XMIT_ACK
//CCX-TXRPT ack for xmit mgmt frames.
/* CCX-TXRPT ack for xmit mgmt frames. */
if (pxmitframe->ack_report) {
#ifdef DBG_CCX
static u16 ccx_sw = 0x123;
@ -426,17 +425,17 @@ if (padapter->registrypriv.mp_mode == 0)
#endif
ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
}
#endif //CONFIG_XMIT_ACK
#endif /* CONFIG_XMIT_ACK */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
//offset 20
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);//retry limit enable
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
if(pattrib->retry_ctrl == true)
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
else
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
#ifdef CONFIG_INTEL_PROXIM
if((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)){
@ -457,39 +456,35 @@ if (padapter->registrypriv.mp_mode == 0)
{
DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);//CAM_ID(MAC_ID)
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);/* CAM_ID(MAC_ID) */
ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);//raid
ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);/* raid */
//offset 8
/* offset 8 */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
//offset 20
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
// 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
// (1) The sequence number of each non-Qos frame / broadcast / multicast /
// mgnt frame should be controled by Hw because Fw will also send null data
// which we cannot control when Fw LPS enable.
// --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
// (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
// (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
// 2010.06.23. Added by tynli.
/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
/* mgnt frame should be controled by Hw because Fw will also send null data */
/* which we cannot control when Fw LPS enable. */
/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
/* 2010.06.23. Added by tynli. */
if(!pattrib->qos_en)
{
//ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
//ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
}
#ifdef CONFIG_HW_ANTENNA_DIVERSITY //CONFIG_ANTENNA_DIVERSITY
#ifdef CONFIG_HW_ANTENNA_DIVERSITY /* CONFIG_ANTENNA_DIVERSITY */
ODM_SetTxAntByTxInfo_88E(&pHalData->odmpriv, pmem, pattrib->mac_id);
#endif
@ -511,13 +506,13 @@ if (padapter->registrypriv.mp_mode == 0)
*/
s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter)
{
//PHAL_DATA_TYPE phal;
/* PHAL_DATA_TYPE phal; */
struct xmit_priv *pxmitpriv;
struct xmit_buf *pxmitbuf;
s32 ret;
//phal = GET_HAL_DATA(padapter);
/* phal = GET_HAL_DATA(padapter); */
pxmitpriv = &padapter->xmitpriv;
ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
@ -566,7 +561,7 @@ s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter)
#ifdef CONFIG_IOL_IOREG_CFG_DBG
#include <rtw_iol.h>
#endif
//for non-agg data frame or management frame
/* for non-agg data frame or management frame */
static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 ret = _SUCCESS;
@ -587,7 +582,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra
{
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
#endif //CONFIG_80211N_HT
#endif /* CONFIG_80211N_HT */
mem_addr = pxmitframe->buf_addr;
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
@ -604,7 +599,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra
sz = pxmitpriv->frag_len;
sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
}
else //no frag
else /* no frag */
{
sz = pattrib->last_txcmdsz;
}
@ -613,9 +608,9 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra
if(pull)
{
mem_addr += PACKET_OFFSET_SZ; //pull txdesc head
mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
//pxmitbuf ->pbuf = mem_addr;
/* pxmitbuf ->pbuf = mem_addr; */
pxmitframe->buf_addr = mem_addr;
w_sz = sz + TXDESC_SIZE;
@ -640,7 +635,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra
rtw_count_tx_stats(padapter, pxmitframe, sz);
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz));
//DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority);
/* DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority); */
mem_addr += w_sz;
@ -663,7 +658,7 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
u32 len = 0;
// no consider fragement
/* no consider fragement */
len = pattrib->hdrlen + pattrib->iv_len +
SNAP_SIZE + sizeof(u16) +
pattrib->pktlen +
@ -675,14 +670,14 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
return len;
}
#define IDEA_CONDITION 1 // check all packets before enqueue
#define IDEA_CONDITION 1 /* check all packets before enqueue */
s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct xmit_frame *pxmitframe = NULL;
struct xmit_frame *pfirstframe = NULL;
// aggregate variable
/* aggregate variable */
struct hw_xmit *phwxmit;
struct sta_info *psta = NULL;
struct tx_servq *ptxservq = NULL;
@ -690,15 +685,15 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
_irqL irqL;
_list *xmitframe_plist = NULL, *xmitframe_phead = NULL;
u32 pbuf; // next pkt address
u32 pbuf_tail; // last pkt tail
u32 len; // packet length, except TXDESC_SIZE and PKT_OFFSET
u32 pbuf; /* next pkt address */
u32 pbuf_tail; /* last pkt tail */
u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */
u32 bulkSize = pHalData->UsbBulkOutSize;
u8 descCount;
u32 bulkPtr;
// dump frame variable
/* dump frame variable */
u32 ff_hwaddr;
#ifndef IDEA_CONDITION
@ -708,24 +703,24 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n"));
// check xmitbuffer is ok
/* check xmitbuffer is ok */
if (pxmitbuf == NULL) {
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (pxmitbuf == NULL){
//DBG_871X("%s #1, connot alloc xmitbuf!!!! \n",__FUNCTION__);
/* DBG_871X("%s #1, connot alloc xmitbuf!!!! \n",__FUNCTION__); */
return false;
}
}
//DBG_8192C("%s ===================================== \n",__FUNCTION__);
//3 1. pick up first frame
/* DBG_8192C("%s ===================================== \n",__FUNCTION__); */
/* 3 1. pick up first frame */
do {
rtw_free_xmitframe(pxmitpriv, pxmitframe);
pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
if (pxmitframe == NULL) {
// no more xmit frame, release xmit buffer
//DBG_8192C("no more xmit frame ,return\n");
/* no more xmit frame, release xmit buffer */
/* DBG_8192C("no more xmit frame ,return\n"); */
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
return false;
}
@ -735,30 +730,30 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
pxmitframe->frame_tag, DATA_FRAMETAG));
// rtw_free_xmitframe(pxmitpriv, pxmitframe);
/* rtw_free_xmitframe(pxmitpriv, pxmitframe); */
continue;
}
// TID 0~15
/* TID 0~15 */
if ((pxmitframe->attrib.priority < 0) ||
(pxmitframe->attrib.priority > 15)) {
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
("xmitframe_complete: TID(%d) should be 0~15!\n",
pxmitframe->attrib.priority));
// rtw_free_xmitframe(pxmitpriv, pxmitframe);
/* rtw_free_xmitframe(pxmitpriv, pxmitframe); */
continue;
}
#endif
//DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
/* DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); */
pxmitframe->pxmitbuf = pxmitbuf;
pxmitframe->buf_addr = pxmitbuf->pbuf;
pxmitbuf->priv_data = pxmitframe;
pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1.
pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */
#ifdef CONFIG_TX_EARLY_MODE
pxmitframe->pkt_offset = 2; // first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check
pxmitframe->pkt_offset = 2; /* first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check */
#else
pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset
pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */
#endif
if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == false) {
@ -766,30 +761,30 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
continue;
}
// always return ndis_packet after rtw_xmitframe_coalesce
/* always return ndis_packet after rtw_xmitframe_coalesce */
rtw_os_xmit_complete(padapter, pxmitframe);
break;
} while (1);
//3 2. aggregate same priority and same DA(AP or STA) frames
/* 3 2. aggregate same priority and same DA(AP or STA) frames */
pfirstframe = pxmitframe;
len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE+(pfirstframe->pkt_offset*PACKET_OFFSET_SZ);
pbuf_tail = len;
pbuf = _RND8(pbuf_tail);
// check pkt amount in one bulk
/* check pkt amount in one bulk */
descCount = 0;
bulkPtr = bulkSize;
if (pbuf < bulkPtr)
descCount++;
else {
descCount = 0;
bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize
bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; /* round to next bulkSize */
}
// dequeue same priority packet from station tx queue
//psta = pfirstframe->attrib.psta;
/* dequeue same priority packet from station tx queue */
/* psta = pfirstframe->attrib.psta; */
psta = rtw_get_stainfo(&padapter->stapriv, pfirstframe->attrib.ra);
if(pfirstframe->attrib.psta != psta){
DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pfirstframe->attrib.psta, psta);
@ -827,8 +822,8 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
phwxmit = pxmitpriv->hwxmits + 2;
break;
}
//DBG_8192C("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n",
//pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset );
/* DBG_8192C("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n", */
/* pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset ); */
_enter_critical_bh(&pxmitpriv->lock, &irqL);
@ -840,19 +835,17 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
xmitframe_plist = get_next(xmitframe_plist);
pxmitframe->agg_num = 0; // not first frame of aggregation
pxmitframe->agg_num = 0; /* not first frame of aggregation */
#ifdef CONFIG_TX_EARLY_MODE
pxmitframe->pkt_offset = 1;// not first frame of aggregation,reserve offset for EM Info
pxmitframe->pkt_offset = 1;/* not first frame of aggregation,reserve offset for EM Info */
#else
pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset
pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */
#endif
len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE +(pxmitframe->pkt_offset*PACKET_OFFSET_SZ);
if (_RND8(pbuf + len) > MAX_XMITBUF_SZ)
//if (_RND8(pbuf + len) > (MAX_XMITBUF_SZ/2))//to do : for TX TP finial tune , Georgia 2012-0323
{
//DBG_8192C("%s....len> MAX_XMITBUF_SZ\n",__FUNCTION__);
pxmitframe->agg_num = 1;
pxmitframe->pkt_offset = 1;
break;
@ -862,7 +855,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
phwxmit->accnt--;
#ifndef IDEA_CONDITION
// suppose only data frames would be in queue
/* suppose only data frames would be in queue */
if (pxmitframe->frame_tag != DATA_FRAMETAG) {
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
@ -871,7 +864,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
continue;
}
// TID 0~15
/* TID 0~15 */
if ((pxmitframe->attrib.priority < 0) ||
(pxmitframe->attrib.priority > 15)) {
RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
@ -882,7 +875,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
}
#endif
// pxmitframe->pxmitbuf = pxmitbuf;
/* pxmitframe->pxmitbuf = pxmitbuf; */
pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == false) {
@ -891,17 +884,17 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
continue;
}
//DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
// always return ndis_packet after rtw_xmitframe_coalesce
/* DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); */
/* always return ndis_packet after rtw_xmitframe_coalesce */
rtw_os_xmit_complete(padapter, pxmitframe);
// (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz
/* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */
update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz,true);
// don't need xmitframe any more
/* don't need xmitframe any more */
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// handle pointer and stop condition
/* handle pointer and stop condition */
pbuf_tail = pbuf + len;
pbuf = _RND8(pbuf_tail);
@ -922,7 +915,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
descCount = 0;
bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize;
}
}//end while( aggregate same priority and same DA(AP or STA) frames)
}/* end while( aggregate same priority and same DA(AP or STA) frames) */
if (_rtw_queue_empty(&ptxservq->sta_pending) == true)
@ -937,36 +930,36 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
{
rtw_issue_addbareq_cmd(padapter, pfirstframe);
}
#endif //CONFIG_80211N_HT
#endif /* CONFIG_80211N_HT */
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
//3 3. update first frame txdesc
/* 3 3. update first frame txdesc */
if ((pbuf_tail % bulkSize) == 0) {
// remove pkt_offset
/* remove pkt_offset */
pbuf_tail -= PACKET_OFFSET_SZ;
pfirstframe->buf_addr += PACKET_OFFSET_SZ;
pfirstframe->pkt_offset--;
//DBG_8192C("$$$$$ buf size equal to USB block size $$$$$$\n");
/* DBG_8192C("$$$$$ buf size equal to USB block size $$$$$$\n"); */
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz,true);
#ifdef CONFIG_TX_EARLY_MODE
//prepare EM info for first frame, agg_num value start from 1
/* prepare EM info for first frame, agg_num value start from 1 */
pxmitpriv->agg_pkt[0].offset = _RND8(pfirstframe->attrib.last_txcmdsz +TXDESC_SIZE +(pfirstframe->pkt_offset*PACKET_OFFSET_SZ));
pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;//get from rtw_xmitframe_coalesce
pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;/* get from rtw_xmitframe_coalesce */
UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf );
#endif
//3 4. write xmit buffer to USB FIFO
/* 3 4. write xmit buffer to USB FIFO */
ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
//DBG_8192C("%s ===================================== write port,buf_size(%d) \n",__FUNCTION__,pbuf_tail);
// xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr
/* DBG_8192C("%s ===================================== write port,buf_size(%d) \n",__FUNCTION__,pbuf_tail); */
/* xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr */
rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf);
//3 5. update statisitc
/* 3 5. update statisitc */
pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
@ -1017,12 +1010,12 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
if(pxmitframe->attrib.priority<=15)//TID0~15
if(pxmitframe->attrib.priority<=15)/* TID0~15 */
{
res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
}
//DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce
/* DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); */
rtw_os_xmit_complete(padapter, pxmitframe);/* always return ndis_packet after rtw_xmitframe_coalesce */
}
@ -1062,7 +1055,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
static s32 xmitframe_direct(struct adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 res = _SUCCESS;
//DBG_8192C("==> %s \n",__FUNCTION__);
/* DBG_8192C("==> %s \n",__FUNCTION__); */
res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
if (res == _SUCCESS) {
@ -1122,7 +1115,7 @@ enqueue:
RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n"));
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// Trick, make the statistics correct
/* Trick, make the statistics correct */
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
return true;
@ -1155,7 +1148,7 @@ s32 rtl8188eu_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame
{
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// Trick, make the statistics correct
/* Trick, make the statistics correct */
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
}
@ -1175,7 +1168,7 @@ static void rtl8188eu_hostap_mgnt_xmit_cb(struct urb *urb)
{
struct sk_buff *skb = (struct sk_buff *)urb->context;
//DBG_8192C("%s\n", __FUNCTION__);
/* DBG_8192C("%s\n", __FUNCTION__); */
rtw_skb_free(skb);
}
@ -1196,7 +1189,7 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
//DBG_8192C("%s\n", __FUNCTION__);
/* DBG_8192C("%s\n", __FUNCTION__); */
skb = pkt;
@ -1220,13 +1213,13 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
goto _exit;
}
// ----- fill tx desc -----
/* ----- fill tx desc ----- */
ptxdesc = (struct tx_desc *)pxmitbuf;
memset(ptxdesc, 0, sizeof(*ptxdesc));
//offset 0
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff);
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);//default = 32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);/* default = 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
if(bmcst)
@ -1234,44 +1227,44 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
}
//offset 4
ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(0x00);/* MAC_ID */
ptxdesc->txdw1 |= cpu_to_le32((0x12<<QSEL_SHT)&0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode
ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);/* b mode */
//offset 8
/* offset 8 */
//offset 12
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000);
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
//offset 20
/* offset 20 */
//HW append seq
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
/* HW append seq */
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
rtl8188eu_cal_txdesc_chksum(ptxdesc);
// ----- end of fill tx desc -----
/* ----- end of fill tx desc ----- */
//
/* */
skb_put(pxmit_skb, len + TXDESC_SIZE);
pxmitbuf = pxmitbuf + TXDESC_SIZE;
memcpy(pxmitbuf, skb->data, len);
//DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len);
/* DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len); */
// ----- prepare urb for submit -----
/* ----- prepare urb for submit ----- */
//translate DMA FIFO addr to pipehandle
//pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);
/* translate DMA FIFO addr to pipehandle */
/* pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX); */
pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f);
usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe,

1055
hal/usb_halinit.c
View file

File diff suppressed because it is too large Load diff

208
hal/usb_ops_linux.c
View file

@ -43,7 +43,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
u8 *tmp_buf;
#else // use stack memory
#else /* use stack memory */
u8 tmp_buf[MAX_USB_IO_CTL_SIZE];
#endif
@ -64,20 +64,20 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
#endif
// Acquire IO memory for vendorreq
/* Acquire IO memory for vendorreq */
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
pIo_buf = pdvobjpriv->usb_vendor_req_buf;
#else
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT);
tmp_buflen = (u32)len + ALIGNMENT_UNIT;
#else // use stack memory
#else /* use stack memory */
tmp_buflen = MAX_USB_IO_CTL_SIZE;
#endif
// Added by Albert 2010/02/09
// For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment.
// Trying to fix it here.
/* Added by Albert 2010/02/09 */
/* For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. */
/* Trying to fix it here. */
pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f );
#endif
@ -93,27 +93,27 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
if (requesttype == 0x01)
{
pipe = usb_rcvctrlpipe(udev, 0);//read_in
pipe = usb_rcvctrlpipe(udev, 0);/* read_in */
reqtype = REALTEK_USB_VENQT_READ;
}
else
{
pipe = usb_sndctrlpipe(udev, 0);//write_out
pipe = usb_sndctrlpipe(udev, 0);/* write_out */
reqtype = REALTEK_USB_VENQT_WRITE;
memcpy( pIo_buf, pdata, len);
}
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
if ( status == len) // Success this control transfer.
if ( status == len) /* Success this control transfer. */
{
rtw_reset_continual_io_error(pdvobjpriv);
if ( requesttype == 0x01 )
{ // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
{ /* For Control read transfer, we have to copy the read data from pIo_buf to pdata. */
memcpy( pdata, pIo_buf, len );
}
}
else { // error cases
else { /* error cases */
DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n"
, value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times);
@ -130,11 +130,11 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
#endif
}
}
else // status != len && status >= 0
else /* status != len && status >= 0 */
{
if (status > 0) {
if ( requesttype == 0x01 )
{ // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
{ /* For Control read transfer, we have to copy the read data from pIo_buf to pdata. */
memcpy( pdata, pIo_buf, len );
}
}
@ -147,13 +147,13 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
}
// firmware download is checksumed, don't retry
/* firmware download is checksumed, don't retry */
if ( (value >= FW_8188E_START_ADDRESS && value <= FW_8188E_END_ADDRESS) || status == len )
break;
}
// release IO memory used by vendorreq
/* release IO memory used by vendorreq */
#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
rtw_mfree(tmp_buf, tmp_buflen);
#endif
@ -177,8 +177,8 @@ static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
u8 data;
request = 0x05;
requesttype = 0x01;//read_in
index = 0;//n/a
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 1;
@ -197,8 +197,8 @@ static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
__le32 data;
request = 0x05;
requesttype = 0x01;//read_in
index = 0;//n/a
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 2;
@ -217,8 +217,8 @@ static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
__le32 data;
request = 0x05;
requesttype = 0x01;//read_in
index = 0;//n/a
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 4;
@ -239,8 +239,8 @@ static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
int ret;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 1;
@ -263,8 +263,8 @@ static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
int ret;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 2;
@ -287,8 +287,8 @@ static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
int ret;
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = 4;
@ -309,8 +309,8 @@ static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata
u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0};
request = 0x05;
requesttype = 0x00;//write_out
index = 0;//n/a
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
wvalue = (u16)(addr&0x0000ffff);
len = length;
@ -330,7 +330,7 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb
return ;
}
// HISR
/* HISR */
memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
@ -338,11 +338,11 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb
if ( pHalData->IntArray[0] & IMR_CPWM_88E ) {
memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1);
//88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow.
/* 88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */
pwr_rpt.state |= PS_STATE_S2;
_set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event));
}
#endif//CONFIG_LPS_LCLK
#endif/* CONFIG_LPS_LCLK */
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
@ -356,12 +356,12 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
//send_beacon(padapter);
/* send_beacon(padapter); */
if (pmlmepriv->update_bcn == true)
set_tx_beacon_cmd(padapter);
}
}
#endif //CONFIG_INTERRUPT_BASED_TXBCN
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
#ifdef DBG_CONFIG_ERROR_DETECT_INT
if ( pHalData->IntArray[1] & IMR_TXERR_88E )
@ -372,12 +372,12 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb
DBG_871X("===> %s Transmit FIFO Overflow \n",__FUNCTION__);
if ( pHalData->IntArray[1] & IMR_RXFOVW_88E )
DBG_871X("===> %s Receive FIFO Overflow \n",__FUNCTION__);
#endif//DBG_CONFIG_ERROR_DETECT_INT
#endif/* DBG_CONFIG_ERROR_DETECT_INT */
// C2H Event
/* C2H Event */
if (pbuf[0]!= 0){
memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16);
//rtw_c2h_wk_cmd(padapter); to do..
/* rtw_c2h_wk_cmd(padapter); to do.. */
}
}
@ -397,7 +397,7 @@ static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
return;
}
if (purb->status==0)//SUCCESS
if (purb->status==0)/* SUCCESS */
{
if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN)
{
@ -421,7 +421,7 @@ static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
//padapter->bSurpriseRemoved=true;
/* padapter->bSurpriseRemoved=true; */
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
case -ENOENT:
padapter->bDriverStopped=true;
@ -451,7 +451,7 @@ static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr)
;
//translate DMA FIFO addr to pipehandle
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe,
@ -520,10 +520,10 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
}
_rtw_init_listhead(&precvframe->u.hdr.list);
precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->u.hdr.len=0;
//rtl8192c_query_rx_desc_status(precvframe, prxstat);
/* rtl8192c_query_rx_desc_status(precvframe, prxstat); */
update_recvframe_attrib_88e(precvframe, prxstat);
pattrib = &precvframe->u.hdr.attrib;
@ -552,9 +552,9 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
goto _exit_recvbuf2recvframe;
}
// Modified by Albert 20101213
// For 8 bytes IP header alignment.
if (pattrib->qos) // Qos data, wireless lan header length is 26
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
{
shift_sz = 6;
}
@ -565,10 +565,9 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
skb_len = pattrib->pkt_len;
// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
//alloc_sz = 1664; //1664 is 128 alignment.
if (skb_len <= 1650)
alloc_sz = 1664;
else
@ -576,8 +575,8 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
}
else {
alloc_sz = skb_len;
// 6 is for IP header 8 bytes alignment in QoS packet case.
// 8 is for skb->data 4 bytes alignment.
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
@ -589,17 +588,17 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
precvframe->u.hdr.pkt = pkt_copy;
precvframe->u.hdr.rx_head = pkt_copy->data;
precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */
skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */
memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
}
else
{
DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n");
//precvframe->u.hdr.pkt = rtw_skb_clone(pskb);
//precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf;
//precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612);
/* precvframe->u.hdr.pkt = rtw_skb_clone(pskb); */
/* precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; */
/* precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612); */
precvframe->u.hdr.pkt = NULL;
rtw_free_recvframe(precvframe, pfree_recv_queue);
@ -608,7 +607,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
}
recvframe_put(precvframe, skb_len);
//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
/* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */
#ifdef CONFIG_USB_RX_AGGREGATION
switch(pHalData->UsbRxAggMode)
@ -626,7 +625,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
}
#endif
if (pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
{
if (pattrib->physt)
update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);
@ -636,17 +635,17 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
}
} else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
} else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */
//enqueue recvframe to txrtp queue
/* enqueue recvframe to txrtp queue */
if (pattrib->pkt_rpt_type == TX_REPORT1){
//DBG_8192C("rx CCX \n");
//CCX-TXRPT ack for xmit mgmt frames.
/* DBG_8192C("rx CCX \n"); */
/* CCX-TXRPT ack for xmit mgmt frames. */
handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
}
else if (pattrib->pkt_rpt_type == TX_REPORT2){
//DBG_8192C("rx TX RPT \n");
/* DBG_8192C("rx TX RPT \n"); */
ODM_RA_TxRPT2Handle_8188E(
&pHalData->odmpriv,
precvframe->u.hdr.rx_data,
@ -658,7 +657,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
}
else if (pattrib->pkt_rpt_type == HIS_REPORT)
{
//DBG_8192C("%s , rx USB HISR \n",__FUNCTION__);
/* DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); */
#ifdef CONFIG_SUPPORT_USB_INT
interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data);
#endif
@ -724,7 +723,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
goto exit;
}
if (purb->status==0)//SUCCESS
if (purb->status==0)/* SUCCESS */
{
if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
{
@ -738,7 +737,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
precvbuf->transfer_len = purb->actual_length;
//rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf);
/* rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); */
rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue);
tasklet_schedule(&precvpriv->recv_tasklet);
@ -759,7 +758,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
//padapter->bSurpriseRemoved=true;
/* padapter->bSurpriseRemoved=true; */
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
case -ENOENT:
padapter->bDriverStopped=true;
@ -823,14 +822,14 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
purb = precvbuf->purb;
//translate DMA FIFO addr to pipehandle
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_bulk_urb(purb, pusbd, pipe,
precvbuf->pbuf,
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
precvbuf);/* context is precvbuf */
purb->transfer_dma = precvbuf->dma_transfer_addr;
purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
@ -856,7 +855,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
return ret;
}
#else // CONFIG_USE_USB_BUFFER_ALLOC_RX
#else /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
{
u8 *pbuf;
@ -896,10 +895,10 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
}
_rtw_init_listhead(&precvframe->u.hdr.list);
precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch.
precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->u.hdr.len=0;
//rtl8192c_query_rx_desc_status(precvframe, prxstat);
/* rtl8192c_query_rx_desc_status(precvframe, prxstat); */
update_recvframe_attrib_88e(precvframe, prxstat);
pattrib = &precvframe->u.hdr.attrib;
@ -927,9 +926,9 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
goto _exit_recvbuf2recvframe;
}
// Modified by Albert 20101213
// For 8 bytes IP header alignment.
if (pattrib->qos) // Qos data, wireless lan header length is 26
/* Modified by Albert 20101213 */
/* For 8 bytes IP header alignment. */
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
{
shift_sz = 6;
}
@ -940,10 +939,9 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
skb_len = pattrib->pkt_len;
// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
//alloc_sz = 1664; //1664 is 128 alignment.
if (skb_len <= 1650)
alloc_sz = 1664;
else
@ -951,8 +949,8 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
}
else {
alloc_sz = skb_len;
// 6 is for IP header 8 bytes alignment in QoS packet case.
// 8 is for skb->data 4 bytes alignment.
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
/* 8 is for skb->data 4 bytes alignment. */
alloc_sz += 14;
}
@ -964,8 +962,8 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
precvframe->u.hdr.pkt = pkt_copy;
precvframe->u.hdr.rx_head = pkt_copy->data;
precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */
skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */
memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
}
@ -995,7 +993,7 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
}
recvframe_put(precvframe, skb_len);
//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
/* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */
#ifdef CONFIG_USB_RX_AGGREGATION
switch(pHalData->UsbRxAggMode)
@ -1013,7 +1011,7 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
}
#endif
if (pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
{
if (pattrib->physt)
update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);
@ -1022,15 +1020,15 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
}
} else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
//enqueue recvframe to txrtp queue
} else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */
/* enqueue recvframe to txrtp queue */
if (pattrib->pkt_rpt_type == TX_REPORT1){
//DBG_8192C("rx CCX \n");
//CCX-TXRPT ack for xmit mgmt frames.
/* DBG_8192C("rx CCX \n"); */
/* CCX-TXRPT ack for xmit mgmt frames. */
handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
}
else if (pattrib->pkt_rpt_type == TX_REPORT2){
//DBG_8192C("rx TX RPT \n");
/* DBG_8192C("rx TX RPT \n"); */
ODM_RA_TxRPT2Handle_8188E(
&pHalData->odmpriv,
precvframe->u.hdr.rx_data,
@ -1042,7 +1040,7 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
}
else if (pattrib->pkt_rpt_type == HIS_REPORT)
{
//DBG_8192C("%s , rx USB HISR \n",__FUNCTION__);
/* DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); */
#ifdef CONFIG_SUPPORT_USB_INT
interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data);
#endif
@ -1111,18 +1109,18 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
//_enter_critical(&precvpriv->lock, &irqL);
//precvbuf->irp_pending=false;
//precvpriv->rx_pending_cnt --;
//_exit_critical(&precvpriv->lock, &irqL);
/* _enter_critical(&precvpriv->lock, &irqL); */
/* precvbuf->irp_pending=false; */
/* precvpriv->rx_pending_cnt --; */
/* _exit_critical(&precvpriv->lock, &irqL); */
precvpriv->rx_pending_cnt --;
//if (precvpriv->rx_pending_cnt== 0)
//{
// RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n"));
// _rtw_up_sema(&precvpriv->allrxreturnevt);
//}
/* if (precvpriv->rx_pending_cnt== 0) */
/* */
/* RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n")); */
/* _rtw_up_sema(&precvpriv->allrxreturnevt); */
/* */
if (padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
{
@ -1141,7 +1139,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
goto exit;
}
if (purb->status==0)//SUCCESS
if (purb->status==0)/* SUCCESS */
{
if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
{
@ -1181,7 +1179,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
case -EPIPE:
case -ENODEV:
case -ESHUTDOWN:
//padapter->bSurpriseRemoved=true;
/* padapter->bSurpriseRemoved=true; */
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
case -ENOENT:
padapter->bDriverStopped=true;
@ -1253,7 +1251,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
if (precvbuf != NULL) {
rtl8188eu_init_recvbuf(adapter, precvbuf);
//re-assign for linux based on skb
/* re-assign for linux based on skb */
if ((precvbuf->reuse == false) || (precvbuf->pskb == NULL)) {
precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
@ -1272,7 +1270,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
} else//reuse skb
} else/* reuse skb */
{
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
@ -1287,12 +1285,12 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
purb = precvbuf->purb;
//translate DMA FIFO addr to pipehandle
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_bulk_urb(purb, pusbd, pipe, precvbuf->pbuf,
MAX_RECVBUF_SZ, usb_read_port_complete,
precvbuf);//context is precvbuf
precvbuf);/* context is precvbuf */
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != (-EPERM))) {
@ -1309,7 +1307,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
}
return ret;
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
void rtl8188eu_xmit_tasklet(void *priv)
{