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rtl8188eu: Convert typedef statements in include/Hal8188EPhyCfg.h

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-07-26 13:36:38 -05:00
parent b925112e2a
commit 7449a3d03b
11 changed files with 92 additions and 119 deletions
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118
include/Hal8188EPhyCfg.h
View file

@ -40,7 +40,7 @@
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
enum sw_chnl_cmd_id {
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
@ -48,32 +48,31 @@ typedef enum _SwChnlCmdID{
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
};
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
struct sw_chnl_cmd {
enum sw_chnl_cmd_id CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
};
typedef enum _HW90_BLOCK{
enum hw90_block {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
};
typedef enum _RF_RADIO_PATH{
enum rf_radio_path {
RF_PATH_A = 0, //Radio Path A
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
};
#define MAX_PG_GROUP 13
@ -85,7 +84,7 @@ typedef enum _RF_RADIO_PATH{
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups
#define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE {
enum wireless_mode {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
@ -94,10 +93,9 @@ typedef enum _WIRELESS_MODE {
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
};
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
enum phy_rate_tx_offset_area {
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
@ -105,79 +103,59 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
};
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
enum RF_TYPE_8190P {
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
// TODO: We should remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
};
struct bb_reg_def {
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
};
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
struct ant_sel_ofdm {
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
@ -187,13 +165,13 @@ typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
};
typedef struct _R_ANTENNA_SELECT_CCK{
struct ant_sel_cck {
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
};
/*------------------------------Define structure----------------------------*/
@ -217,8 +195,8 @@ void rtl8188e_PHY_SetBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
void rtl8188e_PHY_SetRFReg(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
u32 rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask);
void rtl8188e_PHY_SetRFReg(PADAPTER Adapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
//
// Initialization related function
@ -229,9 +207,9 @@ int PHY_BBConfig8188E( PADAPTER Adapter );
int PHY_RFConfig8188E( PADAPTER Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(PADAPTER Adapter, u8 * pFileName, RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithParaFile(PADAPTER Adapter, u8 * pFileName, enum rf_radio_path eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath);
enum rf_radio_path eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( PADAPTER Adapter );

8
include/hal_intf.h
View file

@ -212,8 +212,8 @@ struct hal_ops {
u32 (*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
u32 (*read_rfreg)(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
void (*write_rfreg)(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
u32 (*read_rfreg)(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask);
void (*write_rfreg)(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest);
@ -405,8 +405,8 @@ void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
u32 rtw_hal_read_rfreg(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
void rtw_hal_write_rfreg(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask);
void rtw_hal_write_rfreg(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
s32 rtw_hal_interrupt_handler(_adapter *padapter);

4
include/rtl8188e_hal.h
View file

@ -302,7 +302,7 @@ typedef struct hal_data_8188e
u8 PGMaxGroup;
//current WIFI_PHY values
u32 ReceiveConfig;
WIRELESS_MODE CurrentWirelessMode;
enum wireless_mode CurrentWirelessMode;
HT_CHANNEL_WIDTH CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
@ -390,7 +390,7 @@ typedef struct hal_data_8188e
//u8 bCurrentTurboEDCA;
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
struct bb_reg_def PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];

2
include/rtw_mp.h
View file

@ -233,7 +233,7 @@ typedef struct _MPT_CONTEXT
// The RfPath of IO operation is depend of MptActType.
ULONG MptRfPath;
WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch.
enum wireless_mode MptWirelessModeToSw; // Wireless mode to switch.
u8 MptChannelToSw; // Channel to switch.
u8 MptInitGainToSet; // Initial gain to set.
//ULONG bMptAntennaA; // true if we want to use antenna A.