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rtl8188eu: Remove dead code inside #if 0 ... #endif

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-05-18 16:16:10 -05:00
parent 3ad757d04a
commit 77e736c66a
64 changed files with 98 additions and 7692 deletions
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246
core/rtw_ap.c
View file

@ -330,13 +330,8 @@ u8 chk_sta_is_alive(struct sta_info *psta)
);
#endif
//if (sta_last_rx_pkts(psta) == sta_rx_pkts(psta))
if ((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts))
{
#if 0
if (psta->state&WIFI_SLEEP_STATE)
ret = _TRUE;
#endif
}
else
{
@ -623,125 +618,6 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level)
}
#endif //CONFIG_80211N_HT
#if 0//gtest
if (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)
{
//is this a 2r STA?
if ((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid)))
{
priv->pshare->has_2r_sta |= BIT(pstat->aid);
if (rtw_read16(padapter, 0x102501f6) != 0xffff)
{
rtw_write16(padapter, 0x102501f6, 0xffff);
reset_1r_sta_RA(priv, 0xffff);
Switch_1SS_Antenna(priv, 3);
}
}
else// bg or 1R STA?
{
if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0)
{
if (rtw_read16(padapter, 0x102501f6) != 0x7777)
{ // MCS7 SGI
rtw_write16(padapter, 0x102501f6,0x7777);
reset_1r_sta_RA(priv, 0x7777);
Switch_1SS_Antenna(priv, 2);
}
}
}
}
if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3))
{
if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper)
pstat->rssi_level = 1;
else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) ||
((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) &&
(pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) &&
(pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_))))
pstat->rssi_level = 2;
else
pstat->rssi_level = 3;
}
// rate adaptive by rssi
if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len)
{
if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R))
{
switch (pstat->rssi_level) {
case 1:
pstat->tx_ra_bitmap &= 0x100f0000;
break;
case 2:
pstat->tx_ra_bitmap &= 0x100ff000;
break;
case 3:
if (priv->pshare->is_40m_bw)
pstat->tx_ra_bitmap &= 0x100ff005;
else
pstat->tx_ra_bitmap &= 0x100ff001;
break;
}
}
else
{
switch (pstat->rssi_level) {
case 1:
pstat->tx_ra_bitmap &= 0x1f0f0000;
break;
case 2:
pstat->tx_ra_bitmap &= 0x1f0ff000;
break;
case 3:
if (priv->pshare->is_40m_bw)
pstat->tx_ra_bitmap &= 0x000ff005;
else
pstat->tx_ra_bitmap &= 0x000ff001;
break;
}
// Don't need to mask high rates due to new rate adaptive parameters
//if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta
// pstat->tx_ra_bitmap &= 0x81ffffff;
// NIC driver will report not supporting MCS15 and MCS14 in asoc req
//if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta)
// pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14
}
}
else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat))
{
switch (pstat->rssi_level) {
case 1:
pstat->tx_ra_bitmap &= 0x00000f00;
break;
case 2:
pstat->tx_ra_bitmap &= 0x00000ff0;
break;
case 3:
pstat->tx_ra_bitmap &= 0x00000ff5;
break;
}
}
else
{
pstat->tx_ra_bitmap &= 0x0000000d;
}
// disable tx short GI when station cannot rx MCS15(AP is 2T2R)
// disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R)
// if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate
if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) ||
(!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R)))
{
pstat->tx_ra_bitmap &= ~BIT(28);
}
#endif
if ( pcur_network->Configuration.DSConfig > 14 ) {
// 5G band
if (tx_ra_bitmap & 0xffff000)
@ -1482,49 +1358,8 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
psecuritypriv->wpa2_group_cipher = group_cipher;
psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher;
#if 0
switch (group_cipher)
{
case WPA_CIPHER_NONE:
psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
break;
case WPA_CIPHER_WEP40:
psecuritypriv->wpa2_group_cipher = _WEP40_;
break;
case WPA_CIPHER_TKIP:
psecuritypriv->wpa2_group_cipher = _TKIP_;
break;
case WPA_CIPHER_CCMP:
psecuritypriv->wpa2_group_cipher = _AES_;
break;
case WPA_CIPHER_WEP104:
psecuritypriv->wpa2_group_cipher = _WEP104_;
break;
}
switch (pairwise_cipher)
{
case WPA_CIPHER_NONE:
psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
break;
case WPA_CIPHER_WEP40:
psecuritypriv->wpa2_pairwise_cipher = _WEP40_;
break;
case WPA_CIPHER_TKIP:
psecuritypriv->wpa2_pairwise_cipher = _TKIP_;
break;
case WPA_CIPHER_CCMP:
psecuritypriv->wpa2_pairwise_cipher = _AES_;
break;
case WPA_CIPHER_WEP104:
psecuritypriv->wpa2_pairwise_cipher = _WEP104_;
break;
}
#endif
}
}
//wpa
ie_len = 0;
group_cipher = 0; pairwise_cipher = 0;
@ -1545,56 +1380,11 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
psecuritypriv->wpa_group_cipher = group_cipher;
psecuritypriv->wpa_pairwise_cipher = pairwise_cipher;
#if 0
switch (group_cipher)
{
case WPA_CIPHER_NONE:
psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
break;
case WPA_CIPHER_WEP40:
psecuritypriv->wpa_group_cipher = _WEP40_;
break;
case WPA_CIPHER_TKIP:
psecuritypriv->wpa_group_cipher = _TKIP_;
break;
case WPA_CIPHER_CCMP:
psecuritypriv->wpa_group_cipher = _AES_;
break;
case WPA_CIPHER_WEP104:
psecuritypriv->wpa_group_cipher = _WEP104_;
break;
}
switch (pairwise_cipher)
{
case WPA_CIPHER_NONE:
psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
break;
case WPA_CIPHER_WEP40:
psecuritypriv->wpa_pairwise_cipher = _WEP40_;
break;
case WPA_CIPHER_TKIP:
psecuritypriv->wpa_pairwise_cipher = _TKIP_;
break;
case WPA_CIPHER_CCMP:
psecuritypriv->wpa_pairwise_cipher = _AES_;
break;
case WPA_CIPHER_WEP104:
psecuritypriv->wpa_pairwise_cipher = _WEP104_;
break;
}
#endif
}
break;
}
if ((p == NULL) || (ie_len == 0))
{
break;
}
break;
}
@ -2254,19 +2044,6 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
#if 0
if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) &&
!psta->no_short_preamble_set) {
psta->no_short_preamble_set = 1;
pmlmepriv->num_sta_no_short_preamble++;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
(pmlmepriv->num_sta_no_short_preamble == 1))
ieee802_11_set_beacons(hapd->iface);
}
#endif
if (!(psta->flags & WLAN_STA_SHORT_PREAMBLE))
{
if (!psta->no_short_preamble_set)
@ -2302,15 +2079,6 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
}
}
#if 0
if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) {
psta->nonerp_set = 1;
pmlmepriv->num_sta_non_erp++;
if (pmlmepriv->num_sta_non_erp == 1)
ieee802_11_set_beacons(hapd->iface);
}
#endif
if (psta->flags & WLAN_STA_NONERP)
{
if (!psta->nonerp_set)
@ -2344,18 +2112,6 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
}
#if 0
if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) &&
!psta->no_short_slot_time_set) {
psta->no_short_slot_time_set = 1;
pmlmepriv->num_sta_no_short_slot_time++;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
(pmlmepriv->num_sta_no_short_slot_time == 1))
ieee802_11_set_beacons(hapd->iface);
}
#endif
if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT))
{
if (!psta->no_short_slot_time_set)

32
core/rtw_br_ext.c
View file

@ -1571,38 +1571,6 @@ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb)
return 0;
}
#if 0
void mac_clone(_adapter *priv, unsigned char *addr)
{
struct sockaddr sa;
memcpy(sa.sa_data, addr, ETH_ALEN);
DEBUG_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n",
addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
rtl8192cd_set_hwaddr(priv->dev, &sa);
}
int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb)
{
if (priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed)
{
if (!(skb->data[ETH_ALEN] & 1)) //// check any other particular MAC add
{
if (memcmp(skb->data+ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) &&
((priv->dev->br_port) &&
memcmp(skb->data+ETH_ALEN, priv->br_mac, ETH_ALEN)))
{
mac_clone(priv, skb->data+ETH_ALEN);
priv->macclone_completed = 1;
}
}
}
return 0;
}
#endif // 0
#define SERVER_PORT 67
#define CLIENT_PORT 68
#define DHCP_MAGIC 0x63825363

30
core/rtw_cmd.c
View file

@ -1302,19 +1302,6 @@ _func_enter_;
DBG_871X("%s: smart_ps=%d\n", __func__, padapter->pwrctrlpriv.smart_ps);
#if 0
psecuritypriv->supplicant_ie[0]=(u8)psecnetwork->IELength;
if (psecnetwork->IELength < (256-1))
{
_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength);
}
else
{
_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256-1));
}
#endif
pcmd->cmdsz = get_WLAN_BSSID_EX_sz(psecnetwork);//get cmdsz before endian conversion
#ifdef CONFIG_RTL8712
@ -2911,23 +2898,6 @@ _func_enter_;
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
#if 0
if ((pmlmepriv->fw_state) & WIFI_AP_STATE)
{
psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress);
if (psta == NULL) { // for AP Mode & Adhoc Master Mode
RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n"));
goto createbss_cmd_fail ;
}
rtw_indicate_connect( padapter);
}
else {
//rtw_indicate_disconnect(dev);
}
#endif
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
// we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback)

11
core/rtw_efuse.c
View file

@ -1262,15 +1262,6 @@ int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
ret = _SUCCESS;
else
ret = _FAIL;
#if 0
if (isAdaptorInfoFileValid()) {
return 0;
} else {
return _FAIL;
}
#endif
} else {
DBG_871X("%s NULL pointer\n",__func__);
ret = _FAIL;
@ -1279,5 +1270,3 @@ int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv)
}
#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
#endif //PLATFORM_LINUX

25
core/rtw_ieee80211.c
View file

@ -1574,17 +1574,6 @@ static uint rtw_p2p_attr_remove(u8 *ie, uint ielen_ori, u8 attr_id)
{
u8 *next_attr = target_attr+target_attr_len;
uint remain_len = ielen-(next_attr-ie);
//dump_ies(ie, ielen);
#if 0
DBG_871X("[%d] ie:%p, ielen:%u\n"
"target_attr:%p, target_attr_len:%u\n"
"next_attr:%p, remain_len:%u\n"
, index++
, ie, ielen
, target_attr, target_attr_len
, next_attr, remain_len
);
#endif
_rtw_memset(target_attr, 0, target_attr_len);
_rtw_memcpy(target_attr, next_attr, remain_len);
@ -1594,8 +1583,6 @@ static uint rtw_p2p_attr_remove(u8 *ie, uint ielen_ori, u8 attr_id)
}
else
{
//if (index>0)
// dump_ies(ie, ielen);
break;
}
}
@ -1611,13 +1598,6 @@ void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
if ( (p2p_ie=rtw_get_p2p_ie(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_, NULL, &p2p_ielen_ori)) )
{
#if 0
if (rtw_get_p2p_attr(p2p_ie, p2p_ielen_ori, attr_id, NULL, NULL)) {
DBG_871X("rtw_get_p2p_attr: GOT P2P_ATTR:%u!!!!!!!!\n", attr_id);
dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_);
}
#endif
p2p_ielen=rtw_p2p_attr_remove(p2p_ie, p2p_ielen_ori, attr_id);
if (p2p_ielen != p2p_ielen_ori) {
@ -1628,11 +1608,6 @@ void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
_rtw_memcpy(next_ie, next_ie_ori, remain_len);
_rtw_memset(next_ie+remain_len, 0, p2p_ielen_ori-p2p_ielen);
bss_ex->IELength -= p2p_ielen_ori-p2p_ielen;
#if 0
DBG_871X("remove P2P_ATTR:%u!\n", attr_id);
dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_);
#endif
}
}
}

16
core/rtw_ioctl_set.c
View file

@ -178,21 +178,6 @@ _func_enter_;
// can't associate ; reset under-linking
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
#if 0
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE))
{
if (_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength))
{
// for funk to do roaming
// funk will reconnect, but funk will not sitesurvey before reconnect
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("for funk to do roaming"));
if (pmlmepriv->sitesurveyctrl.traffic_busy==_FALSE)
rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
}
}
#endif
//when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue
//we try to issue sitesurvey firstly
if (pmlmepriv->LinkDetectInfo.bBusyTraffic==_FALSE
@ -201,7 +186,6 @@ _func_enter_;
#endif
)
{
//DBG_871X("rtw_do_join() when no desired bss in scanning queue\n");
if ( _SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ){
pmlmepriv->to_join = _FALSE;
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("do_join(): site survey return error\n."));

207
core/rtw_mlme.c
View file

@ -774,41 +774,6 @@ _func_enter_;
}
#endif
#if 0 // old codes, may be useful one day...
// DBG_871X("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi);
if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src))
{
//DBG_871X("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal);
if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
{
padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
padapter->recvpriv.signal_qual_data.total_val -= last_evm;
}
padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi);
padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi);
if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
padapter->recvpriv.signal_qual_data.index = 0;
//DBG_871X("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi);
// <1> Showed on UI for user,in percentage.
tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
padapter->recvpriv.signal=(u8)tmpVal;//Link quality
src->Rssi= translate_percentage_to_dbm(padapter->recvpriv.signal) ;
}
else{
// DBG_871X("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi);
src->Rssi=(src->Rssi +dst->Rssi)/2;//dBM
}
// DBG_871X("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal);
#endif
_func_exit_;
}
@ -827,26 +792,15 @@ _func_enter_;
if ( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork)))
{
//RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n");
//if (pmlmepriv->cur_network.network.IELength<= pnetwork->IELength)
{
update_network(&(pmlmepriv->cur_network.network), pnetwork,adapter, _TRUE);
rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof (NDIS_802_11_FIXED_IEs),
pmlmepriv->cur_network.network.IELength);
}
update_network(&(pmlmepriv->cur_network.network), pnetwork,adapter, _TRUE);
rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof (NDIS_802_11_FIXED_IEs),
pmlmepriv->cur_network.network.IELength);
}
_func_exit_;
}
/*
Caller must hold pmlmepriv->lock first.
*/
void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
{
@ -2364,13 +2318,6 @@ void _rtw_join_timeout_handler (_adapter *adapter)
int do_join_r;
#endif //CONFIG_LAYER2_ROAMING
#if 0
if (adapter->bDriverStopped == _TRUE){
_rtw_up_sema(&pmlmepriv->assoc_terminate);
return;
}
#endif
_func_enter_;
#ifdef PLATFORM_FREEBSD
rtw_mtx_lock(NULL);
@ -2701,47 +2648,6 @@ static int rtw_check_join_candidate(struct mlme_priv *pmlmepriv
*candidate = competitor;
updated = _TRUE;
}
#if 0
if (pmlmepriv->assoc_by_bssid==_TRUE) { // associate with bssid
if ( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
&& _rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE
) {
*candidate = competitor;
updated = _TRUE;
}
} else if (pmlmepriv->assoc_ssid.SsidLength == 0 ) { // associate with ssid, but ssidlength is 0
if ( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi ) ) {
*candidate = competitor;
updated = _TRUE;
}
} else
#ifdef CONFIG_LAYER2_ROAMING
if (pmlmepriv->to_roaming) { // roaming
if ( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
&& is_same_ess(&competitor->network, &pmlmepriv->cur_network.network)
//&&(!is_same_network(&competitor->network, &pmlmepriv->cur_network.network))
&& rtw_get_passing_time_ms((u32)competitor->last_scanned) < RTW_SCAN_RESULT_EXPIRE
&& rtw_is_desired_network(adapter, competitor)
) {
*candidate = competitor;
updated = _TRUE;
}
} else
#endif
{ // associate with ssid
if ( (*candidate == NULL ||(*candidate)->network.Rssi<competitor->network.Rssi )
&& (competitor->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength)
&&((_rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE)
&& rtw_is_desired_network(adapter, competitor)
) {
*candidate = competitor;
updated = _TRUE;
}
}
#endif
if (updated){
DBG_871X("[by_bssid:%u][assoc_ssid:%s]"
#ifdef CONFIG_LAYER2_ROAMING
@ -2766,12 +2672,8 @@ exit:
/*
Calling context:
The caller of the sub-routine will be in critical section...
The caller must hold the following spinlock
pmlmepriv->lock
*/
int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv )
@ -2804,10 +2706,6 @@ _func_enter_;
pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
#if 0
DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid);
#endif
rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);
}
@ -2831,18 +2729,6 @@ _func_enter_;
{
DBG_871X("%s: _FW_LINKED while ask_for_joinbss!!!\n", __func__);
#if 0 // for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP...
if (is_same_network(&pmlmepriv->cur_network.network, &candidate->network))
{
DBG_871X("%s: _FW_LINKED and is same network, it needn't join again\n", __func__);
rtw_indicate_connect(adapter);//rtw_indicate_connect again
ret = 2;
goto exit;
}
else
#endif
{
rtw_disassoc_cmd(adapter, 0, _TRUE);
rtw_indicate_disconnect(adapter);
@ -2911,25 +2797,16 @@ _func_enter_;
pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
#if 0
DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid);
#endif
if (pmlmepriv->assoc_by_bssid==_TRUE)
{
if (_rtw_memcmp(pnetwork->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE)
{
//remove the condition @ 20081125
//if ((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)||
// pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode)
// goto ask_for_joinbss;
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
{
if (is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network))
{
//DBG_871X("select_and_join(1): _FW_LINKED and is same network, it needn't join again\n");
rtw_indicate_connect(adapter);//rtw_indicate_connect again
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
return 2;
@ -3002,27 +2879,11 @@ _func_enter_;
{
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
{
#if 0
if (is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network))
{
DBG_871X("select_and_join(2): _FW_LINKED and is same network, it needn't join again\n");
rtw_indicate_connect(adapter);//rtw_indicate_connect again
return 2;
}
else
#endif
{
rtw_disassoc_cmd(adapter, 0, _TRUE);
//rtw_indicate_disconnect(adapter);//
rtw_free_assoc_resources(adapter, 0);
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
goto ask_for_joinbss;
}
}
else
{
rtw_disassoc_cmd(adapter, 0, _TRUE);
rtw_free_assoc_resources(adapter, 0);
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
goto ask_for_joinbss;
} else {
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
goto ask_for_joinbss;
}
@ -3422,16 +3283,6 @@ void rtw_update_registrypriv_dev_network(_adapter* adapter)
_func_enter_;
#if 0
pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
pxmitpriv->vcs = pregistrypriv->vcs_type;
pxmitpriv->vcs_type = pregistrypriv->vcs_type;
//pxmitpriv->rts_thresh = pregistrypriv->rts_thresh;
pxmitpriv->frag_len = pregistrypriv->frag_thresh;
adapter->qospriv.qos_option = pregistrypriv->wmm_enable;
#endif
pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; // adhoc no 802.1x
pdev_network->Rssi = 0;
@ -3780,47 +3631,6 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len)
#if 0 //move to rtw_update_sta_info_client()
//for A-MPDU Rx reordering buffer control for bmc_sta & sta_info
//if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff
//todo: check if AP can send A-MPDU packets
bmc_sta = rtw_get_bcmc_stainfo(padapter);
if (bmc_sta)
{
for (i=0; i < 16 ; i++)
{
//preorder_ctrl = &precvpriv->recvreorder_ctrl[i];
preorder_ctrl = &bmc_sta->recvreorder_ctrl[i];
preorder_ctrl->enable = _FALSE;
preorder_ctrl->indicate_seq = 0xffff;
#ifdef DBG_RX_SEQ
DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __func__, __LINE__,
preorder_ctrl->indicate_seq);
#endif
preorder_ctrl->wend_b= 0xffff;
preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32
}
}
psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
if (psta)
{
for (i=0; i < 16 ; i++)
{
//preorder_ctrl = &precvpriv->recvreorder_ctrl[i];
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->enable = _FALSE;
preorder_ctrl->indicate_seq = 0xffff;
#ifdef DBG_RX_SEQ
DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __func__, __LINE__,
preorder_ctrl->indicate_seq);
#endif
preorder_ctrl->wend_b= 0xffff;
preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32
}
}
#endif
}
void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe)
@ -3832,7 +3642,6 @@ void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe)
struct pkt_attrib *pattrib =&pxmitframe->attrib;
s32 bmcst = IS_MCAST(pattrib->ra);
//if (bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE))
if (bmcst || (padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod<100))
return;

289
core/rtw_mlme_ext.c
View file

@ -372,10 +372,6 @@ static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set,
struct p2p_oper_class_map op_class[] = {
{ IEEE80211G, 81, 1, 13, 1, BW20 },
{ IEEE80211G, 82, 14, 14, 1, BW20 },
#if 0 /* Do not enable HT40 on 2 GHz */
{ IEEE80211G, 83, 1, 9, 1, BW40PLUS },
{ IEEE80211G, 84, 5, 13, 1, BW40MINUS },
#endif
{ IEEE80211A, 115, 36, 48, 4, BW20 },
{ IEEE80211A, 116, 36, 44, 8, BW40PLUS },
{ IEEE80211A, 117, 40, 48, 8, BW40MINUS },
@ -634,18 +630,6 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n",
GetFrameType(pframe), GetFrameSubType(pframe)));
#if 0
{
u8 *pbuf;
pbuf = GetAddr1Ptr(pframe);
DBG_871X("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5));
pbuf = GetAddr2Ptr(pframe);
DBG_871X("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5));
pbuf = GetAddr3Ptr(pframe);
DBG_871X("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5));
}
#endif
if (GetFrameType(pframe) != WIFI_MGT_TYPE)
{
RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe)));
@ -994,19 +978,6 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
}
#if 0 //move to validate_recv_mgnt_frame
if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))
{
if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
{
if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL)
{
psta->sta_stats.rx_mgnt_pkts++;
}
}
}
#endif
return _SUCCESS;
}
@ -1102,9 +1073,6 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
#endif //CONFIG_P2P_PS
#if 0 //move to validate_recv_mgnt_frame
psta->sta_stats.rx_mgnt_pkts++;
#endif
}
}
else if ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
@ -1119,9 +1087,6 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
update_beacon_info(padapter, pframe, len, psta);
}
#if 0 //move to validate_recv_mgnt_frame
psta->sta_stats.rx_mgnt_pkts++;
#endif
}
else
{
@ -1191,28 +1156,6 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
seq = cpu_to_le16(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + 2));
algorithm = cpu_to_le16(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN));
if (GetPrivacy(pframe))
{
#if 0 //TODO: SW rtw_wep_decrypt
if (SWCRYPTO)
{
status = rtw_wep_decrypt(priv, pframe, pfrinfo->pktlen,
priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm);
if (status == FALSE)
{
SAVE_INT_AND_CLI(flags);
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"wep-decrypt a Auth frame error!\n");
status = _STATS_CHALLENGE_FAIL_;
goto auth_fail;
}
}
seq = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4 + 2));
algorithm = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4));
#endif
}
DBG_871X("auth alg=%x, seq=%X\n", algorithm, seq);
if (auth_mode == 2 &&
@ -1231,42 +1174,11 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
goto auth_fail;
}
#if 0 //ACL control
phead = &priv->wlan_acl_list;
plist = phead->next;
//check sa
if (acl_mode == 1) // 1: positive check, only those on acl_list can be connected.
res = FAIL;
else
res = SUCCESS;
while (plist != phead)
{
paclnode = list_entry(plist, struct rtw_wlan_acl_node, list);
plist = plist->next;
if (!memcmp((void *)sa, paclnode->addr, 6)) {
if (paclnode->mode & 2) { // deny
res = FAIL;
break;
}
else {
res = SUCCESS;
break;
}
}
}
if (res != SUCCESS) {
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"auth abort because ACL!\n");
return FAIL;
}
#else
if (rtw_access_ctrl(padapter, sa) == _FALSE)
{
status = _STATS_UNABLE_HANDLE_STA_;
goto auth_fail;
}
#endif
pstat = rtw_get_stainfo(pstapriv, sa);
if (pstat == NULL)
@ -1284,8 +1196,6 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
pstat->state = WIFI_FW_AUTH_NULL;
pstat->auth_seq = 0;
//pstat->flags = 0;
//pstat->capability = 0;
}
else
{
@ -1628,31 +1538,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
pstat->state &= (~WIFI_FW_AUTH_SUCCESS);
pstat->state |= WIFI_FW_ASSOC_STATE;
}
#if 0// todo:tkip_countermeasures
if (hapd->tkip_countermeasures) {
resp = WLAN_REASON_MICHAEL_MIC_FAILURE;
goto fail;
}
#endif
pstat->capability = capab_info;
#if 0//todo:
//check listen_interval
if (listen_interval > hapd->conf->max_listen_interval) {
hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211,
HOSTAPD_LEVEL_DEBUG,
"Too large Listen Interval (%d)",
listen_interval);
resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE;
goto fail;
}
pstat->listen_interval = listen_interval;
#endif
//now parse all ieee802_11 ie to point to elems
if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed ||
!elems.ssid) {
@ -6785,16 +6671,6 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, int wai
pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
}
#if 0
//add wps_ie for wps2.0
if (pmlmepriv->probereq_wpsie_len>0 && pmlmepriv->probereq_wpsie_len<MAX_WPS_IE_LEN)
{
_rtw_memcpy(pframe, pmlmepriv->probereq_wpsie, pmlmepriv->probereq_wpsie_len);
pframe += pmlmepriv->probereq_wpsie_len;
pattrib->pktlen += pmlmepriv->probereq_wpsie_len;
//pmlmepriv->probereq_wpsie_len = 0 ;//reset to zero
}
#else
//add wps_ie for wps2.0
if (pmlmepriv->wps_probe_req_ie_len>0 && pmlmepriv->wps_probe_req_ie)
{
@ -6803,7 +6679,6 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, int wai
pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
//pmlmepriv->wps_probe_req_ie_len = 0 ;//reset to zero
}
#endif
pattrib->last_txcmdsz = pattrib->pktlen;
@ -7326,9 +7201,6 @@ void issue_assocreq(_adapter *padapter)
DBG_871X("bssrate_len = %d\n", bssrate_len);
#else // Check if the AP's supported rates are also supported by STA.
#if 0
get_rate_set(padapter, bssrate, &bssrate_len);
#else
for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) {
if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) break;
@ -7337,7 +7209,6 @@ void issue_assocreq(_adapter *padapter)
bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len];
}
#endif
#endif // Check if the AP's supported rates are also supported by STA.
if (bssrate_len == 0) {
@ -9078,16 +8949,7 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
}
//todo:
#if 0
if (judge_network_type(bssid->SupportedRates, (len + i)) == WIRELESS_11B)
{
bssid->NetworkTypeInUse = Ndis802_11DS;
}
else
#endif
{
bssid->NetworkTypeInUse = Ndis802_11OFDM24;
}
bssid->NetworkTypeInUse = Ndis802_11OFDM24;
if (bssid->IELength < 12)
return _FAIL;
@ -9680,22 +9542,6 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
#endif
#endif
#if 0
// recover the right channel index
channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
k = 0;
while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0))
{
if (chplan_new[k].ChannelNum == channel) {
RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_,
("%s: change mlme_ext sitesurvey channel index from %d to %d\n",
__func__, pmlmeext->sitesurvey_res.channel_idx, k));
pmlmeext->sitesurvey_res.channel_idx = k;
break;
}
k++;
}
#endif
}
// If channel is used by AP, set channel scan type to active
@ -10280,22 +10126,6 @@ void _linked_rx_signal_strehgth_display(_adapter *padapter)
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 mac_id;
int UndecoratedSmoothedPWDB;
#if 0
DBG_871X("============ linked status check ===================\n");
DBG_871X("pathA Rx SNRdb:%d, pathB Rx SNRdb:%d\n",padapter->recvpriv.RxSNRdB[0], padapter->recvpriv.RxSNRdB[1]);
DBG_871X("pathA Rx PWDB:%d\n",padapter->recvpriv.rxpwdb);
rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
DBG_871X("UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB);
DBG_871X("Rx RSSI:%d\n",padapter->recvpriv.rssi);
DBG_871X("Rx Signal_strength:%d\n",padapter->recvpriv.signal_strength);
DBG_871X("Rx Signal_qual:%d\n",padapter->recvpriv.signal_qual);
if ( check_fwstate( &padapter->mlmepriv, _FW_LINKED ) )
{
DBG_871X("bw mode: %d, channel: %d\n", padapter->mlmeextpriv.cur_bwmode, padapter->mlmeextpriv.cur_channel );
DBG_871X("received bytes = %d\n", (u32) (padapter->recvpriv.rx_bytes - padapter->recvpriv.last_rx_bytes ) );
}
DBG_871X("============ linked status check ===================\n");
#endif
if ((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
{
mac_id=0;
@ -10306,15 +10136,6 @@ void _linked_rx_signal_strehgth_display(_adapter *padapter)
}
rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP,&mac_id);
#if 0
DBG_871X("============ RX GAIN / FALSE ALARM ===================\n");
DBG_871X(" DIG PATH-A(0x%02x), PATH-B(0x%02x)\n",rtw_read8(padapter,0xc50),rtw_read8(padapter,0xc58));
DBG_871X(" OFDM -Alarm DA2(0x%04x),DA4(0x%04x),DA6(0x%04x),DA8(0x%04x)\n",
rtw_read16(padapter,0xDA2),rtw_read16(padapter,0xDA4),rtw_read16(padapter,0xDA6),rtw_read16(padapter,0xDA8));
DBG_871X(" CCK -Alarm A5B(0x%02x),A5C(0x%02x)\n",rtw_read8(padapter,0xA5B),rtw_read8(padapter,0xA5C));
#endif
rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
DBG_871X("UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB);
@ -10685,69 +10506,6 @@ void link_timer_hdl(_adapter *padapter)
issue_assocreq(padapter);
set_link_timer(pmlmeext, REASSOC_TO);
}
#if 0
else if (is_client_associated_to_ap(padapter))
{
//linked infrastructure client mode
if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL)
{
/*to monitor whether the AP is alive or not*/
if (rx_pkt == psta->sta_stats.rx_pkts)
{
receive_disconnect(padapter, pmlmeinfo->network.MacAddress);
return;
}
else
{
rx_pkt = psta->sta_stats.rx_pkts;
set_link_timer(pmlmeext, DISCONNECT_TO);
}
//update the EDCA paramter according to the Tx/RX mode
update_EDCA_param(padapter);
/*to send the AP a nulldata if no frame is xmitted in order to keep alive*/
if (pmlmeinfo->link_count++ == 0)
{
tx_cnt = pxmitpriv->tx_pkts;
}
else if ((pmlmeinfo->link_count & 0xf) == 0)
{
if (tx_cnt == pxmitpriv->tx_pkts)
{
issue_nulldata(padapter, NULL, 0, 0, 0);
}
tx_cnt = pxmitpriv->tx_pkts;
}
} //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL)
}
else if (is_client_associated_to_ibss(padapter))
{
//linked IBSS mode
//for each assoc list entry to check the rx pkt counter
for (i = IBSS_START_MAC_ID; i < NUM_STA; i++)
{
if (pmlmeinfo->FW_sta_info[i].status == 1)
{
psta = pmlmeinfo->FW_sta_info[i].psta;
if (pmlmeinfo->FW_sta_info[i].rx_pkt == psta->sta_stats.rx_pkts)
{
pmlmeinfo->FW_sta_info[i].status = 0;
report_del_sta_event(padapter, psta->hwaddr);
}
else
{
pmlmeinfo->FW_sta_info[i].rx_pkt = psta->sta_stats.rx_pkts;
}
}
}
set_link_timer(pmlmeext, DISCONNECT_TO);
}
#endif
#ifdef PLATFORM_FREEBSD
rtw_mtx_unlock(NULL);
#endif
@ -10975,9 +10733,6 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
pmlmeinfo->HT_info_enable = 1;
//spec case only for cisco's ap because cisco's ap issue assoc rsp using mcs rate @40MHz or @20MHz
//#if !defined(CONFIG_CONCURRENT_MODE) && !defined(CONFIG_DUALMAC_CONCURRENT)
// if (pmlmeinfo->assoc_AP_vendor == ciscoAP)
//#endif
{
struct HT_info_element *pht_info = (struct HT_info_element *)(pIE->data);
@ -11012,41 +10767,9 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
i += (pIE->Length + 2);
}
#if 0
if (padapter->registrypriv.wifi_spec) {
// for WiFi test, follow WMM test plan spec
acparm = 0x002F431C; // VO
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
acparm = 0x005E541C; // VI
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
acparm = 0x0000A525; // BE
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
acparm = 0x0000A549; // BK
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
// for WiFi test, mixed mode with intel STA under bg mode throughput issue
if (padapter->mlmepriv.htpriv.ht_option == _FALSE){
acparm = 0x00004320;
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
}
}
else {
acparm = 0x002F3217; // VO
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
acparm = 0x005E4317; // VI
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
acparm = 0x00105320; // BE
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
acparm = 0x0000A444; // BK
rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
}
#endif
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
//config the initial gain under linking, need to write the BB registers
//initialgain = 0x1E;
//rtw_hal_set_hwreg(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain));
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
join_type = 0;
@ -11074,11 +10797,6 @@ u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms/100, 100);
}
//set_opmode_cmd(padapter, infra_client_with_mlme);
//pmlmeinfo->state = WIFI_FW_NULL_STATE;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
@ -11256,11 +10974,6 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
if ((pmlmeext->sitesurvey_res.state == SCAN_START) || (pmlmeext->sitesurvey_res.state == SCAN_TXNULL))
{
#ifdef CONFIG_FIND_BEST_CHANNEL
#if 0
for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) {
pmlmeext->channel_set[i].rx_count = 0;
}
#endif
#endif /* CONFIG_FIND_BEST_CHANNEL */
//disable dynamic functions, such as high power, DIG

88
core/rtw_mp.c
View file

@ -380,17 +380,6 @@ MPT_InitializeAdapter(
pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db
pMptCtx->h2cReqNum = 0x0;
/* Init mpt event. */
#if 0 // for Windows
NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) );
NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
PlatformInitializeWorkItem(
Adapter,
&(pMptCtx->MptWorkItem),
(RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback,
(PVOID)Adapter,
"MptWorkItem");
#endif
//init for BT MP
#ifdef CONFIG_RTL8723A
pMptCtx->bMPh2c_timeout = _FALSE;
@ -415,17 +404,6 @@ MPT_InitializeAdapter(
rtw_write32(pAdapter, REG_RCR, 0x70000101);
#endif
#if 0
// If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP.
if (pHalData->AutoloadFailFlag == TRUE)
{
pHalData->RF_Type = RF_2T2R;
}
#endif
//ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
//rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
if (IS_HARDWARE_TYPE_8192DU(pAdapter))
{
rtw_write32(pAdapter, REG_LEDCFG0, 0x8888);
@ -502,18 +480,6 @@ MPT_DeInitAdapter(
_rtw_free_sema(&(pMptCtx->MPh2c_Sema));
_cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer);
#endif
#if 0 // for Windows
PlatformFreeWorkItem( &(pMptCtx->MptWorkItem) );
while (pMptCtx->bMptWorkItemInProgress)
{
if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
{
break;
}
}
NdisFreeSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
#endif
}
static u8 mpt_ProStartTest(PADAPTER padapter)
@ -656,14 +622,6 @@ s32 mp_start_test(PADAPTER padapter)
pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
if (padapter->registrypriv.mp_mode == 1)
pmlmepriv->fw_state = WIFI_MP_STATE;
#if 0
if (pmppriv->mode == _LOOPBOOK_MODE_) {
set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc
RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in Lookback mode\n"));
} else {
RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in normal mode\n"));
}
#endif
set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
//3 2. create a new psta for mp driver
@ -756,52 +714,6 @@ end_of_mp_stop_test:
}
}
/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
#if 0
//#ifdef CONFIG_USB_HCI
static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
{
u8 eRFPath;
u32 rfReg0x26;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
if (RateIdx < MPT_RATE_6M) { // CCK rate,for 88cu
rfReg0x26 = 0xf400;
}
else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {// OFDM rate,for 88cu
if ((4 == Channel) || (8 == Channel) || (12 == Channel))
rfReg0x26 = 0xf000;
else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
rfReg0x26 = 0xf400;
else
rfReg0x26 = 0x4f200;
}
else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {// MCS 20M ,for 88cu // MCS40M rate,for 88cu
if (HT_CHANNEL_WIDTH_20 == BandWidthID) {
if ((4 == Channel) || (8 == Channel))
rfReg0x26 = 0xf000;
else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
rfReg0x26 = 0xf400;
else
rfReg0x26 = 0x4f200;
}
else{
if ((4 == Channel) || (8 == Channel))
rfReg0x26 = 0xf000;
else if ((5 == Channel) || (7 == Channel))
rfReg0x26 = 0xf400;
else
rfReg0x26 = 0x4f200;
}
}
// RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26));
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
}
}
#endif
/*-----------------------------------------------------------------------------
* Function: mpt_SwitchRfSetting
*

1338
core/rtw_mp_ioctl.c
View file

File diff suppressed because it is too large Load diff

35
core/rtw_p2p.c
View file

@ -367,37 +367,19 @@ static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8* raddr,
wpsielen = 0;
// WPS OUI
//*(u32*) ( wpsie ) = cpu_to_be32( WPSOUI );
RTW_PUT_BE32(wpsie, WPSOUI);
wpsielen += 4;
#if 0
// WPS version
// Type:
*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 );
wpsielen += 2;
// Length:
*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 );
wpsielen += 2;
// Value:
wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0
#endif
// Config Method
// Type:
//*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD );
RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
wpsielen += 2;
// Length:
//*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 );
RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
wpsielen += 2;
// Value:
//*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method );
RTW_PUT_BE16(wpsie + wpsielen, config_method);
wpsielen += 2;
@ -4706,21 +4688,7 @@ void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE st
);
}
}
#if 0
void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line)
{
if (wdinfo->pre_p2p_state != -1) {
DBG_871X("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line
, p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state]
);
_rtw_p2p_restore_state(wdinfo);
} else {
DBG_871X("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line
, p2p_state_str[wdinfo->p2p_state]
);
}
}
#endif
void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line)
{
if (wdinfo->role != role) {
@ -4737,7 +4705,6 @@ void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, co
}
#endif //CONFIG_DBG_P2P
int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
{
int ret = _SUCCESS;

9
core/rtw_pwrctrl.c
View file

@ -892,15 +892,6 @@ void cpwm_int_hdl(
_func_enter_;
pwrpriv = &padapter->pwrctrlpriv;
#if 0
if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
("cpwm_int_hdl: tog(old)=0x%02x cpwm(new)=0x%02x toggle bit didn't change!?\n",
pwrpriv->cpwm_tog, preportpwrstate->state));
goto exit;
}
#endif
_enter_pwrlock(&pwrpriv->lock);
#ifdef CONFIG_LPS_RPWM_TIMER

196
core/rtw_recv.c
View file

@ -701,28 +701,12 @@ _func_enter_;
&& (psecuritypriv->busetkipkey==1 || prxattrib->encrypt !=_TKIP_ )
)
{
#if 0
if ((prxstat->icv==1)&&(prxattrib->encrypt!=_AES_))
{
psecuritypriv->hw_decrypted=_FALSE;
psecuritypriv->hw_decrypted=_TRUE;
#ifdef DBG_RX_DECRYPTOR
DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n"
, prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted);
#endif
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->hw_decrypted=_FALSE"));
rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);
return_packet=NULL;
}
else
#endif
{
psecuritypriv->hw_decrypted=_TRUE;
#ifdef DBG_RX_DECRYPTOR
DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n"
, prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted);
#endif
}
}
else {
#ifdef DBG_RX_DECRYPTOR
@ -737,7 +721,6 @@ _func_enter_;
return_packet = NULL;
}
//recvframe_chkmic(adapter, precv_frame); //move to recvframme_defrag function
_func_exit_;
@ -1734,21 +1717,6 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n"));
#if 0
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
{
#ifdef CONFIG_NATIVEAP_MLME
mgt_dispatcher(padapter, precv_frame);
#else
rtw_hostapd_mlme_rx(padapter, precv_frame);
#endif
}
else
{
mgt_dispatcher(padapter, precv_frame);
}
#endif
precv_frame = recvframe_chk_defrag(padapter, precv_frame);
if (precv_frame == NULL) {
RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,("%s: fragment packet\n",__func__));
@ -1964,14 +1932,6 @@ _func_enter_;
goto exit;
}
#if 0
if (psta->tdls_sta_state & TDLS_LINKED_STATE )
{
if (psta->dot118021XPrivacy==_AES_)
pattrib->encrypt=psta->dot118021XPrivacy;
}
#endif //CONFIG_TDLS
if (pattrib->privacy){
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy));
@ -2923,19 +2883,6 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
/* Indicat the packets to upper layer */
if (sub_m) {
#if 0
#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) {
sub_skb->ip_summed = CHECKSUM_UNNECESSARY;
} else {
sub_skb->ip_summed = CHECKSUM_NONE;
}
#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */
sub_skb->ip_summed = CHECKSUM_NONE;
#endif //CONFIG_TCP_CSUM_OFFLOAD_RX
#endif //0
if ( ((u32)(mtod(sub_m, caddr_t) + 14) % 4) != 0)
printf("%s()-%d: mtod(sub_m) = %p\n", __func__, __LINE__, mtod(sub_m, caddr_t));
#ifdef CONFIG_RX_INDICATE_QUEUE
@ -3111,74 +3058,6 @@ exit:
a_len -= (type_len + ETH_HLEN + padding_len) ;
#if 0
if (a_len > ETH_HLEN)
{
pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue);
if (pnrframe_new)
{
_pkt *pskb_copy;
unsigned int copy_len = pnrframe->u.hdr.len;
_rtw_init_listhead(&pnrframe_new->u.hdr.list);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
pskb_copy = dev_alloc_skb(copy_len+64);
#else
pskb_copy = netdev_alloc_skb(padapter->pnetdev, copy_len + 64);
#endif
if (pskb_copy==NULL)
{
DBG_871X("amsdu_to_msdu:can not all(ocate memory for skb copy\n");
}
pnrframe_new->u.hdr.pkt = pskb_copy;
_rtw_memcpy(pskb_copy->data, pnrframe->u.hdr.rx_data, copy_len);
pnrframe_new->u.hdr.rx_data = pnrframe->u.hdr.rx_data;
pnrframe_new->u.hdr.rx_tail = pnrframe->u.hdr.rx_data + copy_len;
if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE))
{
rtw_recv_indicatepkt(padapter, pnrframe_new);//indicate this recv_frame
}
else
{
rtw_free_recvframe(pnrframe_new, pfree_recv_queue);//free this recv_frame
}
}
else
{
DBG_871X("amsdu_to_msdu:can not allocate memory for pnrframe_new\n");
}
}
else
{
if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE))
{
rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame
}
else
{
rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame
}
pnrframe = NULL;
}
#else // 0
//padding_len = (4) - ((type_len + ETH_HLEN)&(4-1));
//a_len -= (type_len + ETH_HLEN + padding_len) ;
pnrframe_new = NULL;
@ -3189,9 +3068,6 @@ exit:
if (pnrframe_new)
{
//pnrframe_new->u.hdr.precvbuf = precvbuf;//precvbuf is assigned before call rtw_init_recvframe()
//rtw_init_recvframe(pnrframe_new, precvpriv);
{
#ifdef PLATFORM_LINUX
_pkt *pskb = pnrframe->u.hdr.pkt;
@ -3244,9 +3120,6 @@ exit:
pnrframe = pnrframe_new;
}
#endif // end defined (PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
}while (pnrframe);
exit:
@ -3255,7 +3128,6 @@ exit:
#endif
}
int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num);
int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
{
u8 wsize = preorder_ctrl->wsize_b;
@ -3408,21 +3280,11 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
phead = get_list_head(ppending_recvframe_queue);
plist = get_next(phead);
#if 0
// Check if there is any other indication thread running.
if (pTS->RxIndicateState == RXTS_INDICATE_PROCESSING)
return;
#endif
// Handling some condition for forced indicate case.
if (bforced==_TRUE)
{
if (rtw_is_list_empty(phead))
{
// _exit_critical_ex(&ppending_recvframe_queue->lock, &irql);
//_rtw_spinunlock_ex(&ppending_recvframe_queue->lock);
return _TRUE;
}
prframe = LIST_CONTAINOR(plist, union recv_frame, u);
pattrib = &prframe->u.hdr.attrib;
@ -3446,17 +3308,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,
("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n",
preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu));
#if 0
// This protect buffer from overflow.
if (index >= REORDER_WIN_SIZE)
{
RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!!\n"));
bPktInBuf = TRUE;
break;
}
#endif
plist = get_next(plist);
rtw_list_delete(&(prframe->u.hdr.list));
@ -3469,33 +3320,12 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
#endif
}
#if 0
index++;
if (index==1)
{
//Cancel previous pending timer.
//PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer);
if (bforced!=_TRUE)
{
//DBG_871X("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n");
_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);
}
}
#endif
//Set this as a lock to make sure that only one thread is indicating packet.
//pTS->RxIndicateState = RXTS_INDICATE_PROCESSING;
// Indicate packets
//RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!!\n"));
//indicate this recv_frame
//DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num);
if (!pattrib->amsdu)
{
//DBG_871X("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num);
if ((padapter->bDriverStopped == _FALSE) &&
(padapter->bSurpriseRemoved == _FALSE))
{
@ -3899,22 +3729,6 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
goto _recv_data_drop;
}
#if 0
if ( padapter->adapter_type == PRIMARY_ADAPTER )
{
DBG_871X("+++\n");
{
int i;
u8 *ptr = get_recvframe_data(prframe);
for (i=0; i<140;i=i+8)
DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i),
*(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7));
}
DBG_871X("---\n");
}
#endif
#ifdef CONFIG_TDLS
//check TDLS frame
psnap_type = get_recvframe_data(orig_prframe);

265
core/rtw_wlan_util.c
View file

@ -405,22 +405,6 @@ void Switch_DM_Func(_adapter *padapter, u32 mode, u8 enable)
#endif
rtw_hal_set_hwreg(padapter, HW_VAR_DM_FUNC_CLR, (u8 *)(&mode));
}
#if 0
u8 val8;
val8 = rtw_read8(padapter, FW_DYNAMIC_FUN_SWITCH);
if (enable == _TRUE)
{
rtw_write8(padapter, FW_DYNAMIC_FUN_SWITCH, (val8 | mode));
}
else
{
rtw_write8(padapter, FW_DYNAMIC_FUN_SWITCH, (val8 & mode));
}
#endif
}
static void Set_NETYPE1_MSR(_adapter *padapter, u8 type)
@ -734,40 +718,10 @@ void invalidate_cam_all(_adapter *padapter)
{
rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, 0);
}
#if 0
static u32 _ReadCAM(_adapter *padapter ,u32 addr)
{
u32 count = 0, cmd;
cmd = CAM_POLLINIG |addr ;
rtw_write32(padapter, RWCAM, cmd);
do{
if (0 == (rtw_read32(padapter,REG_CAMCMD) & CAM_POLLINIG)){
break;
}
}while (count++ < 100);
return rtw_read32(padapter,REG_CAMREAD);
}
void read_cam(_adapter *padapter ,u8 entry)
{
u32 j,count = 0, addr, cmd;
addr = entry << 3;
DBG_8192C("********* DUMP CAM Entry_#%02d***************\n",entry);
for (j = 0; j < 6; j++)
{
cmd = _ReadCAM(padapter ,addr+j);
DBG_8192C("offset:0x%02x => 0x%08x\n",addr+j,cmd);
}
DBG_8192C("*********************************\n");
}
#endif
void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key)
{
unsigned int i, val, addr;
//unsigned int cmd;
int j;
u32 cam_val[2];
@ -810,33 +764,10 @@ void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key)
void clear_cam_entry(_adapter *padapter, u8 entry)
{
#if 0
u32 addr, val=0;
u32 cam_val[2];
addr = entry << 3;
cam_val[0] = val;
cam_val[1] = addr + (unsigned int)0;
rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val);
cam_val[0] = val;
cam_val[1] = addr + (unsigned int)1;
rtw_hal_set_hwreg(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val);
#else
unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00};
write_cam(padapter, entry, 0, null_sta, null_key);
#endif
}
int allocate_fw_sta_entry(_adapter *padapter)
@ -1346,57 +1277,6 @@ void HTOnAssocRsp(_adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
#if 0 //move to rtw_update_ht_cap()
if ((pregpriv->cbw40_enable) &&
(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
(pmlmeinfo->HT_info.infos[0] & BIT(2)))
{
//switch to the 40M Hz mode accoring to the AP
pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40;
switch ((pmlmeinfo->HT_info.infos[0] & 0x3))
{
case HT_EXTCHNL_OFFSET_UPPER:
pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
break;
case HT_EXTCHNL_OFFSET_LOWER:
pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
break;
default:
pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
break;
}
//SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset);
}
#endif
//set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
#if 0 //move to rtw_update_ht_cap()
//
// Config SM Power Save setting
//
pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC)
{
/*u8 i;
//update the MCS rates
for (i = 0; i < 16; i++)
{
pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
}*/
DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__func__);
}
//
// Config current HT Protection mode.
//
pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
#endif
}
void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
@ -1707,16 +1587,6 @@ void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta
switch (pIE->ElementID)
{
#if 0
case _VENDOR_SPECIFIC_IE_:
//todo: to update WMM paramter set while receiving beacon
if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM
{
(WMM_param_handler(padapter, pIE))? WMMOnAssocRsp(padapter): 0;
}
break;
#endif
case _HT_EXTRA_INFO_IE_: //HT info
//HT_info_handler(padapter, pIE);
bwmode_update_check(padapter, pIE);
@ -2374,29 +2244,6 @@ void update_wireless_mode(_adapter *padapter)
void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value);
void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value)
{
#if 0
struct cmd_obj *ph2c;
struct reg_rw_parm *pwriteMacPara;
struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL)
{
return;
}
if ((pwriteMacPara = (struct reg_rw_parm*)rtw_malloc(sizeof(struct reg_rw_parm))) == NULL)
{
rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
return;
}
pwriteMacPara->rw = 1;
pwriteMacPara->addr = addr;
pwriteMacPara->value = value;
init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG));
rtw_enqueue_cmd(pcmdpriv, ph2c);
#endif
}
void update_bmc_sta_support_rate(_adapter *padapter, u32 mac_id)
@ -2503,108 +2350,6 @@ void beacon_timing_control(_adapter *padapter)
rtw_hal_bcn_related_reg_setting(padapter);
}
#if 0
unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
{
unsigned short ATIMWindow;
unsigned char *pframe;
struct tx_desc *ptxdesc;
struct rtw_ieee80211_hdr *pwlanhdr;
unsigned short *fctrl;
unsigned int rate_len, len = 0;
struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
_rtw_memset(beacon_frame, 0, 256);
pframe = beacon_frame + TXDESC_SIZE;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
SetFrameSubType(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
len = sizeof(struct rtw_ieee80211_hdr_3addr);
//timestamp will be inserted by hardware
pframe += 8;
len += 8;
// beacon interval: 2 bytes
_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
pframe += 2;
len += 2;
// capability info: 2 bytes
_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
pframe += 2;
len += 2;
// SSID
pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len);
// supported rates...
rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &len);
// DS parameter set
pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len);
// IBSS Parameter Set...
//ATIMWindow = cur->Configuration.ATIMWindow;
ATIMWindow = 0;
pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len);
//todo: ERP IE
// EXTERNDED SUPPORTED RATE
if (rate_len > 8)
{
pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len);
}
if ((len + TXDESC_SIZE) > 256)
{
//DBG_871X("marc: beacon frame too large\n");
return 0;
}
//fill the tx descriptor
ptxdesc = (struct tx_desc *)beacon_frame;
//offset 0
ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); //default = 32 bytes for TX Desc
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00);
//offset 8
ptxdesc->txdw2 |= cpu_to_le32(BMC);
ptxdesc->txdw2 |= cpu_to_le32(BK);
//offset 16
ptxdesc->txdw4 = 0x80000000;
//offset 20
ptxdesc->txdw5 = 0x00000000; //1M
return (len + TXDESC_SIZE);
}
#endif
static _adapter *pbuddy_padapter = NULL;
int rtw_handle_dualmac(_adapter *adapter, bool init)
@ -2613,16 +2358,6 @@ int rtw_handle_dualmac(_adapter *adapter, bool init)
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
if (init) {
#if 0
/* For SMSP on 92DU-VC, driver do not probe another Interface. */
if (dvobj->NumInterfaces == 2 && dvobj->InterfaceNumber != 0 &&
adapter->registrypriv.mac_phy_mode == 1) {
DBG_871X("%s(): Do not init another USB Interface because SMSP\n",__func__);
status = _FAIL;
goto exit;
}
#endif
if (pbuddy_padapter == NULL) {
pbuddy_padapter = adapter;
DBG_871X("%s(): pbuddy_padapter == NULL, Set pbuddy_padapter\n",__func__);

42
core/rtw_xmit.c
View file

@ -459,22 +459,6 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf
{
while (_TRUE)
{
#if 0 //Todo
//check IOT action
if (pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF)
{
pattrib->vcs_mode = CTS_TO_SELF;
pattrib->rts_rate = MGN_24M;
break;
}
else if (pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE))
{
pattrib->vcs_mode = RTS_CTS;
pattrib->rts_rate = MGN_24M;
break;
}
#endif
//IOT action
if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en==_TRUE) &&
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ))
@ -2371,14 +2355,6 @@ _func_enter_;
if (pregpriv->wifi_spec==1)
{
int j, tmp, acirp_cnt[4];
#if 0
if (flags<XMIT_QUEUE_ENTRY)
{
//priority exchange according to the completed xmitbuf flags.
inx[flags] = 0;
inx[0] = flags;
}
#endif
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
for (j=0; j<4; j++)
@ -2836,24 +2812,6 @@ int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb)
*((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr;
}
}
#if 0
else{
if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) {
is_vlan_tag = 1;
}
if (is_vlan_tag){
if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)){
memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
}
}else
{
if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)){
memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
}
}
}
#endif // 0
// check if SA is equal to our MAC
if (memcmp(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) {

16
hal/Hal8188ERateAdaptive.c
View file

@ -61,16 +61,6 @@ static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate
static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
#if 0
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SS<TH
4,4,5,5,6,0x0a,0x11,0x13,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
@ -124,12 +114,6 @@ static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
2,2,3,3,4,4,5,7,
4,4,7,10,10,12,12,18,
5,7,7,8,11,18,36,60}; // 0329 // 1207
#if 0
static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30,
30,30,25,25,20,15,15,10,
30,25,25,20,15,10,10,10,
30,25,25,20,15,10,10,10};
#endif
static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
1,2,3,4,5,6,7,8,

6
hal/HalPhyRf.c
View file

@ -799,12 +799,6 @@ phy_APCalibrate_8192C(
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
};
#if 0
u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
{0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
{0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
};
#endif
u4Byte AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on

120
hal/HalPhyRf_8188e.c
View file

@ -512,25 +512,9 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
#if 0
//wirte new elements A, C, D to regC80 and regC94, element B is always 0
value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
value32 = (ele_C&0x000003C0)>>6;
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
value32 = ((X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
#endif
}
else
{
#if 0
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[0]]);
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking for path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xe94 = 0x%x 0xe9c = 0x%x\n",
@ -541,29 +525,6 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
#if 0
//Adjust CCK according to IQK result
if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14){
ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][0]);
ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][1]);
ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][2]);
ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][3]);
ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][4]);
ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][5]);
ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][6]);
ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][7]);
}
else{
ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14[(u1Byte)CCK_index][0]);
ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14[(u1Byte)CCK_index][1]);
ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14[(u1Byte)CCK_index][2]);
ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14[(u1Byte)CCK_index][3]);
ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14[(u1Byte)CCK_index][4]);
ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14[(u1Byte)CCK_index][5]);
ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14[(u1Byte)CCK_index][6]);
ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14[(u1Byte)CCK_index][7]);
}
#endif
}
if (is2T)
@ -575,9 +536,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
Y = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][5];
//if (X != 0 && pHalData->CurrentBandType92D == ODM_BAND_ON_2_4G)
if ((X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
{
if ((X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) {
if ((X & 0x00000200) != 0) //consider minus
X = X | 0xFFFFFC00;
ele_A = ((X * ele_D)>>8)&0x000003FF;
@ -587,7 +546,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
Y = Y | 0xFFFFFC00;
ele_C = ((Y * ele_D)>>8)&0x00003FF;
//wirte new elements A, C, D to regC88 and regC9C, element B is always 0
//wtite new elements A, C, D to regC88 and regC9C, element B is always 0
value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
@ -597,9 +556,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
value32 = ((X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
}
else
{
} else {
ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[1]]);
ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);
@ -731,20 +688,8 @@ phy_PathA_IQK_8188E(
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
#if 0
if (!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
else
RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
#endif
return result;
}
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK(
@ -877,15 +822,6 @@ phy_PathA_RxIQK(
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );
#if 0
if (!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
#endif
if (!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
@ -1690,15 +1626,6 @@ else
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
break;
}
#if 0
else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
{
RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
}
#endif
}
for (i = 0 ; i < retryCount ; i++){
@ -1709,14 +1636,10 @@ else
#endif
if (PathAOK == 0x03){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
break;
}
else
{
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
}
}
@ -2504,22 +2427,7 @@ if (*(pDM_Odm->mp_mode) == 1)
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
#if 0//Suggested by Edlu,120413
// IQK on channel 7, should switch back when completed.
//originChannel = pHalData->CurrentChannel;
originChannel = *(pDM_Odm->pChannel);
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK);
#endif
#endif
for (i = 0; i < 8; i++)
{
for (i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
result[2][i] = 0;
@ -2535,11 +2443,7 @@ if (*(pDM_Odm->mp_mode) == 1)
is23simular = FALSE;
is13simular = FALSE;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter)));
// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));
for (i=0; i<3; i++)
{
for (i=0; i<3; i++) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
phy_IQCalibrate_8188E(pAdapter, result, i, is2T);
@ -2682,16 +2586,6 @@ if (*(pDM_Odm->mp_mode) == 1)
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
#if 0 //Suggested by Edlu,120413
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel);
#endif
#endif
}

424
hal/odm.c
View file

@ -717,42 +717,6 @@ odm_HwAntDiv(
IN PDM_ODM_T pDM_Odm
);
#if 0
//#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&defined(HW_ANT_SWITCH))
VOID
odm_HW_AntennaSwitchInit(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_SetRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
odm_StaAntSelect(
IN PDM_ODM_T pDM_Odm,
IN struct stat_info *pstat
);
VOID
odm_HW_IdleAntennaSelect(
IN PDM_ODM_T pDM_Odm
);
u1Byte
ODM_Diversity_AntennaSelect(
IN PDM_ODM_T pDM_Odm,
IN u1Byte *data
);
#endif
//============================================================
//3 Export Interface
//============================================================
@ -1726,12 +1690,6 @@ odm_DIGbyRSSI_LPS(
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
#if 0 //and 2.3.5 coding rule
struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
#endif
u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
u1Byte bFwCurrentInPSMode = FALSE;
u1Byte CurrentIGI=pDM_Odm->RSSI_Min;
@ -1895,16 +1853,6 @@ odm_DIG(
//if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
{
#if 0
if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1))
CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30;
else
CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20;
ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
return;
}
@ -3023,26 +2971,6 @@ odm_RefreshRateAdaptiveMaskMP(
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
{
#if 0 //By YJ,120208
if ( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated)
{
pEntry = pTargetAdapter->MgntInfo.AsocEntry+i;
pEntryRA = &pEntry->RateAdaptive;
if ( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) )
{
ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState));
pAdapter->HalFunc.UpdateHalRAMaskHandler(
pTargetAdapter,
FALSE,
pEntry->AID+1,
pEntry->MacAddr,
pEntry,
pEntryRA->RATRState,
RAMask_Normal);
}
}
#else
pEntry = AsocEntry_EnumStation(pTargetAdapter, i);
if (NULL != pEntry)
{
@ -3064,7 +2992,6 @@ odm_RefreshRateAdaptiveMaskMP(
}
}
}
#endif
}
}
@ -3638,22 +3565,7 @@ odm_DynamicTxPower_92C(
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
else // associated entry pwdb
{
@ -3895,22 +3807,7 @@ odm_DynamicTxPower_92D(
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
else // associated entry pwdb
{
@ -4170,43 +4067,6 @@ FindMinimumRSSI_Dmsp(
IN PADAPTER pAdapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
s32 Rssi_val_min_back_for_mac0;
BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter);
BOOLEAN bRestoreRssi = _FALSE;
PADAPTER BuddyAdapter = pAdapter->BuddyAdapter;
if (pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
if (BuddyAdapter!= NULL)
{
if (pHalData->bSlaveOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n"));
BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM;
}
else
{
if (bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n"));
bRestoreRssi = _TRUE;
Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM;
pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP;
}
}
}
}
if (bRestoreRssi)
{
bRestoreRssi = _FALSE;
pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0;
}
#endif
}
static void
@ -4241,21 +4101,6 @@ IN PADAPTER pAdapter
pdmpriv->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB;
}
#if 0
if ((pdmpriv->UndecoratedSmoothedPWDB != (-1)) &&
(pbuddy_dmpriv->UndecoratedSmoothedPWDB != (-1)))
{
if ((pdmpriv->UndecoratedSmoothedPWDB > pbuddy_dmpriv->UndecoratedSmoothedPWDB) &&
(pbuddy_dmpriv->UndecoratedSmoothedPWDB!=0))
pdmpriv->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB;
}
else
{
if ((pdmpriv->UndecoratedSmoothedPWDB == (-1)) && (pbuddy_dmpriv->UndecoratedSmoothedPWDB!=0))
pdmpriv->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB;
}
#endif
}
#endif
@ -4267,22 +4112,7 @@ IN PADAPTER pAdapter
}
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("AP Client PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM));
}
else//for STA mode
{
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM));
}
#else
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
@ -4292,8 +4122,6 @@ IN PADAPTER pAdapter
#if (RTL8192D_SUPPORT==1)
FindMinimumRSSI_Dmsp(pAdapter);
#endif
//DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__func__,pdmpriv->MinUndecoratedPWDBForDM);
//ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));
}
#endif
@ -4340,12 +4168,6 @@ odm_RSSIMonitorCheckCE(
if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
#if 0
DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__,
psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB);
#endif
if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
#if (RTL8192D_SUPPORT==1)
PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
@ -4446,25 +4268,6 @@ odm_RSSIMonitorCheckCE(
pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
}
#if 0
if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
{
if (pHalData->fw_ractrl == _TRUE)
{
u32 param = (u32)(pdmpriv->UndecoratedSmoothedPWDB<<16);
printk("%s==> rssi(%d)\n",__func__,pdmpriv->UndecoratedSmoothedPWDB);
param |= 0;//macid=0 for sta mode;
rtl8192c_set_rssi_cmd(Adapter, (u8*)&param);
}
else
{
rtw_write8(Adapter, 0x4fe, (u8)pdmpriv->UndecoratedSmoothedPWDB);
//DBG_8192C("0x4fe write %x %d\n", pdmpriv->UndecoratedSmoothedPWDB, pdmpriv->UndecoratedSmoothedPWDB);
}
}
#endif
FindMinimumRSSI(Adapter);
ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE)
@ -6348,109 +6151,6 @@ odm_HwAntDiv(
#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
#if 0
VOID
odm_HwAntDiv(
IN PDM_ODM_T pDM_Odm
)
{
struct rtl8192cd_priv *priv=pDM_Odm->priv;
struct stat_info *pstat, *pstat_min=NULL;
struct list_head *phead, *plist;
int rssi_min= 0xff, i;
u1Byte idleAnt=priv->pshare->rf_ft_var.CurAntenna;
u1Byte nextAnt;
BOOLEAN bRet=FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
if ((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
return;
//if test, return
if (priv->pshare->rf_ft_var.CurAntenna & 0x80)
return;
phead = &priv->asoc_list;
plist = phead->next;
////=========================
//find mimum rssi sta
////=========================
while (plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if ((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) {
int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1];
if ((!pstat_min) || ( rssi < rssi_min) ) {
pstat_min = pstat;
rssi_min = rssi;
}
}
///STA: found out default antenna
bRet=odm_StaDefAntSel(pDM_Odm,
pstat->hwRxAntSel[1],
pstat->hwRxAntSel[0],
pstat->cckPktCount[1],
pstat->cckPktCount[0],
&nextAnt
);
//if default antenna selection: successful
if (bRet){
pstat->CurAntenna = nextAnt;
//update rssi
for (i=0; i<2; i++) {
if (pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0)
pstat->AntRSSI[i] = 0;
}
if (pstat->AntRSSI[idleAnt]==0)
pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1];
// reset variables
pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0;
pstat->cckPktCount[1]= pstat->cckPktCount[0] =0;
}
if (plist == plist->next)
break;
plist = plist->next;
};
////=========================
//Choose RX Idle antenna according to minmum rssi
////=========================
if (pstat_min) {
if (priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna)
odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE);
priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna;
}
#ifdef TX_SHORTCUT
if (!priv->pmib->dot11OperationEntry.disable_txsc) {
plist = phead->next;
while (plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if (pstat->expire_to) {
for (i=0; i<TX_SC_ENTRY_NUM; i++) {
struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
if ((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
if ((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
}
}
if (plist == plist->next)
break;
plist = plist->next;
};
}
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n");
}
#endif
u1Byte
ODM_Diversity_AntennaSelect(
@ -6725,12 +6425,6 @@ odm_EdcaTurboCheckCE(
if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
{
#if 0
//adjust EDCA parameter for BE queue
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
#else
if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
{
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
@ -6739,7 +6433,6 @@ odm_EdcaTurboCheckCE(
{
edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
}
#endif
#ifdef CONFIG_PCI_HCI
if (IS_92C_SERIAL(pHalData->VersionID))
@ -7663,20 +7356,6 @@ odm_IotEngine(
if ((GET_ROOT(priv)->up_time % 2) == 0)
priv->pshare->highTP_found_pstat==NULL;
#if 0
phead = &priv->asoc_list;
plist = phead->next;
while (plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if (ODM_ChooseIotMainSTA(pDM_Odm, pstat)); //find the correct station
break;
if (plist == plist->next) //the last plist
break;
plist = plist->next;
};
#endif
//find highTP STA
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
pstat = pDM_Odm->pODM_StaInfo[i];
@ -7871,25 +7550,6 @@ odm_IotEngine(
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
#if 0
if (priv->pshare->txop_enlarge != 2)
{
#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
#else
if (pstat->is_intel_sta)
#endif
priv->pshare->txop_enlarge = 0xe;
#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
priv->pshare->txop_enlarge = 0xd;
#endif
else
priv->pshare->txop_enlarge = 2;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
}
else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
@ -8580,43 +8240,8 @@ odm_PSD_Monitor(
for (i = 0; i < 80; i++)
PSD_report[i] = 0;
}
#if 0 //for test only
DbgPrint("cosa odm_PSD_Monitor call()\n");
DbgPrint("cosa pHalData->RSSI_BT = %d\n", pHalData->RSSI_BT);
DbgPrint("cosa pHalData->bUserAssignLevel = %d\n", pHalData->bUserAssignLevel);
#if 0
psd_cnt++;
if (psd_cnt < ReScan)
PlatformSetTimer( Adapter, &pHalData->PSDTimer, Interval); //ms
else
psd_cnt = 0;
return;
#endif
#endif
//1 Backup Current Settings
CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
/*
if (pDM_Odm->SupportICType==ODM_RTL8192D)
{
//2 Record Current synthesizer parameters based on current channel
if ((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))
{
SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord);
SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord);
SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord);
SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord);
SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord);
}
else // DualMAC_DualPHY 2G
{
SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord);
SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord);
SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord);
SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord);
SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord);
}
}
*/
//RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
@ -8628,15 +8253,12 @@ odm_PSD_Monitor(
ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
//1 Turn off CCK
//PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
//1 Turn off TX
//Pause TX Queue
//PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);
ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);
//Force RX to stop TX immediately
//PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
//1 Turn off RX
@ -8649,16 +8271,11 @@ odm_PSD_Monitor(
//Turn off CCA
//PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
//BB Reset
//BBReset = PlatformEFIORead1Byte(Adapter, 0x02);
BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
//PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));
//PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);
ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));
ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);
@ -10509,17 +10126,6 @@ ODM_PathDiversityBeforeLink92C(
pDM_PDTable->OFDMTXPath = 0x0;
pDM_PDTable->CCKTXPath = 0x0;
}
#if 0
pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
RT_TRACE(COMP_SWAS, DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
#endif
// Go back to scan function again.
RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
@ -11687,12 +11293,6 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
u8 sign;
u8 resp_txagc=0;
#if 0
/* As DIG is disabled, DTC is also disable */
if (!(pDM_Odm->SupportAbility & ODM_XXXXXX))
return;
#endif
if (DTC_BASE < pDM_Odm->RSSI_Min) {
/* need to decade the CTS TX power */
sign = 1;
@ -11703,24 +11303,7 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
else
dtc_steps++;
}
}
#if 0
else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min)
{
/* needs to increase the CTS TX power */
sign = 0;
dtc_steps = 1;
for (i=0;i<ARRAY_SIZE(dtc_table_up);i++)
{
if ((dtc_table_up[i] <= pDM_Odm->RSSI_Min) || (dtc_steps>=10))
break;
else
dtc_steps++;
}
}
#endif
else
{
} else {
sign = 0;
dtc_steps = 0;
}
@ -11735,4 +11318,3 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
}
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */

79
hal/odm_HWConfig.c
View file

@ -84,35 +84,35 @@ odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
{
RetSig = 100;
}
else if (CurrSig>=42 && CurrSig <= 53 )
else if (CurrSig>=42 && CurrSig <= 53)
{
RetSig = 95;
}
else if (CurrSig>=36 && CurrSig <= 41 )
else if (CurrSig>=36 && CurrSig <= 41)
{
RetSig = 74 + ((CurrSig - 36) *20)/6;
}
else if (CurrSig>=33 && CurrSig <= 35 )
else if (CurrSig>=33 && CurrSig <= 35)
{
RetSig = 65 + ((CurrSig - 33) *8)/2;
}
else if (CurrSig>=18 && CurrSig <= 32 )
else if (CurrSig>=18 && CurrSig <= 32)
{
RetSig = 62 + ((CurrSig - 18) *2)/15;
}
else if (CurrSig>=15 && CurrSig <= 17 )
else if (CurrSig>=15 && CurrSig <= 17)
{
RetSig = 33 + ((CurrSig - 15) *28)/2;
}
else if (CurrSig>=10 && CurrSig <= 14 )
else if (CurrSig>=10 && CurrSig <= 14)
{
RetSig = 39;
}
else if (CurrSig>=8 && CurrSig <= 9 )
else if (CurrSig>=8 && CurrSig <= 9)
{
RetSig = 33;
}
else if (CurrSig <= 8 )
else if (CurrSig <= 8)
{
RetSig = 19;
}
@ -237,7 +237,7 @@ odm_SignalScaleMapping_92CSeries(
#endif
#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE))
if ((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) )
if ((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO))
{
if (CurrSig >= 51 && CurrSig <= 100)
{
@ -349,7 +349,7 @@ static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
static u1Byte
odm_EVMdbToPercentage(
IN s1Byte Value
)
)
{
//
// -33dB~0dB to 0%~99%
@ -397,7 +397,7 @@ odm_RxPhyStatus92CSeries_Parsing(
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M))?TRUE :FALSE;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
@ -481,7 +481,7 @@ odm_RxPhyStatus92CSeries_Parsing(
{
if (!cck_highpwr)
{
report =( cck_agc_rpt & 0xc0 )>>6;
report =(cck_agc_rpt & 0xc0)>>6;
switch (report)
{
// 03312009 modified by cosa
@ -654,7 +654,7 @@ odm_RxPhyStatus92CSeries_Parsing(
//
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110;
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1)& 0x7f) -110;
//RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n", PWDB_ALL));
PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
@ -685,7 +685,7 @@ odm_RxPhyStatus92CSeries_Parsing(
// Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
// fill most significant bit to "zero" when doing shifting operation which may change a negative
// value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm
EVM = odm_EVMdbToPercentage((pPhyStaRpt->stream_rxevm[i])); //dbm
//RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",
//GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM));
@ -772,15 +772,15 @@ odm_Process_RSSIForDM(
}
pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID];
if (!IS_STA_VALID(pEntry) ){
if (!IS_STA_VALID(pEntry)){
return;
}
if ((!pPktinfo->bPacketMatchBSSID) )
if ((!pPktinfo->bPacketMatchBSSID))
{
return;
}
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M))?TRUE :FALSE;
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))
@ -884,14 +884,14 @@ odm_Process_RSSIForDM(
if (pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM)
{
UndecoratedSmoothedOFDM =
( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(RSSI_Ave)) /(Rx_Smooth_Factor);
UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1;
}
else
{
UndecoratedSmoothedOFDM =
( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(RSSI_Ave)) /(Rx_Smooth_Factor);
}
}
@ -913,14 +913,14 @@ odm_Process_RSSIForDM(
if (pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK)
{
UndecoratedSmoothedCCK =
( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor);
UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1;
}
else
{
UndecoratedSmoothedCCK =
( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor);
}
}
@ -983,29 +983,11 @@ ODM_PhyStatusQuery_92CSeries(
pPhyStatus,
pPktinfo);
if ( pDM_Odm->RSSI_test == TRUE)
{
if (pDM_Odm->RSSI_test == TRUE) {
// Select the packets to do RSSI checking for antenna switching.
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon )
{
/*
#if 0//(DM_ODM_SUPPORT_TYPE == ODM_MP)
dm_SWAW_RSSI_Check(
Adapter,
(tmppAdapter!=NULL)?(tmppAdapter==Adapter):TRUE,
bPacketMatchBSSID,
pEntry,
pRfd);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
// Select the packets to do RSSI checking for antenna switching.
//odm_SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll);
#endif
*/
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo);
}
}
else
{
} else {
odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo);
}
@ -1036,16 +1018,7 @@ ODM_PhyStatusQuery(
IN PODM_PACKET_INFO_T pPktinfo
)
{
#if 0 // How to jaguar jugar series??
if (pDM_Odm->SupportICType >= ODM_RTL8195 )
{
ODM_PhyStatusQuery_JaguarSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
else
#endif
{
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
// For future use.
@ -1070,7 +1043,7 @@ ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
)
)
{
//RT_STATUS rtStatus = RT_STATUS_SUCCESS;

61
hal/odm_RTL8188E.c
View file

@ -531,46 +531,6 @@ odm_SetNextMACAddrTarget(
}
#if 0
//
//2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn
//
#if ( DM_ODM_SUPPORT_TYPE & ODM_MP)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
for (i=0; i<6; i++)
{
Bssid[i] = pMgntInfo->Bssid[i];
//DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);
}
}
#endif
//odm_SetNextMACAddrTarget(pDM_Odm);
//1 Select MAC Address Filter
for (i=0; i<6; i++)
{
if (Bssid[i] != pDM_FatTable->Bssid[i])
{
bMatchBSSID = FALSE;
break;
}
}
if (bMatchBSSID == FALSE)
{
//Match MAC ADDR
value32 = (Bssid[5]<<8)|Bssid[4];
ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];
ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
}
return bMatchBSSID;
#endif
}
VOID
@ -629,20 +589,9 @@ odm_FastAntTraining(
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
#if 0
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if (IS_STA_VALID(pEntry))
{
pEntry->antsel_a = TargetAnt&BIT0;
pEntry->antsel_b = (TargetAnt&BIT1)>>1;
pEntry->antsel_c = (TargetAnt&BIT2)>>2;
}
#else
pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;
pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;
pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;
#endif
if (TargetAnt == 0)
@ -668,16 +617,6 @@ odm_FastAntTraining(
odm_SetNextMACAddrTarget(pDM_Odm);
#if 0
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if (IS_STA_VALID(pEntry))
{
pEntry->antsel_a = TargetAnt&BIT0;
pEntry->antsel_b = (TargetAnt&BIT1)>>1;
pEntry->antsel_c = (TargetAnt&BIT2)>>2;
}
#endif
//2 Prepare Training
pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training

6
hal/rtl8188e_cmd.c
View file

@ -218,11 +218,7 @@ u8 rtl8188e_set_rssi_cmd(_adapter*padapter, u8 *param)
_func_enter_;
if (pHalData->fw_ractrl == _TRUE){
#if 0
*((u32*) param ) = cpu_to_le32( *((u32*) param ) );
FillH2CCmd_88E(padapter, RSSI_SETTING_EID, 3, param);
#endif
;
}else{
DBG_8192C("==>%s fw dont support RA\n",__func__);
res=_FAIL;

44
hal/rtl8188e_dm.c
View file

@ -45,26 +45,6 @@ dm_CheckProtection(
IN PADAPTER Adapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte CurRate, RateThreshold;
if (pMgntInfo->pHTInfo->bCurBW40MHz)
RateThreshold = MGN_MCS1;
else
RateThreshold = MGN_MCS3;
if (Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
{
pMgntInfo->bDmDisableProtect = TRUE;
DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
else
{
pMgntInfo->bDmDisableProtect = FALSE;
DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
#endif
}
static VOID
@ -72,20 +52,6 @@ dm_CheckStatistics(
IN PADAPTER Adapter
)
{
#if 0
if (!Adapter->MgntInfo.bMediaConnect)
return;
//2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.
rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );
// Calculate current Tx Rate(Successful transmited!!)
// Calculate current Rx Rate(Successful received!!)
//for tx tx retry count
rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );
#endif
}
static void dm_CheckPbcGPIO(_adapter *padapter)
@ -303,17 +269,7 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
#if 0
//#ifdef CONFIG_USB_HCI
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType);
if (pHalData->BoardType == BOARD_USB_High_PA){
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE);
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE);
}
#endif
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);
// ODM_CMNINFO_BINHCT_TEST only for MP Team
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);

73
hal/rtl8188e_hal_init.c
View file

@ -332,24 +332,7 @@ void efuse_read_phymap_from_txpktbuf(
lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
#if 0
DBG_871X("%s lo32:0x%08x, %02x %02x %02x %02x\n", __func__, lo32
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+2)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+3)
);
DBG_871X("%s hi32:0x%08x, %02x %02x %02x %02x\n", __func__, hi32
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+1)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+2)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+3)
);
#endif
if (i==0)
{
#if 1 //for debug
if (i==0) {
u8 lenc[2];
u16 lenbak, aaabak;
u16 aaa;
@ -359,7 +342,6 @@ void efuse_read_phymap_from_txpktbuf(
aaabak = le16_to_cpup((u16*)lenc);
lenbak = le16_to_cpu(*((u16*)lenc));
aaa = le16_to_cpup((u16*)&lo32);
#endif
len = le16_to_cpu(*((u16*)&lo32));
limit = (len-2<limit)?len-2:limit;
@ -370,9 +352,7 @@ void efuse_read_phymap_from_txpktbuf(
count+= (limit>=count+2)?2:limit-count;
pos=content+count;
}
else
{
} else {
_rtw_memcpy(pos, ((u8*)&lo32), (limit>=count+4)?4:limit-count);
count+=(limit>=count+4)?4:limit-count;
pos=content+count;
@ -428,17 +408,6 @@ static s32 iol_read_efuse(
if (status == _SUCCESS)
efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
#if 0
DBG_871X("%s physical map\n", __func__);
for (i=0;i<size;i++)
{
DBG_871X("%02x ", physical_map[i]);
if (i%16==15)
DBG_871X("\n");
}
DBG_871X("\n");
#endif
efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
return status;
@ -3669,38 +3638,6 @@ Hal_InitChannelPlan(
IN PADAPTER padapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(padapter->MgntInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if ((pMgntInfo->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
{
pMgntInfo->ChannelPlan = hal_MapChannelPlan8192C(padapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
}
else
{
pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
}
switch (pMgntInfo->ChannelPlan)
{
case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
pDot11dInfo->bEnabled = TRUE;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
break;
default: //for MacOSX compiler warning.
break;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
#endif
}
BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter)
@ -3776,12 +3713,6 @@ void SetBcnCtrlReg(
pHalData->RegBcnCtrlVal |= SetBits;
pHalData->RegBcnCtrlVal &= ~ClearBits;
#if 0
//#ifdef CONFIG_SDIO_HCI
if (pHalData->sdio_himr & (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK))
pHalData->RegBcnCtrlVal |= EN_TXBCN_RPT;
#endif
rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
}

78
hal/rtl8188e_mp.c
View file

@ -225,19 +225,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
if (!IS_92C_SERIAL(pHalData->VersionID))
return;
#if 0
while (PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)
{
PlatformSleepUs(100);
TimeOut--;
if (TimeOut <= 0)
{
RTPRINT(FINIT, INIT_TxPower,
("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));
break;
}
}
#endif
if (beven && !pMptCtx->bMptIndexEven) //odd->even
{
Action = 2;
@ -306,12 +293,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
}
}
#if 0
RTPRINT(FINIT, INIT_TxPower,
("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));
PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);
#endif
}
/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
@ -323,12 +304,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
*/
void Hal_SetChannel(PADAPTER pAdapter)
{
#if 0
struct mp_priv *pmp = &pAdapter->mppriv;
// SelectChannel(pAdapter, pmp->channel);
set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);
#else
u8 eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@ -361,8 +336,6 @@ void Hal_SetChannel(PADAPTER pAdapter)
pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _FALSE;
Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
}
#endif
}
/*
@ -635,19 +608,11 @@ void Hal_SetAntenna(PADAPTER pAdapter)
// Disable Power save
//cosa r_ant_select_ofdm_val = 0x3321333;
#if 0
// 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.
if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.
{
mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);
}
#endif
// 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
if (pHalData->rf_type == RF_2T2R)
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
@ -762,17 +727,9 @@ u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)
{
#if 0
fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
rtw_msleep_os(1000);
fw_cmd_data(pAdapter, value, 1);
*value &= 0xFF;
#else
Hal_TriggerRFThermalMeter(pAdapter);
rtw_msleep_os(1000);
*value = Hal_ReadRFThermalMeter(pAdapter);
#endif
}
void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
@ -1002,28 +959,7 @@ void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
//Set CCK Tx Test Rate
#if 0
switch (pAdapter->mppriv.rateidx)
{
case 2:
cckrate = 0;
break;
case 4:
cckrate = 1;
break;
case 11:
cckrate = 2;
break;
case 22:
cckrate = 3;
break;
default:
cckrate = 0;
break;
}
#else
cckrate = pAdapter->mppriv.rateidx;
#endif
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
@ -1108,13 +1044,6 @@ void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
{
#if 0
// ADC turn off [bit24-21] adc port0 ~ port1
if (bStart) {
write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);
rtw_usleep_os(100);
}
#endif
RT_TRACE(_module_mp_, _drv_info_,
("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
@ -1128,13 +1057,6 @@ void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
{
Hal_SetOFDMContinuousTx(pAdapter, bStart);
}
#if 0
// ADC turn on [bit24-21] adc port0 ~ port1
if (!bStart) {
write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);
}
#endif
}
#endif // CONFIG_MP_INCLUDE

570
hal/rtl8188e_phycfg.c
View file

@ -494,12 +494,6 @@ phy_RFSerialRead(
u32 NewOffset;
u32 tmplong,tmplong2;
u8 RfPiEnable=0;
#if 0
if (pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return retValue;
if (pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return retValue;
#endif
//
// Make sure RF register offset is correct
//
@ -616,13 +610,6 @@ phy_RFSerialWrite(
BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
u32 NewOffset;
#if 0
//<Roger_TODO> We should check valid regs for RF_6052 case.
if (pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return;
if (pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return;
#endif
// 2009/06/17 MH We can not execute IO for power save or other accident mode.
//if (RT_CANNOT_IO(Adapter))
@ -1098,22 +1085,10 @@ phy_ConfigBBExternalPA(
u32 temp=0;
if (!pHalData->ExternalPA)
{
return;
}
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in PHY_REG_1T_HP.txt.
#if 0
PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
temp |= (BIT26|BIT21|BIT10|BIT5);
PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
#endif
#endif
}
@ -1442,39 +1417,11 @@ phy_ConfigBBWithPgHeaderFile(
{
for (i=0;i<PHY_REGArrayPGLen;i=i+3)
{
#if 0 //without IO, no delay is neeeded...
if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
}
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
rtw_mdelay_os(5);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
rtw_mdelay_os(1);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
rtw_udelay_os(50);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
rtw_udelay_os(5);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
rtw_udelay_os(1);
//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
#endif
storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
Rtl819XPHY_REGArray_Table_PG[i+1],
Rtl819XPHY_REGArray_Table_PG[i+2]);
//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
//RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx\n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
}
}
else
{
//RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != CONFIG_BB_PHY_REG\n"));
}
return _SUCCESS;
@ -1488,16 +1435,6 @@ phy_BB8192C_Config_1T(
IN PADAPTER Adapter
)
{
#if 0
//for path - A
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
#endif
//for path - B
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
@ -1664,16 +1601,6 @@ PHY_BBConfig8188E(
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
#endif
#if 0
#ifdef CONFIG_USB_HCI
//To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
rtw_write8(Adapter, 0x15, 0xe9);
#endif
rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
#endif
#ifdef CONFIG_USB_HCI
//rtw_write8(Adapter, 0x15, 0xe9);
#endif
@ -1715,27 +1642,6 @@ PHY_RFConfig8188E(
// RF config
//
rtStatus = PHY_RF6052_Config8188E(Adapter);
#if 0
switch (pHalData->rf_chip)
{
case RF_6052:
rtStatus = PHY_RF6052_Config(Adapter);
break;
case RF_8225:
rtStatus = PHY_RF8225_Config(Adapter);
break;
case RF_8256:
rtStatus = PHY_RF8256_Config(Adapter);
break;
case RF_8258:
break;
case RF_PSEUDO_11N:
rtStatus = PHY_RF8225_Config(Adapter);
break;
default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
break;
}
#endif
return rtStatus;
}
@ -1802,21 +1708,10 @@ PHY_ConfigRFExternalPA(
u16 i=0;
if (!pHalData->ExternalPA)
{
return rtStatus;
}
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in radio_a_1T_HP.txt.
#if 0
//add for SU High Power PA
for (i = 0;i<HighPowerRadioAArrayLen; i=i+2)
{
RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
}
#endif
#endif
return rtStatus;
}
@ -1968,20 +1863,12 @@ rtl8188e_PHY_ConfigRFWithHeaderFile(
for (i = 0;i<RadioB_ArrayLen; i=i+2)
{
if (Rtl819XRadioB_Array_Table[i] == 0xfe)
{ // Deay specific ms. Only RF configuration require delay.
#if 0//#ifdef CONFIG_USB_HCI
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(1000);
#else
rtw_mdelay_os(1000);
#endif
#else
{ // Delay specific ms. Only RF configuration require delay.
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
#endif
}
else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
rtw_mdelay_os(5);
@ -2278,37 +2165,6 @@ PHY_GetTxPowerLevel8188E(
*powerlevel = TxPwrDbm;
}
#if 0
static void getTxPowerIndex(
IN PADAPTER Adapter,
IN u8 channel,
IN OUT u8* cckPowerLevel,
IN OUT u8* ofdmPowerLevel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 index = (channel -1);
// 1. CCK
cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
// 2. OFDM for 1S or 2S
if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
{
// Read HT 40 OFDM TX power
ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
}
else if (GET_RF_TYPE(Adapter) == RF_2T2R)
{
// Read HT 40 OFDM TX power
ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
}
//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
}
#endif
void getTxPowerIndex88E(
IN PADAPTER Adapter,
IN u8 channel,
@ -2343,13 +2199,7 @@ void getTxPowerIndex88E(
pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];
//2. BW40
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
//RTPRINT(FPHY, PHY_TXPWR, ("getTxPowerIndex88E(): 40MBase=0x%x 20Mdiff=%d 20MBase=0x%x!!\n",
// pHalData->Index24G_BW40_Base[RF_PATH_A][index],
// pHalData->BW20_24G_Diff[TxCount][RF_PATH_A],
// BW20PowerLevel[TxCount]));
}
else if (TxCount==RF_PATH_B)
{
} else if (TxCount==RF_PATH_B) {
// 1. CCK
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
//2. OFDM
@ -2405,41 +2255,6 @@ void getTxPowerIndex88E(
{
}
}
#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
switch (pMgntInfo->IntelProximityModeInfo.PowerOutput){
case 1: // 100%
break;
case 2: // 70%
cckPowerLevel[0] -= 3;
cckPowerLevel[1] -= 3;
ofdmPowerLevel[0] -=3;
ofdmPowerLevel[1] -= 3;
break;
case 3: // 50%
cckPowerLevel[0] -= 6;
cckPowerLevel[1] -= 6;
ofdmPowerLevel[0] -=6;
ofdmPowerLevel[1] -= 6;
break;
case 4: // 35%
cckPowerLevel[0] -= 9;
cckPowerLevel[1] -= 9;
ofdmPowerLevel[0] -=9;
ofdmPowerLevel[1] -= 9;
break;
case 5: // 15%
cckPowerLevel[0] -= 17;
cckPowerLevel[1] -= 17;
ofdmPowerLevel[0] -=17;
ofdmPowerLevel[1] -= 17;
break;
default:
break;
}
#endif
//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
}
void phy_PowerIndexCheck88E(
@ -2453,70 +2268,13 @@ void phy_PowerIndexCheck88E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if 0 // (CCX_SUPPORT == 1)
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
//
// CCX 2 S31, AP control of client transmit power:
// 1. We shall not exceed Cell Power Limit as possible as we can.
// 2. Tolerance is +/- 5dB.
// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
//
// TODO:
// 1. 802.11h power contraint
//
// 071011, by rcnjko.
//
if ( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
pMgntInfo->mAssoc &&
pCcxInfo->bUpdateCcxPwr &&
pCcxInfo->bWithCcxCellPwr &&
channel == pMgntInfo->dot11CurrentChannelNumber)
{
u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
// CCK
if (cckPowerLevel[0] > CckCellPwrIdx)
cckPowerLevel[0] = CckCellPwrIdx;
// Legacy OFDM, HT OFDM
if (ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
{
if ((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
{
ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
}
else
{
ofdmPowerLevel[0] = 0;
}
}
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
}
#else
// Add or not ???
#endif
pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
//DBG_871X("PHY_SetTxPowerLevel8188E(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x, CurrentBW2024GTxPwrIdx: 0x%dx, CurrentBW4024GTxPwrIdx: 0x%x\n",
// pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx, pHalData->CurrentBW2024GTxPwrIdx, pHalData->CurrentBW4024GTxPwrIdx);
}
/*-----------------------------------------------------------------------------
* Function: SetTxPowerLevel8190()
*
@ -2565,30 +2323,6 @@ PHY_SetTxPowerLevel8188E(
rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel);
#if 0
switch (pHalData->rf_chip)
{
case RF_8225:
PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
break;
case RF_8256:
PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
break;
case RF_6052:
PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
break;
case RF_8258:
break;
}
#endif
}
@ -2662,30 +2396,6 @@ PHY_ScanOperationBackup8188E(
IN u8 Operation
)
{
#if 0
IO_TYPE IoType;
if (!Adapter->bDriverStopped)
{
switch (Operation)
{
case SCAN_OPT_BACKUP:
IoType = IO_CMD_PAUSE_DM_BY_SCAN;
rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
break;
case SCAN_OPT_RESTORE:
IoType = IO_CMD_RESUME_DM_BY_SCAN;
rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
break;
default:
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation.\n"));
break;
}
}
#endif
}
/*-----------------------------------------------------------------------------
@ -2708,25 +2418,12 @@ _PHY_SetBWMode92C(
IN PADAPTER Adapter
)
{
// PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 regBwOpMode;
u8 regRRSR_RSC;
//return;
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//u4Byte NowL, NowH;
//u8Byte BeginTime, EndTime;
/*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \
pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
if (pHalData->rf_chip == RF_PSEUDO_11N)
{
//pHalData->SetBWModeInProgress= _FALSE;
return;
}
// There is no 40MHz mode in RF_8225.
if (pHalData->rf_chip==RF_8225)
@ -2735,19 +2432,12 @@ _PHY_SetBWMode92C(
if (Adapter->bDriverStopped)
return;
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//NowL = PlatformEFIORead4Byte(Adapter, TSFR);
//NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
//BeginTime = ((u8Byte)NowH << 32) + NowL;
//3//
//3//<1>Set MAC register
//3//
//Adapter->HalFunc.SetBWModeHandler();
//3
//3<1>Set MAC register
//3
regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
//regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);
switch (pHalData->CurrentChannelBW)
{
@ -2904,32 +2594,12 @@ PHY_SetBWMode8188E(
pHalData->CurrentChannelBW = Bandwidth;
#if 0
if (Offset==HT_EXTCHNL_OFFSET_LOWER)
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
else if (Offset==HT_EXTCHNL_OFFSET_UPPER)
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
else
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
#else
pHalData->nCur40MhzPrimeSC = Offset;
#endif
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
#if 0
//PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
#else
_PHY_SetBWMode92C(Adapter);
#endif
}
else
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
//pHalData->SetBWModeInProgress= FALSE;
pHalData->CurrentChannelBW = tmpBW;
}
}
@ -3013,29 +2683,13 @@ PHY_SwChnl8188E( // Call after initialization
pHalData->CurrentChannel=channel;
//pHalData->SwChnlStage=0;
//pHalData->SwChnlStep=0;
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
#if 0
//PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
#else
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
_PHY_SwChnl8192C(Adapter, channel);
#endif
if (bResult)
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
}
else
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
//if (IS_HARDWARE_TYPE_8192SU(Adapter))
//{
// pHalData->SwChnlInProgress = FALSE;
pHalData->CurrentChannel = tmpchannel;
//}
if (bResult) {
;
} else {
pHalData->CurrentChannel = tmpchannel;
}
}
@ -3060,154 +2714,6 @@ phy_SwChnlStepByStep(
OUT u32 *delay
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
u4Byte PreCommonCmdCnt;
SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
u4Byte PostCommonCmdCnt;
SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
u4Byte RfDependCmdCnt;
SwChnlCmd *CurrentCmd;
u1Byte eRFPath;
u4Byte RfTXPowerCtrl;
BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
#if (MP_DRIVER != 1)
RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
#endif
RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
//for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//{
// <1> Fill up pre common command.
PreCommonCmdCnt = 0;
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
CmdID_SetTxPowerLevel, 0, 0, 0);
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
CmdID_End, 0, 0, 0);
// <2> Fill up post common command.
PostCommonCmdCnt = 0;
phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
CmdID_End, 0, 0, 0);
// <3> Fill up RF dependent command.
RfDependCmdCnt = 0;
switch ( pHalData->RFChipID )
{
case RF_8225:
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
// 2008/09/04 MH Change channel.
if (channel==14) channel++;
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8256:
// TEST!! This is not the table for 8256!!
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, rRfChannel, channel, 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_6052:
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8258:
break;
// For FPGA two MAC verification
case RF_PSEUDO_11N:
return TRUE;
default:
RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
return FALSE;
break;
}
do{
switch (*stage)
{
case 0:
CurrentCmd=&PreCommonCmd[*step];
break;
case 1:
CurrentCmd=&RfDependCmd[*step];
break;
case 2:
CurrentCmd=&PostCommonCmd[*step];
break;
}
if (CurrentCmd->CmdID==CmdID_End)
{
if ((*stage)==2)
{
return TRUE;
}
else
{
(*stage)++;
(*step)=0;
continue;
}
}
switch (CurrentCmd->CmdID)
{
case CmdID_SetTxPowerLevel:
PHY_SetTxPowerLevel8192C(Adapter,channel);
break;
case CmdID_WritePortUlong:
PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
break;
case CmdID_WritePortUshort:
PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
break;
case CmdID_WritePortUchar:
PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
break;
case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
#if 1
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
#else
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
#endif
}
break;
}
break;
}while (TRUE);
//cosa }/*for (Number of RF paths)*/
(*delay)=CurrentCmd->msDelay;
(*step)++;
return FALSE;
#endif
return _TRUE;
}
@ -3226,17 +2732,9 @@ phy_SetSwChnlCmdArray(
SwChnlCmd* pCmd;
if (CmdTable == NULL)
{
//RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
return _FALSE;
}
if (CmdTableIdx >= CmdTableSz)
{
//RT_ASSERT(FALSE,
// ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",
// CmdTableIdx, CmdTableSz));
return _FALSE;
}
pCmd = CmdTable + CmdTableIdx;
pCmd->CmdID = CmdID;
@ -3254,20 +2752,8 @@ phy_FinishSwChnlNow( // We should not call this function directly
IN u8 channel
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u32 delay;
while (!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
{
if (delay>0)
rtw_mdelay_os(delay);
}
#endif
}
//
// Description:
// Switch channel synchronously. Called by SwChnlByDelayHandler.
@ -3329,30 +2815,6 @@ PHY_SetMonitorMode8192C(
IN BOOLEAN bEnableMonitorMode
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
//2 Note: we may need to stop antenna diversity.
if (bEnableMonitorMode)
{
bFilterOutNonAssociatedBSSID = FALSE;
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
pHalData->bInMonitorMode = TRUE;
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
}
else
{
bFilterOutNonAssociatedBSSID = TRUE;
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
pHalData->bInMonitorMode = FALSE;
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
}
#endif
}
@ -3382,16 +2844,6 @@ PHY_CheckIsLegalRfPath8192C(
BOOLEAN rtValue = _TRUE;
// NOt check RF Path now.!
#if 0
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
{
rtValue = FALSE;
}
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
{
}
#endif
return rtValue;
} /* PHY_CheckIsLegalRfPath8192C */

250
hal/rtl8188e_rf6052.c
View file

@ -96,50 +96,6 @@ void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
#if 0//(RTL92SE_FPGA_VERIFY == 0)
static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
// Set PA to high value
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
// Set PA low gain
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
}
#endif
} /* RF_ChangeTxPath */
@ -322,50 +278,6 @@ rtl8188e_PHY_RF6052SetCckTxPower(
} /* PHY_RF6052SetCckTxPower */
#if 0
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
//
static void getPowerBase(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel,
IN OUT u32* OfdmBase,
IN OUT u32* MCSBase
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff=0, HT20_pwrdiff=0;
u8 i, powerlevel[2];
for (i=0; i<2; i++)
{
powerlevel[i] = pPowerLevel[i];
Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
powerBase0 = powerlevel[i] + Legacy_pwrdiff;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
*(OfdmBase+i) = powerBase0;
//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
}
for (i=0; i<2; i++)
{
//Check HT20 to HT40 diff
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
powerlevel[i] += HT20_pwrdiff;
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
*(MCSBase+i) = powerBase1;
//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
}
}
#endif
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
@ -412,139 +324,7 @@ void getPowerBase88E(
//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
}
}
#if 0
static void getTxPowerWriteValByRegulatory(
IN PADAPTER Adapter,
IN u8 Channel,
IN u8 index,
IN u32* powerBase0,
IN u32* powerBase1,
OUT u32* pOutWriteVal
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 i, chnlGroup, pwr_diff_limit[4];
u32 writeVal, customer_limit, rf;
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
for (rf=0; rf<2; rf++)
{
switch (pHalData->EEPROMRegulatory)
{
case 0: // Realtek better performance
// increase power diff defined by Realtek for large power
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 1: // Realtek regulatory
// increase power diff defined by Realtek for regulatory
{
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= 3)
{
if (Channel <= 3)
chnlGroup = 0;
else if (Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if (Channel > 9)
chnlGroup = 2;
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=4;
}
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
}
break;
case 2: // Better regulatory
// don't increase any power diff
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 3: // Customer defined power diff.
// increase power diff defined by customer.
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
{
//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
// ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
}
else
{
//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
// ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
}
for (i=0; i<4; i++)
{
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
{
if (pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
}
else
{
if (pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
}
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
}
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
// 20100628 Joseph: High power mode for BT-Coexist mechanism.
// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
writeVal = writeVal - 0x06060606;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
writeVal = writeVal;
}
*(pOutWriteVal+rf) = writeVal;
}
}
#endif
void getTxPowerWriteValByRegulatory88E(
IN PADAPTER Adapter,
IN u8 Channel,
@ -565,13 +345,8 @@ void getTxPowerWriteValByRegulatory88E(
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
if (pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
Regulatory = 2;
#endif
for (rf=0; rf<2; rf++)
{
for (rf=0; rf<2; rf++) {
switch (Regulatory)
{
case 0: // Realtek better performance
@ -1001,30 +776,7 @@ PHY_RF6052_Config8188E(
// Config BB and RF
//
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
#if 0
switch ( Adapter->MgntInfo.bRegHwParaFile )
{
case 0:
phy_RF6052_Config_HardCode(Adapter);
break;
case 1:
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
break;
case 2:
// Partial Modify.
phy_RF6052_Config_HardCode(Adapter);
phy_RF6052_Config_ParaFile(Adapter);
break;
default:
phy_RF6052_Config_HardCode(Adapter);
break;
}
#endif
return rtStatus;
}

6
hal/rtl8188e_rxdesc.c
View file

@ -295,12 +295,6 @@ void update_recvframe_phyinfo_88e(
if (pkt_info.bPacketBeacon){
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
sa = padapter->mlmepriv.cur_network.network.MacAddress;
#if 0
{
DBG_8192C("==> rx beacon from AP[%02x:%02x:%02x:%02x:%02x:%02x]\n",
sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]);
}
#endif
}
//to do Ad-hoc
}

16
hal/rtl8188e_sreset.c
View file

@ -236,22 +236,6 @@ void rtl8188e_sreset_linked_status_check(_adapter *padapter)
else if (fw_status == 2)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__func__,fw_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if ( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __func__,
regc50, regc58, reg824, reg800);
rtl8188e_silentreset_for_specific_platform(padapter);
}
#endif
}
#endif

7
hal/rtl8188eu_xmit.c
View file

@ -394,13 +394,6 @@ if (padapter->registrypriv.mp_mode == 0)
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
//for debug
#if 0
if (padapter->fix_rate!= 0xFF){
ptxdesc->datarate = padapter->fix_rate;
}
#endif
#if (POWER_TRAINING_ACTIVE==1)
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT);

833
hal/usb_halinit.c
View file

@ -454,19 +454,6 @@ _InitPageBoundary(
//
u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
#if 0
// RX Page Boundary
//srand(static_cast<unsigned int>(time(NULL)) );
if (bSupportRemoteWakeUp)
{
Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE;
Offset = Offset / 128; // RX page size = 128 byte
rxff_bndy= (Offset*128) -1;
}
else
#endif
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
}
@ -1010,36 +997,6 @@ HalRxAggr8188EUsb(
IN BOOLEAN Value
)
{
#if 0//USB_RX_AGGREGATION_92C
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
u1Byte valueDMATimeout;
u1Byte valueDMAPageCount;
u1Byte valueUSBTimeout;
u1Byte valueUSBBlockCount;
// selection to prevent bad TP.
if ( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg)
{
// 2010.04.27 hpfan
// Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
// Timeout value is calculated by 34 / (2^n)
valueDMATimeout = 0x0f;
valueDMAPageCount = 0x01;
valueUSBTimeout = 0x0f;
valueUSBBlockCount = 0x01;
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
}
else
{
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
}
#endif
}
/*-----------------------------------------------------------------------------
@ -1066,88 +1023,6 @@ USB_AggModeSwitch(
IN PADAPTER Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
//pHalData->UsbRxHighSpeedMode = FALSE;
// How to measure the RX speed? We assume that when traffic is more than
if (pMgntInfo->bRegAggDMEnable == FALSE)
{
return; // Inf not support.
}
if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE &&
pHalData->UsbRxHighSpeedMode == FALSE)
{
pHalData->UsbRxHighSpeedMode = TRUE;
RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to HIGH\n"));
}
else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE &&
pHalData->UsbRxHighSpeedMode == TRUE)
{
pHalData->UsbRxHighSpeedMode = FALSE;
RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to LOW\n"));
}
else
{
return;
}
#if USB_RX_AGGREGATION_92C
if (pHalData->UsbRxHighSpeedMode == TRUE)
{
// 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
// USB mode
#if (RT_PLATFORM == PLATFORM_LINUX)
if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic)
{
pHalData->RxAggBlockCount = 16;
pHalData->RxAggBlockTimeout = 7;
}
else
#endif
{
pHalData->RxAggBlockCount = 40;
pHalData->RxAggBlockTimeout = 5;
}
// Mix mode
pHalData->RxAggPageCount = 72;
pHalData->RxAggPageTimeout = 6;
}
else
{
// USB mode
pHalData->RxAggBlockCount = pMgntInfo->RegRxAggBlockCount;
pHalData->RxAggBlockTimeout = pMgntInfo->RegRxAggBlockTimeout;
// Mix mode
pHalData->RxAggPageCount = pMgntInfo->RegRxAggPageCount;
pHalData->RxAggPageTimeout = pMgntInfo->RegRxAggPageTimeout;
}
if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT)
pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT;
#if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX) // do not support WINXP to prevent usbehci.sys BSOD
if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter))
{
//
// 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test
// with the aggregation dynamic change!! We need to disable the function to prevent it is broken
// in usbehci.sys.
//
usb_AggSettingRxUpdate_8188E(Adapter);
// 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse
// there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the
// issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may
// BSOD.
}
#endif
#endif
#endif
} // USB_AggModeSwitch
static VOID
@ -1155,68 +1030,6 @@ _InitOperationMode(
IN PADAPTER Adapter
)
{
#if 0//gtest
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
u1Byte regBwOpMode = 0;
u4Byte regRATR = 0, regRRSR = 0;
//1 This part need to modified according to the rate set we filtered!!
//
// Set RRSR, RATR, and REG_BWOPMODE registers
//
switch (Adapter->RegWirelessMode)
{
case WIRELESS_MODE_B:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK;
regRRSR = RATE_ALL_CCK;
break;
case WIRELESS_MODE_A:
regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
regRATR = RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_G:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_AUTO:
if (Adapter->bInHctTest)
{
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
}
else
{
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
}
break;
case WIRELESS_MODE_N_24G:
// It support CCK rate by default.
// CCK rate will be filtered out only when associated AP does not support it.
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_N_5G:
regBwOpMode = BW_OPMODE_5G;
regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_OFDM_AG;
break;
default: //for MacOSX compiler warning.
break;
}
// Ziv ????????
//PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
#endif
}
@ -1307,34 +1120,6 @@ static VOID _RfPowerSave(
IN PADAPTER Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte eRFPath;
#if (DISABLE_BB_RF)
return;
#endif
if (pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
// Those action will be discard in MgntActSet_RF_State because off the same state
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
}
else if (pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
}
else{
pHalData->eRFPowerState = eRfOn;
pMgntInfo->RfOffReason = 0;
if (Adapter->bInSetPower || Adapter->bResetInProgress)
PlatformUsbEnableInPipes(Adapter);
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
}
#endif
}
enum {
@ -1374,39 +1159,6 @@ HalDetectSelectiveSuspendMode(
IN PADAPTER Adapter
)
{
#if 0
u8 tmpvalue;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
// If support HW radio detect, we need to enable WOL ability, otherwise, we
// can not use FW to notify host the power state switch.
EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
if (tmpvalue & BIT1)
{
DBG_8192C("Enable\n");
}
else
{
DBG_8192C("Disable\n");
pdvobjpriv->RegUsbSS = _FALSE;
}
// 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
{
//PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
//if (!pMgntInfo->bRegDongleSS)
//{
// RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
pdvobjpriv->RegUsbSS = _FALSE;
//}
}
#endif
} // HalDetectSelectiveSuspendMode
/*-----------------------------------------------------------------------------
* Function: HwSuspendModeEnable92Cu()
@ -1691,11 +1443,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
else
#endif //MP_DRIVER == 1
{
#if 0
Adapter->bFWReady = _FALSE; //because no fw for test chip
pHalData->fw_ractrl = _FALSE;
#else
#ifdef CONFIG_WOWLAN
status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
#else
@ -1712,13 +1459,9 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
Adapter->bFWReady = _TRUE;
pHalData->fw_ractrl = _FALSE;
}
#endif
}
rtl8188e_InitializeFirmwareVars(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
#if (HAL_MAC_ENABLE == 1)
status = PHY_MACConfig8188E(Adapter);
@ -1817,12 +1560,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
}
#endif
#if 0
if (pHTInfo->bRDGEnable){
_InitRDGSetting_8188E(Adapter);
}
#endif
#ifdef CONFIG_TX_EARLY_MODE
if ( pHalData->bEarlyModeEnable)
{
@ -1931,97 +1668,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
// Added by tynli. 2010.03.30.
pwrctrlpriv->rf_pwrstate = rf_on;
#if 0 //to do
RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
#if 1 //Todo
// 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
// 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
if (pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
pwrctrlpriv->b_hw_radio_off = _TRUE;
DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
if (pwrctrlpriv->reg_rfoff == _TRUE)
{ // User disable RF via registry.
DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
// Those action will be discard in MgntActSet_RF_State because off the same state
//for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
}
else if (pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
{ // H/W or S/W RF OFF before sleep.
DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
//pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->rf_pwrstate = rf_on;
//MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
}
else
{
// Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
if (pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
{
DBG_8192C("InitializeAdapter8192CU(): RF=%d\n", eRfPowerStateToSet);
if (eRfPowerStateToSet == rf_off)
{
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
pwrctrlpriv->b_hw_radio_off = _TRUE;
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->b_hw_radio_off = _FALSE;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
pwrctrlpriv->rfoff_reason = 0;
pwrctrlpriv->b_hw_radio_off = _FALSE;
pwrctrlpriv->rf_pwrstate = rf_on;
rtw_led_control(Adapter, LED_CTL_POWER_ON);
}
// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
if (pHalData->pwrdown && eRfPowerStateToSet == rf_off)
{
// Enable register area 0x0-0xc.
rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
//
// <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
// our HW will be set in power-down mode if PDn source from all functions are configured.
// 2010.10.06.
//
//if (IS_HARDWARE_TYPE_8723AU(Adapter))
//{
// u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
// rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
//}
//else
//{
rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
//}
}
//DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
#endif
#endif
// enable Tx report.
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
@ -2284,291 +1930,13 @@ unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter)
return _SUCCESS;
}
//-------------------------------------------------------------------------
//
// EEPROM Power index mapping
//
//-------------------------------------------------------------------------
#if 0
static VOID
_ReadPowerValueFromPROM(
IN PTxPowerInfo pwrInfo,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
u32 rfPath, eeAddr, group;
_rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo));
if (AutoLoadFail){
for (group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
pwrInfo->CCKIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
pwrInfo->HT40_1SIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff;
pwrInfo->HT20IndexDiff[rfPath][group] = EEPROM_Default_HT20_Diff;
pwrInfo->OFDMIndexDiff[rfPath][group] = EEPROM_Default_LegacyHTTxPowerDiff;
pwrInfo->HT40MaxOffset[rfPath][group] = EEPROM_Default_HT40_PwrMaxOffset;
pwrInfo->HT20MaxOffset[rfPath][group] = EEPROM_Default_HT20_PwrMaxOffset;
}
}
pwrInfo->TSSI_A = EEPROM_Default_TSSI;
pwrInfo->TSSI_B = EEPROM_Default_TSSI;
return;
}
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for (group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group;
pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group;
pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr];
}
}
for (group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
pwrInfo->HT40_2SIndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
#if 1
pwrInfo->HT20IndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
if (pwrInfo->HT20IndexDiff[rfPath][group] & BIT3) //4bit sign number to 8 bit sign number
pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
#else
pwrInfo->HT20IndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
#endif
pwrInfo->OFDMIndexDiff[rfPath][group] =
(PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF;
pwrInfo->HT40MaxOffset[rfPath][group] =
(PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
pwrInfo->HT20MaxOffset[rfPath][group] =
(PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
}
}
pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A];
pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B];
}
static u32
_GetChannelGroup(
IN u32 channel
)
{
//RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
if (channel < 3){ // Channel 1~3
return 0;
}
else if (channel < 9){ // Channel 4~9
return 1;
}
return 2; // Channel 10~14
}
static VOID
ReadTxPowerInfo(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
TxPowerInfo pwrInfo;
u32 rfPath, ch, group;
u8 pwr, diff;
_ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail);
if (!AutoLoadFail)
pHalData->bTXPowerDataReadFromEEPORM = _TRUE;
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
group = _GetChannelGroup(ch);
pHalData->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group];
pHalData->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group];
pHalData->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group];
pHalData->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group];
pHalData->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group];
pHalData->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group];
pwr = pwrInfo.HT40_1SIndex[rfPath][group];
diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
pHalData->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0;
}
}
#if 0 //DBG
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower,
("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch],
pHalData->TxPwrLevelHT40_1S[rfPath][ch],
pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
}
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
}
#endif
// 2010/10/19 MH Add Regulator recognize for CU.
if (!AutoLoadFail)
{
pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7); //bit0~2
}
else
{
pHalData->EEPROMRegulatory = 0;
}
DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
}
#endif
//-------------------------------------------------------------------
//
// EEPROM/EFUSE Content Parsing
//
//-------------------------------------------------------------------
static void
_ReadIDs(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
static void _ReadIDs(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if (_FALSE == AutoloadFail){
// VID, PID
pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
}
else{
pHalData->EEPROMVID = EEPROM_Default_VID;
pHalData->EEPROMPID = EEPROM_Default_PID;
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID;
pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
}
// For customized behavior.
if ((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
pHalData->CustomerID = RT_CID_819x_HP;
// Decide CustomerID according to VID/DID or EEPROM
switch (pHalData->EEPROMCustomerID)
{
case EEPROM_CID_DEFAULT:
if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pHalData->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pHalData->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pHalData->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
/*
Adapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->keepAliveLevel = 0;
Adapter->bUnloadDriverwhenS3S4 = FALSE;
*/
break;
default:
pHalData->CustomerID = RT_CID_DEFAULT;
break;
}
MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
#endif
}
static VOID
_ReadMACAddress(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
{
#if 0
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
if (_FALSE == AutoloadFail){
//Read Permanent MAC address and set value to hardware
_rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
}
else{
//Random assigh MAC address
u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
//sMacAddr[5] = (u8)GetRandomNumber(1, 254);
_rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
}
DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__func__, MAC_ARG(pEEPROM->mac_addr));
//NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
//RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
#endif
}
static VOID
@ -2613,33 +1981,6 @@ _ReadThermalMeter(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 tempval;
//
// ThermalMeter from EEPROM
//
if (!AutoloadFail)
tempval = PROMContent[EEPROM_THERMAL_METER];
else
tempval = EEPROM_Default_ThermalMeter;
pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0]
if (pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
pdmpriv->bAPKThermalMeterIgnore = _TRUE;
#if 0
if (pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
pHalData->EEPROMThermalMeter = 0x12;
#endif
pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
//RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
#endif
}
static VOID
@ -2658,16 +1999,6 @@ _ReadPROMVersion(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if (AutoloadFail){
pHalData->EEPROMVersion = EEPROM_Default_Version;
}
else{
pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION];
}
#endif
}
static VOID
@ -2681,28 +2012,6 @@ readAntennaDiversity(
struct registry_priv *registry_par = &pAdapter->registrypriv;
pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct registry_priv *registry_par = &pAdapter->registrypriv;
if (!AutoLoadFail)
{
// Antenna Diversity setting.
if (registry_par->antdiv_cfg == 2) // 2: From Efuse
pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
else
pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
//if (pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
// pHalData->AntDivCfg = 0;
}
else
{
pHalData->AntDivCfg = 0;
}
#endif
}
static VOID
@ -2711,39 +2020,6 @@ hal_InitPGData(
IN OUT u8 *PROMContent
)
{
#if 0
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u32 i;
u16 value16;
if (_FALSE == pEEPROM->bautoload_fail_flag)
{ // autoload OK.
if (_TRUE == pEEPROM->EepromOrEfuse)
{
// Read all Content from EEPROM or EFUSE.
for (i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
{
//value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
//*((u16 *)(&PROMContent[i])) = value16;
}
}
else
{
// Read EFUSE real map to shadow.
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
_rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
}
}
else
{//autoload fail
//RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n"));
pEEPROM->bautoload_fail_flag = _TRUE;
//update to default value 0xFF
if (_FALSE == pEEPROM->EepromOrEfuse)
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
}
#endif
}
static void
Hal_EfuseParsePIDVID_8188EU(
@ -2819,87 +2095,11 @@ Hal_CustomizeByCustomerID_8188EU(
IN PADAPTER padapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(padapter->MgntInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
// For customized behavior.
if ((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
pMgntInfo->CustomerID = RT_CID_819x_HP;
// Decide CustomerID according to VID/DID or EEPROM
switch (pHalData->EEPROMCustomerID)
{
case EEPROM_CID_DEFAULT:
if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pMgntInfo->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pMgntInfo->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pMgntInfo->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
padapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE;
pMgntInfo->keepAliveLevel = 0;
padapter->bUnloadDriverwhenS3S4 = FALSE;
break;
default:
pMgntInfo->CustomerID = RT_CID_DEFAULT;
break;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pMgntInfo->CustomerID));
hal_CustomizedBehavior_8723U(padapter);
#endif
}
// Read HW power down mode selection
static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail)
{
#if 0
if (AutoloadFail){
Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
}
else {
//if (SUPPORT_HW_RADIO_DETECT(Adapter))
Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
//else
//Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
//hw power down mode selection , 0:rf-off / 1:power down
if (Adapter->registrypriv.hwpdn_mode==2)
Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
else
Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
// decide hw if support remote wakeup function
// if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
//if (SUPPORT_HW_RADIO_DETECT(Adapter))
//Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__func__,
Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
}
#endif
}
#ifdef CONFIG_EFUSE_CONFIG_FILE
@ -4084,30 +3284,12 @@ _func_enter_;
}
break;
case HW_VAR_RESP_SIFS:
{
#if 0
// SIFS for OFDM Data ACK
rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]);
// SIFS for OFDM consecutive tx like CTS data!
rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]);
rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]);
rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]);
// 20100719 Joseph: Revise SIFS setting due to Hardware register definition change.
rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]);
rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]);
#else
//SIFS_Timer = 0x0a0a0808;
//RESP_SIFS for CCK
rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
//RESP_SIFS for OFDM
rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
#endif
}
//RESP_SIFS for CCK
rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
//RESP_SIFS for OFDM
rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
break;
case HW_VAR_ACK_PREAMBLE:
{
@ -4115,7 +3297,6 @@ _func_enter_;
u8 bShortPreamble = *( (PBOOLEAN)val );
// Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
//regTmp = 0;
if (bShortPreamble)
regTmp |= 0x80;

132
hal/usb_ops_linux.c
View file

@ -120,14 +120,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
_rtw_memcpy( pIo_buf, pdata, len);
}
#if 0
//timeout test for firmware downloading
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len
, (value == FW_8188E_START_ADDRESS) ?RTW_USB_CONTROL_MSG_TIMEOUT_TEST : RTW_USB_CONTROL_MSG_TIMEOUT
);
#else
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
#endif
if ( status == len) // Success this control transfer.
{
@ -399,21 +392,6 @@ void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
#if 0 //DBG
{
u32 hisr=0 ,hisr_ex=0;
_rtw_memcpy(&hisr,&(pHalData->IntArray[0]),4);
hisr = le32_to_cpu(hisr);
_rtw_memcpy(&hisr_ex,&(pHalData->IntArray[1]),4);
hisr_ex = le32_to_cpu(hisr_ex);
if ((hisr != 0) || (hisr_ex!=0))
DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x\n",__func__,hisr,hisr_ex);
}
#endif
#ifdef CONFIG_LPS_LCLK
if ( pHalData->IntArray[0] & IMR_CPWM_88E )
{
@ -436,34 +414,15 @@ void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0
if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDOK_88E)
DBG_8192C("%s: HISR_TXBCNOK\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDER_88E)
DBG_8192C("%s: HISR_TXBCNERR\n", __func__);
#endif
if (check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
if (pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#ifdef CONFIG_CONCURRENT_MODE
if (check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if (check_buddy_fwstate(padapter, WIFI_AP_STATE)) {
if (padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
@ -618,81 +577,7 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
}
else // Handle BC/MC Packets
{
u8 clone = _TRUE;
#if 0
u8 type, subtype, *paddr2, *paddr3;
type = GetFrameType(pbuf);
subtype = GetFrameSubType(pbuf); //bit(7)~bit(2)
switch (type)
{
case WIFI_MGT_TYPE: //Handle BC/MC mgnt Packets
if (subtype == WIFI_BEACON)
{
paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data);
if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) &&
_rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
{
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
if (check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) &&
_rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN))
{
if (clone==_FALSE)
{
clone = _TRUE;
}
else
{
clone = _FALSE;
}
precvframe->u.hdr.adapter = primary_padapter;
}
if (check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) ||
check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING))
{
clone = _TRUE;
precvframe->u.hdr.adapter = primary_padapter;
}
}
else if (subtype == WIFI_PROBEREQ)
{
//probe req frame is only for interface2
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
break;
case WIFI_CTRL_TYPE: // Handle BC/MC ctrl Packets
break;
case WIFI_DATA_TYPE: //Handle BC/MC data Packets
//Notes: AP MODE never rx BC/MC data packets
paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data);
if (_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
{
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
break;
default:
break;
}
#endif
if (_TRUE == clone)
{
@ -811,13 +696,6 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
#if 0 //temp remove when disable usb rx aggregation
if ((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
{
return _FAIL;
}
#endif
do{
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
@ -1217,12 +1095,6 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
#if 0 //temp remove when disable usb rx aggregation
if ((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
{
return _FAIL;
}
#endif
do{
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",

19
include/HalHWImg8188E_FW.h
View file

@ -36,27 +36,8 @@ ODM_ReadFirmware_8188E_FW_AP(
#else
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
#if 0
void
ODM_ReadFirmware_8188E_FW_NIC(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
#if 0
void
ODM_ReadFirmware_8188E_FW_WoWLAN(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
#define ArrayLength_8188E_FW_WoWLAN 15764
extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
#endif

11
include/drv_types_ce.h
View file

@ -65,17 +65,6 @@ typedef struct _USB_EXTENSION {
LPCUSB_FUNCS _lpUsbFuncs;
USB_HANDLE _hDevice;
PVOID pAdapter;
#if 0
USB_ENDPOINT_DESCRIPTOR _endpACLIn;
USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh;
USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal;
USB_PIPE pPipeIn;
USB_PIPE pPipeOutNormal;
USB_PIPE pPipeOutHigh;
#endif
} USB_EXTENSION, *PUSB_EXTENSION;
#endif

56
include/ieee80211.h
View file

@ -1088,49 +1088,6 @@ struct ieee80211_txb {
#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
#define IW_ESSID_MAX_SIZE 32
#if 0
struct ieee80211_network {
/* These entries are used to identify a unique network */
u8 bssid[ETH_ALEN];
u8 channel;
/* Ensure null-terminated for any debug msgs */
u8 ssid[IW_ESSID_MAX_SIZE + 1];
u8 ssid_len;
u8 rssi; //relative signal strength
u8 sq; //signal quality
/* These are network statistics */
//struct ieee80211_rx_stats stats;
u16 capability;
u16 aid;
u8 rates[MAX_RATES_LENGTH];
u8 rates_len;
u8 rates_ex[MAX_RATES_EX_LENGTH];
u8 rates_ex_len;
u8 edca_parmsets[18];
u8 mode;
u8 flags;
u8 time_stamp[8];
u16 beacon_interval;
u16 listen_interval;
u16 atim_window;
u8 wpa_ie[MAX_WPA_IE_LEN];
size_t wpa_ie_len;
u8 rsn_ie[MAX_WPA_IE_LEN];
size_t rsn_ie_len;
u8 country[6];
u8 dtim_period;
u8 dtim_data;
u8 power_constraint;
u8 qosinfo;
u8 qbssload[5];
u8 network_type;
int join_res;
unsigned long last_scanned;
};
#endif
/*
join_res:
-1: authentication fail
@ -1224,19 +1181,6 @@ typedef struct tx_pending_t{
int ieee80211_is_empty_essid(const char *essid, int essid_len);
int ieee80211_get_hdrlen(u16 fc);
#if 0
/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */
#define WLAN_ACTION_SPECTRUM_MGMT 0
#define WLAN_ACTION_QOS 1
#define WLAN_ACTION_DLS 2
#define WLAN_ACTION_BLOCK_ACK 3
#define WLAN_ACTION_RADIO_MEASUREMENT 5
#define WLAN_ACTION_FT 6
#define WLAN_ACTION_SA_QUERY 8
#define WLAN_ACTION_WMM 17
#endif
/* Action category code */
enum rtw_ieee80211_category {
RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0,

53
include/ieee80211_ext.h
View file

@ -272,21 +272,6 @@ struct ieee80211_mgmt {
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
#if 0
struct{
u8 action_code;
u8 element_id;
u8 length;
struct ieee80211_channel_sw_ie sw_elem;
} __attribute__ ((packed)) chan_switch;
struct{
u8 action_code;
u8 dialog_token;
u8 element_id;
u8 length;
struct ieee80211_msrment_ie msr_elem;
} __attribute__ ((packed)) measurement;
#endif
struct{
u8 action_code;
u8 dialog_token;
@ -376,29 +361,6 @@ struct ieee80211_mgmt {
struct {
u16 reason_code;
} disassoc;
#if 0
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} probe_resp;
#endif
struct {
u8 category;
union {
@ -408,21 +370,6 @@ struct ieee80211_mgmt {
u8 status_code;
u8 variable[0];
} wme_action;
/*
struct{
u8 action_code;
u8 element_id;
u8 length;
struct ieee80211_channel_sw_ie sw_elem;
} chan_switch;
struct{
u8 action_code;
u8 dialog_token;
u8 element_id;
u8 length;
struct ieee80211_msrment_ie msr_elem;
} measurement;
*/
struct{
u8 action_code;
u8 dialog_token;

49
include/odm.h
View file

@ -509,48 +509,11 @@ typedef struct _ODM_STA_INFO{
u1Byte RXEVM[4];
u1Byte RXSNR[4];
// ODM Write
//1 TX_INFO (may changed by IC)
//TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer.
#if 0
u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit
u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit
u1Byte ANTSEL_C; //only in Jagar: 4bit
u1Byte ANTSEL_D; //only in Jagar: 4bit
u1Byte TX_ANTL; //not in Jagar: 2bit
u1Byte TX_ANT_HT; //not in Jagar: 2bit
u1Byte TX_ANT_CCK; //not in Jagar: 2bit
u1Byte TXAGC_A; //not in Jagar: 4bit
u1Byte TXAGC_B; //not in Jagar: 4bit
u1Byte TXPWR_OFFSET; //only in Jagar: 3bit
u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK
#endif
//
// Please use compile flag to disabe the strcutrue for other IC except 88E.
// Please use compile flag to disable the struictrue for other IC except 88E.
// Move To lower layer.
//
// ODM Write Wilson will handle this part(said by Luke.Lee)
//TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer.
#if 0
//1 For 88E RA (don't redefine the naming)
u1Byte rate_id;
u1Byte rate_SGI;
u1Byte rssi_sta_ra;
u1Byte SGI_enable;
u1Byte Decision_rate;
u1Byte Pre_rate;
u1Byte Active;
// Driver write Wilson handle.
//1 TX_RPT (don't redefine the naming)
u2Byte RTY[4]; // ???
u2Byte TOTAL; // ???
u2Byte DROP; // ???
//
// Please use compile flag to disabe the strcutrue for other IC except 88E.
//
#endif
}ODM_STA_INFO_T, *PODM_STA_INFO_T;
#endif
@ -1521,16 +1484,6 @@ typedef enum tag_DIG_Connect_Definition
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
//3===========================================================
//3 Tx Power Tracking
//3===========================================================
#if 0 //mask this, since these have been defined in typdef.h, vivi
#define OFDM_TABLE_SIZE 37
#define OFDM_TABLE_SIZE_92D 43
#define CCK_TABLE_SIZE 33
#endif
//3===========================================================
//3 Rate Adaptive
//3===========================================================

734
include/odm_debug.h
View file

@ -168,738 +168,6 @@
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID
ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
);
#if 0
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if (((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for ( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if (((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for ( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if (((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for ( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for ( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if (((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for ( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if ( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif
#if 0
/* Define debug print header for every service module.*/
typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}ODM_DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_ODM_DBGP_Flag_Type_Definition
{
ODM_FTX = 0,
ODM_FRX ,
ODM_FPHY ,
ODM_FPWR ,
ODM_FDM ,
ODM_FC2H ,
ODM_FBT ,
ODM_DBGP_TYPE_MAX
}ODM_DBGP_FLAG_E;
// Define TX relative debug bit --> FTX
#define ODM_TX_DESC BIT0
#define ODM_TX_DESC_TID BIT1
#define ODM_TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define ODM_RX_DATA BIT0
#define ODM_RX_PHY_STS BIT1
#define ODM_RX_PHY_SS BIT2
#define ODM_RX_PHY_SQ BIT3
#define ODM_RX_PHY_ASTS BIT4
#define ODM_RX_ERR_LEN BIT5
#define ODM_RX_DEFRAG BIT6
#define ODM_RX_ERR_RATE BIT7
#define ODM_RX_PATH BIT8
#define ODM_RX_BEACON BIT9
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define ODM_PHY_BBR BIT0
#define ODM_PHY_BBW BIT1
#define ODM_PHY_RFR BIT2
#define ODM_PHY_RFW BIT3
#define ODM_PHY_MACR BIT4
#define ODM_PHY_MACW BIT5
#define ODM_PHY_ALLR BIT6
#define ODM_PHY_ALLW BIT7
#define ODM_PHY_TXPWR BIT8
#define ODM_PHY_PWRDIFF BIT9
#define ODM_PHY_SICR BIT10
#define ODM_PHY_SICW BIT11
extern u4Byte ODM_GlobalDebugLevel;
#if DBG
extern u8Byte ODM_GlobalDebugComponents;
#endif
#endif
#if 0
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
//
#define DBG_OFF 0
//
// Deprecated! Don't use it!
// TODO: fix related debug message!
//
//#define DBG_SEC 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
#define COMP_TRACE BIT0 // For function call tracing.
#define COMP_DBG BIT1 // Only for temporary debug message.
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
#define COMP_OID_QUERY BIT3 // Query OID.
#define COMP_OID_SET BIT4 // Set OID.
#define COMP_RECV BIT5 // Reveive part data path.
#define COMP_SEND BIT6 // Send part path.
#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02.
#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related.
#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS.
#define COMP_SCAN BIT10 // For site survey.
#define COMP_SYSTEM BIT11 // For general platform function.
#define COMP_SEC BIT12 // For Security.
#define COMP_AP BIT13 // For AP mode related.
#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21.
#define COMP_QOS BIT15 // For QoS.
#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30.
#define COMP_BEACON BIT17 // For Beacon related, by rcnjko.
#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko.
#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
#define COMP_EVENTS BIT20 // Event handling
#define COMP_FPGA BIT21 // For FPGA verfication
#define COMP_RM BIT22 // For Radio Measurement.
#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13
#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko.
#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko.
#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko.
#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW.
#define COMP_INDIC BIT31 // For link indication
#define COMP_LED BIT32 // For LED.
#define COMP_RF BIT33 // For RF.
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11
#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING
#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder
#define COMP_AMSDU BIT37 // For A-MSDU Debugging
#define COMP_WPS BIT38 //WPS Debug Message
#define COMP_RATR BIT39
#define COMP_RESET BIT40
// For debug command to print on dbgview!!
#define COMP_CMD BIT41
#define COMP_EFUSE BIT42
#define COMP_MESH_INTERWORKING BIT43
#define COMP_CCX BIT44 //CCX Debug Flag
#define COMP_IOCTL BIT45 // IO Control
#define COMP_GP BIT46 // For generic parser.
#define COMP_TXAGG BIT47
#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
#define COMP_TEST BIT49
#define COMP_BB_POWERSAVING BIT50
#define COMP_SWAS BIT51 // For SW Antenna Switch
#define COMP_P2P BIT52
#define COMP_MUX BIT53
#define COMP_FUNC BIT54
#define COMP_TDLS BIT55
#define COMP_OMNIPEEK BIT56
#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug
#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug
#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH
#define COMP_DFS BIT62
#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
// For debug print flag to use
/*------------------------------Define structure----------------------------*/
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/* Defnie structure to store different debug flag variable. Every debug flag
is a UINT32 integer and you can assign 32 different events. */
typedef struct tag_DBGP_Debug_Flag_Structure
{
u4Byte Mans; /* Main Scheduler module. */
u4Byte Rtos; /* RTOS module. */
u4Byte Alarm; /* Alarm module. */
u4Byte Pm; /* Performance monitor module. */
}DBGP_FLAG_T;
/* Define debug print header for every service module.*/
typedef struct tag_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_DBGP_Flag_Type_Definition
{
FQoS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBG_CTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
FSHORT_CUT = 19,
DBGP_TYPE_MAX
}DBGP_FLAG_E;
// Define Qos Relative debug flag bit --> FQoS
#define QoS_INIT BIT0
#define QoS_VISTA BIT1
// Define TX relative debug bit --> FTX
#define TX_DESC BIT0
#define TX_DESC_TID BIT1
#define TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define RX_DATA BIT0
#define RX_PHY_STS BIT1
#define RX_PHY_SS BIT2
#define RX_PHY_SQ BIT3
#define RX_PHY_ASTS BIT4
#define RX_ERR_LEN BIT5
#define RX_DEFRAG BIT6
#define RX_ERR_RATE BIT7
#define RX_PATH BIT8
#define RX_BEACON BIT9
// Define Security relative debug bit --> FSEC
// Define MGNT relative debug bit --> FMGNT
// Define MLME relative debug bit --> FMLME
#define MEDIA_STS BIT0
#define LINK_STS BIT1
// Define OS resource check module bit --> FRESOURCE
#define OS_CHK BIT0
// Define beacon content check module bit --> FBEACON
#define BCN_SHOW BIT0
#define BCN_PEER BIT1
// Define ISR/IMR check module bit --> FISR
#define ISR_CHK BIT0
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define PHY_BBR BIT0
#define PHY_BBW BIT1
#define PHY_RFR BIT2
#define PHY_RFW BIT3
#define PHY_MACR BIT4
#define PHY_MACW BIT5
#define PHY_ALLR BIT6
#define PHY_ALLW BIT7
#define PHY_TXPWR BIT8
#define PHY_PWRDIFF BIT9
#define PHY_SICR BIT10
#define PHY_SICW BIT11
// Define MPT driver check module bit --> FMP
#define MP_RX BIT0
#define MP_SWICH_CH BIT1
// Define EEPROM and EFUSE check module bit --> FEEPROM
#define EEPROM_W BIT0
#define EFUSE_PG BIT1
#define EFUSE_READ_ALL BIT2
#define EFUSE_ANALYSIS BIT3
#define EFUSE_PG_DETAIL BIT4
// Define power save check module bit --> FPWR
#define LPS BIT0
#define IPS BIT1
#define PWRSW BIT2
#define PWRHW BIT3
#define PWRHAL BIT4
// Define Dynamic Mechanism check module bit --> FDM
#define WA_IOT BIT0
#define DM_PWDB BIT1
#define DM_Monitor BIT2
#define DM_DIG BIT3
#define DM_EDCA_Turbo BIT4
#define DM_BT30 BIT5
// Define Dbg Control module bit --> FDBG_CTRL
#define DBG_CTRL_TRACE BIT0
#define DBG_CTRL_INBAND_NOISE BIT1
// Define FW C2H Cmd check module bit --> FC2H
#define C2H_Summary BIT0
#define C2H_PacketData BIT1
#define C2H_ContentData BIT2
// Define BT Cmd check module bit --> FBT
#define BT_TRACE BIT0
#define BT_RFPoll BIT1
// Define init check for module bit --> FINIT
#define INIT_EEPROM BIT0
#define INIT_TxPower BIT1
#define INIT_IQK BIT2
#define INIT_RF BIT3
// Define IOCTL Cmd check module bit --> FIOCTL
// section 1 : IRP related
#define IOCTL_IRP BIT0
#define IOCTL_IRP_DETAIL BIT1
#define IOCTL_IRP_STATISTICS BIT2
#define IOCTL_IRP_HANDLE BIT3
// section 2 : HCI command/event
#define IOCTL_BT_HCICMD BIT8
#define IOCTL_BT_HCICMD_DETAIL BIT9
#define IOCTL_BT_HCICMD_EXT BIT10
#define IOCTL_BT_EVENT BIT11
#define IOCTL_BT_EVENT_DETAIL BIT12
#define IOCTL_BT_EVENT_PERIODICAL BIT13
// section 3 : BT tx/rx data and throughput
#define IOCTL_BT_TX_ACLDATA BIT16
#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17
#define IOCTL_BT_RX_ACLDATA BIT18
#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19
#define IOCTL_BT_TP BIT20
// section 4 : BT connection state machine.
#define IOCTL_STATE BIT21
#define IOCTL_BT_LOGO BIT22
// section 5 : BT function trace
#define IOCTL_CALLBACK_FUN BIT24
#define IOCTL_PARSE_BT_PKT BIT25
#define IOCTL_BT_TX_PKT BIT26
#define IOCTL_BT_FLAG_MON BIT27
//
// Define init check for module bit --> FSHORT_CUT
// 2011/07/20 MH Add for short but definition.
//
#define SHCUT_TX BIT0
#define SHCUT_RX BIT1
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __func__, ## args);
#if DBG
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \
if (((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_TRACE_F(comp, level, fmt) \
if (((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_ASSERT(expr,fmt) \
if (!(expr)) { \
printk( "Assertion failed! %s at ......\n", #expr); \
printk( " ......%s,%s,line=%d\n",__FILE__,__func__,__LINE__); \
}
#define dbg_enter() { printk("==> %s\n", __func__); }
#define dbg_exit() { printk("<== %s\n", __func__); }
#define dbg_trace(str) { printk("%s:%s\n", __func__, str); }
#else
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
#define RT_TRACE_F(comp, level, fmt)
#define RT_ASSERT(expr, fmt)
#define dbg_enter()
#define dbg_exit()
#define dbg_trace(str)
#endif
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if (((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for ( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if (((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for ( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if (((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for ( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for ( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if (((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for ( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if ( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_MP)
#define DEBUG_PRINT 1
// Please add new OS's print API by yourself
//#if (RT_PLATFORM==PLATFORM_WINDOWS)
#if (DEBUG_PRINT == 1) && DBG
#define RTPRINT(dbgtype, dbgflag, printstr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for ( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for ( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#define FuncEntry FunctionIn(COMP_FUNC)
#define FuncExit FunctionOut(COMP_FUNC)
#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __func__))
#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __func__))
#else
#define DBGP(dbgtype, dbgflag, printstr)
#define RTPRINT(dbgtype, dbgflag, printstr)
#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#define FuncEntry
#define FuncExit
#define FunctionIn(_comp)
#define FunctionOut(_comp)
#endif
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export global variable----------------------------*/
extern u4Byte DBGP_Type[DBGP_TYPE_MAX];
extern DBGP_HEAD_T DBGP_Head;
/*------------------------Export global variable----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
extern void DBGP_Flag_Init(void);
extern void DBG_PrintAllFlag(void);
extern void DBG_PrintAllComp(void);
extern void DBG_PrintFlagEvent(u1Byte DbgFlag);
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len);
/*--------------------------Exported Function prototype---------------------*/
extern u4Byte GlobalDebugLevel;
extern u8Byte GlobalDebugComponents;
#endif
VOID ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
#endif // __ODM_DBG_H__

37
include/odm_interface.h
View file

@ -40,12 +40,6 @@
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
#if 0
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name) \
)
#endif
/*===================================
@ -67,17 +61,6 @@ ODM_REG(DIG,_pDM_Odm)
_func##_11AC(_name) \
)
#endif
#if 0 // only sample code
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \
((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \
((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \
((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \
((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
_func##_ic(_name, _8195) \
)
#endif
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
@ -102,26 +85,6 @@ typedef enum _ODM_H2C_CMD
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#if 0
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
typedef struct _RT_WORK_ITEM
{
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
PVOID Adapter; // Pointer to Adapter object.
PVOID pContext; // Parameter to passed to CallBackFunc().
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
PVOID pPlatformExt; // Pointer to platform-dependent extension.
BOOLEAN bFree;
char szID[36]; // An identity string of this workitem.
}RT_WORK_ITEM, *PRT_WORK_ITEM;
#endif
#endif
//

11
include/odm_types.h
View file

@ -169,16 +169,6 @@ typedef enum _RT_SPINLOCK_TYPE{
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <basic_types.h>
#if 0
typedef u8 u1Byte, *pu1Byte;
typedef u16 u2Byte,*pu2Byte;
typedef u32 u4Byte,*pu4Byte;
typedef u64 u8Byte,*pu8Byte;
typedef s8 s1Byte,*ps1Byte;
typedef s16 s2Byte,*ps2Byte;
typedef s32 s4Byte,*ps4Byte;
typedef s64 s8Byte,*ps8Byte;
#else
#define u1Byte u8
#define pu1Byte u8*
@ -203,7 +193,6 @@ typedef enum _RT_SPINLOCK_TYPE{
#define s8Byte s64
#define ps8Byte s64*
#endif
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)

22
include/rtl8188e_cmd.h
View file

@ -20,24 +20,6 @@
#ifndef __RTL8188E_CMD_H__
#define __RTL8188E_CMD_H__
#if 0
enum cmd_msg_element_id
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID = 0,
SET_PWRMODE_EID = 1,
JOINBSS_RPT_EID = 2,
RSVD_PAGE_EID = 3,
RSSI_4_EID = 4,
RSSI_SETTING_EID = 5,
MACID_CONFIG_EID = 6,
MACID_PS_MODE_EID = 7,
P2P_PS_OFFLOAD_EID = 8,
SELECTIVE_SUSPEND_ROF_CMD = 9,
P2P_PS_CTW_CMD_EID = 32,
MAX_CMDMSG_EID
};
#else
typedef enum _RTL8188E_H2C_CMD_ID
{
//Class Common
@ -83,9 +65,6 @@ typedef enum _RTL8188E_H2C_CMD_ID
H2C_RESET_TSF =0xc0,
}RTL8188E_H2C_CMD_ID;
#endif
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
@ -98,7 +77,6 @@ enum{
typedef struct _SETPWRMODE_PARM {
u8 Mode;//0:Active,1:LPS,2:WMMPS
//u8 RLBM:4;//0:Min,1:Max,2: User define
u8 SmartPS_RLBM;//LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData
u8 AwakeInterval; // unit: beacon interval
u8 bAllQueueUAPSD;

115
include/rtl8188e_dm.h
View file

@ -44,134 +44,21 @@ struct dm_priv
int MinUndecoratedPWDBForDM;
int LastMinUndecoratedPWDBForDM;
//###### duplicate code,will move to ODM #########
/*
//for DIG
u8 bDMInitialGainEnable;
u8 binitialized; // for dm_initial_gain_Multi_STA use.
DIG_T DM_DigTable;
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
*/
//for High Power
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
u8 PowerIndex_backup[6];
#if 0
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u8 ThermalValue;
u8 ThermalValue_LCK;
u8 ThermalValue_IQK;
u8 ThermalValue_DPK;
u8 bRfPiEnable;
//for APK
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
//for IQK
u32 RegC04;
u32 Reg874;
u32 RegC08;
u32 RegB68;
u32 RegB6C;
u32 Reg870;
u32 Reg860;
u32 Reg864;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 bCCKinCH14;
u8 CCK_index;
u8 OFDM_index[2];
u8 bDoneTxpower;
u8 CCK_index_HP;
u8 OFDM_index_HP[2];
u8 ThermalValue_HP[HP_THERMAL_NUM];
u8 ThermalValue_HP_index;
//for TxPwrTracking
s32 RegE94;
s32 RegE9C;
s32 RegEB4;
s32 RegEBC;
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
u32 prv_traffic_idx; // edca turbo
/*
// for dm_RF_Saving
u8 initialize;
u32 rf_saving_Reg874;
u32 rf_saving_RegC70;
u32 rf_saving_Reg85C;
u32 rf_saving_RegA74;
*/
//for Antenna diversity
#ifdef CONFIG_ANTENNA_DIVERSITY
// SWAT_T DM_SWAT_Table;
#endif
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
// _timer SwAntennaSwitchTimer;
/*
u64 lastTxOkCnt;
u64 lastRxOkCnt;
u64 TXByteCnt_A;
u64 TXByteCnt_B;
u64 RXByteCnt_A;
u64 RXByteCnt_B;
u8 DoubleComfirm;
u8 TrafficLoad;
*/
#endif
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
// u8 DIG_Dynamic_MIN ;
//###### duplicate code,will move to ODM #########
#endif
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
//u8 INIDATA_RATE[32];
};
void rtl8188e_init_dm_priv(IN PADAPTER Adapter);
void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8188e_InitHalDm(IN PADAPTER Adapter);
void rtl8188e_HalDmWatchDog(IN PADAPTER Adapter);
//VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter);
//void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal);
#ifdef CONFIG_ANTENNA_DIVERSITY
void AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
u8 AntDivBeforeLink8188E(PADAPTER Adapter );
#endif
#endif
#endif

11
include/rtl8188e_hal.h
View file

@ -63,11 +63,6 @@
//---------------------------------------------------------------------
// RTL8188E From header
//---------------------------------------------------------------------
#if 0
#define Rtl8188E_PHY_REG_Array_PG Rtl8188ESPHY_REG_Array_PG
#define Rtl8188E_PHY_REG_Array_PGLength Rtl8188ESPHY_REG_Array_PGLength
#endif
//---------------------------------------------------------------------
// RTL8188E Power Configuration CMDs for USB/SDIO interfaces
@ -92,12 +87,6 @@
#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
#if 0
#define Rtl8188E_PHY_REG_Array_PG Rtl8188EUPHY_REG_Array_PG
#define Rtl8188E_PHY_REG_Array_PGLength Rtl8188EUPHY_REG_Array_PGLength
#endif
//---------------------------------------------------------------------
// RTL8188E Power Configuration CMDs for USB/SDIO interfaces
//---------------------------------------------------------------------

86
include/rtl8188e_spec.h
View file

@ -1452,18 +1452,6 @@ Current IOREG MAP
#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page
#define SDIO_TX_FIFO_PAGE_SZ 128
/* move to rtl8188e_xmit.h
#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
#define MAX_TX_AGG_PACKET_NUMBER 0x8
#else
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
#endif
*/
// vivi added for new cam search flow, 20091028
//#define SCR_TxUseBroadcastDK BIT6 // Force Tx Use Broadcast Default Key
//#define SCR_RxUseBroadcastDK BIT7 // Force Rx Use Broadcast Default Key
//-----------------------------------------------------
//
// 0xFE00h ~ 0xFE55h USB Configuration
@ -1518,84 +1506,13 @@ Current IOREG MAP
//========================================================
// General definitions
//========================================================
//#if (HAL_8195A_USB == 1)
//#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
//#else
#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 // 22k 22528 bytes
//#endif
#define POLLING_LLT_THRESHOLD 20
//#if RTL8188E_FOR_MP_TEST == 1
//#define POLLING_READY_TIMEOUT_COUNT 3000
//#else
#define POLLING_READY_TIMEOUT_COUNT 1000
//#endif
// GPIO BIT
#define HAL_8192C_HW_GPIO_WPS_BIT BIT2
#if 0//(RTL8188E_SUPPORT == 1)
////////////////////////////////ONLY for 88EE/////////////////////////////////
//
// Host Interrupt Status Registers (Offset: 0x00B4-00B7, 0x00BC-00BF)
// Host Interrupt Mask Registers (Offset: 0x00B0-00B3, 0x00B8-00BB)
//
//----------------------------------------------------------------------------
// 8188 IMR/ISR bits
//----------------------------------------------------------------------------
#define IMR_DISABLED_88E 0x0
// IMR DW0(0x00B0-00B3) Bit 0-31
#define IMR_TXCCK_88E BIT30 // TXRPT interrupt when CCX bit of the packet is set
#define IMR_PSTIMEOUT_88E BIT29 // Power Save Time Out Interrupt
#define IMR_GTINT4_88E BIT28 // When GTIMER4 expires, this bit is set to 1
#define IMR_GTINT3_88E BIT27 // When GTIMER3 expires, this bit is set to 1
#define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error
#define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK
#define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt
#define IMR_BcnInt_88E BIT20 // Beacon DMA Interrupt 0
#define IMR_BDOK_88E BIT16 // Beacon Queue DMA OK0
#define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7
#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End
#define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)
#define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear
#define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK
#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK
#define IMR_BKDOK_88E BIT5 // AC_BK DMA OK
#define IMR_BEDOK_88E BIT4 // AC_BE DMA OK
#define IMR_VIDOK_88E BIT3 // AC_VI DMA OK
#define IMR_VODOK_88E BIT2 // AC_VO DMA OK
#define IMR_RDU_88E BIT1 // Rx Descriptor Unavailable
#define IMR_ROK_88E BIT0 // Receive DMA OK
// IMR DW1(0x00B8-00BB) Bit 0-31
#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7
#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6
#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5
#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4
#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3
#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2
#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1
#define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7
#define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6
#define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5
#define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4
#define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3
#define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2
#define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1
#define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7
#define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
#define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear
#define IMR_TXFOVW_88E BIT9 // Transmit FIFO Overflow
#define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow
////////////////////////////////ONLY for 88EE/////////////////////////////////
#endif //(RTL8188E_SUPPORT == 1)
//----------------------------------------------------------------------------
// 8192C EEPROM/EFUSE share register definition.
//----------------------------------------------------------------------------
@ -1724,9 +1641,6 @@ Current IOREG MAP
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#define EEPROM_CID_QMI 0x0D
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define RTL_EEPROM_ID 0x8129
#endif //__RTL8188E_SPEC_H__

22
include/rtl8192c_spec.h
View file

@ -892,28 +892,6 @@ typedef enum _BOARD_TYPE_8192CUSB{
#define EEPROM_USB_DEVICE_PWR BIT(2)
#define EEPROM_EP_NUMBER (BIT(3)|BIT(4))
#if 0
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#endif
#endif

23
include/rtl8192d_spec.h
View file

@ -930,30 +930,7 @@ Default: 00b.
#define EEPROM_USB_DEVICE_PWR BIT(2)
#define EEPROM_EP_NUMBER (BIT(3)|BIT(4))
#if 0
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#endif
#endif
/*===================================================================
=====================================================================

25
include/rtl8723a_bt-coexist.h
View file

@ -66,31 +66,6 @@ void BT_LpsLeave(PADAPTER padapter);
#define TKIP_ENC_KEY_POS 32 //(KEK_LEN+KEK_LEN)
#define MAXRSNIELEN 256
// HEADER/QoSType.h
#if 0
//
// BSS QOS data.
// Ref: BssDscr in 8185 code. [def. in BssDscr.h]
//
typedef struct _BSS_QOS
{
// Part 0. Ref. 8185 QoS code (From Emily)
QOS_MODE bdQoSMode;
u8 bdWMMIEBuf[MAX_WMMELE_LENGTH];
OCTET_STRING bdWMMIE;
QOS_ELE_SUBTYPE EleSubType;
// Part 2. EDCA Parameter (perAC)
u8 *pWMMInfoEle;
u8 *pWMMParamEle;
// QBSS Load.
u8 QBssLoad[QBSS_LOAD_SIZE];
u8 bQBssLoadValid;
} BSS_QOS, *PBSS_QOS;
#endif
// COMMON/Protocol802_11.h
//----------------------------------------------------------------------------
// 802.11 Management frame Status Code field

59
include/rtl8723a_cmd.h
View file

@ -70,17 +70,10 @@ typedef struct _SETPWRMODE_PARM
u8 AwakeInterval; // unit: beacon interval
u8 bAllQueueUAPSD;
#if 0
u8 LowRxBCN:1;
u8 AutoAntSwitch:1;
u8 PSAllowBTHighPriority:1;
u8 rsvd43:5;
#else
#define SETPM_LOWRXBCN BIT(0)
#define SETPM_AUTOANTSWITCH BIT(1)
#define SETPM_PSALLOWBTHIGHPRI BIT(2)
u8 BcnAntMode;
#endif
}__attribute__((__packed__)) SETPWRMODE_PARM, *PSETPWRMODE_PARM;
struct H2C_SS_RFOFF_PARAM{
@ -119,16 +112,6 @@ struct P2P_PS_CTWPeriod_t {
typedef struct _B_TYPE_TDMA_PARM
{
#if 0
u8 En:1;
u8 FixAntennaInBTSide:1;
u8 TxPspoll:1;
u8 val870:1; // value of 870, when disable
u8 AutoWakeUp:1;
u8 NoPS:1;
u8 WlanHighPriority:1;
u8 rsvd07:1;
#else
#define B_TDMA_EN BIT(0)
#define B_TDMA_FIXANTINBT BIT(1)
#define B_TDMA_TXPSPOLL BIT(2)
@ -137,7 +120,6 @@ typedef struct _B_TYPE_TDMA_PARM
#define B_TDMA_NOPS BIT(5)
#define B_TDMA_WLANHIGHPRI BIT(6)
u8 option;
#endif
u8 TBTTOnPeriod;
u8 MedPeriod;
@ -145,45 +127,16 @@ typedef struct _B_TYPE_TDMA_PARM
}__attribute__((__packed__)) B_TYPE_TDMA_PARM, *PB_TYPE_TDMA_PARM;
typedef struct _SCAN_EN_PARM {
#if 0
u8 En:1;
u8 rsvd01:7;
#else
u8 En;
#endif
}__attribute__((__packed__)) SCAN_EN_PARM, *PSCAN_EN_PARM;
// BT_PWR
#define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
// BT_FW_PATCH
#if 0
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
#else
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) // SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
#endif
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) // SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
#if 0
/*
* H2C_LOWPWR_LPS
* h2c cmd = 71
* byte1[6:0]= bcn count : how many bcn not recevied should return to old mechanism
* byte1[7] = enable : enable mechanism
* byte2=bcn period : bcn recv time of this AP, unit 32 us
* byte3= drop threshold : how many pkts be droped, rx dma should be release
* byte4 = max early period
* byte5 = max bcn timeout period
*/
#define SET_H2CCMD_LOWPWR_LPS_BCN_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_H2CCMD_LOWPWR_LPS_TB_BCN_THRESH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
#define SET_H2CCMD_LOWPWR_LPS_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_H2CCMD_LOWPWR_LPS_BCN_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_LOWPWR_LPS_BCN_DROP_THRESH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_LOWPWR_LPS_MAX_EARLY_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_LOWPWR_LPS_MAX_BCN_TO_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
#else
typedef struct _LOWPWR_LPS_PARM
{
u8 bcn_count:4;
@ -194,7 +147,6 @@ typedef struct _LOWPWR_LPS_PARM
u8 max_early_period;
u8 max_bcn_timeout_period;
}__attribute__((__packed__)) LOWPWR_LPS_PARM, *PLOWPWR_LPS_PARM;
#endif
// host message to firmware cmd
@ -204,17 +156,12 @@ void rtl8723a_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter);
#endif
u8 rtl8192c_set_rssi_cmd(PADAPTER padapter, u8 *param);
//u8 rtl8723a_set_rssi_cmd(PADAPTER padapter, u8 *param);
u8 rtl8192c_set_raid_cmd(PADAPTER padapter, u32 mask, u8 arg);
//u8 rtl8723a_set_raid_cmd(PADAPTER padapter, u32 mask, u8 arg);
void rtl8192c_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg, u8 rssi_level);
//void rtl8723a_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg);
u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
//u8 rtl8723a_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
#ifdef CONFIG_P2P
void rtl8192c_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
//void rtl8723a_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);

5
include/rtl8723a_hal.h
View file

@ -647,12 +647,7 @@ typedef struct hal_data_8723a
#endif
} HAL_DATA_8723A, *PHAL_DATA_8723A;
#if 0
#define HAL_DATA_TYPE HAL_DATA_8723A
#define PHAL_DATA_TYPE PHAL_DATA_8723A
#else
typedef struct hal_data_8723a HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#endif
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)

31
include/rtl8723a_pg.h
View file

@ -89,37 +89,6 @@ typedef struct _TxPowerInfo
u8 TSSI_B_5G[3];
} TxPowerInfo, *PTxPowerInfo;
#if 0
#define MAX_RF_PATH 4
#define MAX_CHNL_GROUP_24G 6
#define MAX_CHNL_GROUP_5G 14
// It must always set to 4, otherwise read efuse table secquence will be wrong.
#define MAX_TX_COUNT 4
typedef struct _TxPowerInfo24G
{
u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1];
//If only one tx, only BW20 and OFDM are used.
s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
} TxPowerInfo24G, *PTxPowerInfo24G;
typedef struct _TxPowerInfo5G
{
u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
//If only one tx, only BW20, OFDM, BW80 and BW160 are used.
s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
} TxPowerInfo5G, *PTxPowerInfo5G;
#endif
typedef enum _BT_Ant_NUM
{
Ant_x2 = 0,

109
include/rtw_mp.h
View file

@ -82,39 +82,6 @@
#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3
#endif /* #ifndef PLATFORM_WINDOWS */
#if 0
#define MPT_NOOP 0
#define MPT_READ_MAC_1BYTE 1
#define MPT_READ_MAC_2BYTE 2
#define MPT_READ_MAC_4BYTE 3
#define MPT_WRITE_MAC_1BYTE 4
#define MPT_WRITE_MAC_2BYTE 5
#define MPT_WRITE_MAC_4BYTE 6
#define MPT_READ_BB_CCK 7
#define MPT_WRITE_BB_CCK 8
#define MPT_READ_BB_OFDM 9
#define MPT_WRITE_BB_OFDM 10
#define MPT_READ_RF 11
#define MPT_WRITE_RF 12
#define MPT_READ_EEPROM_1BYTE 13
#define MPT_WRITE_EEPROM_1BYTE 14
#define MPT_READ_EEPROM_2BYTE 15
#define MPT_WRITE_EEPROM_2BYTE 16
#define MPT_SET_CSTHRESHOLD 21
#define MPT_SET_INITGAIN 22
#define MPT_SWITCH_BAND 23
#define MPT_SWITCH_CHANNEL 24
#define MPT_SET_DATARATE 25
#define MPT_SWITCH_ANTENNA 26
#define MPT_SET_TX_POWER 27
#define MPT_SET_CONT_TX 28
#define MPT_SET_SINGLE_CARRIER 29
#define MPT_SET_CARRIER_SUPPRESSION 30
#define MPT_GET_RATE_TABLE 31
#define MPT_READ_TSSI 32
#define MPT_GET_THERMAL_METER 33
#endif
typedef enum _ANTENNA_PATH{
ANTENNA_NONE = 0x00,
ANTENNA_D ,
@ -508,30 +475,9 @@ struct bb_reg_param {
#define RAISE _FALSE
/* Hardware Registers */
#if 0
#if 0
#define IOCMD_CTRL_REG 0x102502C0
#define IOCMD_DATA_REG 0x102502C4
#else
#define IOCMD_CTRL_REG 0x10250370
#define IOCMD_DATA_REG 0x10250374
#endif
#define IOCMD_GET_THERMAL_METER 0xFD000028
#define IOCMD_CLASS_BB_RF 0xF0
#define IOCMD_BB_READ_IDX 0x00
#define IOCMD_BB_WRITE_IDX 0x01
#define IOCMD_RF_READ_IDX 0x02
#define IOCMD_RF_WRIT_IDX 0x03
#endif
#define BB_REG_BASE_ADDR 0x800
/* MP variables */
#if 0
#define _2MAC_MODE_ 0
#define _LOOPBOOK_MODE_ 1
#endif
typedef enum _MP_MODE_ {
MP_OFF,
MP_ON,
@ -589,14 +535,6 @@ typedef enum _MPT_RATE_INDEX
MPT_RATE_LAST
}MPT_RATE_E, *PMPT_RATE_E;
#if 0
// Represent Channel Width in HT Capabilities
typedef enum _HT_CHANNEL_WIDTH {
HT_CHANNEL_WIDTH_20 = 0,
HT_CHANNEL_WIDTH_40 = 1,
}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
#endif
#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F
typedef enum _POWER_MODE_ {
@ -609,42 +547,6 @@ typedef enum _POWER_MODE_ {
#define RX_PKT_DEST_ADDR 2
#define RX_PKT_PHY_MATCH 3
#if 0
#define RPTMaxCount 0x000FFFFF;
// parameter 1 : BitMask
// bit 0 : OFDM PPDU
// bit 1 : OFDM False Alarm
// bit 2 : OFDM MPDU OK
// bit 3 : OFDM MPDU Fail
// bit 4 : CCK PPDU
// bit 5 : CCK False Alarm
// bit 6 : CCK MPDU ok
// bit 7 : CCK MPDU fail
// bit 8 : HT PPDU counter
// bit 9 : HT false alarm
// bit 10 : HT MPDU total
// bit 11 : HT MPDU OK
// bit 12 : HT MPDU fail
// bit 15 : RX full drop
typedef enum _RXPHY_BITMASK_
{
OFDM_PPDU_BIT = 0,
OFDM_FALSE_BIT,
OFDM_MPDU_OK_BIT,
OFDM_MPDU_FAIL_BIT,
CCK_PPDU_BIT,
CCK_FALSE_BIT,
CCK_MPDU_OK_BIT,
CCK_MPDU_FAIL_BIT,
HT_PPDU_BIT,
HT_FALSE_BIT,
HT_MPDU_BIT,
HT_MPDU_OK_BIT,
HT_MPDU_FAIL_BIT,
} RXPHY_BITMASK;
#endif
typedef enum _ENCRY_CTRL_STATE_ {
HW_CONTROL, //hw encryption& decryption
SW_CONTROL, //sw encryption& decryption
@ -665,17 +567,6 @@ extern s32 mp_start_test(PADAPTER padapter);
extern void mp_stop_test(PADAPTER padapter);
//=======================================================================
//extern void IQCalibrateBcut(PADAPTER pAdapter);
//extern u32 bb_reg_read(PADAPTER Adapter, u16 offset);
//extern u8 bb_reg_write(PADAPTER Adapter, u16 offset, u32 value);
//extern u32 rf_reg_read(PADAPTER Adapter, u8 path, u8 offset);
//extern u8 rf_reg_write(PADAPTER Adapter, u8 path, u8 offset, u32 value);
//extern u32 get_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask);
//extern u8 set_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask, u32 value);
//extern u32 get_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask);
//extern u8 set_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask, u32 value);
extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);
extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);

7
include/rtw_mp_ioctl.h
View file

@ -29,13 +29,6 @@
#include <rtw_efuse.h>
#include <rtw_mp.h>
#if 0
#define TESTFWCMDNUMBER 1000000
#define TEST_H2CINT_WAIT_TIME 500
#define TEST_C2HINT_WAIT_TIME 500
#define HCI_TEST_SYSCFG_HWMASK 1
#define _BUSCLK_40M (4 << 2)
#endif
//------------------------------------------------------------------------------
typedef struct CFG_DBG_MSG_STRUCT {
u32 DebugLevel;

9
include/rtw_mp_phy_regdef.h
View file

@ -1063,15 +1063,6 @@
#define bWMACControl 0x1
#define bWNICControl 0x2
#if 0
#define ANTENNA_A 0x1 // Useless
#define ANTENNA_B 0x2
#define ANTENNA_AB 0x3 // ANTENNA_A|ANTENNA_B
#define ANTENNA_C 0x4
#define ANTENNA_D 0x8
#endif
#define RCR_AAP BIT(0) // accept all physical address
#define RCR_APM BIT(1) // accept physical match
#define RCR_AM BIT(2) // accept multicast

11
include/rtw_p2p.h
View file

@ -81,21 +81,14 @@ static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_S
wdinfo->p2p_state = state;
}
}
static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
{
if (wdinfo->pre_p2p_state != state) {
wdinfo->pre_p2p_state = state;
}
}
#if 0
static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)
{
if (wdinfo->pre_p2p_state != -1) {
wdinfo->p2p_state = wdinfo->pre_p2p_state;
wdinfo->pre_p2p_state = -1;
}
}
#endif
static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
{
if (wdinfo->role != role) {

62
include/rtw_xmit.h
View file

@ -234,58 +234,6 @@ struct hw_xmit {
int accnt;
};
#if 0
struct pkt_attrib
{
u8 type;
u8 subtype;
u8 bswenc;
u8 dhcp_pkt;
u16 ether_type;
int pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data)
int pkt_hdrlen; //the original 802.3 pkt header len
int hdrlen; //the WLAN Header Len
int nr_frags;
int last_txcmdsz;
int encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
u8 iv[8];
int iv_len;
u8 icv[8];
int icv_len;
int priority;
int ack_policy;
int mac_id;
int vcs_mode; //virtual carrier sense method
u8 dst[ETH_ALEN];
u8 src[ETH_ALEN];
u8 ta[ETH_ALEN];
u8 ra[ETH_ALEN];
u8 key_idx;
u8 qos_en;
u8 ht_en;
u8 raid;//rate adpative id
u8 bwmode;
u8 ch_offset;//PRIME_CHNL_OFFSET
u8 sgi;//short GI
u8 ampdu_en;//tx ampdu enable
u8 mdata;//more data bit
u8 eosp;
u8 pctrl;//per packet txdesc control enable
u8 triggered;//for ap mode handling Power Saving sta
u32 qsel;
u16 seqnum;
struct sta_info * psta;
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
u8 hw_tcp_csum;
#endif
};
#else
//reduce size
struct pkt_attrib
{
@ -334,22 +282,12 @@ struct pkt_attrib
u8 hw_tcp_csum;
#endif
};
#endif
#ifdef PLATFORM_FREEBSD
#define ETH_ALEN 6 /* Octets in one ethernet addr */
#define ETH_HLEN 14 /* Total octets in header. */
#define ETH_P_IP 0x0800 /* Internet Protocol packet */
/*struct rtw_ieee80211_hdr {
uint16_t frame_control;
uint16_t duration_id;
u8 addr1[6];
u8 addr2[6];
u8 addr3[6];
uint16_t seq_ctrl;
u8 addr4[6];
} ;*/
#endif //PLATFORM_FREEBSD
#define WLANHDR_OFFSET 64

21
include/wifi.h
View file

@ -133,8 +133,8 @@ enum WIFI_REASON_CODE {
_RSON_TDLS_TEAR_UN_RSN_ = 26,
};
/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */
#if 0
/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22)
#define WLAN_REASON_UNSPECIFIED 1
#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
#define WLAN_REASON_DEAUTH_LEAVING 3
@ -143,13 +143,12 @@ enum WIFI_REASON_CODE {
#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
#endif
#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 */
/* IEEE 802.11h */
#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10
#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11
#if 0
/* IEEE 802.11i */
/* IEEE 802.11i
#define WLAN_REASON_INVALID_IE 13
#define WLAN_REASON_MICHAEL_MIC_FAILURE 14
#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15
@ -161,8 +160,7 @@ enum WIFI_REASON_CODE {
#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21
#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
#define WLAN_REASON_CIPHER_SUITE_REJECTED 24
#endif
#define WLAN_REASON_CIPHER_SUITE_REJECTED 24 */
enum WIFI_STATUS_CODE {
_STATS_SUCCESSFUL_ = 0,
@ -178,8 +176,7 @@ enum WIFI_STATUS_CODE {
_STATS_RATE_FAIL_ = 18,
};
/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */
#if 0
/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23)
#define WLAN_STATUS_SUCCESS 0
#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
#define WLAN_STATUS_CAPS_UNSUPPORTED 10
@ -190,8 +187,8 @@ enum WIFI_STATUS_CODE {
#define WLAN_STATUS_CHALLENGE_FAIL 15
#define WLAN_STATUS_AUTH_TIMEOUT 16
#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
#define WLAN_STATUS_ASSOC_DENIED_RATES 18
#endif
#define WLAN_STATUS_ASSOC_DENIED_RATES 18 */
//entended
/* IEEE 802.11b */
#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19

7
include/wireless.h
View file

@ -23,16 +23,9 @@
/***************************** INCLUDES *****************************/
#if 0
#include <linux/types.h> /* for __u* and __s* typedefs */
#include <linux/socket.h> /* for "struct sockaddr" et al */
#include <linux/if.h> /* for IFNAMSIZ and co... */
#else
#define __user
//typedef uint16_t __u16;
#include <sys/socket.h> /* for "struct sockaddr" et al */
#include <net/if.h> /* for IFNAMSIZ and co... */
#endif
/****************************** TYPES ******************************/

72
include/wlan_bssdef.h
View file

@ -123,31 +123,6 @@ Except the IELength, all other fields are fixed length. Therefore, we can define
partial sum.
*/
#if 0
typedef struct _NDIS_WLAN_BSSID_EX
{
ULONG Length;
NDIS_802_11_MAC_ADDRESS MacAddress;
UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity;
NDIS_802_11_SSID Ssid;
ULONG Privacy;
NDIS_802_11_RSSI Rssi;
NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
NDIS_802_11_CONFIGURATION Configuration;
NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
NDIS_802_11_RATES_EX SupportedRates;
ULONG IELength;
UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information)
} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
typedef struct _NDIS_802_11_BSSID_LIST_EX
{
ULONG NumberOfItems;
NDIS_WLAN_BSSID_EX Bssid[1];
} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
#endif
typedef enum _NDIS_802_11_AUTHENTICATION_MODE
{
Ndis802_11AuthModeOpen,
@ -395,30 +370,6 @@ Except the IELength, all other fields are fixed length. Therefore, we can define
partial sum.
*/
#if 0
typedef struct _NDIS_WLAN_BSSID_EX
{
ULONG Length;
NDIS_802_11_MAC_ADDRESS MacAddress;
UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity;
NDIS_802_11_SSID Ssid;
ULONG Privacy;
NDIS_802_11_RSSI Rssi;
NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
NDIS_802_11_CONFIGURATION Configuration;
NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
NDIS_802_11_RATES_EX SupportedRates;
ULONG IELength;
UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information)
} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
typedef struct _NDIS_802_11_BSSID_LIST_EX
{
ULONG NumberOfItems;
NDIS_WLAN_BSSID_EX Bssid[1];
} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
#endif
typedef enum _NDIS_802_11_AUTHENTICATION_MODE
{
@ -624,28 +575,7 @@ WLAN_BSSID_EX, *PWLAN_BSSID_EX;
__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)
{
#if 0
uint t_len;
t_len = sizeof (ULONG)
+ sizeof (NDIS_802_11_MAC_ADDRESS)
+ 2
+ sizeof (NDIS_802_11_SSID)
+ sizeof (ULONG)
+ sizeof (NDIS_802_11_RSSI)
+ sizeof (NDIS_802_11_NETWORK_TYPE)
+ sizeof (NDIS_802_11_CONFIGURATION)
+ sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE)
+ sizeof (NDIS_802_11_RATES_EX)
//all new member add here
+ sizeof(WLAN_PHY_INFO)
//all new member add here
+ sizeof (ULONG)
+ bss->IELength;
return t_len;
#else
return (sizeof(WLAN_BSSID_EX) -MAX_IE_SZ + bss->IELength);
#endif
return sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength;
}
struct wlan_network {

124
os_dep/ioctl_cfg80211.c
View file

@ -1397,25 +1397,6 @@ static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev,
void (*callback)(void *cookie,
struct key_params*))
{
#if 0
struct iwm_priv *iwm = ndev_to_iwm(ndev);
struct iwm_key *key = &iwm->keys[key_index];
struct key_params params;
IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index);
memset(&params, 0, sizeof(params));
params.cipher = key->cipher;
params.key_len = key->key_len;
params.seq_len = key->seq_len;
params.seq = key->seq;
params.key = key->key;
callback(cookie, &params);
return key->key_len ? 0 : -ENOENT;
#endif
DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
return 0;
}
@ -2079,35 +2060,6 @@ exit:
static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)
{
#if 0
struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
(iwm->conf.rts_threshold != wiphy->rts_threshold)) {
int ret;
iwm->conf.rts_threshold = wiphy->rts_threshold;
ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
CFG_RTS_THRESHOLD,
iwm->conf.rts_threshold);
if (ret < 0)
return ret;
}
if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
(iwm->conf.frag_threshold != wiphy->frag_threshold)) {
int ret;
iwm->conf.frag_threshold = wiphy->frag_threshold;
ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX,
CFG_FRAG_THRESHOLD,
iwm->conf.frag_threshold);
if (ret < 0)
return ret;
}
#endif
DBG_8192C("%s\n", __func__);
return 0;
}
@ -2115,38 +2067,12 @@ static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)
static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
struct cfg80211_ibss_params *params)
{
#if 0
struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
struct ieee80211_channel *chan = params->channel;
if (!test_bit(IWM_STATUS_READY, &iwm->status))
return -EIO;
/* UMAC doesn't support creating or joining an IBSS network
* with specified bssid. */
if (params->bssid)
return -EOPNOTSUPP;
iwm->channel = ieee80211_frequency_to_channel(chan->center_freq);
iwm->umac_profile->ibss.band = chan->band;
iwm->umac_profile->ibss.channel = iwm->channel;
iwm->umac_profile->ssid.ssid_len = params->ssid_len;
memcpy(iwm->umac_profile->ssid.ssid, params->ssid, params->ssid_len);
return iwm_send_mlme_profile(iwm);
#endif
DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
return 0;
}
static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
{
#if 0
struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
if (iwm->umac_profile_active)
return iwm_invalidate_mlme_profile(iwm);
#endif
DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
return 0;
}
@ -2166,12 +2092,6 @@ static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32
psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
}
/*
if (wpa_version & NL80211_WPA_VERSION_2)
{
psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
}
*/
return 0;
@ -2876,40 +2796,12 @@ static int cfg80211_rtw_set_txpower(struct wiphy *wiphy,
enum tx_power_setting type, int dbm)
#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
{
#if 0
struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
int ret;
switch (type) {
case NL80211_TX_POWER_AUTOMATIC:
return 0;
case NL80211_TX_POWER_FIXED:
if (mbm < 0 || (mbm % 100))
return -EOPNOTSUPP;
if (!test_bit(IWM_STATUS_READY, &iwm->status))
return 0;
ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
CFG_TX_PWR_LIMIT_USR,
MBM_TO_DBM(mbm) * 2);
if (ret < 0)
return ret;
return iwm_tx_power_trigger(iwm);
default:
IWM_ERR(iwm, "Unsupported power type: %d\n", type);
return -EOPNOTSUPP;
}
#endif
DBG_8192C("%s\n", __func__);
return 0;
}
static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, int *dbm)
{
//_adapter *padapter = wiphy_to_adapter(wiphy);
DBG_8192C("%s\n", __func__);
*dbm = (12);
@ -4351,22 +4243,6 @@ static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, struct net
p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK);
}
#if 0
// Disable P2P Listen State
if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
{
if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
{
_cancel_timer_ex( &pwdinfo->find_phase_timer );
_cancel_timer_ex( &pwdinfo->restore_p2p_state_timer );
_cancel_timer_ex( &pwdinfo->pre_tx_scan_timer);
rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
_rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info));
}
}
else
#endif
{
rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
#ifdef CONFIG_DEBUG_CFG80211

313
os_dep/ioctl_linux.c
View file

@ -1089,21 +1089,6 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen)
goto exit;
}
#if 0
pos += RSN_HEADER_LEN;
left = ielen - RSN_HEADER_LEN;
if (left >= RSN_SELECTOR_LEN){
pos += RSN_SELECTOR_LEN;
left -= RSN_SELECTOR_LEN;
}
else if (left > 0){
RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie length mismatch, %u too much\n", left));
ret =-1;
goto exit;
}
#endif
if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS)
{
padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X;
@ -1756,29 +1741,9 @@ static int rtw_wx_set_wap(struct net_device *dev,
phead = get_list_head(queue);
pmlmepriv->pscanned = get_next(phead);
while (1)
{
while (1) {
if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE)
{
#if 0
ret = -EINVAL;
goto exit;
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
{
rtw_set_802_11_bssid(padapter, temp->sa_data);
goto exit;
}
else
{
ret = -EINVAL;
goto exit;
}
#endif
break;
}
pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
@ -1856,16 +1821,6 @@ static int rtw_wx_set_mlme(struct net_device *dev,
struct iw_request_info *info,
union iwreq_data *wrqu, char *extra)
{
#if 0
/* SIOCSIWMLME data */
struct iw_mlme
{
__u16 cmd; /* IW_MLME_* */
__u16 reason_code;
struct sockaddr addr;
};
#endif
int ret=0;
u16 reason;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
@ -2136,17 +2091,9 @@ if (padapter->registrypriv.mp_mode == 1)
//DBG_871X("WEXT_CSCAN_TYPE_SECTION\n");
pos+=1; len-=1;
break;
#if 0
case WEXT_CSCAN_NPROBE_SECTION:
DBG_871X("WEXT_CSCAN_NPROBE_SECTION\n");
break;
#endif
default:
//DBG_871X("Unknown CSCAN section %c\n", section);
len = 0; // stop parsing
}
//DBG_871X("len:%d\n", len);
}
@ -2442,24 +2389,8 @@ static int rtw_wx_set_essid(struct net_device *dev,
phead = get_list_head(queue);
pmlmepriv->pscanned = get_next(phead);
while (1)
{
if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE)
{
#if 0
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
{
rtw_set_802_11_ssid(padapter, &ndis_ssid);
goto exit;
}
else
{
RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("rtw_wx_set_ssid(): scanned_queue is empty\n"));
ret = -EINVAL;
goto exit;
}
#endif
while (1) {
if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) {
RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_warning_,
("rtw_wx_set_essid: scan_q is empty, set ssid to check if scanning again!\n"));
@ -2774,29 +2705,6 @@ static int rtw_wx_get_retry(struct net_device *dev,
}
#if 0
#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */
#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */
#define IW_ENCODE_MODE 0xF000 /* Modes defined below */
#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */
#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */
#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */
#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */
#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */
#define IW_ENCODE_TEMP 0x0400 /* Temporary key */
/*
iwconfig wlan0 key on -> flags = 0x6001 -> maybe it means auto
iwconfig wlan0 key off -> flags = 0x8800
iwconfig wlan0 key open -> flags = 0x2800
iwconfig wlan0 key open 1234567890 -> flags = 0x2000
iwconfig wlan0 key restricted -> flags = 0x4800
iwconfig wlan0 key open [3] 1234567890 -> flags = 0x2003
iwconfig wlan0 key restricted [2] 1234567890 -> flags = 0x4002
iwconfig wlan0 key open [3] -> flags = 0x2803
iwconfig wlan0 key restricted [2] -> flags = 0x4802
*/
#endif
static int rtw_wx_set_enc(struct net_device *dev,
struct iw_request_info *info,
union iwreq_data *wrqu, char *keybuf)
@ -3341,52 +3249,7 @@ static int rtw_wx_get_nick(struct net_device *dev,
//rtw_signal_process(pid, SIGUSR1); //for test
//dump debug info here
/*
u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, and 8021x
u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm.
u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key
u32 ndisauthtype;
u32 ndisencryptstatus;
*/
//DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
// psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
// psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
//DBG_871X("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm);
//DBG_871X("auth_type=0x%x\n", psecuritypriv->ndisauthtype);
//DBG_871X("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus);
#if 0
DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
DBG_871X("\n");
DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
#endif
return 0;
}
static int rtw_wx_read32(struct net_device *dev,
@ -3546,12 +3409,6 @@ static int rtw_wx_set_channel_plan(struct net_device *dev,
extern int rtw_channel_plan;
u8 channel_plan_req = (u8) (*((int *)wrqu));
#if 0
rtw_channel_plan = (int)wrqu->data.pointer;
pregistrypriv->channel_plan = rtw_channel_plan;
pmlmepriv->ChannelPlan = pregistrypriv->channel_plan;
#endif
if (_SUCCESS == rtw_set_chplan_cmd(padapter, channel_plan_req, 1)) {
DBG_871X("%s set channel_plan = 0x%02X\n", __func__, pmlmepriv->ChannelPlan);
} else
@ -3615,15 +3472,6 @@ static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info,
union iwreq_data *wrqu, char *extra)
{
#if 0
struct iw_point
{
void __user *pointer; /* Pointer to the data (in user space) */
__u16 length; /* number of fields or size in bytes */
__u16 flags; /* Optional params */
};
#endif
#ifdef CONFIG_DRVEXT_MODULE
u8 res;
struct drvext_handler *phandler;
@ -6984,17 +6832,6 @@ static int rtw_dbg_port(struct net_device *dev,
}
}
break;
#if 0
case 0x0d://dump cam
{
//u8 entry = (u8) extra_arg;
u8 entry=0;
//dump cam
for (entry=0;entry<32;entry++)
read_cam(padapter,entry);
}
break;
#endif
#ifdef DBG_CONFIG_ERROR_DETECT
case 0x0f:
{
@ -7251,26 +7088,6 @@ static int wpa_set_param(struct net_device *dev, u8 name, u32 value)
* be set.
*/
#if 0
struct ieee80211_security sec = {
.flags = SEC_ENABLED,
.enabled = value,
};
ieee->drop_unencrypted = value;
/* We only change SEC_LEVEL for open mode. Others
* are set by ipw_wpa_set_encryption.
*/
if (!value) {
sec.flags |= SEC_LEVEL;
sec.level = SEC_LEVEL_0;
}
else {
sec.flags |= SEC_LEVEL;
sec.level = SEC_LEVEL_1;
}
if (ieee->set_security)
ieee->set_security(ieee->dev, &sec);
#endif
break;
}
@ -8089,23 +7906,6 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par
psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr);
if (psta)
{
#if 0
struct {
u16 aid;
u16 capability;
int flags;
u32 sta_set;
u8 tx_supp_rates[16];
u32 tx_supp_rates_len;
struct rtw_ieee80211_ht_cap ht_cap;
u64 rx_pkts;
u64 rx_bytes;
u64 rx_drops;
u64 tx_pkts;
u64 tx_bytes;
u64 tx_drops;
} get_sta;
#endif
psta_data->aid = (u16)psta->aid;
psta_data->capability = psta->capability;
psta_data->flags = psta->flags;
@ -12008,10 +11808,6 @@ static s32 createpseudoadhoc(PADAPTER padapter)
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
_exit_critical_bh(&pmlmepriv->lock, &irqL);
#if 0
err = rtw_createbss_cmd(padapter);
if (err == _FAIL) return _FAIL;
#else
{
struct wlan_network *pcur_network;
struct sta_info *psta;
@ -12032,9 +11828,6 @@ static s32 createpseudoadhoc(PADAPTER padapter)
_rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network));
// set msr to WIFI_FW_ADHOC_STATE
#if 0
Set_NETYPE0_MSR(padapter, WIFI_FW_ADHOC_STATE);
#else
{
u8 val8;
@ -12043,9 +11836,7 @@ static s32 createpseudoadhoc(PADAPTER padapter)
val8 |= WIFI_FW_ADHOC_STATE & 0x3;
rtw_write8(padapter, MSR, val8);
}
#endif
}
#endif
return _SUCCESS;
}
@ -12512,33 +12303,6 @@ static int rtw_test(
#endif
#ifdef CONFIG_RTL8723A
#if 0
if (strcmp(pch, "poweron") == 0)
{
s32 ret;
ret = _InitPowerOn(padapter);
DBG_871X("%s: power on %s\n", __func__, (_FAIL==ret) ? "FAIL!":"OK.");
sprintf(extra, "Power ON %s", (_FAIL==ret) ? "FAIL!":"OK.");
wrqu->data.length = strlen(extra) + 1;
rtw_mfree(pbuf, len);
return 0;
}
if (strcmp(pch, "dlfw") == 0)
{
s32 ret;
ret = rtl8723a_FirmwareDownload(padapter);
DBG_871X("%s: download FW %s\n", __func__, (_FAIL==ret) ? "FAIL!":"OK.");
sprintf(extra, "download FW %s", (_FAIL==ret) ? "FAIL!":"OK.");
wrqu->data.length = strlen(extra) + 1;
rtw_mfree(pbuf, len);
return 0;
}
#endif
#ifdef CONFIG_BT_COEXIST
#define GET_BT_INFO(padapter) (&GET_HAL_DATA(padapter)->BtInfo)
@ -12684,71 +12448,6 @@ static iw_handler rtw_handlers[] =
NULL, /*---hole---*/
};
#if 0
//defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT)
static const struct iw_priv_args rtw_private_args[] =
{
{ SIOCIWFIRSTPRIV + 0x00, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, //set
{ SIOCIWFIRSTPRIV + 0x01, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},//get
/* --- sub-ioctls definitions --- */
{ MP_START , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_start" }, //set
{ MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },//get
{ MP_STOP , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_stop" }, //set
{ MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },//get
{ MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_bandwidth"}, //set
{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },//get
{ MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_reset_stats"},
{ MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, //get
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" },
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" },
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"},
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" },
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"},
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"},
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"},
{ WRITE_REG, IW_PRIV_TYPE_CHAR | 1024, 0,"write_reg"},//set
{ MP_NULL, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL" },
{ WRITE_RF, IW_PRIV_TYPE_CHAR | 1024, 0,"write_rf"},//set
{ MP_NULL, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL" },
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"},
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"},
{ MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set
{ MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"},
{ EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set" },
{ EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" },
{ MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_pwrtrk"},
{ MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" },
{ MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, // mp_ioctl
{ MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_setrfpath" },
#ifdef CONFIG_RTL8723A
{ MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" },
#endif
{ SIOCIWFIRSTPRIV + 0x02, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "test"},//set
};
static iw_handler rtw_private_handler[] =
{
rtw_mp_set,
rtw_mp_get,
};
#else // not inlucde MP
static const struct iw_priv_args rtw_private_args[] = {
{
SIOCIWFIRSTPRIV + 0x0,
@ -12809,11 +12508,6 @@ static const struct iw_priv_args rtw_private_args[] = {
SIOCIWFIRSTPRIV + 0xD,
IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr"
},
#if 0
{
SIOCIWFIRSTPRIV + 0xE,0,0, "wowlan_ctrl"
},
#endif
{
SIOCIWFIRSTPRIV + 0x10,
IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, 0, "p2p_set"
@ -12897,7 +12591,6 @@ static const struct iw_priv_args rtw_private_args[] = {
{ MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" },
#endif
{ CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"},
#endif
};
static iw_handler rtw_private_handler[] =

33
os_dep/osdep_service.c
View file

@ -547,22 +547,7 @@ int _rtw_memcmp(void *dst, void *src, u32 sz)
void _rtw_memset(void *pbuf, int c, u32 sz)
{
#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD)
memset(pbuf, c, sz);
#endif
#ifdef PLATFORM_WINDOWS
#if 0
NdisZeroMemory(pbuf, sz);
if (c != 0) memset(pbuf, c, sz);
#else
NdisFillMemory(pbuf, sz, c);
#endif
#endif
}
#ifdef PLATFORM_FREEBSD
@ -1181,14 +1166,6 @@ void rtw_usleep_os(int us)
#ifdef DBG_DELAY_OS
void _rtw_mdelay_os(int ms, const char *func, const int line)
{
#if 0
if (ms>10)
DBG_871X("%s:%d %s(%d)\n", func, line, __func__, ms);
rtw_msleep_os(ms);
return;
#endif
DBG_871X("%s:%d %s(%d)\n", func, line, __func__, ms);
#if defined(PLATFORM_LINUX)
@ -1205,16 +1182,6 @@ void _rtw_mdelay_os(int ms, const char *func, const int line)
}
void _rtw_udelay_os(int us, const char *func, const int line)
{
#if 0
if (us > 1000) {
DBG_871X("%s:%d %s(%d)\n", func, line, __func__, us);
rtw_usleep_os(us);
return;
}
#endif
DBG_871X("%s:%d %s(%d)\n", func, line, __func__, us);

20
os_dep/rtw_android.c
View file

@ -440,44 +440,24 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
/* TBD: BTCOEXSCAN-STOP */
break;
case ANDROID_WIFI_CMD_BTCOEXMODE:
#if 0
uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
if (mode == 1)
net_os_set_packet_filter(net, 0); /* DHCP starts */
else
net_os_set_packet_filter(net, 1); /* DHCP ends */
#ifdef WL_CFG80211
bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command);
#endif
#endif
break;
case ANDROID_WIFI_CMD_SETSUSPENDOPT:
//bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len);
break;
case ANDROID_WIFI_CMD_SETBAND:
//uint band = *(command + strlen(CMD_SETBAND) + 1) - '0';
//bytes_written = wldev_set_band(net, band);
break;
case ANDROID_WIFI_CMD_GETBAND:
//bytes_written = wl_android_get_band(net, command, priv_cmd.total_len);
break;
case ANDROID_WIFI_CMD_COUNTRY:
bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);
break;
#ifdef PNO_SUPPORT
case ANDROID_WIFI_CMD_PNOSSIDCLR_SET:
//bytes_written = dhd_dev_pno_reset(net);
break;
case ANDROID_WIFI_CMD_PNOSETUP_SET:
//bytes_written = wl_android_set_pno_setup(net, command, priv_cmd.total_len);
break;
case ANDROID_WIFI_CMD_PNOENABLE_SET:
//uint pfn_enabled = *(command + strlen(CMD_PNOENABLE_SET) + 1) - '0';
//bytes_written = dhd_dev_pno_enable(net, pfn_enabled);
break;
#endif

56
os_dep/usb_intf.c
View file

@ -513,68 +513,18 @@ _func_enter_;
pdvobjpriv->RtNumInPipes = 0;
pdvobjpriv->RtNumOutPipes = 0;
//padapter->EepromAddressSize = 6;
//pdvobjpriv->nr_endpoint = 6;
pdev_desc = &pusbd->descriptor;
#if 0
DBG_871X("\n8712_usb_device_descriptor:\n");
DBG_871X("bLength=%x\n", pdev_desc->bLength);
DBG_871X("bDescriptorType=%x\n", pdev_desc->bDescriptorType);
DBG_871X("bcdUSB=%x\n", pdev_desc->bcdUSB);
DBG_871X("bDeviceClass=%x\n", pdev_desc->bDeviceClass);
DBG_871X("bDeviceSubClass=%x\n", pdev_desc->bDeviceSubClass);
DBG_871X("bDeviceProtocol=%x\n", pdev_desc->bDeviceProtocol);
DBG_871X("bMaxPacketSize0=%x\n", pdev_desc->bMaxPacketSize0);
DBG_871X("idVendor=%x\n", pdev_desc->idVendor);
DBG_871X("idProduct=%x\n", pdev_desc->idProduct);
DBG_871X("bcdDevice=%x\n", pdev_desc->bcdDevice);
DBG_871X("iManufacturer=%x\n", pdev_desc->iManufacturer);
DBG_871X("iProduct=%x\n", pdev_desc->iProduct);
DBG_871X("iSerialNumber=%x\n", pdev_desc->iSerialNumber);
DBG_871X("bNumConfigurations=%x\n", pdev_desc->bNumConfigurations);
#endif
phost_conf = pusbd->actconfig;
pconf_desc = &phost_conf->desc;
#if 0
DBG_871X("\n8712_usb_configuration_descriptor:\n");
DBG_871X("bLength=%x\n", pconf_desc->bLength);
DBG_871X("bDescriptorType=%x\n", pconf_desc->bDescriptorType);
DBG_871X("wTotalLength=%x\n", pconf_desc->wTotalLength);
DBG_871X("bNumInterfaces=%x\n", pconf_desc->bNumInterfaces);
DBG_871X("bConfigurationValue=%x\n", pconf_desc->bConfigurationValue);
DBG_871X("iConfiguration=%x\n", pconf_desc->iConfiguration);
DBG_871X("bmAttributes=%x\n", pconf_desc->bmAttributes);
DBG_871X("bMaxPower=%x\n", pconf_desc->bMaxPower);
#endif
//DBG_871X("\n/****** num of altsetting = (%d) ******/\n", pusb_interface->num_altsetting);
phost_iface = &usb_intf->altsetting[0];
piface_desc = &phost_iface->desc;
#if 0
DBG_871X("\n8712_usb_interface_descriptor:\n");
DBG_871X("bLength=%x\n", piface_desc->bLength);
DBG_871X("bDescriptorType=%x\n", piface_desc->bDescriptorType);
DBG_871X("bInterfaceNumber=%x\n", piface_desc->bInterfaceNumber);
DBG_871X("bAlternateSetting=%x\n", piface_desc->bAlternateSetting);
DBG_871X("bNumEndpoints=%x\n", piface_desc->bNumEndpoints);
DBG_871X("bInterfaceClass=%x\n", piface_desc->bInterfaceClass);
DBG_871X("bInterfaceSubClass=%x\n", piface_desc->bInterfaceSubClass);
DBG_871X("bInterfaceProtocol=%x\n", piface_desc->bInterfaceProtocol);
DBG_871X("iInterface=%x\n", piface_desc->iInterface);
#endif
pdvobjpriv->NumInterfaces = pconf_desc->bNumInterfaces;
pdvobjpriv->InterfaceNumber = piface_desc->bInterfaceNumber;
pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints;
//DBG_871X("\ndump usb_endpoint_descriptor:\n");
for (i = 0; i < pdvobjpriv->nr_endpoint; i++)
{
phost_endp = phost_iface->endpoint + i;
@ -586,14 +536,10 @@ _func_enter_;
DBG_871X("bLength=%x\n",pendp_desc->bLength);
DBG_871X("bDescriptorType=%x\n",pendp_desc->bDescriptorType);
DBG_871X("bEndpointAddress=%x\n",pendp_desc->bEndpointAddress);
//DBG_871X("bmAttributes=%x\n",pendp_desc->bmAttributes);
DBG_871X("wMaxPacketSize=%d\n",le16_to_cpu(pendp_desc->wMaxPacketSize));
DBG_871X("bInterval=%x\n",pendp_desc->bInterval);
//DBG_871X("bRefresh=%x\n",pendp_desc->bRefresh);
//DBG_871X("bSynchAddress=%x\n",pendp_desc->bSynchAddress);
if (RT_usb_endpoint_is_bulk_in(pendp_desc))
{
if (RT_usb_endpoint_is_bulk_in(pendp_desc)) {
DBG_871X("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(pendp_desc));
pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc);
pdvobjpriv->RtNumInPipes++;

27
os_dep/usb_ops_linux.c
View file

@ -515,25 +515,6 @@ _func_enter_;
purb = pxmitbuf->pxmit_urb[0];
#if 0
if (pdvobj->ishighspeed)
{
if (cnt> 0 && cnt%512 == 0)
{
//DBG_8192C("ishighspeed, cnt=%d\n", cnt);
bwritezero = _TRUE;
}
}
else
{
if (cnt > 0 && cnt%64 == 0)
{
//DBG_8192C("cnt=%d\n", cnt);
bwritezero = _TRUE;
}
}
#endif
//translate DMA FIFO addr to pipehandle
pipe = ffaddr2pipehdl(pdvobj, addr);
@ -544,7 +525,6 @@ _func_enter_;
purb->transfer_flags &= (~URB_NO_INTERRUPT);
} else {
purb->transfer_flags |= URB_NO_INTERRUPT;
//DBG_8192C("URB_NO_INTERRUPT ");
}
#endif
@ -561,13 +541,6 @@ _func_enter_;
purb->transfer_flags |= URB_ZERO_PACKET;
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
#if 0
if (bwritezero)
{
purb->transfer_flags |= URB_ZERO_PACKET;
}
#endif
status = usb_submit_urb(purb, GFP_ATOMIC);
if (!status) {
#ifdef DBG_CONFIG_ERROR_DETECT