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rtl8188eu: Remove dead code inside #if 0 ... #endif

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-05-18 16:16:10 -05:00
parent 3ad757d04a
commit 77e736c66a
64 changed files with 98 additions and 7692 deletions
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16
hal/Hal8188ERateAdaptive.c
View file

@ -61,16 +61,6 @@ static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate
static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
#if 0
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SS<TH
4,4,5,5,6,0x0a,0x11,0x13,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
@ -124,12 +114,6 @@ static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
2,2,3,3,4,4,5,7,
4,4,7,10,10,12,12,18,
5,7,7,8,11,18,36,60}; // 0329 // 1207
#if 0
static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30,
30,30,25,25,20,15,15,10,
30,25,25,20,15,10,10,10,
30,25,25,20,15,10,10,10};
#endif
static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
1,2,3,4,5,6,7,8,

6
hal/HalPhyRf.c
View file

@ -799,12 +799,6 @@ phy_APCalibrate_8192C(
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
};
#if 0
u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
{0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
{0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
};
#endif
u4Byte AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on

120
hal/HalPhyRf_8188e.c
View file

@ -512,25 +512,9 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
#if 0
//wirte new elements A, C, D to regC80 and regC94, element B is always 0
value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
value32 = (ele_C&0x000003C0)>>6;
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
value32 = ((X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
#endif
}
else
{
#if 0
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[0]]);
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking for path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xe94 = 0x%x 0xe9c = 0x%x\n",
@ -541,29 +525,6 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
#if 0
//Adjust CCK according to IQK result
if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14){
ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][0]);
ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][1]);
ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][2]);
ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][3]);
ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][4]);
ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][5]);
ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][6]);
ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][7]);
}
else{
ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14[(u1Byte)CCK_index][0]);
ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14[(u1Byte)CCK_index][1]);
ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14[(u1Byte)CCK_index][2]);
ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14[(u1Byte)CCK_index][3]);
ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14[(u1Byte)CCK_index][4]);
ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14[(u1Byte)CCK_index][5]);
ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14[(u1Byte)CCK_index][6]);
ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14[(u1Byte)CCK_index][7]);
}
#endif
}
if (is2T)
@ -575,9 +536,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
Y = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][5];
//if (X != 0 && pHalData->CurrentBandType92D == ODM_BAND_ON_2_4G)
if ((X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
{
if ((X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) {
if ((X & 0x00000200) != 0) //consider minus
X = X | 0xFFFFFC00;
ele_A = ((X * ele_D)>>8)&0x000003FF;
@ -587,7 +546,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
Y = Y | 0xFFFFFC00;
ele_C = ((Y * ele_D)>>8)&0x00003FF;
//wirte new elements A, C, D to regC88 and regC9C, element B is always 0
//wtite new elements A, C, D to regC88 and regC9C, element B is always 0
value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
@ -597,9 +556,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
value32 = ((X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
}
else
{
} else {
ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[1]]);
ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);
@ -731,20 +688,8 @@ phy_PathA_IQK_8188E(
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
#if 0
if (!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
else
RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
#endif
return result;
}
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK(
@ -877,15 +822,6 @@ phy_PathA_RxIQK(
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );
#if 0
if (!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
#endif
if (!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
@ -1690,15 +1626,6 @@ else
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
break;
}
#if 0
else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
{
RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
}
#endif
}
for (i = 0 ; i < retryCount ; i++){
@ -1709,14 +1636,10 @@ else
#endif
if (PathAOK == 0x03){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
break;
}
else
{
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
}
}
@ -2504,22 +2427,7 @@ if (*(pDM_Odm->mp_mode) == 1)
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
#if 0//Suggested by Edlu,120413
// IQK on channel 7, should switch back when completed.
//originChannel = pHalData->CurrentChannel;
originChannel = *(pDM_Odm->pChannel);
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK);
#endif
#endif
for (i = 0; i < 8; i++)
{
for (i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
result[2][i] = 0;
@ -2535,11 +2443,7 @@ if (*(pDM_Odm->mp_mode) == 1)
is23simular = FALSE;
is13simular = FALSE;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter)));
// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));
for (i=0; i<3; i++)
{
for (i=0; i<3; i++) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
phy_IQCalibrate_8188E(pAdapter, result, i, is2T);
@ -2682,16 +2586,6 @@ if (*(pDM_Odm->mp_mode) == 1)
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
#if 0 //Suggested by Edlu,120413
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel);
#endif
#endif
}

424
hal/odm.c
View file

@ -717,42 +717,6 @@ odm_HwAntDiv(
IN PDM_ODM_T pDM_Odm
);
#if 0
//#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&defined(HW_ANT_SWITCH))
VOID
odm_HW_AntennaSwitchInit(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_SetRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
odm_StaAntSelect(
IN PDM_ODM_T pDM_Odm,
IN struct stat_info *pstat
);
VOID
odm_HW_IdleAntennaSelect(
IN PDM_ODM_T pDM_Odm
);
u1Byte
ODM_Diversity_AntennaSelect(
IN PDM_ODM_T pDM_Odm,
IN u1Byte *data
);
#endif
//============================================================
//3 Export Interface
//============================================================
@ -1726,12 +1690,6 @@ odm_DIGbyRSSI_LPS(
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
#if 0 //and 2.3.5 coding rule
struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
#endif
u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
u1Byte bFwCurrentInPSMode = FALSE;
u1Byte CurrentIGI=pDM_Odm->RSSI_Min;
@ -1895,16 +1853,6 @@ odm_DIG(
//if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
{
#if 0
if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1))
CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30;
else
CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20;
ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
return;
}
@ -3023,26 +2971,6 @@ odm_RefreshRateAdaptiveMaskMP(
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
{
#if 0 //By YJ,120208
if ( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated)
{
pEntry = pTargetAdapter->MgntInfo.AsocEntry+i;
pEntryRA = &pEntry->RateAdaptive;
if ( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) )
{
ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState));
pAdapter->HalFunc.UpdateHalRAMaskHandler(
pTargetAdapter,
FALSE,
pEntry->AID+1,
pEntry->MacAddr,
pEntry,
pEntryRA->RATRState,
RAMask_Normal);
}
}
#else
pEntry = AsocEntry_EnumStation(pTargetAdapter, i);
if (NULL != pEntry)
{
@ -3064,7 +2992,6 @@ odm_RefreshRateAdaptiveMaskMP(
}
}
}
#endif
}
}
@ -3638,22 +3565,7 @@ odm_DynamicTxPower_92C(
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
else // associated entry pwdb
{
@ -3895,22 +3807,7 @@ odm_DynamicTxPower_92D(
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
else // associated entry pwdb
{
@ -4170,43 +4067,6 @@ FindMinimumRSSI_Dmsp(
IN PADAPTER pAdapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
s32 Rssi_val_min_back_for_mac0;
BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter);
BOOLEAN bRestoreRssi = _FALSE;
PADAPTER BuddyAdapter = pAdapter->BuddyAdapter;
if (pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
if (BuddyAdapter!= NULL)
{
if (pHalData->bSlaveOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n"));
BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM;
}
else
{
if (bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n"));
bRestoreRssi = _TRUE;
Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM;
pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP;
}
}
}
}
if (bRestoreRssi)
{
bRestoreRssi = _FALSE;
pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0;
}
#endif
}
static void
@ -4241,21 +4101,6 @@ IN PADAPTER pAdapter
pdmpriv->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB;
}
#if 0
if ((pdmpriv->UndecoratedSmoothedPWDB != (-1)) &&
(pbuddy_dmpriv->UndecoratedSmoothedPWDB != (-1)))
{
if ((pdmpriv->UndecoratedSmoothedPWDB > pbuddy_dmpriv->UndecoratedSmoothedPWDB) &&
(pbuddy_dmpriv->UndecoratedSmoothedPWDB!=0))
pdmpriv->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB;
}
else
{
if ((pdmpriv->UndecoratedSmoothedPWDB == (-1)) && (pbuddy_dmpriv->UndecoratedSmoothedPWDB!=0))
pdmpriv->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB;
}
#endif
}
#endif
@ -4267,22 +4112,7 @@ IN PADAPTER pAdapter
}
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("AP Client PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM));
}
else//for STA mode
{
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM));
}
#else
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
@ -4292,8 +4122,6 @@ IN PADAPTER pAdapter
#if (RTL8192D_SUPPORT==1)
FindMinimumRSSI_Dmsp(pAdapter);
#endif
//DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__func__,pdmpriv->MinUndecoratedPWDBForDM);
//ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));
}
#endif
@ -4340,12 +4168,6 @@ odm_RSSIMonitorCheckCE(
if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
#if 0
DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__,
psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB);
#endif
if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
#if (RTL8192D_SUPPORT==1)
PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
@ -4446,25 +4268,6 @@ odm_RSSIMonitorCheckCE(
pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
}
#if 0
if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
{
if (pHalData->fw_ractrl == _TRUE)
{
u32 param = (u32)(pdmpriv->UndecoratedSmoothedPWDB<<16);
printk("%s==> rssi(%d)\n",__func__,pdmpriv->UndecoratedSmoothedPWDB);
param |= 0;//macid=0 for sta mode;
rtl8192c_set_rssi_cmd(Adapter, (u8*)&param);
}
else
{
rtw_write8(Adapter, 0x4fe, (u8)pdmpriv->UndecoratedSmoothedPWDB);
//DBG_8192C("0x4fe write %x %d\n", pdmpriv->UndecoratedSmoothedPWDB, pdmpriv->UndecoratedSmoothedPWDB);
}
}
#endif
FindMinimumRSSI(Adapter);
ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE)
@ -6348,109 +6151,6 @@ odm_HwAntDiv(
#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
#if 0
VOID
odm_HwAntDiv(
IN PDM_ODM_T pDM_Odm
)
{
struct rtl8192cd_priv *priv=pDM_Odm->priv;
struct stat_info *pstat, *pstat_min=NULL;
struct list_head *phead, *plist;
int rssi_min= 0xff, i;
u1Byte idleAnt=priv->pshare->rf_ft_var.CurAntenna;
u1Byte nextAnt;
BOOLEAN bRet=FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
if ((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
return;
//if test, return
if (priv->pshare->rf_ft_var.CurAntenna & 0x80)
return;
phead = &priv->asoc_list;
plist = phead->next;
////=========================
//find mimum rssi sta
////=========================
while (plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if ((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) {
int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1];
if ((!pstat_min) || ( rssi < rssi_min) ) {
pstat_min = pstat;
rssi_min = rssi;
}
}
///STA: found out default antenna
bRet=odm_StaDefAntSel(pDM_Odm,
pstat->hwRxAntSel[1],
pstat->hwRxAntSel[0],
pstat->cckPktCount[1],
pstat->cckPktCount[0],
&nextAnt
);
//if default antenna selection: successful
if (bRet){
pstat->CurAntenna = nextAnt;
//update rssi
for (i=0; i<2; i++) {
if (pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0)
pstat->AntRSSI[i] = 0;
}
if (pstat->AntRSSI[idleAnt]==0)
pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1];
// reset variables
pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0;
pstat->cckPktCount[1]= pstat->cckPktCount[0] =0;
}
if (plist == plist->next)
break;
plist = plist->next;
};
////=========================
//Choose RX Idle antenna according to minmum rssi
////=========================
if (pstat_min) {
if (priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna)
odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE);
priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna;
}
#ifdef TX_SHORTCUT
if (!priv->pmib->dot11OperationEntry.disable_txsc) {
plist = phead->next;
while (plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if (pstat->expire_to) {
for (i=0; i<TX_SC_ENTRY_NUM; i++) {
struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
if ((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
if ((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
}
}
if (plist == plist->next)
break;
plist = plist->next;
};
}
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n");
}
#endif
u1Byte
ODM_Diversity_AntennaSelect(
@ -6725,12 +6425,6 @@ odm_EdcaTurboCheckCE(
if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
{
#if 0
//adjust EDCA parameter for BE queue
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
#else
if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
{
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
@ -6739,7 +6433,6 @@ odm_EdcaTurboCheckCE(
{
edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
}
#endif
#ifdef CONFIG_PCI_HCI
if (IS_92C_SERIAL(pHalData->VersionID))
@ -7663,20 +7356,6 @@ odm_IotEngine(
if ((GET_ROOT(priv)->up_time % 2) == 0)
priv->pshare->highTP_found_pstat==NULL;
#if 0
phead = &priv->asoc_list;
plist = phead->next;
while (plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if (ODM_ChooseIotMainSTA(pDM_Odm, pstat)); //find the correct station
break;
if (plist == plist->next) //the last plist
break;
plist = plist->next;
};
#endif
//find highTP STA
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
pstat = pDM_Odm->pODM_StaInfo[i];
@ -7871,25 +7550,6 @@ odm_IotEngine(
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
#if 0
if (priv->pshare->txop_enlarge != 2)
{
#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
#else
if (pstat->is_intel_sta)
#endif
priv->pshare->txop_enlarge = 0xe;
#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
priv->pshare->txop_enlarge = 0xd;
#endif
else
priv->pshare->txop_enlarge = 2;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
}
else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
@ -8580,43 +8240,8 @@ odm_PSD_Monitor(
for (i = 0; i < 80; i++)
PSD_report[i] = 0;
}
#if 0 //for test only
DbgPrint("cosa odm_PSD_Monitor call()\n");
DbgPrint("cosa pHalData->RSSI_BT = %d\n", pHalData->RSSI_BT);
DbgPrint("cosa pHalData->bUserAssignLevel = %d\n", pHalData->bUserAssignLevel);
#if 0
psd_cnt++;
if (psd_cnt < ReScan)
PlatformSetTimer( Adapter, &pHalData->PSDTimer, Interval); //ms
else
psd_cnt = 0;
return;
#endif
#endif
//1 Backup Current Settings
CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
/*
if (pDM_Odm->SupportICType==ODM_RTL8192D)
{
//2 Record Current synthesizer parameters based on current channel
if ((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))
{
SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord);
SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord);
SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord);
SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord);
SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord);
}
else // DualMAC_DualPHY 2G
{
SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord);
SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord);
SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord);
SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord);
SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord);
}
}
*/
//RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
@ -8628,15 +8253,12 @@ odm_PSD_Monitor(
ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
//1 Turn off CCK
//PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
//1 Turn off TX
//Pause TX Queue
//PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);
ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);
//Force RX to stop TX immediately
//PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
//1 Turn off RX
@ -8649,16 +8271,11 @@ odm_PSD_Monitor(
//Turn off CCA
//PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
//BB Reset
//BBReset = PlatformEFIORead1Byte(Adapter, 0x02);
BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
//PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));
//PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);
ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));
ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);
@ -10509,17 +10126,6 @@ ODM_PathDiversityBeforeLink92C(
pDM_PDTable->OFDMTXPath = 0x0;
pDM_PDTable->CCKTXPath = 0x0;
}
#if 0
pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
RT_TRACE(COMP_SWAS, DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
#endif
// Go back to scan function again.
RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
@ -11687,12 +11293,6 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
u8 sign;
u8 resp_txagc=0;
#if 0
/* As DIG is disabled, DTC is also disable */
if (!(pDM_Odm->SupportAbility & ODM_XXXXXX))
return;
#endif
if (DTC_BASE < pDM_Odm->RSSI_Min) {
/* need to decade the CTS TX power */
sign = 1;
@ -11703,24 +11303,7 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
else
dtc_steps++;
}
}
#if 0
else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min)
{
/* needs to increase the CTS TX power */
sign = 0;
dtc_steps = 1;
for (i=0;i<ARRAY_SIZE(dtc_table_up);i++)
{
if ((dtc_table_up[i] <= pDM_Odm->RSSI_Min) || (dtc_steps>=10))
break;
else
dtc_steps++;
}
}
#endif
else
{
} else {
sign = 0;
dtc_steps = 0;
}
@ -11735,4 +11318,3 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
}
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */

79
hal/odm_HWConfig.c
View file

@ -84,35 +84,35 @@ odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
{
RetSig = 100;
}
else if (CurrSig>=42 && CurrSig <= 53 )
else if (CurrSig>=42 && CurrSig <= 53)
{
RetSig = 95;
}
else if (CurrSig>=36 && CurrSig <= 41 )
else if (CurrSig>=36 && CurrSig <= 41)
{
RetSig = 74 + ((CurrSig - 36) *20)/6;
}
else if (CurrSig>=33 && CurrSig <= 35 )
else if (CurrSig>=33 && CurrSig <= 35)
{
RetSig = 65 + ((CurrSig - 33) *8)/2;
}
else if (CurrSig>=18 && CurrSig <= 32 )
else if (CurrSig>=18 && CurrSig <= 32)
{
RetSig = 62 + ((CurrSig - 18) *2)/15;
}
else if (CurrSig>=15 && CurrSig <= 17 )
else if (CurrSig>=15 && CurrSig <= 17)
{
RetSig = 33 + ((CurrSig - 15) *28)/2;
}
else if (CurrSig>=10 && CurrSig <= 14 )
else if (CurrSig>=10 && CurrSig <= 14)
{
RetSig = 39;
}
else if (CurrSig>=8 && CurrSig <= 9 )
else if (CurrSig>=8 && CurrSig <= 9)
{
RetSig = 33;
}
else if (CurrSig <= 8 )
else if (CurrSig <= 8)
{
RetSig = 19;
}
@ -237,7 +237,7 @@ odm_SignalScaleMapping_92CSeries(
#endif
#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE))
if ((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) )
if ((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO))
{
if (CurrSig >= 51 && CurrSig <= 100)
{
@ -349,7 +349,7 @@ static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
static u1Byte
odm_EVMdbToPercentage(
IN s1Byte Value
)
)
{
//
// -33dB~0dB to 0%~99%
@ -397,7 +397,7 @@ odm_RxPhyStatus92CSeries_Parsing(
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M))?TRUE :FALSE;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
@ -481,7 +481,7 @@ odm_RxPhyStatus92CSeries_Parsing(
{
if (!cck_highpwr)
{
report =( cck_agc_rpt & 0xc0 )>>6;
report =(cck_agc_rpt & 0xc0)>>6;
switch (report)
{
// 03312009 modified by cosa
@ -654,7 +654,7 @@ odm_RxPhyStatus92CSeries_Parsing(
//
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110;
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1)& 0x7f) -110;
//RTPRINT(FRX, RX_PHY_SS, ("PWDB_ALL=%d\n", PWDB_ALL));
PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
@ -685,7 +685,7 @@ odm_RxPhyStatus92CSeries_Parsing(
// Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment
// fill most significant bit to "zero" when doing shifting operation which may change a negative
// value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.
EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm
EVM = odm_EVMdbToPercentage((pPhyStaRpt->stream_rxevm[i])); //dbm
//RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",
//GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM));
@ -772,15 +772,15 @@ odm_Process_RSSIForDM(
}
pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID];
if (!IS_STA_VALID(pEntry) ){
if (!IS_STA_VALID(pEntry)){
return;
}
if ((!pPktinfo->bPacketMatchBSSID) )
if ((!pPktinfo->bPacketMatchBSSID))
{
return;
}
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?TRUE :FALSE;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M))?TRUE :FALSE;
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))
@ -884,14 +884,14 @@ odm_Process_RSSIForDM(
if (pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM)
{
UndecoratedSmoothedOFDM =
( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(RSSI_Ave)) /(Rx_Smooth_Factor);
UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1;
}
else
{
UndecoratedSmoothedOFDM =
( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
(RSSI_Ave)) /(Rx_Smooth_Factor);
}
}
@ -913,14 +913,14 @@ odm_Process_RSSIForDM(
if (pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK)
{
UndecoratedSmoothedCCK =
( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor);
UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1;
}
else
{
UndecoratedSmoothedCCK =
( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
(pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor);
}
}
@ -983,29 +983,11 @@ ODM_PhyStatusQuery_92CSeries(
pPhyStatus,
pPktinfo);
if ( pDM_Odm->RSSI_test == TRUE)
{
if (pDM_Odm->RSSI_test == TRUE) {
// Select the packets to do RSSI checking for antenna switching.
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon )
{
/*
#if 0//(DM_ODM_SUPPORT_TYPE == ODM_MP)
dm_SWAW_RSSI_Check(
Adapter,
(tmppAdapter!=NULL)?(tmppAdapter==Adapter):TRUE,
bPacketMatchBSSID,
pEntry,
pRfd);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
// Select the packets to do RSSI checking for antenna switching.
//odm_SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll);
#endif
*/
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo);
}
}
else
{
} else {
odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo);
}
@ -1036,16 +1018,7 @@ ODM_PhyStatusQuery(
IN PODM_PACKET_INFO_T pPktinfo
)
{
#if 0 // How to jaguar jugar series??
if (pDM_Odm->SupportICType >= ODM_RTL8195 )
{
ODM_PhyStatusQuery_JaguarSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
else
#endif
{
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
// For future use.
@ -1070,7 +1043,7 @@ ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
)
)
{
//RT_STATUS rtStatus = RT_STATUS_SUCCESS;

61
hal/odm_RTL8188E.c
View file

@ -531,46 +531,6 @@ odm_SetNextMACAddrTarget(
}
#if 0
//
//2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn
//
#if ( DM_ODM_SUPPORT_TYPE & ODM_MP)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
for (i=0; i<6; i++)
{
Bssid[i] = pMgntInfo->Bssid[i];
//DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);
}
}
#endif
//odm_SetNextMACAddrTarget(pDM_Odm);
//1 Select MAC Address Filter
for (i=0; i<6; i++)
{
if (Bssid[i] != pDM_FatTable->Bssid[i])
{
bMatchBSSID = FALSE;
break;
}
}
if (bMatchBSSID == FALSE)
{
//Match MAC ADDR
value32 = (Bssid[5]<<8)|Bssid[4];
ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];
ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
}
return bMatchBSSID;
#endif
}
VOID
@ -629,20 +589,9 @@ odm_FastAntTraining(
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
#if 0
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if (IS_STA_VALID(pEntry))
{
pEntry->antsel_a = TargetAnt&BIT0;
pEntry->antsel_b = (TargetAnt&BIT1)>>1;
pEntry->antsel_c = (TargetAnt&BIT2)>>2;
}
#else
pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;
pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;
pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;
#endif
if (TargetAnt == 0)
@ -668,16 +617,6 @@ odm_FastAntTraining(
odm_SetNextMACAddrTarget(pDM_Odm);
#if 0
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if (IS_STA_VALID(pEntry))
{
pEntry->antsel_a = TargetAnt&BIT0;
pEntry->antsel_b = (TargetAnt&BIT1)>>1;
pEntry->antsel_c = (TargetAnt&BIT2)>>2;
}
#endif
//2 Prepare Training
pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training

6
hal/rtl8188e_cmd.c
View file

@ -218,11 +218,7 @@ u8 rtl8188e_set_rssi_cmd(_adapter*padapter, u8 *param)
_func_enter_;
if (pHalData->fw_ractrl == _TRUE){
#if 0
*((u32*) param ) = cpu_to_le32( *((u32*) param ) );
FillH2CCmd_88E(padapter, RSSI_SETTING_EID, 3, param);
#endif
;
}else{
DBG_8192C("==>%s fw dont support RA\n",__func__);
res=_FAIL;

44
hal/rtl8188e_dm.c
View file

@ -45,26 +45,6 @@ dm_CheckProtection(
IN PADAPTER Adapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte CurRate, RateThreshold;
if (pMgntInfo->pHTInfo->bCurBW40MHz)
RateThreshold = MGN_MCS1;
else
RateThreshold = MGN_MCS3;
if (Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
{
pMgntInfo->bDmDisableProtect = TRUE;
DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
else
{
pMgntInfo->bDmDisableProtect = FALSE;
DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
#endif
}
static VOID
@ -72,20 +52,6 @@ dm_CheckStatistics(
IN PADAPTER Adapter
)
{
#if 0
if (!Adapter->MgntInfo.bMediaConnect)
return;
//2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.
rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );
// Calculate current Tx Rate(Successful transmited!!)
// Calculate current Rx Rate(Successful received!!)
//for tx tx retry count
rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );
#endif
}
static void dm_CheckPbcGPIO(_adapter *padapter)
@ -303,17 +269,7 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
#if 0
//#ifdef CONFIG_USB_HCI
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType);
if (pHalData->BoardType == BOARD_USB_High_PA){
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE);
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE);
}
#endif
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);
// ODM_CMNINFO_BINHCT_TEST only for MP Team
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);

73
hal/rtl8188e_hal_init.c
View file

@ -332,24 +332,7 @@ void efuse_read_phymap_from_txpktbuf(
lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
#if 0
DBG_871X("%s lo32:0x%08x, %02x %02x %02x %02x\n", __func__, lo32
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+2)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+3)
);
DBG_871X("%s hi32:0x%08x, %02x %02x %02x %02x\n", __func__, hi32
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+1)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+2)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+3)
);
#endif
if (i==0)
{
#if 1 //for debug
if (i==0) {
u8 lenc[2];
u16 lenbak, aaabak;
u16 aaa;
@ -359,7 +342,6 @@ void efuse_read_phymap_from_txpktbuf(
aaabak = le16_to_cpup((u16*)lenc);
lenbak = le16_to_cpu(*((u16*)lenc));
aaa = le16_to_cpup((u16*)&lo32);
#endif
len = le16_to_cpu(*((u16*)&lo32));
limit = (len-2<limit)?len-2:limit;
@ -370,9 +352,7 @@ void efuse_read_phymap_from_txpktbuf(
count+= (limit>=count+2)?2:limit-count;
pos=content+count;
}
else
{
} else {
_rtw_memcpy(pos, ((u8*)&lo32), (limit>=count+4)?4:limit-count);
count+=(limit>=count+4)?4:limit-count;
pos=content+count;
@ -428,17 +408,6 @@ static s32 iol_read_efuse(
if (status == _SUCCESS)
efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
#if 0
DBG_871X("%s physical map\n", __func__);
for (i=0;i<size;i++)
{
DBG_871X("%02x ", physical_map[i]);
if (i%16==15)
DBG_871X("\n");
}
DBG_871X("\n");
#endif
efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
return status;
@ -3669,38 +3638,6 @@ Hal_InitChannelPlan(
IN PADAPTER padapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(padapter->MgntInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if ((pMgntInfo->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
{
pMgntInfo->ChannelPlan = hal_MapChannelPlan8192C(padapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
}
else
{
pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
}
switch (pMgntInfo->ChannelPlan)
{
case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
pDot11dInfo->bEnabled = TRUE;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
break;
default: //for MacOSX compiler warning.
break;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
#endif
}
BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter)
@ -3776,12 +3713,6 @@ void SetBcnCtrlReg(
pHalData->RegBcnCtrlVal |= SetBits;
pHalData->RegBcnCtrlVal &= ~ClearBits;
#if 0
//#ifdef CONFIG_SDIO_HCI
if (pHalData->sdio_himr & (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK))
pHalData->RegBcnCtrlVal |= EN_TXBCN_RPT;
#endif
rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
}

78
hal/rtl8188e_mp.c
View file

@ -225,19 +225,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
if (!IS_92C_SERIAL(pHalData->VersionID))
return;
#if 0
while (PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)
{
PlatformSleepUs(100);
TimeOut--;
if (TimeOut <= 0)
{
RTPRINT(FINIT, INIT_TxPower,
("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));
break;
}
}
#endif
if (beven && !pMptCtx->bMptIndexEven) //odd->even
{
Action = 2;
@ -306,12 +293,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
}
}
#if 0
RTPRINT(FINIT, INIT_TxPower,
("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));
PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);
#endif
}
/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
@ -323,12 +304,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
*/
void Hal_SetChannel(PADAPTER pAdapter)
{
#if 0
struct mp_priv *pmp = &pAdapter->mppriv;
// SelectChannel(pAdapter, pmp->channel);
set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);
#else
u8 eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@ -361,8 +336,6 @@ void Hal_SetChannel(PADAPTER pAdapter)
pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _FALSE;
Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
}
#endif
}
/*
@ -635,19 +608,11 @@ void Hal_SetAntenna(PADAPTER pAdapter)
// Disable Power save
//cosa r_ant_select_ofdm_val = 0x3321333;
#if 0
// 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.
if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.
{
mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);
}
#endif
// 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
if (pHalData->rf_type == RF_2T2R)
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
@ -762,17 +727,9 @@ u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)
{
#if 0
fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
rtw_msleep_os(1000);
fw_cmd_data(pAdapter, value, 1);
*value &= 0xFF;
#else
Hal_TriggerRFThermalMeter(pAdapter);
rtw_msleep_os(1000);
*value = Hal_ReadRFThermalMeter(pAdapter);
#endif
}
void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
@ -1002,28 +959,7 @@ void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
//Set CCK Tx Test Rate
#if 0
switch (pAdapter->mppriv.rateidx)
{
case 2:
cckrate = 0;
break;
case 4:
cckrate = 1;
break;
case 11:
cckrate = 2;
break;
case 22:
cckrate = 3;
break;
default:
cckrate = 0;
break;
}
#else
cckrate = pAdapter->mppriv.rateidx;
#endif
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
@ -1108,13 +1044,6 @@ void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
{
#if 0
// ADC turn off [bit24-21] adc port0 ~ port1
if (bStart) {
write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);
rtw_usleep_os(100);
}
#endif
RT_TRACE(_module_mp_, _drv_info_,
("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
@ -1128,13 +1057,6 @@ void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
{
Hal_SetOFDMContinuousTx(pAdapter, bStart);
}
#if 0
// ADC turn on [bit24-21] adc port0 ~ port1
if (!bStart) {
write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);
}
#endif
}
#endif // CONFIG_MP_INCLUDE

570
hal/rtl8188e_phycfg.c
View file

@ -494,12 +494,6 @@ phy_RFSerialRead(
u32 NewOffset;
u32 tmplong,tmplong2;
u8 RfPiEnable=0;
#if 0
if (pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return retValue;
if (pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return retValue;
#endif
//
// Make sure RF register offset is correct
//
@ -616,13 +610,6 @@ phy_RFSerialWrite(
BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
u32 NewOffset;
#if 0
//<Roger_TODO> We should check valid regs for RF_6052 case.
if (pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return;
if (pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return;
#endif
// 2009/06/17 MH We can not execute IO for power save or other accident mode.
//if (RT_CANNOT_IO(Adapter))
@ -1098,22 +1085,10 @@ phy_ConfigBBExternalPA(
u32 temp=0;
if (!pHalData->ExternalPA)
{
return;
}
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in PHY_REG_1T_HP.txt.
#if 0
PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
temp |= (BIT26|BIT21|BIT10|BIT5);
PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
#endif
#endif
}
@ -1442,39 +1417,11 @@ phy_ConfigBBWithPgHeaderFile(
{
for (i=0;i<PHY_REGArrayPGLen;i=i+3)
{
#if 0 //without IO, no delay is neeeded...
if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
}
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
rtw_mdelay_os(5);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
rtw_mdelay_os(1);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
rtw_udelay_os(50);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
rtw_udelay_os(5);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
rtw_udelay_os(1);
//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
#endif
storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
Rtl819XPHY_REGArray_Table_PG[i+1],
Rtl819XPHY_REGArray_Table_PG[i+2]);
//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
//RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx\n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
}
}
else
{
//RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != CONFIG_BB_PHY_REG\n"));
}
return _SUCCESS;
@ -1488,16 +1435,6 @@ phy_BB8192C_Config_1T(
IN PADAPTER Adapter
)
{
#if 0
//for path - A
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
#endif
//for path - B
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
@ -1664,16 +1601,6 @@ PHY_BBConfig8188E(
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
#endif
#if 0
#ifdef CONFIG_USB_HCI
//To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
rtw_write8(Adapter, 0x15, 0xe9);
#endif
rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
#endif
#ifdef CONFIG_USB_HCI
//rtw_write8(Adapter, 0x15, 0xe9);
#endif
@ -1715,27 +1642,6 @@ PHY_RFConfig8188E(
// RF config
//
rtStatus = PHY_RF6052_Config8188E(Adapter);
#if 0
switch (pHalData->rf_chip)
{
case RF_6052:
rtStatus = PHY_RF6052_Config(Adapter);
break;
case RF_8225:
rtStatus = PHY_RF8225_Config(Adapter);
break;
case RF_8256:
rtStatus = PHY_RF8256_Config(Adapter);
break;
case RF_8258:
break;
case RF_PSEUDO_11N:
rtStatus = PHY_RF8225_Config(Adapter);
break;
default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
break;
}
#endif
return rtStatus;
}
@ -1802,21 +1708,10 @@ PHY_ConfigRFExternalPA(
u16 i=0;
if (!pHalData->ExternalPA)
{
return rtStatus;
}
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in radio_a_1T_HP.txt.
#if 0
//add for SU High Power PA
for (i = 0;i<HighPowerRadioAArrayLen; i=i+2)
{
RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
}
#endif
#endif
return rtStatus;
}
@ -1968,20 +1863,12 @@ rtl8188e_PHY_ConfigRFWithHeaderFile(
for (i = 0;i<RadioB_ArrayLen; i=i+2)
{
if (Rtl819XRadioB_Array_Table[i] == 0xfe)
{ // Deay specific ms. Only RF configuration require delay.
#if 0//#ifdef CONFIG_USB_HCI
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(1000);
#else
rtw_mdelay_os(1000);
#endif
#else
{ // Delay specific ms. Only RF configuration require delay.
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
#endif
}
else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
rtw_mdelay_os(5);
@ -2278,37 +2165,6 @@ PHY_GetTxPowerLevel8188E(
*powerlevel = TxPwrDbm;
}
#if 0
static void getTxPowerIndex(
IN PADAPTER Adapter,
IN u8 channel,
IN OUT u8* cckPowerLevel,
IN OUT u8* ofdmPowerLevel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 index = (channel -1);
// 1. CCK
cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
// 2. OFDM for 1S or 2S
if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
{
// Read HT 40 OFDM TX power
ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
}
else if (GET_RF_TYPE(Adapter) == RF_2T2R)
{
// Read HT 40 OFDM TX power
ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
}
//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
}
#endif
void getTxPowerIndex88E(
IN PADAPTER Adapter,
IN u8 channel,
@ -2343,13 +2199,7 @@ void getTxPowerIndex88E(
pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];
//2. BW40
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
//RTPRINT(FPHY, PHY_TXPWR, ("getTxPowerIndex88E(): 40MBase=0x%x 20Mdiff=%d 20MBase=0x%x!!\n",
// pHalData->Index24G_BW40_Base[RF_PATH_A][index],
// pHalData->BW20_24G_Diff[TxCount][RF_PATH_A],
// BW20PowerLevel[TxCount]));
}
else if (TxCount==RF_PATH_B)
{
} else if (TxCount==RF_PATH_B) {
// 1. CCK
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
//2. OFDM
@ -2405,41 +2255,6 @@ void getTxPowerIndex88E(
{
}
}
#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
switch (pMgntInfo->IntelProximityModeInfo.PowerOutput){
case 1: // 100%
break;
case 2: // 70%
cckPowerLevel[0] -= 3;
cckPowerLevel[1] -= 3;
ofdmPowerLevel[0] -=3;
ofdmPowerLevel[1] -= 3;
break;
case 3: // 50%
cckPowerLevel[0] -= 6;
cckPowerLevel[1] -= 6;
ofdmPowerLevel[0] -=6;
ofdmPowerLevel[1] -= 6;
break;
case 4: // 35%
cckPowerLevel[0] -= 9;
cckPowerLevel[1] -= 9;
ofdmPowerLevel[0] -=9;
ofdmPowerLevel[1] -= 9;
break;
case 5: // 15%
cckPowerLevel[0] -= 17;
cckPowerLevel[1] -= 17;
ofdmPowerLevel[0] -=17;
ofdmPowerLevel[1] -= 17;
break;
default:
break;
}
#endif
//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
}
void phy_PowerIndexCheck88E(
@ -2453,70 +2268,13 @@ void phy_PowerIndexCheck88E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if 0 // (CCX_SUPPORT == 1)
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
//
// CCX 2 S31, AP control of client transmit power:
// 1. We shall not exceed Cell Power Limit as possible as we can.
// 2. Tolerance is +/- 5dB.
// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
//
// TODO:
// 1. 802.11h power contraint
//
// 071011, by rcnjko.
//
if ( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
pMgntInfo->mAssoc &&
pCcxInfo->bUpdateCcxPwr &&
pCcxInfo->bWithCcxCellPwr &&
channel == pMgntInfo->dot11CurrentChannelNumber)
{
u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
// CCK
if (cckPowerLevel[0] > CckCellPwrIdx)
cckPowerLevel[0] = CckCellPwrIdx;
// Legacy OFDM, HT OFDM
if (ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
{
if ((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
{
ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
}
else
{
ofdmPowerLevel[0] = 0;
}
}
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
}
#else
// Add or not ???
#endif
pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
//DBG_871X("PHY_SetTxPowerLevel8188E(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x, CurrentBW2024GTxPwrIdx: 0x%dx, CurrentBW4024GTxPwrIdx: 0x%x\n",
// pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx, pHalData->CurrentBW2024GTxPwrIdx, pHalData->CurrentBW4024GTxPwrIdx);
}
/*-----------------------------------------------------------------------------
* Function: SetTxPowerLevel8190()
*
@ -2565,30 +2323,6 @@ PHY_SetTxPowerLevel8188E(
rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel);
#if 0
switch (pHalData->rf_chip)
{
case RF_8225:
PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
break;
case RF_8256:
PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
break;
case RF_6052:
PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
break;
case RF_8258:
break;
}
#endif
}
@ -2662,30 +2396,6 @@ PHY_ScanOperationBackup8188E(
IN u8 Operation
)
{
#if 0
IO_TYPE IoType;
if (!Adapter->bDriverStopped)
{
switch (Operation)
{
case SCAN_OPT_BACKUP:
IoType = IO_CMD_PAUSE_DM_BY_SCAN;
rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
break;
case SCAN_OPT_RESTORE:
IoType = IO_CMD_RESUME_DM_BY_SCAN;
rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
break;
default:
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation.\n"));
break;
}
}
#endif
}
/*-----------------------------------------------------------------------------
@ -2708,25 +2418,12 @@ _PHY_SetBWMode92C(
IN PADAPTER Adapter
)
{
// PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 regBwOpMode;
u8 regRRSR_RSC;
//return;
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//u4Byte NowL, NowH;
//u8Byte BeginTime, EndTime;
/*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \
pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
if (pHalData->rf_chip == RF_PSEUDO_11N)
{
//pHalData->SetBWModeInProgress= _FALSE;
return;
}
// There is no 40MHz mode in RF_8225.
if (pHalData->rf_chip==RF_8225)
@ -2735,19 +2432,12 @@ _PHY_SetBWMode92C(
if (Adapter->bDriverStopped)
return;
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//NowL = PlatformEFIORead4Byte(Adapter, TSFR);
//NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
//BeginTime = ((u8Byte)NowH << 32) + NowL;
//3//
//3//<1>Set MAC register
//3//
//Adapter->HalFunc.SetBWModeHandler();
//3
//3<1>Set MAC register
//3
regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
//regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);
switch (pHalData->CurrentChannelBW)
{
@ -2904,32 +2594,12 @@ PHY_SetBWMode8188E(
pHalData->CurrentChannelBW = Bandwidth;
#if 0
if (Offset==HT_EXTCHNL_OFFSET_LOWER)
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
else if (Offset==HT_EXTCHNL_OFFSET_UPPER)
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
else
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
#else
pHalData->nCur40MhzPrimeSC = Offset;
#endif
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
#if 0
//PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
#else
_PHY_SetBWMode92C(Adapter);
#endif
}
else
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
//pHalData->SetBWModeInProgress= FALSE;
pHalData->CurrentChannelBW = tmpBW;
}
}
@ -3013,29 +2683,13 @@ PHY_SwChnl8188E( // Call after initialization
pHalData->CurrentChannel=channel;
//pHalData->SwChnlStage=0;
//pHalData->SwChnlStep=0;
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
#if 0
//PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
#else
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
_PHY_SwChnl8192C(Adapter, channel);
#endif
if (bResult)
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
}
else
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
//if (IS_HARDWARE_TYPE_8192SU(Adapter))
//{
// pHalData->SwChnlInProgress = FALSE;
pHalData->CurrentChannel = tmpchannel;
//}
if (bResult) {
;
} else {
pHalData->CurrentChannel = tmpchannel;
}
}
@ -3060,154 +2714,6 @@ phy_SwChnlStepByStep(
OUT u32 *delay
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
u4Byte PreCommonCmdCnt;
SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
u4Byte PostCommonCmdCnt;
SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
u4Byte RfDependCmdCnt;
SwChnlCmd *CurrentCmd;
u1Byte eRFPath;
u4Byte RfTXPowerCtrl;
BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
#if (MP_DRIVER != 1)
RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
#endif
RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
//for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//{
// <1> Fill up pre common command.
PreCommonCmdCnt = 0;
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
CmdID_SetTxPowerLevel, 0, 0, 0);
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
CmdID_End, 0, 0, 0);
// <2> Fill up post common command.
PostCommonCmdCnt = 0;
phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
CmdID_End, 0, 0, 0);
// <3> Fill up RF dependent command.
RfDependCmdCnt = 0;
switch ( pHalData->RFChipID )
{
case RF_8225:
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
// 2008/09/04 MH Change channel.
if (channel==14) channel++;
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8256:
// TEST!! This is not the table for 8256!!
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, rRfChannel, channel, 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_6052:
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8258:
break;
// For FPGA two MAC verification
case RF_PSEUDO_11N:
return TRUE;
default:
RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
return FALSE;
break;
}
do{
switch (*stage)
{
case 0:
CurrentCmd=&PreCommonCmd[*step];
break;
case 1:
CurrentCmd=&RfDependCmd[*step];
break;
case 2:
CurrentCmd=&PostCommonCmd[*step];
break;
}
if (CurrentCmd->CmdID==CmdID_End)
{
if ((*stage)==2)
{
return TRUE;
}
else
{
(*stage)++;
(*step)=0;
continue;
}
}
switch (CurrentCmd->CmdID)
{
case CmdID_SetTxPowerLevel:
PHY_SetTxPowerLevel8192C(Adapter,channel);
break;
case CmdID_WritePortUlong:
PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
break;
case CmdID_WritePortUshort:
PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
break;
case CmdID_WritePortUchar:
PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
break;
case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
#if 1
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
#else
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
#endif
}
break;
}
break;
}while (TRUE);
//cosa }/*for (Number of RF paths)*/
(*delay)=CurrentCmd->msDelay;
(*step)++;
return FALSE;
#endif
return _TRUE;
}
@ -3226,17 +2732,9 @@ phy_SetSwChnlCmdArray(
SwChnlCmd* pCmd;
if (CmdTable == NULL)
{
//RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
return _FALSE;
}
if (CmdTableIdx >= CmdTableSz)
{
//RT_ASSERT(FALSE,
// ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",
// CmdTableIdx, CmdTableSz));
return _FALSE;
}
pCmd = CmdTable + CmdTableIdx;
pCmd->CmdID = CmdID;
@ -3254,20 +2752,8 @@ phy_FinishSwChnlNow( // We should not call this function directly
IN u8 channel
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u32 delay;
while (!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
{
if (delay>0)
rtw_mdelay_os(delay);
}
#endif
}
//
// Description:
// Switch channel synchronously. Called by SwChnlByDelayHandler.
@ -3329,30 +2815,6 @@ PHY_SetMonitorMode8192C(
IN BOOLEAN bEnableMonitorMode
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
//2 Note: we may need to stop antenna diversity.
if (bEnableMonitorMode)
{
bFilterOutNonAssociatedBSSID = FALSE;
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
pHalData->bInMonitorMode = TRUE;
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
}
else
{
bFilterOutNonAssociatedBSSID = TRUE;
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
pHalData->bInMonitorMode = FALSE;
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
}
#endif
}
@ -3382,16 +2844,6 @@ PHY_CheckIsLegalRfPath8192C(
BOOLEAN rtValue = _TRUE;
// NOt check RF Path now.!
#if 0
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
{
rtValue = FALSE;
}
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
{
}
#endif
return rtValue;
} /* PHY_CheckIsLegalRfPath8192C */

250
hal/rtl8188e_rf6052.c
View file

@ -96,50 +96,6 @@ void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
#if 0//(RTL92SE_FPGA_VERIFY == 0)
static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
// Set PA to high value
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
// Set PA low gain
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
}
#endif
} /* RF_ChangeTxPath */
@ -322,50 +278,6 @@ rtl8188e_PHY_RF6052SetCckTxPower(
} /* PHY_RF6052SetCckTxPower */
#if 0
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
//
static void getPowerBase(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel,
IN OUT u32* OfdmBase,
IN OUT u32* MCSBase
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff=0, HT20_pwrdiff=0;
u8 i, powerlevel[2];
for (i=0; i<2; i++)
{
powerlevel[i] = pPowerLevel[i];
Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
powerBase0 = powerlevel[i] + Legacy_pwrdiff;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
*(OfdmBase+i) = powerBase0;
//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
}
for (i=0; i<2; i++)
{
//Check HT20 to HT40 diff
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
powerlevel[i] += HT20_pwrdiff;
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
*(MCSBase+i) = powerBase1;
//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
}
}
#endif
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
@ -412,139 +324,7 @@ void getPowerBase88E(
//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
}
}
#if 0
static void getTxPowerWriteValByRegulatory(
IN PADAPTER Adapter,
IN u8 Channel,
IN u8 index,
IN u32* powerBase0,
IN u32* powerBase1,
OUT u32* pOutWriteVal
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 i, chnlGroup, pwr_diff_limit[4];
u32 writeVal, customer_limit, rf;
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
for (rf=0; rf<2; rf++)
{
switch (pHalData->EEPROMRegulatory)
{
case 0: // Realtek better performance
// increase power diff defined by Realtek for large power
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 1: // Realtek regulatory
// increase power diff defined by Realtek for regulatory
{
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= 3)
{
if (Channel <= 3)
chnlGroup = 0;
else if (Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if (Channel > 9)
chnlGroup = 2;
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=4;
}
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
}
break;
case 2: // Better regulatory
// don't increase any power diff
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 3: // Customer defined power diff.
// increase power diff defined by customer.
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
{
//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
// ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
}
else
{
//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
// ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
}
for (i=0; i<4; i++)
{
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
{
if (pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
}
else
{
if (pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
}
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
}
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
// 20100628 Joseph: High power mode for BT-Coexist mechanism.
// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
writeVal = writeVal - 0x06060606;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
writeVal = writeVal;
}
*(pOutWriteVal+rf) = writeVal;
}
}
#endif
void getTxPowerWriteValByRegulatory88E(
IN PADAPTER Adapter,
IN u8 Channel,
@ -565,13 +345,8 @@ void getTxPowerWriteValByRegulatory88E(
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
if (pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
Regulatory = 2;
#endif
for (rf=0; rf<2; rf++)
{
for (rf=0; rf<2; rf++) {
switch (Regulatory)
{
case 0: // Realtek better performance
@ -1001,30 +776,7 @@ PHY_RF6052_Config8188E(
// Config BB and RF
//
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
#if 0
switch ( Adapter->MgntInfo.bRegHwParaFile )
{
case 0:
phy_RF6052_Config_HardCode(Adapter);
break;
case 1:
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
break;
case 2:
// Partial Modify.
phy_RF6052_Config_HardCode(Adapter);
phy_RF6052_Config_ParaFile(Adapter);
break;
default:
phy_RF6052_Config_HardCode(Adapter);
break;
}
#endif
return rtStatus;
}

6
hal/rtl8188e_rxdesc.c
View file

@ -295,12 +295,6 @@ void update_recvframe_phyinfo_88e(
if (pkt_info.bPacketBeacon){
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
sa = padapter->mlmepriv.cur_network.network.MacAddress;
#if 0
{
DBG_8192C("==> rx beacon from AP[%02x:%02x:%02x:%02x:%02x:%02x]\n",
sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]);
}
#endif
}
//to do Ad-hoc
}

16
hal/rtl8188e_sreset.c
View file

@ -236,22 +236,6 @@ void rtl8188e_sreset_linked_status_check(_adapter *padapter)
else if (fw_status == 2)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__func__,fw_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if ( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __func__,
regc50, regc58, reg824, reg800);
rtl8188e_silentreset_for_specific_platform(padapter);
}
#endif
}
#endif

7
hal/rtl8188eu_xmit.c
View file

@ -394,13 +394,6 @@ if (padapter->registrypriv.mp_mode == 0)
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
//for debug
#if 0
if (padapter->fix_rate!= 0xFF){
ptxdesc->datarate = padapter->fix_rate;
}
#endif
#if (POWER_TRAINING_ACTIVE==1)
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT);

833
hal/usb_halinit.c
View file

@ -454,19 +454,6 @@ _InitPageBoundary(
//
u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
#if 0
// RX Page Boundary
//srand(static_cast<unsigned int>(time(NULL)) );
if (bSupportRemoteWakeUp)
{
Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE;
Offset = Offset / 128; // RX page size = 128 byte
rxff_bndy= (Offset*128) -1;
}
else
#endif
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
}
@ -1010,36 +997,6 @@ HalRxAggr8188EUsb(
IN BOOLEAN Value
)
{
#if 0//USB_RX_AGGREGATION_92C
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
u1Byte valueDMATimeout;
u1Byte valueDMAPageCount;
u1Byte valueUSBTimeout;
u1Byte valueUSBBlockCount;
// selection to prevent bad TP.
if ( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg)
{
// 2010.04.27 hpfan
// Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
// Timeout value is calculated by 34 / (2^n)
valueDMATimeout = 0x0f;
valueDMAPageCount = 0x01;
valueUSBTimeout = 0x0f;
valueUSBBlockCount = 0x01;
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
}
else
{
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
}
#endif
}
/*-----------------------------------------------------------------------------
@ -1066,88 +1023,6 @@ USB_AggModeSwitch(
IN PADAPTER Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
//pHalData->UsbRxHighSpeedMode = FALSE;
// How to measure the RX speed? We assume that when traffic is more than
if (pMgntInfo->bRegAggDMEnable == FALSE)
{
return; // Inf not support.
}
if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE &&
pHalData->UsbRxHighSpeedMode == FALSE)
{
pHalData->UsbRxHighSpeedMode = TRUE;
RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to HIGH\n"));
}
else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE &&
pHalData->UsbRxHighSpeedMode == TRUE)
{
pHalData->UsbRxHighSpeedMode = FALSE;
RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to LOW\n"));
}
else
{
return;
}
#if USB_RX_AGGREGATION_92C
if (pHalData->UsbRxHighSpeedMode == TRUE)
{
// 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
// USB mode
#if (RT_PLATFORM == PLATFORM_LINUX)
if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic)
{
pHalData->RxAggBlockCount = 16;
pHalData->RxAggBlockTimeout = 7;
}
else
#endif
{
pHalData->RxAggBlockCount = 40;
pHalData->RxAggBlockTimeout = 5;
}
// Mix mode
pHalData->RxAggPageCount = 72;
pHalData->RxAggPageTimeout = 6;
}
else
{
// USB mode
pHalData->RxAggBlockCount = pMgntInfo->RegRxAggBlockCount;
pHalData->RxAggBlockTimeout = pMgntInfo->RegRxAggBlockTimeout;
// Mix mode
pHalData->RxAggPageCount = pMgntInfo->RegRxAggPageCount;
pHalData->RxAggPageTimeout = pMgntInfo->RegRxAggPageTimeout;
}
if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT)
pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT;
#if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX) // do not support WINXP to prevent usbehci.sys BSOD
if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter))
{
//
// 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test
// with the aggregation dynamic change!! We need to disable the function to prevent it is broken
// in usbehci.sys.
//
usb_AggSettingRxUpdate_8188E(Adapter);
// 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse
// there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the
// issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may
// BSOD.
}
#endif
#endif
#endif
} // USB_AggModeSwitch
static VOID
@ -1155,68 +1030,6 @@ _InitOperationMode(
IN PADAPTER Adapter
)
{
#if 0//gtest
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
u1Byte regBwOpMode = 0;
u4Byte regRATR = 0, regRRSR = 0;
//1 This part need to modified according to the rate set we filtered!!
//
// Set RRSR, RATR, and REG_BWOPMODE registers
//
switch (Adapter->RegWirelessMode)
{
case WIRELESS_MODE_B:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK;
regRRSR = RATE_ALL_CCK;
break;
case WIRELESS_MODE_A:
regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
regRATR = RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_G:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_AUTO:
if (Adapter->bInHctTest)
{
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
}
else
{
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
}
break;
case WIRELESS_MODE_N_24G:
// It support CCK rate by default.
// CCK rate will be filtered out only when associated AP does not support it.
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_N_5G:
regBwOpMode = BW_OPMODE_5G;
regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_OFDM_AG;
break;
default: //for MacOSX compiler warning.
break;
}
// Ziv ????????
//PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
#endif
}
@ -1307,34 +1120,6 @@ static VOID _RfPowerSave(
IN PADAPTER Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte eRFPath;
#if (DISABLE_BB_RF)
return;
#endif
if (pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
// Those action will be discard in MgntActSet_RF_State because off the same state
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
}
else if (pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
}
else{
pHalData->eRFPowerState = eRfOn;
pMgntInfo->RfOffReason = 0;
if (Adapter->bInSetPower || Adapter->bResetInProgress)
PlatformUsbEnableInPipes(Adapter);
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
}
#endif
}
enum {
@ -1374,39 +1159,6 @@ HalDetectSelectiveSuspendMode(
IN PADAPTER Adapter
)
{
#if 0
u8 tmpvalue;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
// If support HW radio detect, we need to enable WOL ability, otherwise, we
// can not use FW to notify host the power state switch.
EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
if (tmpvalue & BIT1)
{
DBG_8192C("Enable\n");
}
else
{
DBG_8192C("Disable\n");
pdvobjpriv->RegUsbSS = _FALSE;
}
// 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
{
//PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
//if (!pMgntInfo->bRegDongleSS)
//{
// RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
pdvobjpriv->RegUsbSS = _FALSE;
//}
}
#endif
} // HalDetectSelectiveSuspendMode
/*-----------------------------------------------------------------------------
* Function: HwSuspendModeEnable92Cu()
@ -1691,11 +1443,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
else
#endif //MP_DRIVER == 1
{
#if 0
Adapter->bFWReady = _FALSE; //because no fw for test chip
pHalData->fw_ractrl = _FALSE;
#else
#ifdef CONFIG_WOWLAN
status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
#else
@ -1712,13 +1459,9 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
Adapter->bFWReady = _TRUE;
pHalData->fw_ractrl = _FALSE;
}
#endif
}
rtl8188e_InitializeFirmwareVars(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
#if (HAL_MAC_ENABLE == 1)
status = PHY_MACConfig8188E(Adapter);
@ -1817,12 +1560,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
}
#endif
#if 0
if (pHTInfo->bRDGEnable){
_InitRDGSetting_8188E(Adapter);
}
#endif
#ifdef CONFIG_TX_EARLY_MODE
if ( pHalData->bEarlyModeEnable)
{
@ -1931,97 +1668,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
// Added by tynli. 2010.03.30.
pwrctrlpriv->rf_pwrstate = rf_on;
#if 0 //to do
RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
#if 1 //Todo
// 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
// 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
if (pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
pwrctrlpriv->b_hw_radio_off = _TRUE;
DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
if (pwrctrlpriv->reg_rfoff == _TRUE)
{ // User disable RF via registry.
DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
// Those action will be discard in MgntActSet_RF_State because off the same state
//for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
}
else if (pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
{ // H/W or S/W RF OFF before sleep.
DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
//pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->rf_pwrstate = rf_on;
//MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
}
else
{
// Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
if (pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
{
DBG_8192C("InitializeAdapter8192CU(): RF=%d\n", eRfPowerStateToSet);
if (eRfPowerStateToSet == rf_off)
{
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
pwrctrlpriv->b_hw_radio_off = _TRUE;
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->b_hw_radio_off = _FALSE;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
pwrctrlpriv->rfoff_reason = 0;
pwrctrlpriv->b_hw_radio_off = _FALSE;
pwrctrlpriv->rf_pwrstate = rf_on;
rtw_led_control(Adapter, LED_CTL_POWER_ON);
}
// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
if (pHalData->pwrdown && eRfPowerStateToSet == rf_off)
{
// Enable register area 0x0-0xc.
rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
//
// <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
// our HW will be set in power-down mode if PDn source from all functions are configured.
// 2010.10.06.
//
//if (IS_HARDWARE_TYPE_8723AU(Adapter))
//{
// u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
// rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
//}
//else
//{
rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
//}
}
//DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
#endif
#endif
// enable Tx report.
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
@ -2284,291 +1930,13 @@ unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter)
return _SUCCESS;
}
//-------------------------------------------------------------------------
//
// EEPROM Power index mapping
//
//-------------------------------------------------------------------------
#if 0
static VOID
_ReadPowerValueFromPROM(
IN PTxPowerInfo pwrInfo,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
u32 rfPath, eeAddr, group;
_rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo));
if (AutoLoadFail){
for (group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
pwrInfo->CCKIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
pwrInfo->HT40_1SIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff;
pwrInfo->HT20IndexDiff[rfPath][group] = EEPROM_Default_HT20_Diff;
pwrInfo->OFDMIndexDiff[rfPath][group] = EEPROM_Default_LegacyHTTxPowerDiff;
pwrInfo->HT40MaxOffset[rfPath][group] = EEPROM_Default_HT40_PwrMaxOffset;
pwrInfo->HT20MaxOffset[rfPath][group] = EEPROM_Default_HT20_PwrMaxOffset;
}
}
pwrInfo->TSSI_A = EEPROM_Default_TSSI;
pwrInfo->TSSI_B = EEPROM_Default_TSSI;
return;
}
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for (group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group;
pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group;
pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr];
}
}
for (group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
pwrInfo->HT40_2SIndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
#if 1
pwrInfo->HT20IndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
if (pwrInfo->HT20IndexDiff[rfPath][group] & BIT3) //4bit sign number to 8 bit sign number
pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
#else
pwrInfo->HT20IndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
#endif
pwrInfo->OFDMIndexDiff[rfPath][group] =
(PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF;
pwrInfo->HT40MaxOffset[rfPath][group] =
(PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
pwrInfo->HT20MaxOffset[rfPath][group] =
(PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
}
}
pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A];
pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B];
}
static u32
_GetChannelGroup(
IN u32 channel
)
{
//RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
if (channel < 3){ // Channel 1~3
return 0;
}
else if (channel < 9){ // Channel 4~9
return 1;
}
return 2; // Channel 10~14
}
static VOID
ReadTxPowerInfo(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
TxPowerInfo pwrInfo;
u32 rfPath, ch, group;
u8 pwr, diff;
_ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail);
if (!AutoLoadFail)
pHalData->bTXPowerDataReadFromEEPORM = _TRUE;
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
group = _GetChannelGroup(ch);
pHalData->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group];
pHalData->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group];
pHalData->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group];
pHalData->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group];
pHalData->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group];
pHalData->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group];
pwr = pwrInfo.HT40_1SIndex[rfPath][group];
diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
pHalData->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0;
}
}
#if 0 //DBG
for (rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower,
("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch],
pHalData->TxPwrLevelHT40_1S[rfPath][ch],
pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
}
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
}
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
}
#endif
// 2010/10/19 MH Add Regulator recognize for CU.
if (!AutoLoadFail)
{
pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7); //bit0~2
}
else
{
pHalData->EEPROMRegulatory = 0;
}
DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
}
#endif
//-------------------------------------------------------------------
//
// EEPROM/EFUSE Content Parsing
//
//-------------------------------------------------------------------
static void
_ReadIDs(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
static void _ReadIDs(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if (_FALSE == AutoloadFail){
// VID, PID
pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
}
else{
pHalData->EEPROMVID = EEPROM_Default_VID;
pHalData->EEPROMPID = EEPROM_Default_PID;
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID;
pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
}
// For customized behavior.
if ((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
pHalData->CustomerID = RT_CID_819x_HP;
// Decide CustomerID according to VID/DID or EEPROM
switch (pHalData->EEPROMCustomerID)
{
case EEPROM_CID_DEFAULT:
if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pHalData->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pHalData->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pHalData->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
/*
Adapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->keepAliveLevel = 0;
Adapter->bUnloadDriverwhenS3S4 = FALSE;
*/
break;
default:
pHalData->CustomerID = RT_CID_DEFAULT;
break;
}
MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
#endif
}
static VOID
_ReadMACAddress(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
{
#if 0
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
if (_FALSE == AutoloadFail){
//Read Permanent MAC address and set value to hardware
_rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
}
else{
//Random assigh MAC address
u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
//sMacAddr[5] = (u8)GetRandomNumber(1, 254);
_rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
}
DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__func__, MAC_ARG(pEEPROM->mac_addr));
//NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
//RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
#endif
}
static VOID
@ -2613,33 +1981,6 @@ _ReadThermalMeter(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 tempval;
//
// ThermalMeter from EEPROM
//
if (!AutoloadFail)
tempval = PROMContent[EEPROM_THERMAL_METER];
else
tempval = EEPROM_Default_ThermalMeter;
pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0]
if (pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
pdmpriv->bAPKThermalMeterIgnore = _TRUE;
#if 0
if (pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
pHalData->EEPROMThermalMeter = 0x12;
#endif
pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
//RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
#endif
}
static VOID
@ -2658,16 +1999,6 @@ _ReadPROMVersion(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if (AutoloadFail){
pHalData->EEPROMVersion = EEPROM_Default_Version;
}
else{
pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION];
}
#endif
}
static VOID
@ -2681,28 +2012,6 @@ readAntennaDiversity(
struct registry_priv *registry_par = &pAdapter->registrypriv;
pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct registry_priv *registry_par = &pAdapter->registrypriv;
if (!AutoLoadFail)
{
// Antenna Diversity setting.
if (registry_par->antdiv_cfg == 2) // 2: From Efuse
pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
else
pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
//if (pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
// pHalData->AntDivCfg = 0;
}
else
{
pHalData->AntDivCfg = 0;
}
#endif
}
static VOID
@ -2711,39 +2020,6 @@ hal_InitPGData(
IN OUT u8 *PROMContent
)
{
#if 0
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u32 i;
u16 value16;
if (_FALSE == pEEPROM->bautoload_fail_flag)
{ // autoload OK.
if (_TRUE == pEEPROM->EepromOrEfuse)
{
// Read all Content from EEPROM or EFUSE.
for (i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
{
//value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
//*((u16 *)(&PROMContent[i])) = value16;
}
}
else
{
// Read EFUSE real map to shadow.
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
_rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
}
}
else
{//autoload fail
//RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n"));
pEEPROM->bautoload_fail_flag = _TRUE;
//update to default value 0xFF
if (_FALSE == pEEPROM->EepromOrEfuse)
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
}
#endif
}
static void
Hal_EfuseParsePIDVID_8188EU(
@ -2819,87 +2095,11 @@ Hal_CustomizeByCustomerID_8188EU(
IN PADAPTER padapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(padapter->MgntInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
// For customized behavior.
if ((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
pMgntInfo->CustomerID = RT_CID_819x_HP;
// Decide CustomerID according to VID/DID or EEPROM
switch (pHalData->EEPROMCustomerID)
{
case EEPROM_CID_DEFAULT:
if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pMgntInfo->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pMgntInfo->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pMgntInfo->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
padapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE;
pMgntInfo->keepAliveLevel = 0;
padapter->bUnloadDriverwhenS3S4 = FALSE;
break;
default:
pMgntInfo->CustomerID = RT_CID_DEFAULT;
break;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pMgntInfo->CustomerID));
hal_CustomizedBehavior_8723U(padapter);
#endif
}
// Read HW power down mode selection
static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail)
{
#if 0
if (AutoloadFail){
Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
}
else {
//if (SUPPORT_HW_RADIO_DETECT(Adapter))
Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
//else
//Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
//hw power down mode selection , 0:rf-off / 1:power down
if (Adapter->registrypriv.hwpdn_mode==2)
Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
else
Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
// decide hw if support remote wakeup function
// if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
//if (SUPPORT_HW_RADIO_DETECT(Adapter))
//Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__func__,
Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
}
#endif
}
#ifdef CONFIG_EFUSE_CONFIG_FILE
@ -4084,30 +3284,12 @@ _func_enter_;
}
break;
case HW_VAR_RESP_SIFS:
{
#if 0
// SIFS for OFDM Data ACK
rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]);
// SIFS for OFDM consecutive tx like CTS data!
rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]);
rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]);
rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]);
// 20100719 Joseph: Revise SIFS setting due to Hardware register definition change.
rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]);
rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]);
#else
//SIFS_Timer = 0x0a0a0808;
//RESP_SIFS for CCK
rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
//RESP_SIFS for OFDM
rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
#endif
}
//RESP_SIFS for CCK
rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
//RESP_SIFS for OFDM
rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
break;
case HW_VAR_ACK_PREAMBLE:
{
@ -4115,7 +3297,6 @@ _func_enter_;
u8 bShortPreamble = *( (PBOOLEAN)val );
// Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
//regTmp = 0;
if (bShortPreamble)
regTmp |= 0x80;

132
hal/usb_ops_linux.c
View file

@ -120,14 +120,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
_rtw_memcpy( pIo_buf, pdata, len);
}
#if 0
//timeout test for firmware downloading
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len
, (value == FW_8188E_START_ADDRESS) ?RTW_USB_CONTROL_MSG_TIMEOUT_TEST : RTW_USB_CONTROL_MSG_TIMEOUT
);
#else
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
#endif
if ( status == len) // Success this control transfer.
{
@ -399,21 +392,6 @@ void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
#if 0 //DBG
{
u32 hisr=0 ,hisr_ex=0;
_rtw_memcpy(&hisr,&(pHalData->IntArray[0]),4);
hisr = le32_to_cpu(hisr);
_rtw_memcpy(&hisr_ex,&(pHalData->IntArray[1]),4);
hisr_ex = le32_to_cpu(hisr_ex);
if ((hisr != 0) || (hisr_ex!=0))
DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x\n",__func__,hisr,hisr_ex);
}
#endif
#ifdef CONFIG_LPS_LCLK
if ( pHalData->IntArray[0] & IMR_CPWM_88E )
{
@ -436,34 +414,15 @@ void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0
if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDOK_88E)
DBG_8192C("%s: HISR_TXBCNOK\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDER_88E)
DBG_8192C("%s: HISR_TXBCNERR\n", __func__);
#endif
if (check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
if (pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#ifdef CONFIG_CONCURRENT_MODE
if (check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if (check_buddy_fwstate(padapter, WIFI_AP_STATE)) {
if (padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
@ -618,81 +577,7 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
}
else // Handle BC/MC Packets
{
u8 clone = _TRUE;
#if 0
u8 type, subtype, *paddr2, *paddr3;
type = GetFrameType(pbuf);
subtype = GetFrameSubType(pbuf); //bit(7)~bit(2)
switch (type)
{
case WIFI_MGT_TYPE: //Handle BC/MC mgnt Packets
if (subtype == WIFI_BEACON)
{
paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data);
if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) &&
_rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
{
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
if (check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) &&
_rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN))
{
if (clone==_FALSE)
{
clone = _TRUE;
}
else
{
clone = _FALSE;
}
precvframe->u.hdr.adapter = primary_padapter;
}
if (check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) ||
check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING))
{
clone = _TRUE;
precvframe->u.hdr.adapter = primary_padapter;
}
}
else if (subtype == WIFI_PROBEREQ)
{
//probe req frame is only for interface2
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
break;
case WIFI_CTRL_TYPE: // Handle BC/MC ctrl Packets
break;
case WIFI_DATA_TYPE: //Handle BC/MC data Packets
//Notes: AP MODE never rx BC/MC data packets
paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data);
if (_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
{
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
break;
default:
break;
}
#endif
if (_TRUE == clone)
{
@ -811,13 +696,6 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
#if 0 //temp remove when disable usb rx aggregation
if ((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
{
return _FAIL;
}
#endif
do{
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
@ -1217,12 +1095,6 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
#if 0 //temp remove when disable usb rx aggregation
if ((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
{
return _FAIL;
}
#endif
do{
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",