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rtl8188eu: Convert u4Bytw to u32

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2014-12-30 16:55:10 -06:00
parent 5f39818cb5
commit 8aad1f53ce
27 changed files with 482 additions and 488 deletions
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24
hal/Hal8188ERateAdaptive.c
View file

@ -81,7 +81,7 @@ static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
1,2,3,4,5,6,7,8,
1,2,3,4,5,6,7,8,
5,6,7,8,9,10,11,12};
static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode
static u32 INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode
0x0f8ff010, // 1: 40M GN mode
0x0f8ff005, // 2: BN mode/ 40M BGN mode
0x0f8ff000, // 3: N mode
@ -287,7 +287,7 @@ odm_RateDecision_8188E(
)
{
u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
//u4Byte pool_retry;
//u32 pool_retry;
static u1Byte DynamicTxRPTTimingCounter=0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n"));
@ -378,7 +378,7 @@ odm_ARFBRefresh_8188E(
IN PODM_RA_INFO_T pRaInfo
)
{ // Wilson 2011/10/26
u4Byte MaskFromReg;
u32 MaskFromReg;
s1Byte i;
switch(pRaInfo->RateID){
@ -544,8 +544,8 @@ odm_PTDecision_8188E(
u1Byte stage_BUF;
u1Byte j;
u1Byte temp_stage;
u4Byte numsc;
u4Byte num_total;
u32 numsc;
u32 num_total;
u1Byte stage_id;
stage_BUF=pRaInfo->PTStage;
@ -751,7 +751,7 @@ ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u4Byte RateMask,
IN u32 RateMask,
IN u1Byte SGIEnable
)
{
@ -803,14 +803,14 @@ ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u16 TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
IN u32 MacIDValidEntry0,
IN u32 MacIDValidEntry1
)
{
PODM_RA_INFO_T pRAInfo = NULL;
u1Byte MacId = 0;
pu1Byte pBuffer = NULL;
u4Byte valid = 0, ItemNum = 0;
u32 valid = 0, ItemNum = 0;
u16 minRptTime = 0x927c;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n",
@ -982,7 +982,7 @@ ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u4Byte RateMask,
IN u32 RateMask,
IN u1Byte SGIEnable
)
{
@ -1013,8 +1013,8 @@ ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u16 TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
IN u32 MacIDValidEntry0,
IN u32 MacIDValidEntry1
)
{
return;

6
hal/Hal8188ERateAdaptive.h
View file

@ -76,7 +76,7 @@ ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u4Byte RateMask,
IN u32 RateMask,
IN u1Byte SGIEnable
);
@ -92,8 +92,8 @@ ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u16 TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
IN u32 MacIDValidEntry0,
IN u32 MacIDValidEntry1
);

106
hal/HalHWImg8188E_BB.c
View file

@ -26,14 +26,14 @@
static BOOLEAN
CheckCondition(
const u4Byte Condition,
const u4Byte Hex
const u32 Condition,
const u32 Hex
)
{
u4Byte _board = (Hex & 0x000000FF);
u4Byte _interface = (Hex & 0x0000FF00) >> 8;
u4Byte _platform = (Hex & 0x00FF0000) >> 16;
u4Byte cond = Condition;
u32 _board = (Hex & 0x000000FF);
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if ( Condition == 0xCDCDCDCD )
return TRUE;
@ -59,7 +59,7 @@ CheckCondition(
* AGC_TAB_1T.TXT
******************************************************************************/
u4Byte Array_AGC_TAB_1T_8188E[] = {
u32 Array_AGC_TAB_1T_8188E[] = {
0xFF0F0718, 0xABCD,
0xC78, 0xF7000001,
0xC78, 0xF6010001,
@ -334,15 +334,15 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u4Byte);
pu4Byte Array = Array_AGC_TAB_1T_8188E;
u32 ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u32);
u32 * Array = Array_AGC_TAB_1T_8188E;
BOOLEAN biol = FALSE;
#ifdef CONFIG_IOL_IOREG_CFG
PADAPTER Adapter = pDM_Odm->Adapter;
@ -368,8 +368,8 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
@ -463,7 +463,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
* AGC_TAB_1T_ICUT.TXT
******************************************************************************/
u4Byte Array_MP_8188E_AGC_TAB_1T_ICUT[] = {
u32 Array_MP_8188E_AGC_TAB_1T_ICUT[] = {
0xC78, 0xFB000001,
0xC78, 0xFB010001,
0xC78, 0xFB020001,
@ -604,15 +604,15 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_MP_8188E_AGC_TAB_1T_ICUT)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8188E_AGC_TAB_1T_ICUT;
u32 ArrayLen = sizeof(Array_MP_8188E_AGC_TAB_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_AGC_TAB_1T_ICUT;
hex += board;
@ -623,8 +623,8 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
@ -671,7 +671,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
* PHY_REG_1T.TXT
******************************************************************************/
u4Byte Array_PHY_REG_1T_8188E[] = {
u32 Array_PHY_REG_1T_8188E[] = {
0x800, 0x80040000,
0x804, 0x00000003,
0x808, 0x0000FC00,
@ -896,15 +896,15 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u4Byte);
pu4Byte Array = Array_PHY_REG_1T_8188E;
u32 ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u32);
u32 * Array = Array_PHY_REG_1T_8188E;
BOOLEAN biol = FALSE;
#ifdef CONFIG_IOL_IOREG_CFG
PADAPTER Adapter = pDM_Odm->Adapter;
@ -912,7 +912,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
u8 bndy_cnt=1;
#ifdef CONFIG_IOL_IOREG_CFG_DBG
struct cmd_cmp cmpdata[ArrayLen];
u4Byte cmpdata_idx=0;
u32 cmpdata_idx=0;
#endif
#endif//#ifdef CONFIG_IOL_IOREG_CFG
HAL_STATUS rst =HAL_STATUS_SUCCESS;
@ -934,8 +934,8 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
@ -1062,8 +1062,8 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
#ifdef CONFIG_IOL_IOREG_CFG_DBG
printk("~~~ %s IOL_exec_cmds Success !!! \n",__FUNCTION__);
{
u4Byte idx;
u4Byte cdata;
u32 idx;
u32 cdata;
printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx);
printk("### %s data compared !!###\n",__FUNCTION__);
for(idx=0;idx< cmpdata_idx;idx++)
@ -1103,7 +1103,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
* PHY_REG_1T_ICUT.TXT
******************************************************************************/
u4Byte Array_MP_8188E_PHY_REG_1T_ICUT[] = {
u32 Array_MP_8188E_PHY_REG_1T_ICUT[] = {
0x800, 0x80040000,
0x804, 0x00000003,
0x808, 0x0000FC00,
@ -1305,15 +1305,15 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_MP_8188E_PHY_REG_1T_ICUT)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8188E_PHY_REG_1T_ICUT;
u32 ArrayLen = sizeof(Array_MP_8188E_PHY_REG_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_PHY_REG_1T_ICUT;
hex += board;
@ -1324,8 +1324,8 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
@ -1373,7 +1373,7 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
* PHY_REG_PG.TXT
******************************************************************************/
u4Byte Array_PHY_REG_PG_8188E[] = {
u32 Array_PHY_REG_PG_8188E[] = {
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00004000,
0, 0, 0, 0x0000086c, 0xffffff00, 0x34363800,
0, 0, 0, 0x00000e00, 0xffffffff, 0x42444646,
@ -1388,15 +1388,15 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u4Byte);
pu4Byte Array = Array_PHY_REG_PG_8188E;
u32 ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u32);
u32 * Array = Array_PHY_REG_PG_8188E;
BOOLEAN biol = FALSE;
hex += board;
@ -1405,12 +1405,12 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 6 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u4Byte v3 = Array[i+2];
u4Byte v4 = Array[i+3];
u4Byte v5 = Array[i+4];
u4Byte v6 = Array[i+5];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
u32 v3 = Array[i+2];
u32 v4 = Array[i+3];
u32 v5 = Array[i+4];
u32 v6 = Array[i+5];
// this line is a line of pure_body
if ( v1 < 0xCDCDCDCD )

2
hal/HalHWImg8188E_BB.h
View file

@ -21,7 +21,7 @@
#ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex);
/******************************************************************************
* AGC_TAB_1T.TXT

48
hal/HalHWImg8188E_MAC.c
View file

@ -24,14 +24,14 @@
#endif
static BOOLEAN
CheckCondition(
const u4Byte Condition,
const u4Byte Hex
const u32 Condition,
const u32 Hex
)
{
u4Byte _board = (Hex & 0x000000FF);
u4Byte _interface = (Hex & 0x0000FF00) >> 8;
u4Byte _platform = (Hex & 0x00FF0000) >> 16;
u4Byte cond = Condition;
u32 _board = (Hex & 0x000000FF);
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if ( Condition == 0xCDCDCDCD )
return TRUE;
@ -57,7 +57,7 @@ CheckCondition(
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MAC_REG_8188E[] = {
u32 Array_MAC_REG_8188E[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0xFF0F0718, 0xABCD,
@ -162,15 +162,15 @@ ODM_ReadAndConfig_MAC_REG_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_MAC_REG_8188E)/sizeof(u4Byte);
pu4Byte Array = Array_MAC_REG_8188E;
u32 ArrayLen = sizeof(Array_MAC_REG_8188E)/sizeof(u32);
u32 * Array = Array_MAC_REG_8188E;
BOOLEAN biol = FALSE;
#ifdef CONFIG_IOL_IOREG_CFG
@ -179,7 +179,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
u8 bndy_cnt = 1;
#ifdef CONFIG_IOL_IOREG_CFG_DBG
struct cmd_cmp cmpdata[ArrayLen];
u4Byte cmpdata_idx=0;
u32 cmpdata_idx=0;
#endif
#endif //CONFIG_IOL_IOREG_CFG
HAL_STATUS rst =HAL_STATUS_SUCCESS;
@ -203,8 +203,8 @@ ODM_ReadAndConfig_MAC_REG_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
@ -288,7 +288,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
printk("~~~ IOL Config MAC Success !!! \n");
//compare writed data
{
u4Byte idx;
u32 idx;
u1Byte cdata;
// HAL_STATUS_FAILURE;
printk(" MAC data compare => array_len:%d \n",cmpdata_idx);
@ -333,7 +333,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
* MAC_REG_ICUT.TXT
******************************************************************************/
u4Byte Array_MP_8188E_MAC_REG_ICUT[] = {
u32 Array_MP_8188E_MAC_REG_ICUT[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x428, 0x0000000A,
@ -434,15 +434,15 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_MP_8188E_MAC_REG_ICUT)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8188E_MAC_REG_ICUT;
u32 ArrayLen = sizeof(Array_MP_8188E_MAC_REG_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_MAC_REG_ICUT;
hex += board;
@ -453,8 +453,8 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )

2
hal/HalHWImg8188E_MAC.h
View file

@ -21,7 +21,7 @@
#ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex);
/******************************************************************************
* MAC_REG.TXT

50
hal/HalHWImg8188E_RF.c
View file

@ -26,14 +26,14 @@
static BOOLEAN
CheckCondition(
const u4Byte Condition,
const u4Byte Hex
const u32 Condition,
const u32 Hex
)
{
u4Byte _board = (Hex & 0x000000FF);
u4Byte _interface = (Hex & 0x0000FF00) >> 8;
u4Byte _platform = (Hex & 0x00FF0000) >> 16;
u4Byte cond = Condition;
u32 _board = (Hex & 0x000000FF);
u32 _interface = (Hex & 0x0000FF00) >> 8;
u32 _platform = (Hex & 0x00FF0000) >> 16;
u32 cond = Condition;
if ( Condition == 0xCDCDCDCD )
return TRUE;
@ -59,7 +59,7 @@ CheckCondition(
* RadioA_1T.TXT
******************************************************************************/
u4Byte Array_RadioA_1T_8188E[] = {
u32 Array_RadioA_1T_8188E[] = {
0x000, 0x00030000,
0x008, 0x00084000,
0x018, 0x00000407,
@ -183,15 +183,15 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u4Byte);
pu4Byte Array = Array_RadioA_1T_8188E;
u32 ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u32);
u32 * Array = Array_RadioA_1T_8188E;
BOOLEAN biol = FALSE;
#ifdef CONFIG_IOL_IOREG_CFG
PADAPTER Adapter = pDM_Odm->Adapter;
@ -199,7 +199,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
u8 bndy_cnt = 1;
#ifdef CONFIG_IOL_IOREG_CFG_DBG
struct cmd_cmp cmpdata[ArrayLen];
u4Byte cmpdata_idx=0;
u32 cmpdata_idx=0;
#endif
#endif//#ifdef CONFIG_IOL_IOREG_CFG
HAL_STATUS rst =HAL_STATUS_SUCCESS;
@ -222,8 +222,8 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
@ -348,8 +348,8 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
#ifdef CONFIG_IOL_IOREG_CFG_DBG
printk("~~~ %s Success !!! \n",__FUNCTION__);
{
u4Byte idx;
u4Byte cdata;
u32 idx;
u32 cdata;
printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx);
printk("### %s data compared !!###\n",__FUNCTION__);
for(idx=0;idx< cmpdata_idx;idx++)
@ -390,7 +390,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
* RadioA_1T_ICUT.TXT
******************************************************************************/
u4Byte Array_MP_8188E_RadioA_1T_ICUT[] = {
u32 Array_MP_8188E_RadioA_1T_ICUT[] = {
0x000, 0x00030000,
0x008, 0x00084000,
0x018, 0x00000407,
@ -500,15 +500,15 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
u4Byte hex = 0;
u4Byte i = 0;
u32 hex = 0;
u32 i = 0;
u16 count = 0;
pu4Byte ptr_array = NULL;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_MP_8188E_RadioA_1T_ICUT)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8188E_RadioA_1T_ICUT;
u32 ArrayLen = sizeof(Array_MP_8188E_RadioA_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_RadioA_1T_ICUT;
hex += board;
@ -519,8 +519,8 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )

2
hal/HalHWImg8188E_RF.h
View file

@ -21,7 +21,7 @@
#ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex);
/******************************************************************************
* RadioA_1T.TXT

128
hal/HalPhyRf_8188e.c
View file

@ -127,7 +127,7 @@ void setIqkMatrix(
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
(u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));
(u32)IqkResult_X, (u32)IqkResult_Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)IqkResult_X, (u32)IqkResult_Y));
}
@ -170,7 +170,7 @@ ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
)
{
u1Byte pwr_value = 0;
@ -260,7 +260,7 @@ odm_TxPwrTrackSetPwr88E(
u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];
u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT];
u1Byte rf = 0;
u4Byte pwr = 0, TxAGC = 0;
u32 pwr = 0, TxAGC = 0;
struct adapter *Adapter = pDM_Odm->Adapter;
//printk("odm_TxPwrTrackSetPwr88E CH=%d, modify TXAGC \n", *(pDM_Odm->pChannel));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel)));
@ -347,12 +347,12 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
u1Byte ThermalValue_AVG_count = 0;
u4Byte ThermalValue_AVG = 0;
u32 ThermalValue_AVG = 0;
s4Byte ele_A=0, ele_D, TempCCk, X, value32;
s4Byte Y, ele_C=0;
s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
s1Byte deltaPowerIndex = 0;
u4Byte i = 0, j = 0;
u32 i = 0, j = 0;
BOOLEAN is2T = FALSE;
BOOLEAN bInteralPA = FALSE;
@ -572,7 +572,7 @@ phy_PathA_IQK_8188E(
IN BOOLEAN configPathB
)
{
u4Byte regEAC, regE94, regE9C, regEA4;
u32 regEAC, regE94, regE9C, regEA4;
u1Byte result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -625,7 +625,7 @@ phy_PathA_RxIQK(
IN BOOLEAN configPathB
)
{
u4Byte regEAC, regE94, regE9C, regEA4, u4tmp;
u32 regEAC, regE94, regE9C, regEA4, u4tmp;
u1Byte result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -761,7 +761,7 @@ phy_PathB_IQK_8188E(
IN struct adapter *pAdapter
)
{
u4Byte regEAC, regEB4, regEBC, regEC4, regECC;
u32 regEAC, regEB4, regEBC, regEC4, regECC;
u1Byte result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -817,7 +817,7 @@ _PHY_PathAFillIQKMatrix(
IN BOOLEAN bTxOnly
)
{
u4Byte Oldval_0, X, TX0_A, reg;
u32 Oldval_0, X, TX0_A, reg;
s4Byte Y, TX0_C;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -877,7 +877,7 @@ _PHY_PathBFillIQKMatrix(
IN BOOLEAN bTxOnly //do Tx only
)
{
u4Byte Oldval_1, X, TX1_A, reg;
u32 Oldval_1, X, TX1_A, reg;
s4Byte Y, TX1_C;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -938,12 +938,12 @@ ODM_CheckPowerStatus(
void
_PHY_SaveADDARegisters(
IN struct adapter *pAdapter,
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
IN u32 * ADDAReg,
IN u32 * ADDABackup,
IN u32 RegisterNum
)
{
u4Byte i;
u32 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -959,11 +959,11 @@ _PHY_SaveADDARegisters(
void
_PHY_SaveMACRegisters(
IN struct adapter *pAdapter,
IN pu4Byte MACReg,
IN pu4Byte MACBackup
IN u32 * MACReg,
IN u32 * MACBackup
)
{
u4Byte i;
u32 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -979,12 +979,12 @@ _PHY_SaveMACRegisters(
void
_PHY_ReloadADDARegisters(
IN struct adapter *pAdapter,
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegiesterNum
IN u32 * ADDAReg,
IN u32 * ADDABackup,
IN u32 RegiesterNum
)
{
u4Byte i;
u32 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -998,11 +998,11 @@ _PHY_ReloadADDARegisters(
void
_PHY_ReloadMACRegisters(
IN struct adapter *pAdapter,
IN pu4Byte MACReg,
IN pu4Byte MACBackup
IN u32 * MACReg,
IN u32 * MACBackup
)
{
u4Byte i;
u32 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -1017,13 +1017,13 @@ _PHY_ReloadMACRegisters(
void
_PHY_PathADDAOn(
IN struct adapter *pAdapter,
IN pu4Byte ADDAReg,
IN u32 * ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
)
{
u4Byte pathOn;
u4Byte i;
u32 pathOn;
u32 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -1047,11 +1047,11 @@ _PHY_PathADDAOn(
void
_PHY_MACSettingCalibration(
IN struct adapter *pAdapter,
IN pu4Byte MACReg,
IN pu4Byte MACBackup
IN u32 * MACReg,
IN u32 * MACBackup
)
{
u4Byte i = 0;
u32 i = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -1087,7 +1087,7 @@ _PHY_PIModeSwitch(
IN BOOLEAN PIMode
)
{
u4Byte mode;
u32 mode;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -1106,7 +1106,7 @@ phy_SimularityCompare_8188E(
IN u1Byte c2
)
{
u4Byte i, j, diff, SimularityBitMap, bound = 0;
u32 i, j, diff, SimularityBitMap, bound = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
@ -1232,9 +1232,9 @@ phy_IQCalibrate_8188E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
u4Byte i;
u32 i;
u1Byte PathAOK, PathBOK;
u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
@ -1243,12 +1243,12 @@ phy_IQCalibrate_8188E(
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
//since 92C & 92D have the different define in IQK_BB_REG
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
@ -1256,9 +1256,9 @@ phy_IQCalibrate_8188E(
};
#if MP_DRIVER
u4Byte retryCount = 9;
u32 retryCount = 9;
#else
u4Byte retryCount = 2;
u32 retryCount = 2;
#endif
if ( *(pDM_Odm->mp_mode) == 1)
retryCount = 9;
@ -1423,7 +1423,7 @@ phy_LCCalibrate_8188E(
)
{
u1Byte tmpReg;
u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
u32 RF_Amode=0, RF_Bmode=0, LC_Cal;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -1494,24 +1494,24 @@ phy_APCalibrate_8188E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
u4Byte regD[PATH_NUM];
u4Byte tmpReg, index, offset, apkbound;
u32 regD[PATH_NUM];
u32 tmpReg, index, offset, apkbound;
u1Byte path, i, pathbound = PATH_NUM;
u4Byte BB_backup[APK_BB_REG_NUM];
u4Byte BB_REG[APK_BB_REG_NUM] = {
u32 BB_backup[APK_BB_REG_NUM];
u32 BB_REG[APK_BB_REG_NUM] = {
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
rFPGA0_RFMOD, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
u32 BB_AP_MODE[APK_BB_REG_NUM] = {
0x00000020, 0x00a05430, 0x02040000,
0x000800e4, 0x00204000 };
u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = {
u32 BB_normal_AP_MODE[APK_BB_REG_NUM] = {
0x00000020, 0x00a05430, 0x02040000,
0x000800e4, 0x22204000 };
u4Byte AFE_backup[IQK_ADDA_REG_NUM];
u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
u32 AFE_backup[IQK_ADDA_REG_NUM];
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
@ -1521,44 +1521,44 @@ phy_APCalibrate_8188E(
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte MAC_backup[IQK_MAC_REG_NUM];
u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
u32 MAC_backup[IQK_MAC_REG_NUM];
u32 MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
u32 APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
{0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
};
u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
{0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
};
u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
u32 APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
{0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
{0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
};
u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
};
u4Byte AFE_on_off[PATH_NUM] = {
u32 AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
u4Byte APK_offset[PATH_NUM] = {
u32 APK_offset[PATH_NUM] = {
rConfig_AntA, rConfig_AntB};
u4Byte APK_normal_offset[PATH_NUM] = {
u32 APK_normal_offset[PATH_NUM] = {
rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
u4Byte APK_value[PATH_NUM] = {
u32 APK_value[PATH_NUM] = {
0x92fc0000, 0x12fc0000};
u4Byte APK_normal_value[PATH_NUM] = {
u32 APK_normal_value[PATH_NUM] = {
0x92680000, 0x12680000};
s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = {
@ -1569,21 +1569,21 @@ phy_APCalibrate_8188E(
{-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
};
u4Byte APK_normal_setting_value_1[13] = {
u32 APK_normal_setting_value_1[13] = {
0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
0x12680000, 0x00880000, 0x00880000
};
u4Byte APK_normal_setting_value_2[16] = {
u32 APK_normal_setting_value_2[16] = {
0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
0x00050006
};
u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
// u32 AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
s4Byte BB_offset, delta_V, delta_offset;
@ -1947,7 +1947,7 @@ PHY_IQCalibrate_8188E(
s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
BOOLEAN is12simular, is13simular, is23simular;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
@ -2117,7 +2117,7 @@ PHY_LCCalibrate_8188E(
)
{
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
u4Byte timeout = 2000, timecount = 0;
u32 timeout = 2000, timecount = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;

14
hal/HalPhyRf_8188e.h
View file

@ -38,7 +38,7 @@ ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
);
@ -79,15 +79,15 @@ PHY_DigitalPredistortion_8188E( IN struct adapter * pAdapter);
void
_PHY_SaveADDARegisters(
IN struct adapter * pAdapter,
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
IN u32 * ADDAReg,
IN u32 * ADDABackup,
IN u32 RegisterNum
);
void
_PHY_PathADDAOn(
IN struct adapter * pAdapter,
IN pu4Byte ADDAReg,
IN u32 * ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
@ -95,8 +95,8 @@ _PHY_PathADDAOn(
void
_PHY_MACSettingCalibration(
IN struct adapter * pAdapter,
IN pu4Byte MACReg,
IN pu4Byte MACBackup
IN u32 * MACReg,
IN u32 * MACBackup
);

4
hal/hal_com.c
View file

@ -403,7 +403,7 @@ SetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_COMP, *((u8Byte*)value));
break;
case HW_DEF_ODM_DBG_LEVEL:
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_LEVEL, *((u4Byte*)value));
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_DBG_LEVEL, *((u32*)value));
break;
default:
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
@ -426,7 +426,7 @@ GetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
*((u8Byte*)value) = pDM_Odm->DebugComponents;
break;
case HW_DEF_ODM_DBG_LEVEL:
*((u4Byte*)value) = pDM_Odm->DebugLevel;
*((u32*)value) = pDM_Odm->DebugLevel;
break;
case HAL_DEF_DBG_DM_FUNC:
*((u32*)value) = pHalData->odmpriv.SupportAbility;

98
hal/odm.c
View file

@ -43,7 +43,7 @@ const u16 dB_Invert_Table[8][12] = {
//============================================================
//avoid to warn in FreeBSD ==> To DO modify
u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
u32 EDCAParam[HT_IOT_PEER_MAX][3] =
{ // UL DL
{0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP
{0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP
@ -64,7 +64,7 @@ u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
//============================================================
// Global var
//============================================================
u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
0x7f8001fe, // 0, +6.0dB
0x788001e2, // 1, +5.5dB
0x71c001c7, // 2, +5.0dB
@ -508,10 +508,10 @@ odm_InitHybridAntDiv(
BOOLEAN
odm_StaDefAntSel(
IN PDM_ODM_T pDM_Odm,
IN u4Byte OFDM_Ant1_Cnt,
IN u4Byte OFDM_Ant2_Cnt,
IN u4Byte CCK_Ant1_Cnt,
IN u4Byte CCK_Ant2_Cnt,
IN u32 OFDM_Ant1_Cnt,
IN u32 OFDM_Ant2_Cnt,
IN u32 CCK_Ant1_Cnt,
IN u32 CCK_Ant2_Cnt,
OUT u1Byte *pDefAnt
);
@ -659,7 +659,7 @@ void
ODM_CmnInfoInit(
IN PDM_ODM_T pDM_Odm,
IN ODM_CMNINFO_E CmnInfo,
IN u4Byte Value
IN u32 Value
)
{
//ODM_RT_TRACE(pDM_Odm,);
@ -673,7 +673,7 @@ ODM_CmnInfoInit(
// Fixed ODM value.
//
case ODM_CMNINFO_ABILITY:
pDM_Odm->SupportAbility = (u4Byte)Value;
pDM_Odm->SupportAbility = (u32)Value;
break;
case ODM_CMNINFO_PLATFORM:
pDM_Odm->SupportPlatform = (u1Byte)Value;
@ -903,7 +903,7 @@ ODM_CmnInfoPtrArrayHook(
void
ODM_CmnInfoUpdate(
IN PDM_ODM_T pDM_Odm,
IN u4Byte CmnInfo,
IN u32 CmnInfo,
IN u8Byte Value
)
{
@ -913,7 +913,7 @@ ODM_CmnInfoUpdate(
switch (CmnInfo)
{
case ODM_CMNINFO_ABILITY:
pDM_Odm->SupportAbility = (u4Byte)Value;
pDM_Odm->SupportAbility = (u32)Value;
break;
case ODM_CMNINFO_RF_TYPE:
@ -943,7 +943,7 @@ ODM_CmnInfoUpdate(
break;
case ODM_CMNINFO_DBG_LEVEL:
pDM_Odm->DebugLevel = (u4Byte)Value;
pDM_Odm->DebugLevel = (u32)Value;
break;
case ODM_CMNINFO_RA_THRESHOLD_HIGH:
pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
@ -1107,8 +1107,8 @@ odm_CmnInfoUpdate_Debug(
void
ODM_ChangeDynamicInitGainThresh(
IN PDM_ODM_T pDM_Odm,
IN u4Byte DM_Type,
IN u4Byte DM_Value
IN u32 DM_Type,
IN u32 DM_Value
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
@ -1309,7 +1309,7 @@ odm_Adaptivity(
{
s1Byte TH_L2H_dmc, TH_H2L_dmc;
s1Byte TH_L2H, TH_H2L, Diff, IGI_target;
u4Byte value32;
u32 value32;
BOOLEAN EDCCA_State = 0;
if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {
@ -2313,7 +2313,7 @@ odm_FalseAlarmCounterStatistics(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte ret_value;
u32 ret_value;
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
@ -2693,14 +2693,14 @@ odm_RateAdaptiveMaskInit(
pOdmRA->LowRSSIThresh = 20;
}
u4Byte ODM_Get_Rate_Bitmap(
u32 ODM_Get_Rate_Bitmap(
IN PDM_ODM_T pDM_Odm,
IN u4Byte macid,
IN u4Byte ra_mask,
IN u32 macid,
IN u32 ra_mask,
IN u1Byte rssi_level)
{
PSTA_INFO_T pEntry;
u4Byte rate_bitmap = 0x0fffffff;
u32 rate_bitmap = 0x0fffffff;
u1Byte WirelessMode;
//u1Byte WirelessMode =*(pDM_Odm->pWirelessMode);
@ -2974,7 +2974,7 @@ odm_DynamicTxPowerSavePowerIndex(
)
{
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
struct adapter *Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -2992,7 +2992,7 @@ odm_DynamicTxPowerRestorePowerIndex(
struct adapter * Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for(index = 0; index< 6; index++)
rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
@ -3005,7 +3005,7 @@ odm_DynamicTxPowerWritePowerIndex(
{
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for(index = 0; index< 6; index++)
//PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
@ -3738,10 +3738,10 @@ odm_InitHybridAntDiv(
BOOLEAN
odm_StaDefAntSel(
IN PDM_ODM_T pDM_Odm,
IN u4Byte OFDM_Ant1_Cnt,
IN u4Byte OFDM_Ant2_Cnt,
IN u4Byte CCK_Ant1_Cnt,
IN u4Byte CCK_Ant2_Cnt,
IN u32 OFDM_Ant1_Cnt,
IN u32 OFDM_Ant2_Cnt,
IN u32 CCK_Ant1_Cnt,
IN u32 CCK_Ant2_Cnt,
OUT u1Byte *pDefAnt
)
@ -3782,7 +3782,7 @@ odm_StaDefAntSel(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2"));
#endif
//u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
//u32 antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
//(*pDefAnt)= (u1Byte) antsel;
@ -3834,7 +3834,7 @@ void
ODM_AntselStatistics_88C(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacId,
IN u4Byte PWDBAll,
IN u32 PWDBAll,
IN BOOLEAN isCCKrate
)
{
@ -3877,7 +3877,7 @@ odm_HwAntDiv_92C_92D(
)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
u32 RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
u1Byte RxIdleAnt, i;
BOOLEAN bRet=FALSE;
PSTA_INFO_T pEntry;
@ -4139,7 +4139,7 @@ dm_CheckEdcaTurbo_EXIT:
//move to here for ANT detection mechanism using
u4Byte
u32
GetPSDData(
IN PDM_ODM_T pDM_Odm,
unsigned int point,
@ -4147,7 +4147,7 @@ GetPSDData(
{
//unsigned int val, rfval;
//int psd_report;
u4Byte psd_report;
u32 psd_report;
//Set DCO frequency index, offset=(40MHz/SamplePts)*point
ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
@ -4160,18 +4160,18 @@ GetPSDData(
//Read PSD report, Reg8B4[15:0]
psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;
psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c);
psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c);
return psd_report;
}
u4Byte
u32
ConvertTo_dB(
u4Byte Value)
u32 Value)
{
u1Byte i;
u1Byte j;
u4Byte dB;
u32 dB;
Value = Value & 0xFFFF;
@ -4226,12 +4226,12 @@ ODM_SingleDualAntennaDefaultSetting(
void
odm_PHY_SaveAFERegisters(
IN PDM_ODM_T pDM_Odm,
IN pu4Byte AFEReg,
IN pu4Byte AFEBackup,
IN u4Byte RegisterNum
IN u32 * AFEReg,
IN u32 * AFEBackup,
IN u32 RegisterNum
)
{
u4Byte i;
u32 i;
//RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
for( i = 0 ; i < RegisterNum ; i++){
@ -4242,12 +4242,12 @@ odm_PHY_SaveAFERegisters(
void
odm_PHY_ReloadAFERegisters(
IN PDM_ODM_T pDM_Odm,
IN pu4Byte AFEReg,
IN pu4Byte AFEBackup,
IN u4Byte RegiesterNum
IN u32 * AFEReg,
IN u32 * AFEBackup,
IN u32 RegiesterNum
)
{
u4Byte i;
u32 i;
//RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
for(i = 0 ; i < RegiesterNum; i++)
@ -4275,15 +4275,15 @@ ODM_SingleDualAntennaDetection(
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
//PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte CurrentChannel,RfLoopReg;
u32 CurrentChannel,RfLoopReg;
u1Byte n;
u4Byte Reg88c, Regc08, Reg874, Regc50;
u32 Reg88c, Regc08, Reg874, Regc50;
u1Byte initial_gain = 0x5a;
u4Byte PSD_report_tmp;
u4Byte AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
u32 PSD_report_tmp;
u32 AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
BOOLEAN bResult = TRUE;
u4Byte AFE_Backup[16];
u4Byte AFE_REG_8723A[16] = {
u32 AFE_Backup[16];
u32 AFE_REG_8723A[16] = {
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,

160
hal/odm.h
View file

@ -138,8 +138,8 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
u32 FALowThresh;
u32 FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
@ -164,15 +164,15 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u4Byte Recover_cnt;
u32 Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
u32 AntDiv_RSSI_max;
u32 RSSI_max;
}DIG_T,*pDIG_T;
typedef struct _Dynamic_Power_Saving_
@ -186,25 +186,25 @@ typedef struct _Dynamic_Power_Saving_
int Rssi_val_min;
u1Byte initialize;
u4Byte Reg874,RegC70,Reg85C,RegA74;
u32 Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
typedef struct false_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
u32 Cnt_Parity_Fail;
u32 Cnt_Rate_Illegal;
u32 Cnt_Crc8_fail;
u32 Cnt_Mcs_fail;
u32 Cnt_Ofdm_fail;
u32 Cnt_Cck_fail;
u32 Cnt_all;
u32 Cnt_Fast_Fsync;
u32 Cnt_SB_Search_fail;
u32 Cnt_OFDM_CCA;
u32 Cnt_CCK_CCA;
u32 Cnt_CCA_all;
u32 Cnt_BW_USC; //Gary
u32 Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef struct _Dynamic_Primary_CCA{
@ -260,7 +260,7 @@ typedef struct _SW_Antenna_Switch_
// Before link Antenna Switch check
u1Byte SWAS_NoLink_State;
u4Byte SWAS_NoLink_BK_Reg860;
u32 SWAS_NoLink_BK_Reg860;
BOOLEAN ANTA_ON; //To indicate Ant A is or not
BOOLEAN ANTB_ON; //To indicate Ant B is on or not
@ -279,12 +279,12 @@ typedef struct _SW_Antenna_Switch_
RT_TIMER SwAntennaSwitchTimer;
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
u1Byte TxAnt[ASSOCIATE_ENTRY_NUM];
u1Byte TargetSTA;
u1Byte antsel;
@ -296,7 +296,7 @@ typedef struct _SW_Antenna_Switch_
typedef struct _EDCA_TURBO_ {
BOOLEAN bCurrentTurboEDCA;
BOOLEAN bIsCurRDLState;
u4Byte prv_traffic_idx; // edca turbo
u32 prv_traffic_idx; // edca turbo
}EDCA_T,*pEDCA_T;
@ -306,7 +306,7 @@ typedef struct _ODM_RATE_ADAPTIVE
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
u4Byte LastRATR; // RATR Register Content
u32 LastRATR; // RATR Register Content
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
@ -484,7 +484,7 @@ typedef enum _ODM_Common_Info_Definition
ODM_CMNINFO_LINK,
ODM_CMNINFO_RSSI_MIN,
ODM_CMNINFO_DBG_COMP, // u8Byte
ODM_CMNINFO_DBG_LEVEL, // u4Byte
ODM_CMNINFO_DBG_LEVEL, // u32
ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte
ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte
ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte
@ -758,8 +758,8 @@ typedef enum tag_CCA_Path
typedef struct _ODM_RA_Info_
{
u1Byte RateID;
u4Byte RateMask;
u4Byte RAUseRate;
u32 RateMask;
u32 RAUseRate;
u1Byte RateSGI;
u1Byte RssiStaRA;
u1Byte PreRssiStaRA;
@ -768,10 +768,10 @@ typedef struct _ODM_RA_Info_
u1Byte PreRate;
u1Byte HighestRate;
u1Byte LowestRate;
u4Byte NscUp;
u4Byte NscDown;
u32 NscUp;
u32 NscDown;
u16 RTY[5];
u4Byte TOTAL;
u32 TOTAL;
u16 DROP;//Retry over or drop
u16 DROP1;//LifeTime over
u1Byte Active;
@ -800,7 +800,7 @@ typedef struct ODM_RF_Calibration_Structure
{
//for tx power tracking
u4Byte RegA24; // for TempCCK
u32 RegA24; // for TempCCK
s4Byte RegE94;
s4Byte RegE9C;
s4Byte RegEB4;
@ -830,7 +830,7 @@ typedef struct ODM_RF_Calibration_Structure
BOOLEAN bReloadtxpowerindex;
u1Byte bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
u1Byte bCCKinCH14;
u1Byte CCK_index;
@ -849,25 +849,25 @@ typedef struct ODM_RF_Calibration_Structure
u1Byte Delta_LCK;
//for IQK
u4Byte RegC04;
u4Byte Reg874;
u4Byte RegC08;
u4Byte RegB68;
u4Byte RegB6C;
u4Byte Reg870;
u4Byte Reg860;
u4Byte Reg864;
u32 RegC04;
u32 Reg874;
u32 RegC08;
u32 RegB68;
u32 RegB6C;
u32 Reg870;
u32 Reg860;
u32 Reg864;
BOOLEAN bIQKInitialized;
BOOLEAN bLCKInProgress;
BOOLEAN bAntennaDetected;
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
u4Byte IQK_BB_backup_recover[9];
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
//for APK
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
u1Byte bDPdone;
@ -884,18 +884,18 @@ typedef struct _FAST_ANTENNA_TRAINNING_
u1Byte antsel_rx_keep_0;
u1Byte antsel_rx_keep_1;
u1Byte antsel_rx_keep_2;
u4Byte antSumRSSI[7];
u4Byte antRSSIcnt[7];
u4Byte antAveRSSI[7];
u32 antSumRSSI[7];
u32 antRSSIcnt[7];
u32 antAveRSSI[7];
u1Byte FAT_State;
u4Byte TrainIdx;
u32 TrainIdx;
u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte RxIdleAnt;
BOOLEAN bBecomeLinked;
@ -946,7 +946,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
rtl8192cd_priv fake_priv;
u8Byte DebugComponents;
u4Byte DebugLevel;
u32 DebugLevel;
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
BOOLEAN bCckHighPower;
@ -975,11 +975,11 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
// ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
u1Byte SupportPlatform;
// ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
u4Byte SupportAbility;
u32 SupportAbility;
// ODM PCIE/USB/SDIO/GSPI = 0/1/2/3
u1Byte SupportInterface;
// ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
u4Byte SupportICType;
u32 SupportICType;
// Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
u1Byte CutVersion;
// Fab Version TSMC/UMC = 0/1
@ -999,7 +999,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
BOOLEAN bWIFITest;
BOOLEAN bDualMacSmartConcurrent;
u4Byte BK_SupportAbility;
u32 BK_SupportAbility;
u1Byte AntDivType;
//-----------HOOK BEFORE REG INIT-----------//
@ -1076,27 +1076,27 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
u1Byte TxRate;
u1Byte LinkedInterval;
u1Byte preChannel;
u4Byte TxagcOffsetValueA;
u32 TxagcOffsetValueA;
BOOLEAN IsTxagcOffsetPositiveA;
u4Byte TxagcOffsetValueB;
u32 TxagcOffsetValueB;
BOOLEAN IsTxagcOffsetPositiveB;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u4Byte BbSwingOffsetA;
u32 BbSwingOffsetA;
BOOLEAN IsBbSwingOffsetPositiveA;
u4Byte BbSwingOffsetB;
u32 BbSwingOffsetB;
BOOLEAN IsBbSwingOffsetPositiveB;
s1Byte TH_L2H_ini;
s1Byte TH_EDCCA_HL_diff;
u4Byte IGI_Base;
u4Byte IGI_target;
u32 IGI_Base;
u32 IGI_target;
BOOLEAN ForceEDCCA;
u1Byte AdapEn_RSSI;
u1Byte AntType;
u1Byte antdiv_rssi;
u1Byte antdiv_period;
u4Byte Force_TH_H;
u4Byte Force_TH_L;
u32 Force_TH_H;
u32 Force_TH_L;
u1Byte IGI_LowerBound;
//2 Define STA info.
@ -1145,7 +1145,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
BOOLEAN RSSI_test;
EDCA_T DM_EDCA_Table;
u4Byte WMMEDCA_BE;
u32 WMMEDCA_BE;
// Copy from SD4 structure
//
// ==================================================
@ -1412,7 +1412,7 @@ typedef enum tag_SW_Antenna_Switch_Definition
#define OFDM_TABLE_SIZE_92D 43
#define CCK_TABLE_SIZE 33
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D];
extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
@ -1468,9 +1468,9 @@ void ODM_SwAntDivChkPerPktRssi(
PODM_PHY_INFO_T pPhyInfo
);
u4Byte ConvertTo_dB(u4Byte Value);
u32 ConvertTo_dB(u32 Value);
u4Byte
u32
GetPSDData(
PDM_ODM_T pDM_Odm,
unsigned int point,
@ -1481,10 +1481,10 @@ odm_DIGbyRSSI_LPS(
PDM_ODM_T pDM_Odm
);
u4Byte ODM_Get_Rate_Bitmap(
u32 ODM_Get_Rate_Bitmap(
PDM_ODM_T pDM_Odm,
u4Byte macid,
u4Byte ra_mask,
u32 macid,
u32 ra_mask,
u1Byte rssi_level);
void ODM_DMInit(PDM_ODM_T pDM_Odm);
@ -1498,7 +1498,7 @@ void
ODM_CmnInfoInit(
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
u4Byte Value
u32 Value
);
void
@ -1519,7 +1519,7 @@ ODM_CmnInfoPtrArrayHook(
void
ODM_CmnInfoUpdate(
PDM_ODM_T pDM_Odm,
u4Byte CmnInfo,
u32 CmnInfo,
u8Byte Value
);
@ -1547,7 +1547,7 @@ void
ODM_AntselStatistics_88C(
PDM_ODM_T pDM_Odm,
u1Byte MacId,
u4Byte PWDBAll,
u32 PWDBAll,
BOOLEAN isCCKrate
);

8
hal/odm_HWConfig.c
View file

@ -601,8 +601,8 @@ odm_Process_RSSIForDM(
s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave;
u1Byte isCCKrate=0;
u1Byte RSSI_max, RSSI_min, i;
u4Byte OFDM_pkt=0;
u4Byte Weighting=0;
u32 OFDM_pkt=0;
u32 Weighting=0;
PSTA_INFO_T pEntry;
@ -716,7 +716,7 @@ odm_Process_RSSIForDM(
}
else
{
if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM)
if(pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM)
{
UndecoratedSmoothedOFDM =
( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
@ -747,7 +747,7 @@ odm_Process_RSSIForDM(
}
else
{
if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK)
if(pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK)
{
UndecoratedSmoothedCCK =
( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +

22
hal/odm_RTL8188E.c
View file

@ -48,7 +48,7 @@ odm_RX_HWAntDivInit(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte value32;
u32 value32;
struct adapter * Adapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1)
@ -86,7 +86,7 @@ odm_TRX_HWAntDivInit(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte value32;
u32 value32;
struct adapter * Adapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
@ -137,9 +137,9 @@ odm_FastAntTrainingInit(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte value32, i;
u32 value32, i;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u4Byte AntCombination = 2;
u32 AntCombination = 2;
struct adapter * Adapter = pDM_Odm->Adapter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n"));
@ -278,7 +278,7 @@ void
ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u4Byte DefaultAnt, OptionalAnt;
u32 DefaultAnt, OptionalAnt;
if(pDM_FatTable->RxIdleAnt != Ant)
{
@ -315,7 +315,7 @@ ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
void
odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId)
odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u32 MacId)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u1Byte TargetAnt;
@ -358,7 +358,7 @@ void
ODM_AntselStatistics_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u32 MacId,
IN u1Byte RxPWDBAll
)
{
@ -401,8 +401,8 @@ odm_HWAntDiv(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
u4Byte Main_RSSI, Aux_RSSI;
u32 i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
u32 Main_RSSI, Aux_RSSI;
u1Byte RxIdleAnt=0, TargetAnt=7;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
@ -478,7 +478,7 @@ ODM_AntennaDiversity_88E(
if(pDM_Odm->bLinked){
if(pDM_Odm->Adapter->registrypriv.force_ant != 0)
{
u4Byte Main_RSSI, Aux_RSSI;
u32 Main_RSSI, Aux_RSSI;
u8 i=0;
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
@ -600,7 +600,7 @@ odm_DynamicPrimaryCCA(
static u1Byte Client_40MHz_pre = 0;
static u8Byte lastTxOkCnt = 0;
static u8Byte lastRxOkCnt = 0;
static u4Byte Counter = 0;
static u32 Counter = 0;
static u1Byte Delay = 1;
u8Byte curTxOkCnt;
u8Byte curRxOkCnt;

2
hal/odm_RTL8188E.h
View file

@ -38,7 +38,7 @@ void ODM_SetTxAntByTxInfo_88E(PDM_ODM_T pDM_Odm, pu1Byte pDesc, u1Byte macId);
void ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant);
void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm, u1Byte antsel_tr_mux, u4Byte MacId, u1Byte RxPWDBAll);
void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm, u1Byte antsel_tr_mux, u32 MacId, u1Byte RxPWDBAll);
void odm_FastAntTraining(PDM_ODM_T pDM_Odm);

42
hal/odm_RegConfig8188E.c
View file

@ -23,10 +23,10 @@
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN u32 Addr,
IN u32 Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
IN u32 RegAddr
)
{
if(Addr == 0xffe)
@ -69,12 +69,12 @@ odm_ConfigRFReg_8188E(
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN u32 Addr,
IN u32 Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
u32 content = 0x1000; // RF_Content: radioa_txt
u32 maskforPhySet= (u32)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
@ -84,12 +84,12 @@ odm_ConfigRF_RadioA_8188E(
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN u32 Addr,
IN u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
u32 content = 0x1001; // RF_Content: radiob_txt
u32 maskforPhySet= (u32)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
@ -100,7 +100,7 @@ odm_ConfigRF_RadioB_8188E(
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u32 Addr,
IN u1Byte Data
)
{
@ -111,9 +111,9 @@ odm_ConfigMAC_8188E(
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN u32 Addr,
IN u32 Bitmask,
IN u32 Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
@ -126,9 +126,9 @@ odm_ConfigBB_AGC_8188E(
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN u32 Addr,
IN u32 Bitmask,
IN u32 Data
)
{
if (Addr == 0xfe){
@ -158,9 +158,9 @@ odm_ConfigBB_PHY_REG_PG_8188E(
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN u32 Addr,
IN u32 Bitmask,
IN u32 Data
)
{
if (Addr == 0xfe){

34
hal/odm_RegConfig8188E.h
View file

@ -23,55 +23,55 @@
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN u32 Addr,
IN u32 Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
IN u32 RegAddr
);
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN u32 Addr,
IN u32 Data
);
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN u32 Addr,
IN u32 Data
);
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u32 Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN u32 Addr,
IN u32 Bitmask,
IN u32 Data
);
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN u32 Addr,
IN u32 Bitmask,
IN u32 Data
);
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN u32 Addr,
IN u32 Bitmask,
IN u32 Data
);
#endif // end of SUPPORT

80
hal/odm_interface.c
View file

@ -30,7 +30,7 @@
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
IN u32 RegAddr
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -41,17 +41,17 @@ ODM_Read1Byte(
u16
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
IN u32 RegAddr
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
return rtw_read16(Adapter,RegAddr);
}
u4Byte
u32
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
IN u32 RegAddr
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -61,7 +61,7 @@ ODM_Read4Byte(
void
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u32 RegAddr,
IN u1Byte Data
)
{
@ -72,7 +72,7 @@ ODM_Write1Byte(
void
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u32 RegAddr,
IN u16 Data
)
{
@ -83,8 +83,8 @@ ODM_Write2Byte(
void
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
IN u32 RegAddr,
IN u32 Data
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -94,20 +94,20 @@ ODM_Write4Byte(
void
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
}
u4Byte
u32
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
IN u32 RegAddr,
IN u32 BitMask
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -117,9 +117,9 @@ ODM_GetMACReg(
void
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -127,11 +127,11 @@ ODM_SetBBReg(
}
u4Byte
u32
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
IN u32 RegAddr,
IN u32 BitMask
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -142,21 +142,21 @@ void
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
}
u4Byte
u32
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
IN u32 RegAddr,
IN u32 BitMask
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -170,7 +170,7 @@ void
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT void * *pPtr,
IN u4Byte length
IN u32 length
)
{
*pPtr = rtw_zvmalloc(length);
@ -181,7 +181,7 @@ void
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT void * pPtr,
IN u4Byte length
IN u32 length
)
{
rtw_vmfree(pPtr, length);
@ -191,7 +191,7 @@ s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN void * pBuf1,
IN void * pBuf2,
IN u4Byte length
IN u32 length
)
{
return _rtw_memcmp(pBuf1,pBuf2,length);
@ -270,32 +270,32 @@ ODM_IsWorkItemScheduled(
//
void
ODM_StallExecution(
IN u4Byte usDelay
IN u32 usDelay
)
{
rtw_udelay_os(usDelay);
}
void
ODM_delay_ms(IN u4Byte ms)
ODM_delay_ms(IN u32 ms)
{
rtw_mdelay_os(ms);
}
void
ODM_delay_us(IN u4Byte us)
ODM_delay_us(IN u32 us)
{
rtw_udelay_os(us);
}
void
ODM_sleep_ms(IN u4Byte ms)
ODM_sleep_ms(IN u32 ms)
{
rtw_msleep_os(ms);
}
void
ODM_sleep_us(IN u4Byte us)
ODM_sleep_us(IN u32 us)
{
rtw_usleep_os(us);
}
@ -304,7 +304,7 @@ void
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
IN u32 msDelay
)
{
_set_timer(pTimer,msDelay ); //ms
@ -343,13 +343,13 @@ ODM_ReleaseTimer(
//
// ODM FW relative API.
//
u4Byte
u32
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN u32 H2CBufferLen,
IN u32 CmdNum,
IN u32 * pElementID,
IN u32 * pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
)

80
hal/odm_interface.h
View file

@ -94,87 +94,87 @@ typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext);
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
IN u32 RegAddr
);
u16
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
IN u32 RegAddr
);
u4Byte
u32
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
IN u32 RegAddr
);
void
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u32 RegAddr,
IN u1Byte Data
);
void
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u32 RegAddr,
IN u16 Data
);
void
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
IN u32 RegAddr,
IN u32 Data
);
void
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u4Byte
u32
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
IN u32 RegAddr,
IN u32 BitMask
);
void
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u4Byte
u32
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
IN u32 RegAddr,
IN u32 BitMask
);
void
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u4Byte
u32
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
IN u32 RegAddr,
IN u32 BitMask
);
@ -185,20 +185,20 @@ void
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT void * *pPtr,
IN u4Byte length
IN u32 length
);
void
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT void * pPtr,
IN u4Byte length
IN u32 length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN void * pBuf1,
IN void * pBuf2,
IN u4Byte length
IN u32 length
);
//
@ -259,27 +259,27 @@ ODM_IsWorkItemScheduled(
//
void
ODM_StallExecution(
IN u4Byte usDelay
IN u32 usDelay
);
void
ODM_delay_ms(IN u4Byte ms);
ODM_delay_ms(IN u32 ms);
void
ODM_delay_us(IN u4Byte us);
ODM_delay_us(IN u32 us);
void
ODM_sleep_ms(IN u4Byte ms);
ODM_sleep_ms(IN u32 ms);
void
ODM_sleep_us(IN u4Byte us);
ODM_sleep_us(IN u32 us);
void
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
IN u32 msDelay
);
void
@ -307,13 +307,13 @@ ODM_ReleaseTimer(
//
// ODM FW relative API.
//
u4Byte
u32
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN u32 H2CBufferLen,
IN u32 CmdNum,
IN u32 * pElementID,
IN u32 * pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
);

3
hal/odm_types.h
View file

@ -56,9 +56,6 @@ typedef enum _RT_SPINLOCK_TYPE{
#define u1Byte u8
#define pu1Byte u8*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*

38
hal/rtl8188e_phycfg.c
View file

@ -62,10 +62,10 @@
* OverView: Get shifted position of the BitMask
*
* Input:
* u4Byte BitMask,
* u32 BitMask,
*
* Output: none
* Return: u4Byte Return the shift bit bit position of the mask
* Return: u32 Return the shift bit bit position of the mask
*/
static u32
phy_CalculateBitShift(
@ -338,11 +338,11 @@ SIC_LedOff(
*
* Input:
* struct adapter * Adapter,
* u4Byte RegAddr, //The target address to be readback
* u4Byte BitMask //The target bit position in the target address
* u32 RegAddr, //The target address to be readback
* u32 BitMask //The target bit position in the target address
* //to be readback
* Output: None
* Return: u4Byte Data //The readback register value
* Return: u32 Data //The readback register value
* Note: This function is equal to "GetRegSetting" in PHY programming guide
*/
u32
@ -384,10 +384,10 @@ rtl8188e_PHY_QueryBBReg(
*
* Input:
* struct adapter * Adapter,
* u4Byte RegAddr, //The target address to be modified
* u4Byte BitMask //The target bit position in the target address
* u32 RegAddr, //The target address to be modified
* u32 BitMask //The target bit position in the target address
* //to be modified
* u4Byte Data //The new register value in the target bit position
* u32 Data //The new register value in the target bit position
* //of the target address
*
* Output: None
@ -443,10 +443,10 @@ rtl8188e_PHY_SetBBReg(
* Input:
* struct adapter * Adapter,
* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
* u4Byte Offset, //The target address to be read
* u32 Offset, //The target address to be read
*
* Output: None
* Return: u4Byte reback value
* Return: u32 reback value
* Note: Threre are three types of serial operations:
* 1. Software serial write
* 2. Hardware LSSI-Low Speed Serial Interface
@ -536,8 +536,8 @@ phy_RFSerialRead(
* Input:
* struct adapter * Adapter,
* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
* u4Byte Offset, //The target address to be read
* u4Byte Data //The new register Data in the target bit position
* u32 Offset, //The target address to be read
* u32 Data //The new register Data in the target bit position
* //of the target to be read
*
* Output: None
@ -610,12 +610,12 @@ phy_RFSerialWrite(
* Input:
* struct adapter * Adapter,
* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
* u4Byte RegAddr, //The target address to be read
* u4Byte BitMask //The target bit position in the target address
* u32 RegAddr, //The target address to be read
* u32 BitMask //The target bit position in the target address
* //to be read
*
* Output: None
* Return: u4Byte Readback value
* Return: u32 Readback value
* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
*/
u32
@ -651,10 +651,10 @@ rtl8188e_PHY_QueryRFReg(
* Input:
* struct adapter * Adapter,
* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
* u4Byte RegAddr, //The target address to be modified
* u4Byte BitMask //The target bit position in the target address
* u32 RegAddr, //The target address to be modified
* u32 BitMask //The target bit position in the target address
* //to be modified
* u4Byte Data //The new register Data in the target bit position
* u32 Data //The new register Data in the target bit position
* //of the target address
*
* Output: None
@ -2310,7 +2310,7 @@ _PHY_SetBWMode92C(
//return;
// Added it for 20/40 mhz switch time evaluation by guangan 070531
//u4Byte NowL, NowH;
//u32 NowL, NowH;
//u8Byte BeginTime, EndTime;
/*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \

2
hal/rtl8188e_rf6052.c
View file

@ -343,7 +343,7 @@ void getTxPowerWriteValByRegulatory88E(
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
s1Byte pwr_diff=0;
u4Byte writeVal, customer_limit, rf;
u32 writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory;
//

2
hal/rtl8188e_xmit.c
View file

@ -135,7 +135,7 @@ InsertEMContent_8188E(
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
u1Byte index=0;
u4Byte dwtmp=0;
u32 dwtmp=0;
#endif
_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);

4
hal/usb_halinit.c
View file

@ -666,7 +666,7 @@ _InitWMACSetting(
IN struct adapter *Adapter
)
{
//u4Byte value32;
//u32 value32;
//u16 value16;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -4299,7 +4299,7 @@ void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rssi_level
//to do
/*
*(pu4Byte)&RateMask=EF4Byte((ratr_bitmap&0x0fffffff) | (ratr_index<<28));
*(u32 *)&RateMask=EF4Byte((ratr_bitmap&0x0fffffff) | (ratr_index<<28));
RateMask[4] = macId | (bShortGI?0x20:0x00) | 0x80;
*/
rtl8188e_set_raid_cmd(padapter, mask);

4
include/rtw_bt_mp.h
View file

@ -47,12 +47,12 @@ typedef enum _MP_BT_MODE{
// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER
typedef struct _BT_TXRX_PARAMETERS{
u1Byte txrxChannel;
u4Byte txrxTxPktCnt;
u32 txrxTxPktCnt;
u1Byte txrxTxPktInterval;
u1Byte txrxPayloadType;
u1Byte txrxPktType;
u16 txrxPayloadLen;
u4Byte txrxPktHeader;
u32 txrxPktHeader;
u1Byte txrxWhitenCoeff;
u1Byte txrxBdaddr[6];
u1Byte txrxTxGainIndex;

5
include/rtw_mp.h
View file

@ -161,14 +161,11 @@ struct mp_tx
#define MP_MAX_LINES_BYTES 256
#define u1Byte u8
#define s1Byte s8
#define u4Byte u32
#define u32 u32
#define s4Byte s32
#define u1Byte u8
#define pu1Byte u8*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*