mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-10 15:39:38 +00:00
8aad1f53ce
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
611 lines
21 KiB
C
Executable file
611 lines
21 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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//============================================================
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// include files
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//============================================================
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#include "odm_precomp.h"
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void
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ODM_DIG_LowerBound_88E(
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IN PDM_ODM_T pDM_Odm
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)
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{
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pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
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if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
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{
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pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
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}
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//If only one Entry connected
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}
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#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
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void
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odm_RX_HWAntDivInit(
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IN PDM_ODM_T pDM_Odm
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)
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{
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u32 value32;
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struct adapter * Adapter = pDM_Odm->Adapter;
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#if (MP_DRIVER == 1)
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if (*(pDM_Odm->mp_mode) == 1)
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{
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pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
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return;
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}
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#endif
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n"));
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//MAC Setting
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value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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//Pin Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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//OFDM Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
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//CCK Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
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ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table
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//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
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//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
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}
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void
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odm_TRX_HWAntDivInit(
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IN PDM_ODM_T pDM_Odm
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)
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{
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u32 value32;
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struct adapter * Adapter = pDM_Odm->Adapter;
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#if (MP_DRIVER == 1)
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if (*(pDM_Odm->mp_mode) == 1)
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{
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pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
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return;
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}
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#endif
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n"));
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//MAC Setting
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value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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//Pin Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
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ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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//OFDM Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
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//CCK Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
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//Tx Settings
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ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
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ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
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//antenna mapping table
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if(!pDM_Odm->bIsMPChip) //testchip
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{
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
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}
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else //MPchip
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001
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//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
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//ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
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}
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void
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odm_FastAntTrainingInit(
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IN PDM_ODM_T pDM_Odm
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)
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{
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u32 value32, i;
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pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
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u32 AntCombination = 2;
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struct adapter * Adapter = pDM_Odm->Adapter;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n"));
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#if (MP_DRIVER == 1)
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if (*(pDM_Odm->mp_mode) == 1)
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{
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
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return;
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}
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#endif
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for(i=0; i<6; i++)
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{
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pDM_FatTable->Bssid[i] = 0;
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pDM_FatTable->antSumRSSI[i] = 0;
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pDM_FatTable->antRSSIcnt[i] = 0;
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pDM_FatTable->antAveRSSI[i] = 0;
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}
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pDM_FatTable->TrainIdx = 0;
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pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
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//MAC Setting
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value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
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value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
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ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
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//value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
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//PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
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//Match MAC ADDR
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ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
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ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
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ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
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ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
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ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
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ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
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//antenna mapping table
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if(AntCombination == 2)
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{
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if(!pDM_Odm->bIsMPChip) //testchip
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{
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
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}
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else //MPchip
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{
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
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}
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}
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else if(AntCombination == 7)
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{
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if(!pDM_Odm->bIsMPChip) //testchip
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{
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
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ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
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ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
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}
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else //MPchip
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{
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2);
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ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3);
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ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4);
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ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5);
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ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6);
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ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7);
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}
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}
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//Default Ant Setting when no fast training
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ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
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//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX
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//Enter Traing state
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ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
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//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
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//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
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//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
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ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
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//SW Control
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//PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
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//PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
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//PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
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//PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
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//PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
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//PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
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}
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void
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ODM_AntennaDiversityInit_88E(
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IN PDM_ODM_T pDM_Odm
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)
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{
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/*
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//2012.03.27 LukeLee: For temp use, should be removed later
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//pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
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//{
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struct adapter * Adapter = pDM_Odm->Adapter;
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HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
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//pHalData->AntDivCfg = 1;
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//}
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*/
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if(pDM_Odm->SupportICType != ODM_RTL8188E)
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return;
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//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n",
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// pDM_Odm->AntDivType, pHalData->AntDivCfg));
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType));
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE")));
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if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
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odm_RX_HWAntDivInit(pDM_Odm);
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else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
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odm_TRX_HWAntDivInit(pDM_Odm);
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else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
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odm_FastAntTrainingInit(pDM_Odm);
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}
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void
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ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
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{
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pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
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u32 DefaultAnt, OptionalAnt;
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if(pDM_FatTable->RxIdleAnt != Ant)
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{
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n"));
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if(Ant == MAIN_ANT)
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{
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DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX;
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OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX;
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}
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else
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{
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DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX;
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OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX;
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}
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if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
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{
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX
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ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx
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}
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else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
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{
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
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}
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}
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pDM_FatTable->RxIdleAnt = Ant;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
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printk("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
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}
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void
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odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u32 MacId)
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{
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pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
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u1Byte TargetAnt;
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if(Ant == MAIN_ANT)
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TargetAnt = MAIN_ANT_CG_TRX;
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else
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TargetAnt = AUX_ANT_CG_TRX;
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pDM_FatTable->antsel_a[MacId] = TargetAnt&BIT0;
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pDM_FatTable->antsel_b[MacId] = (TargetAnt&BIT1)>>1;
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pDM_FatTable->antsel_c[MacId] = (TargetAnt&BIT2)>>2;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Tx from TxInfo, TargetAnt=%s\n",
|
|
(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",
|
|
pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));
|
|
}
|
|
|
|
void
|
|
ODM_SetTxAntByTxInfo_88E(
|
|
IN PDM_ODM_T pDM_Odm,
|
|
IN pu1Byte pDesc,
|
|
IN u1Byte macId
|
|
)
|
|
{
|
|
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
|
|
|
if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
|
|
{
|
|
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
|
|
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
|
|
SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
|
|
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
|
|
// macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
|
|
}
|
|
}
|
|
|
|
void
|
|
ODM_AntselStatistics_88E(
|
|
IN PDM_ODM_T pDM_Odm,
|
|
IN u1Byte antsel_tr_mux,
|
|
IN u32 MacId,
|
|
IN u1Byte RxPWDBAll
|
|
)
|
|
{
|
|
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
|
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
|
{
|
|
if(antsel_tr_mux == MAIN_ANT_CG_TRX)
|
|
{
|
|
|
|
pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
|
|
pDM_FatTable->MainAnt_Cnt[MacId]++;
|
|
}
|
|
else
|
|
{
|
|
pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
|
|
pDM_FatTable->AuxAnt_Cnt[MacId]++;
|
|
|
|
}
|
|
}
|
|
else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
|
|
{
|
|
if(antsel_tr_mux == MAIN_ANT_CGCS_RX)
|
|
{
|
|
|
|
pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
|
|
pDM_FatTable->MainAnt_Cnt[MacId]++;
|
|
}
|
|
else
|
|
{
|
|
pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
|
|
pDM_FatTable->AuxAnt_Cnt[MacId]++;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
#define TX_BY_REG 0
|
|
void
|
|
odm_HWAntDiv(
|
|
IN PDM_ODM_T pDM_Odm
|
|
)
|
|
{
|
|
u32 i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
|
|
u32 Main_RSSI, Aux_RSSI;
|
|
u1Byte RxIdleAnt=0, TargetAnt=7;
|
|
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
|
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
|
|
BOOLEAN bMatchBSSID;
|
|
BOOLEAN bPktFilterMacth = FALSE;
|
|
PSTA_INFO_T pEntry;
|
|
|
|
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
|
|
{
|
|
pEntry = pDM_Odm->pODM_StaInfo[i];
|
|
if(IS_STA_VALID(pEntry))
|
|
{
|
|
//2 Caculate RSSI per Antenna
|
|
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
|
|
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
|
|
TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT;
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i]));
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
|
|
|
|
//2 Select MaxRSSI for DIG
|
|
LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
|
|
if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
|
|
AntDivMaxRSSI = LocalMaxRSSI;
|
|
if(LocalMaxRSSI > MaxRSSI)
|
|
MaxRSSI = LocalMaxRSSI;
|
|
|
|
//2 Select RX Idle Antenna
|
|
if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
|
|
Main_RSSI = Aux_RSSI;
|
|
else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
|
|
Aux_RSSI = Main_RSSI;
|
|
|
|
LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;
|
|
if(LocalMinRSSI < MinRSSI)
|
|
{
|
|
MinRSSI = LocalMinRSSI;
|
|
RxIdleAnt = TargetAnt;
|
|
}
|
|
#if TX_BY_REG
|
|
|
|
#else
|
|
//2 Select TRX Antenna
|
|
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
|
odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i);
|
|
#endif
|
|
}
|
|
pDM_FatTable->MainAnt_Sum[i] = 0;
|
|
pDM_FatTable->AuxAnt_Sum[i] = 0;
|
|
pDM_FatTable->MainAnt_Cnt[i] = 0;
|
|
pDM_FatTable->AuxAnt_Cnt[i] = 0;
|
|
}
|
|
|
|
//2 Set RX Idle Antenna
|
|
ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt);
|
|
|
|
pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
|
|
pDM_DigTable->RSSI_max = MaxRSSI;
|
|
}
|
|
|
|
void
|
|
ODM_AntennaDiversity_88E(
|
|
IN PDM_ODM_T pDM_Odm
|
|
)
|
|
{
|
|
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
|
if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
|
|
{
|
|
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n"));
|
|
return;
|
|
}
|
|
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
|
|
if(pDM_Odm->bLinked){
|
|
if(pDM_Odm->Adapter->registrypriv.force_ant != 0)
|
|
{
|
|
u32 Main_RSSI, Aux_RSSI;
|
|
u8 i=0;
|
|
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
|
|
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
|
|
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i]));
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
|
|
pDM_FatTable->MainAnt_Sum[i] = 0;
|
|
pDM_FatTable->AuxAnt_Sum[i] = 0;
|
|
pDM_FatTable->MainAnt_Cnt[i] = 0;
|
|
pDM_FatTable->AuxAnt_Cnt[i] = 0;
|
|
}
|
|
if(pDM_Odm->Adapter->registrypriv.force_ant==1){
|
|
ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
|
|
printk("%s fixed antenna in Main ant\n",__FUNCTION__);
|
|
return;
|
|
}
|
|
else if(pDM_Odm->Adapter->registrypriv.force_ant==2){
|
|
ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT);
|
|
printk("%s fixed antenna in AUX ant\n",__FUNCTION__);
|
|
return;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
|
|
if(!pDM_Odm->bLinked)
|
|
{
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n"));
|
|
if(pDM_FatTable->bBecomeLinked == TRUE)
|
|
{
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv
|
|
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
|
|
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
|
|
}
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
if(pDM_FatTable->bBecomeLinked ==FALSE)
|
|
{
|
|
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
|
|
//Because HW AntDiv is disabled before Link, we enable HW AntDiv after link
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv
|
|
//ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv
|
|
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
|
|
{
|
|
#if TX_BY_REG
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg
|
|
#else
|
|
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
|
|
#endif
|
|
}
|
|
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV))
|
|
odm_HWAntDiv(pDM_Odm);
|
|
}
|
|
|
|
|
|
#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
|
|
void
|
|
ODM_SetTxAntByTxInfo_88E(
|
|
IN PDM_ODM_T pDM_Odm,
|
|
IN pu1Byte pDesc,
|
|
IN u1Byte macId
|
|
)
|
|
{
|
|
}
|
|
#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
|
|
//3============================================================
|
|
//3 Dynamic Primary CCA
|
|
//3============================================================
|
|
|
|
void
|
|
odm_PrimaryCCA_Init(
|
|
IN PDM_ODM_T pDM_Odm)
|
|
{
|
|
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
|
|
PrimaryCCA->DupRTS_flag = 0;
|
|
PrimaryCCA->intf_flag = 0;
|
|
PrimaryCCA->intf_type = 0;
|
|
PrimaryCCA->Monitor_flag = 0;
|
|
PrimaryCCA->PriCCA_flag = 0;
|
|
}
|
|
|
|
BOOLEAN
|
|
ODM_DynamicPrimaryCCA_DupRTS(
|
|
IN PDM_ODM_T pDM_Odm
|
|
)
|
|
{
|
|
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
|
|
|
|
return PrimaryCCA->DupRTS_flag;
|
|
}
|
|
|
|
void
|
|
odm_DynamicPrimaryCCA(
|
|
IN PDM_ODM_T pDM_Odm
|
|
)
|
|
{
|
|
struct adapter *Adapter = pDM_Odm->Adapter; // for NIC
|
|
prtl8192cd_priv priv = pDM_Odm->priv; // for AP
|
|
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
|
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
|
|
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
|
|
BOOLEAN Is40MHz;
|
|
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW
|
|
BOOLEAN bConnected = FALSE; // connected or not
|
|
static u1Byte Client_40MHz_pre = 0;
|
|
static u8Byte lastTxOkCnt = 0;
|
|
static u8Byte lastRxOkCnt = 0;
|
|
static u32 Counter = 0;
|
|
static u1Byte Delay = 1;
|
|
u8Byte curTxOkCnt;
|
|
u8Byte curRxOkCnt;
|
|
u1Byte SecCHOffset;
|
|
u1Byte i;
|
|
|
|
return;
|
|
}
|