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rtl8188eu: Remove dead code inside #if 0

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2014-12-28 20:00:11 -06:00
parent 2d60bad9ad
commit b6b121512b
56 changed files with 121 additions and 6115 deletions
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37
hal/Hal8188ERateAdaptive.c
View file

@ -61,32 +61,22 @@ static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate
static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
#if 0
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SS<TH
4,4,5,5,6,0x0a,0x11,0x13,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SS<TH
0x0e,0x0f,0x10,0x10,0x11,0x14,0x14,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SS<TH
0x0e,0x0f,0x10,0x10,0x11,0x14,0x14,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x10,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x14, // SS>TH
0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
0,0,0,0,0,0x24,0x26,0x2a,
0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};
0,0,0,0,0,0x24,0x26,0x2a,
0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};
#else
// wilson modify
@ -124,13 +114,6 @@ static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
2,2,3,3,4,4,5,7,
4,4,7,10,10,12,12,18,
5,7,7,8,11,18,36,60}; // 0329 // 1207
#if 0
static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30,
30,30,25,25,20,15,15,10,
30,25,25,20,15,10,10,10,
30,25,25,20,15,10,10,10};
#endif
static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
1,2,3,4,5,6,7,8,
1,2,3,4,5,6,7,8,

39
hal/HalHWImg8188E_FW.c
View file

@ -17,9 +17,6 @@
*
*
******************************************************************************/
#if 0
#include "Mp_Precomp.h"
#endif
#include "../odm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
@ -46,25 +43,6 @@ ODM_ReadFirmware_8188E_FW_AP(
#else
#if 0
u1Byte Array_8188E_FW_NIC[] = {
};
u4Byte ArrayLength_8188E_FW_NIC = 0;
void
ODM_ReadFirmware_8188E_FW_NIC(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
)
{
ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_NIC, ArrayLength_8188E_FW_NIC);
*pFirmwareSize = ArrayLength_8188E_FW_NIC;
}
#endif
const u8 Array_8188E_FW_WoWLAN[] = {
0xE1, 0x88, 0x30, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x06, 0x27, 0x15, 0x23, 0xC8, 0x3A, 0x00, 0x00,
0x6E, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@ -1010,24 +988,7 @@ const u8 Array_8188E_FW_WoWLAN[] = {
0x13, 0x01, 0x75, 0x14, 0x82, 0x75, 0x15, 0xFD, 0x75, 0x16, 0x03, 0x90, 0x82, 0xF9, 0x12, 0x42,
0x4A, 0x12, 0x2B, 0xED, 0x22, 0x00, 0xDB, 0x90,
};
#if 0
u4Byte ArrayLength_8188E_FW_WoWLAN = 15554;
void
ODM_ReadFirmware_8188E_FW_WoWLAN(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
)
{
ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_WoWLAN, ArrayLength_8188E_FW_WoWLAN);
*pFirmwareSize = ArrayLength_8188E_FW_WoWLAN;
}
#endif
#endif // end of DM_ODM_SUPPORT_TYPE & (ODM_AP)
#endif // end of HWIMG_SUPPORT

19
hal/HalHWImg8188E_FW.h
View file

@ -36,27 +36,8 @@ ODM_ReadFirmware_8188E_FW_AP(
#else
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
#if 0
void
ODM_ReadFirmware_8188E_FW_NIC(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
#if 0
void
ODM_ReadFirmware_8188E_FW_WoWLAN(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
#define ArrayLength_8188E_FW_WoWLAN 15080
extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
#endif

6
hal/HalPhyRf.c
View file

@ -799,12 +799,6 @@ phy_APCalibrate_8192C(
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
};
#if 0
u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
{0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
{0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
};
#endif
u4Byte AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on

64
hal/HalPhyRf_8188e.c
View file

@ -699,20 +699,8 @@ phy_PathA_IQK_8188E(
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
#if 0
if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
else
RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
#endif
return result;
}
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK(
@ -852,15 +840,6 @@ phy_PathA_RxIQK(
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );
#if 0
if(!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
#endif
if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
@ -869,10 +848,6 @@ phy_PathA_RxIQK(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n"));
return result;
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
@ -1665,15 +1640,6 @@ else
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
break;
}
#if 0
else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
{
RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
}
#endif
}
for(i = 0 ; i < retryCount ; i++){
@ -2479,22 +2445,7 @@ if (*(pDM_Odm->mp_mode) == 1)
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
#if 0//Suggested by Edlu,120413
// IQK on channel 7, should switch back when completed.
//originChannel = pHalData->CurrentChannel;
originChannel = *(pDM_Odm->pChannel);
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK);
#endif
#endif
for(i = 0; i < 8; i++)
{
for(i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
result[2][i] = 0;
@ -2657,19 +2608,8 @@ if (*(pDM_Odm->mp_mode) == 1)
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
#if 0 //Suggested by Edlu,120413
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel);
#endif
#endif
}
VOID
PHY_LCCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)

423
hal/odm.c
View file

@ -727,42 +727,6 @@ odm_HwAntDiv(
IN PDM_ODM_T pDM_Odm
);
#if 0
//#if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&defined(HW_ANT_SWITCH))
VOID
odm_HW_AntennaSwitchInit(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_SetRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
odm_StaAntSelect(
IN PDM_ODM_T pDM_Odm,
IN struct stat_info *pstat
);
VOID
odm_HW_IdleAntennaSelect(
IN PDM_ODM_T pDM_Odm
);
u1Byte
ODM_Diversity_AntennaSelect(
IN PDM_ODM_T pDM_Odm,
IN u1Byte *data
);
#endif
//============================================================
//3 Export Interface
//============================================================
@ -1733,13 +1697,6 @@ odm_DIGbyRSSI_LPS(
struct adapter * pAdapter =pDM_Odm->Adapter;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
#if 0 //and 2.3.5 coding rule
struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
#endif
u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
u1Byte bFwCurrentInPSMode = FALSE;
u1Byte CurrentIGI=pDM_Odm->RSSI_Min;
@ -1747,9 +1704,6 @@ odm_DIGbyRSSI_LPS(
if(! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E)))
return;
//if((pDM_Odm->SupportInterface==ODM_ITRF_PCIE)||(pDM_Odm->SupportInterface ==ODM_ITRF_USB))
// return;
CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG;
#ifdef CONFIG_LPS
bFwCurrentInPSMode = adapter_to_pwrctl(pAdapter)->bFwCurrentInPSMode;
@ -2093,16 +2047,6 @@ odm_DIG(
//if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
{
#if 0
if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1))
CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30;
else
CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20;
ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
return;
}
@ -2551,38 +2495,6 @@ odm_DIG(
}
}
}
#if 0
if((pDM_Odm->SupportICType & ODM_RTL8723A)&&(pMgntInfo->CustomerID = RT_CID_LENOVO_CHINA))
{
OKCntAll = (curTxOkCnt+curRxOkCnt);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", CurrentIGI));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): OKCntAll(%#x)\n", OKCntAll));
//8723AS_VAU
if(pDM_Odm->SupportInterface==ODM_ITRF_USB)
{
if(pHalData->UndecoratedSmoothedPWDB < 12)
{
if(CurrentIGI > DM_DIG_MIN_NIC)
{
if(OKCntAll >= 1500000) // >=6Mbps
CurrentIGI=0x1B;
else if(OKCntAll >= 1000000) //4Mbps
CurrentIGI=0x1A;
else if(OKCntAll >= 500000) //2Mbps
CurrentIGI=0x19;
else if(OKCntAll >= 250000) //1Mbps
CurrentIGI=0x18;
else
{
CurrentIGI=0x17; //SCAN mode
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Modify---->CurIGValue(%#x)\n", CurrentIGI));
}
}
}
#endif
}
#endif
@ -2809,16 +2721,6 @@ odm_DIG(
//if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
{
#if 0
if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1))
CurrentIGI = 0x30; //pDM_DigTable->CurIGValue = 0x30;
else
CurrentIGI = 0x20; //pDM_DigTable->CurIGValue = 0x20;
ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
return;
}
@ -3938,26 +3840,6 @@ odm_RefreshRateAdaptiveMaskMP(
for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
{
#if 0 //By YJ,120208
if( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated)
{
pEntry = pTargetAdapter->MgntInfo.AsocEntry+i;
pEntryRA = &pEntry->RateAdaptive;
if( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) )
{
ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState));
pAdapter->HalFunc.UpdateHalRAMaskHandler(
pTargetAdapter,
FALSE,
pEntry->AID+1,
pEntry->MacAddr,
pEntry,
pEntryRA->RATRState,
RAMask_Normal);
}
}
#else
pEntry = AsocEntry_EnumStation(pTargetAdapter, i);
if(NULL != pEntry)
{
@ -3979,7 +3861,6 @@ odm_RefreshRateAdaptiveMaskMP(
}
}
}
#endif
}
}
@ -4544,22 +4425,7 @@ odm_DynamicTxPower_92C(
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
}
else // associated entry pwdb
{
@ -4801,27 +4667,11 @@ odm_DynamicTxPower_92D(
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port
{
#if 0
//todo: AP Mode
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
else
{
UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#else
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
#endif
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
else // associated entry pwdb
{
UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
//ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
}
#if TX_POWER_FOR_5G_BAND == 1
if(pHalData->CurrentBandType92D == BAND_ON_5G){
@ -5076,43 +4926,6 @@ FindMinimumRSSI_Dmsp(
IN struct adapter *pAdapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
s32 Rssi_val_min_back_for_mac0;
BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter);
BOOLEAN bRestoreRssi = _FALSE;
struct adapter *BuddyAdapter = pAdapter->BuddyAdapter;
if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
{
if(BuddyAdapter!= NULL)
{
if(pHalData->bSlaveOfDMSP)
{
//ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n"));
BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM;
}
else
{
if(bGetValueFromBuddyAdapter)
{
//ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n"));
bRestoreRssi = _TRUE;
Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM;
pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP;
}
}
}
}
if(bRestoreRssi)
{
bRestoreRssi = _FALSE;
pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0;
}
#endif
}
static void
@ -5128,17 +4941,9 @@ IN struct adapter *pAdapter
if((pDM_Odm->bLinked != _TRUE) &&
(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
{
pdmpriv->MinUndecoratedPWDBForDM = 0;
//ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n"));
}
else
{
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
}
//DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);
//ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));
}
#endif
@ -5177,11 +4982,6 @@ odm_RSSIMonitorCheckCE(
if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
#if 0
DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__,
psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB);
#endif
if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
#if(RTL8192D_SUPPORT==1)
PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
@ -7129,112 +6929,7 @@ odm_HwAntDiv(
}
#if(DM_ODM_SUPPORT_TYPE==ODM_AP)
#if 0
VOID
odm_HwAntDiv(
IN PDM_ODM_T pDM_Odm
)
{
struct rtl8192cd_priv *priv=pDM_Odm->priv;
struct stat_info *pstat, *pstat_min=NULL;
struct list_head *phead, *plist;
int rssi_min= 0xff, i;
u1Byte idleAnt=priv->pshare->rf_ft_var.CurAntenna;
u1Byte nextAnt;
BOOLEAN bRet=FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
if((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
return;
//if test, return
if(priv->pshare->rf_ft_var.CurAntenna & 0x80)
return;
phead = &priv->asoc_list;
plist = phead->next;
////=========================
//find mimum rssi sta
////=========================
while(plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) {
int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1];
if((!pstat_min) || ( rssi < rssi_min) ) {
pstat_min = pstat;
rssi_min = rssi;
}
}
///STA: found out default antenna
bRet=odm_StaDefAntSel(pDM_Odm,
pstat->hwRxAntSel[1],
pstat->hwRxAntSel[0],
pstat->cckPktCount[1],
pstat->cckPktCount[0],
&nextAnt
);
//if default antenna selection: successful
if(bRet){
pstat->CurAntenna = nextAnt;
//update rssi
for(i=0; i<2; i++) {
if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0)
pstat->AntRSSI[i] = 0;
}
if(pstat->AntRSSI[idleAnt]==0)
pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1];
// reset variables
pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0;
pstat->cckPktCount[1]= pstat->cckPktCount[0] =0;
}
if (plist == plist->next)
break;
plist = plist->next;
};
////=========================
//Choose RX Idle antenna according to minmum rssi
////=========================
if(pstat_min) {
if(priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna)
odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE);
priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna;
}
#ifdef TX_SHORTCUT
if (!priv->pmib->dot11OperationEntry.disable_txsc) {
plist = phead->next;
while(plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if(pstat->expire_to) {
for (i=0; i<TX_SC_ENTRY_NUM; i++) {
struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
}
}
if (plist == plist->next)
break;
plist = plist->next;
};
}
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n");
}
#endif
u1Byte
ODM_Diversity_AntennaSelect(
IN PDM_ODM_T pDM_Odm,
@ -7508,12 +7203,6 @@ odm_EdcaTurboCheckCE(
if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
{
#if 0
//adjust EDCA parameter for BE queue
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
#else
if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
{
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
@ -7522,8 +7211,6 @@ odm_EdcaTurboCheckCE(
{
edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
}
#endif
if(IS_92C_SERIAL(pHalData->VersionID))
edca_param = 0x60a42b;
else
@ -8433,20 +8120,6 @@ odm_IotEngine(
if ((GET_ROOT(priv)->up_time % 2) == 0)
priv->pshare->highTP_found_pstat==NULL;
#if 0
phead = &priv->asoc_list;
plist = phead->next;
while(plist != phead) {
pstat = list_entry(plist, struct stat_info, asoc_list);
if(ODM_ChooseIotMainSTA(pDM_Odm, pstat)); //find the correct station
break;
if (plist == plist->next) //the last plist
break;
plist = plist->next;
};
#endif
//find highTP STA
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
pstat = pDM_Odm->pODM_StaInfo[i];
@ -8641,25 +8314,6 @@ odm_IotEngine(
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
#if 0
if (priv->pshare->txop_enlarge != 2)
{
#if(DM_ODM_SUPPORT_TYPE==ODM_AP)
if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
#else
if (pstat->is_intel_sta)
#endif
priv->pshare->txop_enlarge = 0xe;
#if(DM_ODM_SUPPORT_TYPE==ODM_AP)
else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
priv->pshare->txop_enlarge = 0xd;
#endif
else
priv->pshare->txop_enlarge = 2;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
}
else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
@ -9326,43 +8980,8 @@ odm_PSD_Monitor(
for(i = 0; i < 80; i++)
PSD_report[i] = 0;
}
#if 0 //for test only
DbgPrint("cosa odm_PSD_Monitor call()\n");
DbgPrint("cosa pHalData->RSSI_BT = %d\n", pHalData->RSSI_BT);
DbgPrint("cosa pHalData->bUserAssignLevel = %d\n", pHalData->bUserAssignLevel);
#if 0
psd_cnt++;
if (psd_cnt < ReScan)
PlatformSetTimer( Adapter, &pHalData->PSDTimer, Interval); //ms
else
psd_cnt = 0;
return;
#endif
#endif
//1 Backup Current Settings
CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
/*
if(pDM_Odm->SupportICType==ODM_RTL8192D)
{
//2 Record Current synthesizer parameters based on current channel
if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))
{
SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord);
SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord);
SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord);
SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord);
SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord);
}
else // DualMAC_DualPHY 2G
{
SYN_RF25 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord);
SYN_RF26 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord);
SYN_RF27 = ODM_GetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord);
SYN_RF2B = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord);
SYN_RF2C = ODM_GetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord);
}
}
*/
//RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
@ -11255,18 +10874,6 @@ ODM_PathDiversityBeforeLink92C(
pDM_PDTable->OFDMTXPath = 0x0;
pDM_PDTable->CCKTXPath = 0x0;
}
#if 0
pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
RT_TRACE(COMP_SWAS, DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
#endif
// Go back to scan function again.
RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
pMgntInfo->ScanStep=0;
@ -12432,40 +12039,16 @@ void odm_dtc(PDM_ODM_T pDM_Odm)
u8 sign;
u8 resp_txagc=0;
#if 0
/* As DIG is disabled, DTC is also disable */
if(!(pDM_Odm->SupportAbility & ODM_XXXXXX))
return;
#endif
if (DTC_BASE < pDM_Odm->RSSI_Min) {
/* need to decade the CTS TX power */
sign = 1;
for (i=0;i<ARRAY_SIZE(dtc_table_down);i++)
{
for (i=0;i<ARRAY_SIZE(dtc_table_down);i++) {
if ((dtc_table_down[i] >= pDM_Odm->RSSI_Min) || (dtc_steps >= 6))
break;
else
dtc_steps++;
}
}
#if 0
else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min)
{
/* needs to increase the CTS TX power */
sign = 0;
dtc_steps = 1;
for (i=0;i<ARRAY_SIZE(dtc_table_up);i++)
{
if ((dtc_table_up[i] <= pDM_Odm->RSSI_Min) || (dtc_steps>=10))
break;
else
dtc_steps++;
}
}
#endif
else
{
} else {
sign = 0;
dtc_steps = 0;
}

54
hal/odm.h
View file

@ -504,7 +504,6 @@ typedef enum tag_Dynamic_ODM_Support_Ability_Type
// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
// Please declare below ODM relative info in your STA info structure.
//
#if 1
typedef struct _ODM_STA_INFO{
// Driver Write
BOOLEAN bUsed; // record the sta status link or not?
@ -517,52 +516,7 @@ typedef struct _ODM_STA_INFO{
u1Byte RSSI_Ave;
u1Byte RXEVM[4];
u1Byte RXSNR[4];
// ODM Write
//1 TX_INFO (may changed by IC)
//TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer.
#if 0
u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit
u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit
u1Byte ANTSEL_C; //only in Jagar: 4bit
u1Byte ANTSEL_D; //only in Jagar: 4bit
u1Byte TX_ANTL; //not in Jagar: 2bit
u1Byte TX_ANT_HT; //not in Jagar: 2bit
u1Byte TX_ANT_CCK; //not in Jagar: 2bit
u1Byte TXAGC_A; //not in Jagar: 4bit
u1Byte TXAGC_B; //not in Jagar: 4bit
u1Byte TXPWR_OFFSET; //only in Jagar: 3bit
u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK
#endif
//
// Please use compile flag to disabe the strcutrue for other IC except 88E.
// Move To lower layer.
//
// ODM Write Wilson will handle this part(said by Luke.Lee)
//TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer.
#if 0
//1 For 88E RA (don't redefine the naming)
u1Byte rate_id;
u1Byte rate_SGI;
u1Byte rssi_sta_ra;
u1Byte SGI_enable;
u1Byte Decision_rate;
u1Byte Pre_rate;
u1Byte Active;
// Driver write Wilson handle.
//1 TX_RPT (don't redefine the naming)
u2Byte RTY[4]; // ???
u2Byte TOTAL; // ???
u2Byte DROP; // ???
//
// Please use compile flag to disabe the strcutrue for other IC except 88E.
//
#endif
}ODM_STA_INFO_T, *PODM_STA_INFO_T;
#endif
} ODM_STA_INFO_T, *PODM_STA_INFO_T;
//
// 2011/10/20 MH Define Common info enum for all team.
@ -1595,12 +1549,6 @@ typedef enum tag_DIG_Connect_Definition
//3===========================================================
//3 Tx Power Tracking
//3===========================================================
#if 0 //mask this, since these have been defined in typdef.h, vivi
#define OFDM_TABLE_SIZE 37
#define OFDM_TABLE_SIZE_92D 43
#define CCK_TABLE_SIZE 33
#endif
//3===========================================================
//3 Rate Adaptive

35
hal/odm_HWConfig.c
View file

@ -990,36 +990,16 @@ ODM_PhyStatusQuery_92CSeries(
pPhyStatus,
pPktinfo);
if( pDM_Odm->RSSI_test == TRUE)
{
if( pDM_Odm->RSSI_test == TRUE) {
// Select the packets to do RSSI checking for antenna switching.
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon )
{
/*
#if 0//(DM_ODM_SUPPORT_TYPE == ODM_MP)
dm_SWAW_RSSI_Check(
Adapter,
(tmppAdapter!=NULL)?(tmppAdapter==Adapter):TRUE,
bPacketMatchBSSID,
pEntry,
pRfd);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
// Select the packets to do RSSI checking for antenna switching.
//odm_SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll);
#endif
*/
ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo);
}
}
else
{
} else {
odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo);
}
}
//
// Endianness before calling this API
//
@ -1043,16 +1023,7 @@ ODM_PhyStatusQuery(
IN PODM_PACKET_INFO_T pPktinfo
)
{
#if 0 // How to jaguar jugar series??
if(pDM_Odm->SupportICType >= ODM_RTL8195 )
{
ODM_PhyStatusQuery_JaguarSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
else
#endif
{
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
}
// For future use.

66
hal/odm_RTL8188E.c
View file

@ -524,53 +524,10 @@ odm_SetNextMACAddrTarget(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",
pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0]));
#endif
break;
}
}
}
#if 0
//
//2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn
//
#if( DM_ODM_SUPPORT_TYPE & ODM_MP)
{
struct adapter *Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
for (i=0; i<6; i++)
{
Bssid[i] = pMgntInfo->Bssid[i];
//DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);
}
}
#endif
//odm_SetNextMACAddrTarget(pDM_Odm);
//1 Select MAC Address Filter
for (i=0; i<6; i++)
{
if(Bssid[i] != pDM_FatTable->Bssid[i])
{
bMatchBSSID = FALSE;
break;
}
}
if(bMatchBSSID == FALSE)
{
//Match MAC ADDR
value32 = (Bssid[5]<<8)|Bssid[4];
ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];
ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
}
return bMatchBSSID;
#endif
}
VOID
@ -629,25 +586,12 @@ odm_FastAntTraining(
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
#if 0
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if(IS_STA_VALID(pEntry))
{
pEntry->antsel_a = TargetAnt&BIT0;
pEntry->antsel_b = (TargetAnt&BIT1)>>1;
pEntry->antsel_c = (TargetAnt&BIT2)>>2;
}
#else
pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;
pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;
pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;
#endif
if(TargetAnt == 0)
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
}
//2 Reset Counter
@ -668,16 +612,6 @@ odm_FastAntTraining(
odm_SetNextMACAddrTarget(pDM_Odm);
#if 0
pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
if(IS_STA_VALID(pEntry))
{
pEntry->antsel_a = TargetAnt&BIT0;
pEntry->antsel_b = (TargetAnt&BIT1)>>1;
pEntry->antsel_c = (TargetAnt&BIT2)>>2;
}
#endif
//2 Prepare Training
pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training

560
hal/odm_debug.c
View file

@ -63,564 +63,4 @@ pDM_Odm->DebugComponents =
0;
}
#if 0
/*------------------Declare variable-----------------------
// Define debug flag array for common debug print macro. */
u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX];
/* Define debug print header for every service module. */
ODM_DBGP_HEAD_T ODM_DBGP_Head;
/*-----------------------------------------------------------------------------
* Function: DBGP_Flag_Init
*
* Overview: Refresh all debug print control flag content to zero.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 10/20/2006 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void ODM_DBGP_Flag_Init(void)
{
u1Byte i;
for (i = 0; i < ODM_DBGP_TYPE_MAX; i++)
{
ODM_DBGP_Type[i] = 0;
}
#ifndef ADSL_AP_BUILD_WORKAROUND
#if DBG
// 2010/06/02 MH Free build driver can not out any debug message!!!
// Init Debug flag enable condition
ODM_DBGP_Type[FINIT] = \
// INIT_EEPROM |
// INIT_TxPower |
// INIT_IQK |
// INIT_RF |
0;
ODM_DBGP_Type[FDM] = \
// WA_IOT |
// DM_PWDB |
// DM_Monitor |
// DM_DIG |
// DM_EDCA_Turbo |
// DM_BT30 |
0;
ODM_DBGP_Type[FIOCTL] = \
// IOCTL_IRP |
// IOCTL_IRP_DETAIL |
// IOCTL_IRP_STATISTICS |
// IOCTL_IRP_HANDLE |
// IOCTL_BT_HCICMD |
// IOCTL_BT_HCICMD_DETAIL |
// IOCTL_BT_HCICMD_EXT |
// IOCTL_BT_EVENT |
// IOCTL_BT_EVENT_DETAIL |
// IOCTL_BT_EVENT_PERIODICAL |
// IOCTL_BT_TX_ACLDATA |
// IOCTL_BT_TX_ACLDATA_DETAIL |
// IOCTL_BT_RX_ACLDATA |
// IOCTL_BT_RX_ACLDATA_DETAIL |
// IOCTL_BT_TP |
// IOCTL_STATE |
// IOCTL_BT_LOGO |
// IOCTL_CALLBACK_FUN |
// IOCTL_PARSE_BT_PKT |
0;
ODM_DBGP_Type[FBT] = \
// BT_TRACE |
0;
ODM_DBGP_Type[FEEPROM] = \
// EEPROM_W |
// EFUSE_PG |
// EFUSE_READ_ALL |
// EFUSE_ANALYSIS |
// EFUSE_PG_DETAIL |
0;
ODM_DBGP_Type[FDBG_CTRL] = \
// DBG_CTRL_TRACE |
// DBG_CTRL_INBAND_NOISE |
0;
// 2011/07/20 MH Add for short cut
ODM_DBGP_Type[FSHORT_CUT] = \
// SHCUT_TX |
// SHCUT_RX |
0;
#endif
#endif
/* Define debug header of every service module. */
//ODM_DBGP_Head.pMANS = "\n\r[MANS] ";
//ODM_DBGP_Head.pRTOS = "\n\r[RTOS] ";
//ODM_DBGP_Head.pALM = "\n\r[ALM] ";
//ODM_DBGP_Head.pPEM = "\n\r[PEM] ";
//ODM_DBGP_Head.pCMPK = "\n\r[CMPK] ";
//ODM_DBGP_Head.pRAPD = "\n\r[RAPD] ";
//ODM_DBGP_Head.pTXPB = "\n\r[TXPB] ";
//ODM_DBGP_Head.pQUMG = "\n\r[QUMG] ";
} /* DBGP_Flag_Init */
#endif
#if 0
u4Byte GlobalDebugLevel = DBG_LOUD;
//
// 2009/06/22 MH Allow Fre build to print none debug info at init time.
//
#if DBG
u8Byte GlobalDebugComponents = \
// COMP_TRACE |
// COMP_DBG |
// COMP_INIT |
// COMP_OID_QUERY |
// COMP_OID_SET |
// COMP_RECV |
// COMP_SEND |
// COMP_IO |
// COMP_POWER |
// COMP_MLME |
// COMP_SCAN |
// COMP_SYSTEM |
// COMP_SEC |
// COMP_AP |
// COMP_TURBO |
// COMP_QOS |
// COMP_AUTHENTICATOR |
// COMP_BEACON |
// COMP_ANTENNA |
// COMP_RATE |
// COMP_EVENTS |
// COMP_FPGA |
// COMP_RM |
// COMP_MP |
// COMP_RXDESC |
// COMP_CKIP |
// COMP_DIG |
// COMP_TXAGC |
// COMP_HIPWR |
// COMP_HALDM |
// COMP_RSNA |
// COMP_INDIC |
// COMP_LED |
// COMP_RF |
// COMP_DUALMACSWITCH |
// COMP_EASY_CONCURRENT |
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
// COMP_HT |
// COMP_POWER_TRACKING |
// COMP_RX_REORDER |
// COMP_AMSDU |
// COMP_WPS |
// COMP_RATR |
// COMP_RESET |
// COMP_CMD |
// COMP_EFUSE |
// COMP_MESH_INTERWORKING |
// COMP_CCX |
// COMP_IOCTL |
// COMP_GP |
// COMP_TXAGG |
// COMP_BB_POWERSAVING |
// COMP_SWAS |
// COMP_P2P |
// COMP_MUX |
// COMP_FUNC |
// COMP_TDLS |
// COMP_OMNIPEEK |
// COMP_PSD |
0;
#else
#define FuncEntry
#define FuncExit
u8Byte GlobalDebugComponents = 0;
#endif
#if (RT_PLATFORM==PLATFORM_LINUX)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
EXPORT_SYMBOL(GlobalDebugComponents);
EXPORT_SYMBOL(GlobalDebugLevel);
#endif
#endif
/*------------------Declare variable-----------------------
// Define debug flag array for common debug print macro. */
u4Byte DBGP_Type[DBGP_TYPE_MAX];
/* Define debug print header for every service module. */
DBGP_HEAD_T DBGP_Head;
/*-----------------------------------------------------------------------------
* Function: DBGP_Flag_Init
*
* Overview: Refresh all debug print control flag content to zero.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 10/20/2006 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBGP_Flag_Init(void)
{
u1Byte i;
for (i = 0; i < DBGP_TYPE_MAX; i++)
{
DBGP_Type[i] = 0;
}
#if DBG
// 2010/06/02 MH Free build driver can not out any debug message!!!
// Init Debug flag enable condition
DBGP_Type[FINIT] = \
// INIT_EEPROM |
// INIT_TxPower |
// INIT_IQK |
// INIT_RF |
0;
DBGP_Type[FDM] = \
// WA_IOT |
// DM_PWDB |
// DM_Monitor |
// DM_DIG |
// DM_EDCA_Turbo |
// DM_BT30 |
0;
DBGP_Type[FIOCTL] = \
// IOCTL_IRP |
// IOCTL_IRP_DETAIL |
// IOCTL_IRP_STATISTICS |
// IOCTL_IRP_HANDLE |
// IOCTL_BT_HCICMD |
// IOCTL_BT_HCICMD_DETAIL |
// IOCTL_BT_HCICMD_EXT |
// IOCTL_BT_EVENT |
// IOCTL_BT_EVENT_DETAIL |
// IOCTL_BT_EVENT_PERIODICAL |
// IOCTL_BT_TX_ACLDATA |
// IOCTL_BT_TX_ACLDATA_DETAIL |
// IOCTL_BT_RX_ACLDATA |
// IOCTL_BT_RX_ACLDATA_DETAIL |
// IOCTL_BT_TP |
// IOCTL_STATE |
// IOCTL_BT_LOGO |
// IOCTL_CALLBACK_FUN |
// IOCTL_PARSE_BT_PKT |
0;
DBGP_Type[FBT] = \
// BT_TRACE |
0;
DBGP_Type[FEEPROM] = \
// EEPROM_W |
// EFUSE_PG |
// EFUSE_READ_ALL |
// EFUSE_ANALYSIS |
// EFUSE_PG_DETAIL |
0;
DBGP_Type[FDBG_CTRL] = \
// DBG_CTRL_TRACE |
// DBG_CTRL_INBAND_NOISE |
0;
// 2011/07/20 MH Add for short cut
DBGP_Type[FSHORT_CUT] = \
// SHCUT_TX |
// SHCUT_RX |
0;
#endif
/* Define debug header of every service module. */
DBGP_Head.pMANS = "\n\r[MANS] ";
DBGP_Head.pRTOS = "\n\r[RTOS] ";
DBGP_Head.pALM = "\n\r[ALM] ";
DBGP_Head.pPEM = "\n\r[PEM] ";
DBGP_Head.pCMPK = "\n\r[CMPK] ";
DBGP_Head.pRAPD = "\n\r[RAPD] ";
DBGP_Head.pTXPB = "\n\r[TXPB] ";
DBGP_Head.pQUMG = "\n\r[QUMG] ";
} /* DBGP_Flag_Init */
/*-----------------------------------------------------------------------------
* Function: DBG_PrintAllFlag
*
* Overview: Print All debug flag
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBG_PrintAllFlag(void)
{
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n"));
} // DBG_PrintAllFlag
extern void DBG_PrintAllComp(void)
{
u1Byte i;
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP ="));
for (i = 0; i < 64; i++)
{
if (GlobalDebugComponents & ((u8Byte)0x1 << i) )
{
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i));
}
}
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n"));
} // DBG_PrintAllComp
/*-----------------------------------------------------------------------------
* Function: DBG_PrintFlagEvent
*
* Overview: Print dedicated debug flag event
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBG_PrintFlagEvent(u1Byte DbgFlag)
{
switch(DbgFlag)
{
case FQoS:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n"));
break;
case FTX:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n"));
break;
case FRX:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n"));
break;
case FSEC:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
break;
case FMGNT:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
break;
case FMLME:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n"));
break;
case FRESOURCE:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n"));
break;
case FBEACON:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n"));
break;
case FISR:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n"));
break;
case FPHY:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n"));
break;
case FMP:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n"));
break;
case FEEPROM:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n"));
break;
case FPWR:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n"));
break;
case FDM:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n"));
break;
case FDBG_CTRL:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n"));
break;
case FC2H:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n"));
break;
case FBT:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n"));
break;
default:
break;
}
} // DBG_PrintFlagEvent
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len)
{
u2Byte i;
for (i=0;i<((Len>>3) + 1);i++)
{
ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n",
*(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)),
*(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7))));
}
}
#endif

726
hal/odm_debug.h
View file

@ -174,731 +174,5 @@ ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
);
#if 0
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif
#if 0
/* Define debug print header for every service module.*/
typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}ODM_DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_ODM_DBGP_Flag_Type_Definition
{
ODM_FTX = 0,
ODM_FRX ,
ODM_FPHY ,
ODM_FPWR ,
ODM_FDM ,
ODM_FC2H ,
ODM_FBT ,
ODM_DBGP_TYPE_MAX
}ODM_DBGP_FLAG_E;
// Define TX relative debug bit --> FTX
#define ODM_TX_DESC BIT0
#define ODM_TX_DESC_TID BIT1
#define ODM_TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define ODM_RX_DATA BIT0
#define ODM_RX_PHY_STS BIT1
#define ODM_RX_PHY_SS BIT2
#define ODM_RX_PHY_SQ BIT3
#define ODM_RX_PHY_ASTS BIT4
#define ODM_RX_ERR_LEN BIT5
#define ODM_RX_DEFRAG BIT6
#define ODM_RX_ERR_RATE BIT7
#define ODM_RX_PATH BIT8
#define ODM_RX_BEACON BIT9
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define ODM_PHY_BBR BIT0
#define ODM_PHY_BBW BIT1
#define ODM_PHY_RFR BIT2
#define ODM_PHY_RFW BIT3
#define ODM_PHY_MACR BIT4
#define ODM_PHY_MACW BIT5
#define ODM_PHY_ALLR BIT6
#define ODM_PHY_ALLW BIT7
#define ODM_PHY_TXPWR BIT8
#define ODM_PHY_PWRDIFF BIT9
#define ODM_PHY_SICR BIT10
#define ODM_PHY_SICW BIT11
extern u4Byte ODM_GlobalDebugLevel;
#if DBG
extern u8Byte ODM_GlobalDebugComponents;
#endif
#endif
#if 0
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
//
#define DBG_OFF 0
//
// Deprecated! Don't use it!
// TODO: fix related debug message!
//
//#define DBG_SEC 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
#define COMP_TRACE BIT0 // For function call tracing.
#define COMP_DBG BIT1 // Only for temporary debug message.
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
#define COMP_OID_QUERY BIT3 // Query OID.
#define COMP_OID_SET BIT4 // Set OID.
#define COMP_RECV BIT5 // Reveive part data path.
#define COMP_SEND BIT6 // Send part path.
#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02.
#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related.
#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS.
#define COMP_SCAN BIT10 // For site survey.
#define COMP_SYSTEM BIT11 // For general platform function.
#define COMP_SEC BIT12 // For Security.
#define COMP_AP BIT13 // For AP mode related.
#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21.
#define COMP_QOS BIT15 // For QoS.
#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30.
#define COMP_BEACON BIT17 // For Beacon related, by rcnjko.
#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko.
#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
#define COMP_EVENTS BIT20 // Event handling
#define COMP_FPGA BIT21 // For FPGA verfication
#define COMP_RM BIT22 // For Radio Measurement.
#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13
#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko.
#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko.
#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko.
#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW.
#define COMP_INDIC BIT31 // For link indication
#define COMP_LED BIT32 // For LED.
#define COMP_RF BIT33 // For RF.
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11
#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING
#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder
#define COMP_AMSDU BIT37 // For A-MSDU Debugging
#define COMP_WPS BIT38 //WPS Debug Message
#define COMP_RATR BIT39
#define COMP_RESET BIT40
// For debug command to print on dbgview!!
#define COMP_CMD BIT41
#define COMP_EFUSE BIT42
#define COMP_MESH_INTERWORKING BIT43
#define COMP_CCX BIT44 //CCX Debug Flag
#define COMP_IOCTL BIT45 // IO Control
#define COMP_GP BIT46 // For generic parser.
#define COMP_TXAGG BIT47
#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
#define COMP_TEST BIT49
#define COMP_BB_POWERSAVING BIT50
#define COMP_SWAS BIT51 // For SW Antenna Switch
#define COMP_P2P BIT52
#define COMP_MUX BIT53
#define COMP_FUNC BIT54
#define COMP_TDLS BIT55
#define COMP_OMNIPEEK BIT56
#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug
#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug
#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH
#define COMP_DFS BIT62
#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
// For debug print flag to use
/*------------------------------Define structure----------------------------*/
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/* Defnie structure to store different debug flag variable. Every debug flag
is a UINT32 integer and you can assign 32 different events. */
typedef struct tag_DBGP_Debug_Flag_Structure
{
u4Byte Mans; /* Main Scheduler module. */
u4Byte Rtos; /* RTOS module. */
u4Byte Alarm; /* Alarm module. */
u4Byte Pm; /* Performance monitor module. */
}DBGP_FLAG_T;
/* Define debug print header for every service module.*/
typedef struct tag_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_DBGP_Flag_Type_Definition
{
FQoS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBG_CTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
FSHORT_CUT = 19,
DBGP_TYPE_MAX
}DBGP_FLAG_E;
// Define Qos Relative debug flag bit --> FQoS
#define QoS_INIT BIT0
#define QoS_VISTA BIT1
// Define TX relative debug bit --> FTX
#define TX_DESC BIT0
#define TX_DESC_TID BIT1
#define TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define RX_DATA BIT0
#define RX_PHY_STS BIT1
#define RX_PHY_SS BIT2
#define RX_PHY_SQ BIT3
#define RX_PHY_ASTS BIT4
#define RX_ERR_LEN BIT5
#define RX_DEFRAG BIT6
#define RX_ERR_RATE BIT7
#define RX_PATH BIT8
#define RX_BEACON BIT9
// Define Security relative debug bit --> FSEC
// Define MGNT relative debug bit --> FMGNT
// Define MLME relative debug bit --> FMLME
#define MEDIA_STS BIT0
#define LINK_STS BIT1
// Define OS resource check module bit --> FRESOURCE
#define OS_CHK BIT0
// Define beacon content check module bit --> FBEACON
#define BCN_SHOW BIT0
#define BCN_PEER BIT1
// Define ISR/IMR check module bit --> FISR
#define ISR_CHK BIT0
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define PHY_BBR BIT0
#define PHY_BBW BIT1
#define PHY_RFR BIT2
#define PHY_RFW BIT3
#define PHY_MACR BIT4
#define PHY_MACW BIT5
#define PHY_ALLR BIT6
#define PHY_ALLW BIT7
#define PHY_TXPWR BIT8
#define PHY_PWRDIFF BIT9
#define PHY_SICR BIT10
#define PHY_SICW BIT11
// Define MPT driver check module bit --> FMP
#define MP_RX BIT0
#define MP_SWICH_CH BIT1
// Define EEPROM and EFUSE check module bit --> FEEPROM
#define EEPROM_W BIT0
#define EFUSE_PG BIT1
#define EFUSE_READ_ALL BIT2
#define EFUSE_ANALYSIS BIT3
#define EFUSE_PG_DETAIL BIT4
// Define power save check module bit --> FPWR
#define LPS BIT0
#define IPS BIT1
#define PWRSW BIT2
#define PWRHW BIT3
#define PWRHAL BIT4
// Define Dynamic Mechanism check module bit --> FDM
#define WA_IOT BIT0
#define DM_PWDB BIT1
#define DM_Monitor BIT2
#define DM_DIG BIT3
#define DM_EDCA_Turbo BIT4
#define DM_BT30 BIT5
// Define Dbg Control module bit --> FDBG_CTRL
#define DBG_CTRL_TRACE BIT0
#define DBG_CTRL_INBAND_NOISE BIT1
// Define FW C2H Cmd check module bit --> FC2H
#define C2H_Summary BIT0
#define C2H_PacketData BIT1
#define C2H_ContentData BIT2
// Define BT Cmd check module bit --> FBT
#define BT_TRACE BIT0
#define BT_RFPoll BIT1
// Define init check for module bit --> FINIT
#define INIT_EEPROM BIT0
#define INIT_TxPower BIT1
#define INIT_IQK BIT2
#define INIT_RF BIT3
// Define IOCTL Cmd check module bit --> FIOCTL
// section 1 : IRP related
#define IOCTL_IRP BIT0
#define IOCTL_IRP_DETAIL BIT1
#define IOCTL_IRP_STATISTICS BIT2
#define IOCTL_IRP_HANDLE BIT3
// section 2 : HCI command/event
#define IOCTL_BT_HCICMD BIT8
#define IOCTL_BT_HCICMD_DETAIL BIT9
#define IOCTL_BT_HCICMD_EXT BIT10
#define IOCTL_BT_EVENT BIT11
#define IOCTL_BT_EVENT_DETAIL BIT12
#define IOCTL_BT_EVENT_PERIODICAL BIT13
// section 3 : BT tx/rx data and throughput
#define IOCTL_BT_TX_ACLDATA BIT16
#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17
#define IOCTL_BT_RX_ACLDATA BIT18
#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19
#define IOCTL_BT_TP BIT20
// section 4 : BT connection state machine.
#define IOCTL_STATE BIT21
#define IOCTL_BT_LOGO BIT22
// section 5 : BT function trace
#define IOCTL_CALLBACK_FUN BIT24
#define IOCTL_PARSE_BT_PKT BIT25
#define IOCTL_BT_TX_PKT BIT26
#define IOCTL_BT_FLAG_MON BIT27
//
// Define init check for module bit --> FSHORT_CUT
// 2011/07/20 MH Add for short but definition.
//
#define SHCUT_TX BIT0
#define SHCUT_RX BIT1
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args);
#if DBG
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_TRACE_F(comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_ASSERT(expr,fmt) \
if(!(expr)) { \
printk( "Assertion failed! %s at ......\n", #expr); \
printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
}
#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
#else
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
#define RT_TRACE_F(comp, level, fmt)
#define RT_ASSERT(expr, fmt)
#define dbg_enter()
#define dbg_exit()
#define dbg_trace(str)
#endif
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_MP)
#define DEBUG_PRINT 1
// Please add new OS's print API by yourself
#if (DEBUG_PRINT == 1) && DBG
#define RTPRINT(dbgtype, dbgflag, printstr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#define FuncEntry FunctionIn(COMP_FUNC)
#define FuncExit FunctionOut(COMP_FUNC)
#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__))
#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__))
#else
#define DBGP(dbgtype, dbgflag, printstr)
#define RTPRINT(dbgtype, dbgflag, printstr)
#define RTPRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define RTPRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#define FuncEntry
#define FuncExit
#define FunctionIn(_comp)
#define FunctionOut(_comp)
#endif
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export global variable----------------------------*/
extern u4Byte DBGP_Type[DBGP_TYPE_MAX];
extern DBGP_HEAD_T DBGP_Head;
/*------------------------Export global variable----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
extern void DBGP_Flag_Init(void);
extern void DBG_PrintAllFlag(void);
extern void DBG_PrintAllComp(void);
extern void DBG_PrintFlagEvent(u1Byte DbgFlag);
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len);
/*--------------------------Exported Function prototype---------------------*/
extern u4Byte GlobalDebugLevel;
extern u8Byte GlobalDebugComponents;
#endif
#endif // __ODM_DBG_H__

41
hal/odm_interface.h
View file

@ -39,14 +39,6 @@
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
#if 0
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name) \
)
#endif
/*===================================
#define ODM_REG_DIG_11N 0xC50
@ -60,24 +52,11 @@ ODM_REG(DIG,_pDM_Odm)
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES.
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
#if 0 // only sample code
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \
((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \
((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \
((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \
((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
_func##_ic(_name, _8195) \
)
#endif
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
@ -102,26 +81,6 @@ typedef enum _ODM_H2C_CMD
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#if 0
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
typedef struct _RT_WORK_ITEM
{
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
PVOID Adapter; // Pointer to Adapter object.
PVOID pContext; // Parameter to passed to CallBackFunc().
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
PVOID pPlatformExt; // Pointer to platform-dependent extension.
BOOLEAN bFree;
char szID[36]; // An identity string of this workitem.
}RT_WORK_ITEM, *PRT_WORK_ITEM;
#endif
#endif
//

11
hal/odm_types.h
View file

@ -173,16 +173,6 @@ typedef enum _RT_SPINLOCK_TYPE{
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <basic_types.h>
#if 0
typedef u8 u1Byte, *pu1Byte;
typedef u16 u2Byte,*pu2Byte;
typedef u32 u4Byte,*pu4Byte;
typedef u64 u8Byte,*pu8Byte;
typedef s8 s1Byte,*ps1Byte;
typedef s16 s2Byte,*ps2Byte;
typedef s32 s4Byte,*ps4Byte;
typedef s64 s8Byte,*ps8Byte;
#else
#define u1Byte u8
#define pu1Byte u8*
@ -207,7 +197,6 @@ typedef enum _RT_SPINLOCK_TYPE{
#define s8Byte s64
#define ps8Byte s64*
#endif
#define DEV_BUS_TYPE RT_USB_INTERFACE
#if defined(CONFIG_LITTLE_ENDIAN)

16
hal/rtl8188e_cmd.c
View file

@ -209,11 +209,6 @@ u8 rtl8188e_set_rssi_cmd(struct adapter*padapter, u8 *param)
_func_enter_;
if(pHalData->fw_ractrl == _TRUE){
#if 0
*((u32*) param ) = cpu_to_le32( *((u32*) param ) );
FillH2CCmd_88E(padapter, RSSI_SETTING_EID, 3, param);
#endif
}else{
DBG_8192C("==>%s fw dont support RA \n",__FUNCTION__);
res=_FAIL;
@ -689,17 +684,6 @@ static void ConstructARPResponse(
*pLength = 24;
//YJ,del,120503
#if 0
//-------------------------------------------------------------------------
// Qos Header: leave space for it if necessary.
//-------------------------------------------------------------------------
if(pStaQos->CurrentQosMode > QOS_DISABLE)
{
SET_80211_HDR_QOS_EN(pARPRspPkt, 1);
PlatformZeroMemory(&(Buffer[*pLength]), sQoSCtlLng);
*pLength += sQoSCtlLng;
}
#endif
//-------------------------------------------------------------------------
// Security Header: leave space for it if necessary.
//-------------------------------------------------------------------------

34
hal/rtl8188e_dm.c
View file

@ -46,26 +46,6 @@ dm_CheckProtection(
IN struct adapter *Adapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte CurRate, RateThreshold;
if(pMgntInfo->pHTInfo->bCurBW40MHz)
RateThreshold = MGN_MCS1;
else
RateThreshold = MGN_MCS3;
if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
{
pMgntInfo->bDmDisableProtect = TRUE;
DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
else
{
pMgntInfo->bDmDisableProtect = FALSE;
DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
#endif
}
static VOID
@ -73,20 +53,6 @@ dm_CheckStatistics(
IN struct adapter *Adapter
)
{
#if 0
if(!Adapter->MgntInfo.bMediaConnect)
return;
//2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.
rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );
// Calculate current Tx Rate(Successful transmited!!)
// Calculate current Rx Rate(Successful received!!)
//for tx tx retry count
rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );
#endif
}
static void dm_CheckPbcGPIO(struct adapter *padapter)

58
hal/rtl8188e_hal_init.c
View file

@ -332,21 +332,6 @@ void efuse_read_phymap_from_txpktbuf(
lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
#if 0
DBG_871X("%s lo32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, lo32
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+2)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+3)
);
DBG_871X("%s hi32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, hi32
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+1)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+2)
, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+3)
);
#endif
if(i==0)
{
#if 1 //for debug
@ -428,17 +413,6 @@ static s32 iol_read_efuse(
if(status == _SUCCESS)
efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
#if 0
DBG_871X("%s physical map\n", __FUNCTION__);
for(i=0;i<size;i++)
{
DBG_871X("%02x ", physical_map[i]);
if(i%16==15)
DBG_871X("\n");
}
DBG_871X("\n");
#endif
efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
return status;
@ -3601,38 +3575,6 @@ Hal_InitChannelPlan(
IN struct adapter *padapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(padapter->MgntInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if((pMgntInfo->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
{
pMgntInfo->ChannelPlan = hal_MapChannelPlan8192C(padapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan.
}
else
{
pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
}
switch(pMgntInfo->ChannelPlan)
{
case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
pDot11dInfo->bEnabled = TRUE;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
break;
default: //for MacOSX compiler warning.
break;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
#endif
}
BOOLEAN HalDetectPwrDownMode88E(struct adapter *Adapter)

487
hal/rtl8188e_phycfg.c
View file

@ -495,12 +495,7 @@ phy_RFSerialRead(
u32 NewOffset;
u32 tmplong,tmplong2;
u8 RfPiEnable=0;
#if 0
if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return retValue;
if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return retValue;
#endif
//
// Make sure RF register offset is correct
//
@ -617,28 +612,8 @@ phy_RFSerialWrite(
BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
u32 NewOffset;
#if 0
//<Roger_TODO> We should check valid regs for RF_6052 case.
if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
return;
if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
return;
#endif
// 2009/06/17 MH We can not execute IO for power save or other accident mode.
//if(RT_CANNOT_IO(Adapter))
//{
// RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
// return;
//}
Offset &= 0xff;
//
// Shadow Update
//
//PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
//
// Switch page for 8256 RF IC
//
@ -647,18 +622,14 @@ phy_RFSerialWrite(
//
// Put write addr in [5:0] and write data in [31:16]
//
//DataAndAddr = (Data<<16) | (NewOffset&0x3f);
DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
//
// Write Operation
//
PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
//RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
}
/**
* Function: PHY_QueryRFReg
*
@ -1374,43 +1345,13 @@ phy_ConfigBBWithPgHeaderFile(
PHY_REGArrayPGLen = Rtl8188E_PHY_REG_Array_PGLength;
Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8188E_PHY_REG_Array_PG;
if(ConfigType == CONFIG_BB_PHY_REG)
{
for(i=0;i<PHY_REGArrayPGLen;i=i+3)
{
#if 0 //without IO, no delay is neeeded...
if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
}
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
rtw_mdelay_os(5);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
rtw_mdelay_os(1);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
rtw_udelay_os(50);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
rtw_udelay_os(5);
else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
rtw_udelay_os(1);
//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
#endif
if(ConfigType == CONFIG_BB_PHY_REG) {
for(i=0;i<PHY_REGArrayPGLen;i=i+3) {
storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
Rtl819XPHY_REGArray_Table_PG[i+1],
Rtl819XPHY_REGArray_Table_PG[i+2]);
//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
//RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
}
}
else
{
//RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != CONFIG_BB_PHY_REG\n"));
}
return _SUCCESS;
@ -1424,16 +1365,6 @@ phy_BB8192C_Config_1T(
IN struct adapter *Adapter
)
{
#if 0
//for path - A
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
#endif
//for path - B
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
@ -1622,27 +1553,6 @@ PHY_RFConfig8188E(
// RF config
//
rtStatus = PHY_RF6052_Config8188E(Adapter);
#if 0
switch(pHalData->rf_chip)
{
case RF_6052:
rtStatus = PHY_RF6052_Config(Adapter);
break;
case RF_8225:
rtStatus = PHY_RF8225_Config(Adapter);
break;
case RF_8256:
rtStatus = PHY_RF8256_Config(Adapter);
break;
case RF_8258:
break;
case RF_PSEUDO_11N:
rtStatus = PHY_RF8225_Config(Adapter);
break;
default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
break;
}
#endif
return rtStatus;
}
@ -2161,37 +2071,6 @@ PHY_GetTxPowerLevel8188E(
*powerlevel = TxPwrDbm;
}
#if 0
static void getTxPowerIndex(
IN struct adapter * Adapter,
IN u8 channel,
IN OUT u8* cckPowerLevel,
IN OUT u8* ofdmPowerLevel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 index = (channel -1);
// 1. CCK
cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
// 2. OFDM for 1S or 2S
if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
{
// Read HT 40 OFDM TX power
ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
}
else if (GET_RF_TYPE(Adapter) == RF_2T2R)
{
// Read HT 40 OFDM TX power
ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
}
//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
}
#endif
void getTxPowerIndex88E(
IN struct adapter * Adapter,
IN u8 channel,
@ -2288,41 +2167,6 @@ void getTxPowerIndex88E(
{
}
}
#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){
case 1: // 100%
break;
case 2: // 70%
cckPowerLevel[0] -= 3;
cckPowerLevel[1] -= 3;
ofdmPowerLevel[0] -=3;
ofdmPowerLevel[1] -= 3;
break;
case 3: // 50%
cckPowerLevel[0] -= 6;
cckPowerLevel[1] -= 6;
ofdmPowerLevel[0] -=6;
ofdmPowerLevel[1] -= 6;
break;
case 4: // 35%
cckPowerLevel[0] -= 9;
cckPowerLevel[1] -= 9;
ofdmPowerLevel[0] -=9;
ofdmPowerLevel[1] -= 9;
break;
case 5: // 15%
cckPowerLevel[0] -= 17;
cckPowerLevel[1] -= 17;
ofdmPowerLevel[0] -=17;
ofdmPowerLevel[1] -= 17;
break;
default:
break;
}
#endif
//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
}
void phy_PowerIndexCheck88E(
@ -2336,70 +2180,13 @@ void phy_PowerIndexCheck88E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if 0 // (CCX_SUPPORT == 1)
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
//
// CCX 2 S31, AP control of client transmit power:
// 1. We shall not exceed Cell Power Limit as possible as we can.
// 2. Tolerance is +/- 5dB.
// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
//
// TODO:
// 1. 802.11h power contraint
//
// 071011, by rcnjko.
//
if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
pMgntInfo->mAssoc &&
pCcxInfo->bUpdateCcxPwr &&
pCcxInfo->bWithCcxCellPwr &&
channel == pMgntInfo->dot11CurrentChannelNumber)
{
u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
// CCK
if(cckPowerLevel[0] > CckCellPwrIdx)
cckPowerLevel[0] = CckCellPwrIdx;
// Legacy OFDM, HT OFDM
if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
{
if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
{
ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
}
else
{
ofdmPowerLevel[0] = 0;
}
}
RT_TRACE(COMP_TXAGC, DBG_LOUD,
("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
}
#else
// Add or not ???
#endif
pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
//DBG_871X("PHY_SetTxPowerLevel8188E(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x, CurrentBW2024GTxPwrIdx: 0x%dx, CurrentBW4024GTxPwrIdx: 0x%x \n",
// pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx, pHalData->CurrentBW2024GTxPwrIdx, pHalData->CurrentBW4024GTxPwrIdx);
}
/*-----------------------------------------------------------------------------
* Function: SetTxPowerLevel8190()
*
@ -2448,30 +2235,6 @@ PHY_SetTxPowerLevel8188E(
rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel);
#if 0
switch(pHalData->rf_chip)
{
case RF_8225:
PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
break;
case RF_8256:
PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
break;
case RF_6052:
PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
break;
case RF_8258:
break;
}
#endif
}
@ -2545,30 +2308,6 @@ PHY_ScanOperationBackup8188E(
IN u8 Operation
)
{
#if 0
IO_TYPE IoType;
if(!Adapter->bDriverStopped)
{
switch(Operation)
{
case SCAN_OPT_BACKUP:
IoType = IO_CMD_PAUSE_DM_BY_SCAN;
rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
break;
case SCAN_OPT_RESTORE:
IoType = IO_CMD_RESUME_DM_BY_SCAN;
rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
break;
default:
RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
break;
}
}
#endif
}
/*-----------------------------------------------------------------------------
@ -2787,31 +2526,12 @@ PHY_SetBWMode8188E(
pHalData->CurrentChannelBW = Bandwidth;
#if 0
if(Offset==HT_EXTCHNL_OFFSET_LOWER)
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
else
pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
#else
pHalData->nCur40MhzPrimeSC = Offset;
#endif
if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
#if 0
//PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
#else
_PHY_SetBWMode92C(Adapter);
#endif
}
else
{
//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
//pHalData->SetBWModeInProgress= FALSE;
pHalData->CurrentChannelBW = tmpBW;
}
}
@ -2919,11 +2639,7 @@ PHY_SwChnl8188E( // Call after initialization
if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
#if 0
//PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
#else
_PHY_SwChnl8192C(Adapter, channel);
#endif
if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
phy_SpurCalibration_8188E( Adapter);
if(bResult)
@ -2962,154 +2678,6 @@ phy_SwChnlStepByStep(
OUT u32 *delay
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
u4Byte PreCommonCmdCnt;
SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
u4Byte PostCommonCmdCnt;
SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
u4Byte RfDependCmdCnt;
SwChnlCmd *CurrentCmd;
u1Byte eRFPath;
u4Byte RfTXPowerCtrl;
BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
#if(MP_DRIVER != 1)
RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
#endif
RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//{
// <1> Fill up pre common command.
PreCommonCmdCnt = 0;
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
CmdID_SetTxPowerLevel, 0, 0, 0);
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
CmdID_End, 0, 0, 0);
// <2> Fill up post common command.
PostCommonCmdCnt = 0;
phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
CmdID_End, 0, 0, 0);
// <3> Fill up RF dependent command.
RfDependCmdCnt = 0;
switch( pHalData->RFChipID )
{
case RF_8225:
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
// 2008/09/04 MH Change channel.
if(channel==14) channel++;
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8256:
// TEST!! This is not the table for 8256!!
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, rRfChannel, channel, 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_6052:
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0);
break;
case RF_8258:
break;
// For FPGA two MAC verification
case RF_PSEUDO_11N:
return TRUE;
default:
RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
return FALSE;
break;
}
do{
switch(*stage)
{
case 0:
CurrentCmd=&PreCommonCmd[*step];
break;
case 1:
CurrentCmd=&RfDependCmd[*step];
break;
case 2:
CurrentCmd=&PostCommonCmd[*step];
break;
}
if(CurrentCmd->CmdID==CmdID_End)
{
if((*stage)==2)
{
return TRUE;
}
else
{
(*stage)++;
(*step)=0;
continue;
}
}
switch(CurrentCmd->CmdID)
{
case CmdID_SetTxPowerLevel:
PHY_SetTxPowerLevel8192C(Adapter,channel);
break;
case CmdID_WritePortUlong:
PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
break;
case CmdID_WritePortUshort:
PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
break;
case CmdID_WritePortUchar:
PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
break;
case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
#if 1
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
#else
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
#endif
}
break;
}
break;
}while(TRUE);
//cosa }/*for(Number of RF paths)*/
(*delay)=CurrentCmd->msDelay;
(*step)++;
return FALSE;
#endif
return _TRUE;
}
@ -3156,20 +2724,8 @@ phy_FinishSwChnlNow( // We should not call this function directly
IN u8 channel
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u32 delay;
while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
{
if(delay>0)
rtw_mdelay_os(delay);
}
#endif
}
//
// Description:
// Switch channel synchronously. Called by SwChnlByDelayHandler.
@ -3231,30 +2787,6 @@ PHY_SetMonitorMode8192C(
IN BOOLEAN bEnableMonitorMode
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
//2 Note: we may need to stop antenna diversity.
if(bEnableMonitorMode)
{
bFilterOutNonAssociatedBSSID = FALSE;
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
pHalData->bInMonitorMode = TRUE;
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
}
else
{
bFilterOutNonAssociatedBSSID = TRUE;
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
pHalData->bInMonitorMode = FALSE;
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
}
#endif
}
@ -3280,20 +2812,9 @@ PHY_CheckIsLegalRfPath8192C(
IN struct adapter *pAdapter,
IN u32 eRFPath)
{
// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN rtValue = _TRUE;
// NOt check RF Path now.!
#if 0
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
{
rtValue = FALSE;
}
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
{
}
#endif
return rtValue;
} /* PHY_CheckIsLegalRfPath8192C */

256
hal/rtl8188e_rf6052.c
View file

@ -97,50 +97,6 @@ void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
#if 0//(RTL92SE_FPGA_VERIFY == 0)
static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
// Set PA to high value
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
// Set PA low gain
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
}
#endif
} /* RF_ChangeTxPath */
@ -328,54 +284,8 @@ rtl8188e_PHY_RF6052SetCckTxPower(
*/
} /* PHY_RF6052SetCckTxPower */
#if 0
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
//
static void getPowerBase(
IN struct adapter *Adapter,
IN u8* pPowerLevel,
IN u8 Channel,
IN OUT u32* OfdmBase,
IN OUT u32* MCSBase
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff=0, HT20_pwrdiff=0;
u8 i, powerlevel[2];
for(i=0; i<2; i++)
{
powerlevel[i] = pPowerLevel[i];
Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
powerBase0 = powerlevel[i] + Legacy_pwrdiff;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
*(OfdmBase+i) = powerBase0;
//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
}
for(i=0; i<2; i++)
{
//Check HT20 to HT40 diff
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
powerlevel[i] += HT20_pwrdiff;
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
*(MCSBase+i) = powerBase1;
//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
}
}
#endif
//
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
//
void getPowerBase88E(
IN struct adapter *Adapter,
IN u8* pPowerLevelOFDM,
@ -418,139 +328,7 @@ void getPowerBase88E(
//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
}
}
#if 0
static void getTxPowerWriteValByRegulatory(
IN struct adapter *Adapter,
IN u8 Channel,
IN u8 index,
IN u32* powerBase0,
IN u32* powerBase1,
OUT u32* pOutWriteVal
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 i, chnlGroup, pwr_diff_limit[4];
u32 writeVal, customer_limit, rf;
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
for(rf=0; rf<2; rf++)
{
switch(pHalData->EEPROMRegulatory)
{
case 0: // Realtek better performance
// increase power diff defined by Realtek for large power
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 1: // Realtek regulatory
// increase power diff defined by Realtek for regulatory
{
if(pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if(pHalData->pwrGroupCnt >= 3)
{
if(Channel <= 3)
chnlGroup = 0;
else if(Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if(Channel > 9)
chnlGroup = 2;
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=4;
}
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
}
break;
case 2: // Better regulatory
// don't increase any power diff
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 3: // Customer defined power diff.
// increase power diff defined by customer.
chnlGroup = 0;
//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
{
//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
// ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
}
else
{
//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
// ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
}
for (i=0; i<4; i++)
{
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
{
if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
}
else
{
if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
}
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
}
// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
// 20100628 Joseph: High power mode for BT-Coexist mechanism.
// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
writeVal = writeVal - 0x06060606;
}
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
writeVal = writeVal;
}
*(pOutWriteVal+rf) = writeVal;
}
}
#endif
void getTxPowerWriteValByRegulatory88E(
IN struct adapter *Adapter,
IN u8 Channel,
@ -571,15 +349,8 @@ void getTxPowerWriteValByRegulatory88E(
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
//
#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
Regulatory = 2;
#endif
for(rf=0; rf<2; rf++)
{
switch(Regulatory)
{
for(rf=0; rf<2; rf++) {
switch(Regulatory) {
case 0: // Realtek better performance
// increase power diff defined by Realtek for large power
chnlGroup = 0;
@ -1012,30 +783,7 @@ PHY_RF6052_Config8188E(
// Config BB and RF
//
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
#if 0
switch( Adapter->MgntInfo.bRegHwParaFile )
{
case 0:
phy_RF6052_Config_HardCode(Adapter);
break;
case 1:
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
break;
case 2:
// Partial Modify.
phy_RF6052_Config_HardCode(Adapter);
phy_RF6052_Config_ParaFile(Adapter);
break;
default:
phy_RF6052_Config_HardCode(Adapter);
break;
}
#endif
return rtStatus;
}

9
hal/rtl8188e_rxdesc.c
View file

@ -295,17 +295,10 @@ void update_recvframe_phyinfo_88e(
if(pkt_info.bPacketBeacon){
if(check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
sa = padapter->mlmepriv.cur_network.network.MacAddress;
#if 0
{
DBG_8192C("==> rx beacon from AP[%02x:%02x:%02x:%02x:%02x:%02x]\n",
sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]);
}
#endif
}
else
sa = get_sa(wlanhdr);
}
else{
} else{
sa = get_sa(wlanhdr);
}

17
hal/rtl8188e_sreset.c
View file

@ -95,23 +95,6 @@ void rtl8188e_sreset_linked_status_check(struct adapter *padapter)
else if(fw_status == 2)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__FUNCTION__,fw_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
#endif
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);

699
hal/usb_halinit.c
View file

@ -446,19 +446,6 @@ _InitPageBoundary(
//
u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
#if 0
// RX Page Boundary
//srand(static_cast<unsigned int>(time(NULL)) );
if(bSupportRemoteWakeUp)
{
Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE;
Offset = Offset / 128; // RX page size = 128 byte
rxff_bndy= (Offset*128) -1;
}
else
#endif
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
}
@ -834,11 +821,9 @@ _InitRetryFunction(
)
{
u8 value8;
//#if 0 //MAC SPEC
value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
value8 |= EN_AMPDU_RTY_NEW;
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
//#endif
// Set ACK timeout
rtw_write8(Adapter, REG_ACKTO, 0x40);
}
@ -1006,36 +991,6 @@ HalRxAggr8188EUsb(
IN BOOLEAN Value
)
{
#if 0//USB_RX_AGGREGATION_92C
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
u1Byte valueDMATimeout;
u1Byte valueDMAPageCount;
u1Byte valueUSBTimeout;
u1Byte valueUSBBlockCount;
// selection to prevent bad TP.
if( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg)
{
// 2010.04.27 hpfan
// Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
// Timeout value is calculated by 34 / (2^n)
valueDMATimeout = 0x0f;
valueDMAPageCount = 0x01;
valueUSBTimeout = 0x0f;
valueUSBBlockCount = 0x01;
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
}
else
{
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
}
#endif
}
/*-----------------------------------------------------------------------------
@ -1159,34 +1114,6 @@ static VOID _RfPowerSave(
IN struct adapter * Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte eRFPath;
#if (DISABLE_BB_RF)
return;
#endif
if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
// Those action will be discard in MgntActSet_RF_State because off the same state
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
}
else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
}
else{
pHalData->eRFPowerState = eRfOn;
pMgntInfo->RfOffReason = 0;
if(Adapter->bInSetPower || Adapter->bResetInProgress)
PlatformUsbEnableInPipes(Adapter);
RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
}
#endif
}
enum {
@ -1226,39 +1153,6 @@ HalDetectSelectiveSuspendMode(
IN struct adapter * Adapter
)
{
#if 0
u8 tmpvalue;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
// If support HW radio detect, we need to enable WOL ability, otherwise, we
// can not use FW to notify host the power state switch.
EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
if(tmpvalue & BIT1)
{
DBG_8192C("Enable\n");
}
else
{
DBG_8192C("Disable\n");
pdvobjpriv->RegUsbSS = _FALSE;
}
// 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
{
//PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
//if (!pMgntInfo->bRegDongleSS)
//{
// RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
pdvobjpriv->RegUsbSS = _FALSE;
//}
}
#endif
} // HalDetectSelectiveSuspendMode
/*-----------------------------------------------------------------------------
* Function: HwSuspendModeEnable92Cu()
@ -1540,10 +1434,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
}
#endif //MP_DRIVER == 1
{
#if 0
Adapter->bFWReady = _FALSE; //because no fw for test chip
pHalData->fw_ractrl = _FALSE;
#else
#ifdef CONFIG_WOWLAN
status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
@ -1561,7 +1451,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
Adapter->bFWReady = _TRUE;
pHalData->fw_ractrl = _FALSE;
}
#endif
}
@ -1666,12 +1555,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
}
#endif
#if 0
if(pHTInfo->bRDGEnable){
_InitRDGSetting_8188E(Adapter);
}
#endif
#ifdef CONFIG_TX_EARLY_MODE
if( pHalData->bEarlyModeEnable)
{
@ -1783,97 +1666,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
// Added by tynli. 2010.03.30.
pwrctrlpriv->rf_pwrstate = rf_on;
#if 0 //to do
RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
#if 1 //Todo
// 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
// 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
pwrctrlpriv->b_hw_radio_off = _TRUE;
DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
if(pwrctrlpriv->reg_rfoff == _TRUE)
{ // User disable RF via registry.
DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
// Those action will be discard in MgntActSet_RF_State because off the same state
//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
}
else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
{ // H/W or S/W RF OFF before sleep.
DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
//pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->rf_pwrstate = rf_on;
//MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
}
else
{
// Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
{
DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet);
if (eRfPowerStateToSet == rf_off)
{
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
pwrctrlpriv->b_hw_radio_off = _TRUE;
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->b_hw_radio_off = _FALSE;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
pwrctrlpriv->rfoff_reason = 0;
pwrctrlpriv->b_hw_radio_off = _FALSE;
pwrctrlpriv->rf_pwrstate = rf_on;
rtw_led_control(Adapter, LED_CTL_POWER_ON);
}
// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
{
// Enable register area 0x0-0xc.
rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
//
// <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
// our HW will be set in power-down mode if PDn source from all functions are configured.
// 2010.10.06.
//
//if(IS_HARDWARE_TYPE_8723AU(Adapter))
//{
// u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
// rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
//}
//else
//{
rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
//}
}
//DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
#endif
#endif
// enable Tx report.
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
@ -2018,11 +1810,6 @@ VOID hal_poweroff_rtl8188eu(
val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
#if 0
// 7. RSV_CTRL 0x1C[7:0] = 0x0E // lock ISO/CLK/Power control register
rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
#endif
#if 1
//YJ,test add, 111207. For Power Consumption.
val8 = rtw_read8(Adapter, GPIO_IN);
rtw_write8(Adapter, GPIO_OUT, val8);
@ -2034,11 +1821,11 @@ VOID hal_poweroff_rtl8188eu(
val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43
rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode
#endif
bMacPwrCtrlOn = _FALSE;
rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
Adapter->bFWReady = _FALSE;
}
static void rtl8188eu_hw_power_down(struct adapter *padapter)
{
// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
@ -2158,184 +1945,6 @@ unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
return _SUCCESS;
}
//-------------------------------------------------------------------------
//
// EEPROM Power index mapping
//
//-------------------------------------------------------------------------
#if 0
static VOID
_ReadPowerValueFromPROM(
IN PTxPowerInfo pwrInfo,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
u32 rfPath, eeAddr, group;
_rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo));
if(AutoLoadFail){
for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
pwrInfo->CCKIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
pwrInfo->HT40_1SIndex[rfPath][group] = EEPROM_Default_TxPowerLevel;
pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff;
pwrInfo->HT20IndexDiff[rfPath][group] = EEPROM_Default_HT20_Diff;
pwrInfo->OFDMIndexDiff[rfPath][group] = EEPROM_Default_LegacyHTTxPowerDiff;
pwrInfo->HT40MaxOffset[rfPath][group] = EEPROM_Default_HT40_PwrMaxOffset;
pwrInfo->HT20MaxOffset[rfPath][group] = EEPROM_Default_HT20_PwrMaxOffset;
}
}
pwrInfo->TSSI_A = EEPROM_Default_TSSI;
pwrInfo->TSSI_B = EEPROM_Default_TSSI;
return;
}
for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group;
pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group;
pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr];
}
}
for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
pwrInfo->HT40_2SIndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
#if 1
pwrInfo->HT20IndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
if(pwrInfo->HT20IndexDiff[rfPath][group] & BIT3) //4bit sign number to 8 bit sign number
pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
#else
pwrInfo->HT20IndexDiff[rfPath][group] =
(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
#endif
pwrInfo->OFDMIndexDiff[rfPath][group] =
(PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF;
pwrInfo->HT40MaxOffset[rfPath][group] =
(PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
pwrInfo->HT20MaxOffset[rfPath][group] =
(PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
}
}
pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A];
pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B];
}
static u32
_GetChannelGroup(
IN u32 channel
)
{
//RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
if(channel < 3){ // Channel 1~3
return 0;
}
else if(channel < 9){ // Channel 4~9
return 1;
}
return 2; // Channel 10~14
}
static VOID
ReadTxPowerInfo(
IN struct adapter * Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
TxPowerInfo pwrInfo;
u32 rfPath, ch, group;
u8 pwr, diff;
_ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail);
if(!AutoLoadFail)
pHalData->bTXPowerDataReadFromEEPORM = _TRUE;
for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
group = _GetChannelGroup(ch);
pHalData->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group];
pHalData->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group];
pHalData->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group];
pHalData->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group];
pHalData->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group];
pHalData->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group];
pwr = pwrInfo.HT40_1SIndex[rfPath][group];
diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
pHalData->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0;
}
}
#if 0 //DBG
for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower,
("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch],
pHalData->TxPwrLevelHT40_1S[rfPath][ch],
pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
}
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
}
#endif
// 2010/10/19 MH Add Regulator recognize for CU.
if(!AutoLoadFail)
{
pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7); //bit0~2
}
else
{
pHalData->EEPROMRegulatory = 0;
}
DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
}
#endif
//-------------------------------------------------------------------
//
// EEPROM/EFUSE Content Parsing
@ -2348,73 +1957,6 @@ _ReadIDs(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(_FALSE == AutoloadFail){
// VID, PID
pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
}
else{
pHalData->EEPROMVID = EEPROM_Default_VID;
pHalData->EEPROMPID = EEPROM_Default_PID;
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID;
pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
}
// For customized behavior.
if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
pHalData->CustomerID = RT_CID_819x_HP;
// Decide CustomerID according to VID/DID or EEPROM
switch(pHalData->EEPROMCustomerID)
{
case EEPROM_CID_DEFAULT:
if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pHalData->CustomerID = RT_CID_DLINK;
else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pHalData->CustomerID = RT_CID_DLINK;
else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pHalData->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
/*
Adapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->keepAliveLevel = 0;
Adapter->bUnloadDriverwhenS3S4 = FALSE;
*/
break;
default:
pHalData->CustomerID = RT_CID_DEFAULT;
break;
}
MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
#endif
}
@ -2425,24 +1967,6 @@ _ReadMACAddress(
IN BOOLEAN AutoloadFail
)
{
#if 0
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
if(_FALSE == AutoloadFail){
//Read Permanent MAC address and set value to hardware
_rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
}
else{
//Random assigh MAC address
u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
//sMacAddr[5] = (u8)GetRandomNumber(1, 254);
_rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
}
DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
//NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
//RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
#endif
}
static VOID
@ -2487,33 +2011,6 @@ _ReadThermalMeter(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 tempval;
//
// ThermalMeter from EEPROM
//
if(!AutoloadFail)
tempval = PROMContent[EEPROM_THERMAL_METER];
else
tempval = EEPROM_Default_ThermalMeter;
pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0]
if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
pdmpriv->bAPKThermalMeterIgnore = _TRUE;
#if 0
if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
pHalData->EEPROMThermalMeter = 0x12;
#endif
pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
//RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
#endif
}
static VOID
@ -2532,16 +2029,6 @@ _ReadPROMVersion(
IN BOOLEAN AutoloadFail
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(AutoloadFail){
pHalData->EEPROMVersion = EEPROM_Default_Version;
}
else{
pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION];
}
#endif
}
static VOID
@ -2555,28 +2042,6 @@ readAntennaDiversity(
struct registry_priv *registry_par = &pAdapter->registrypriv;
pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct registry_priv *registry_par = &pAdapter->registrypriv;
if(!AutoLoadFail)
{
// Antenna Diversity setting.
if(registry_par->antdiv_cfg == 2) // 2: From Efuse
pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
else
pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON,
DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
//if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
// pHalData->AntDivCfg = 0;
}
else
{
pHalData->AntDivCfg = 0;
}
#endif
}
static VOID
@ -2585,39 +2050,6 @@ hal_InitPGData(
IN OUT u8 *PROMContent
)
{
#if 0
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u32 i;
u16 value16;
if(_FALSE == pEEPROM->bautoload_fail_flag)
{ // autoload OK.
if (_TRUE == pEEPROM->EepromOrEfuse)
{
// Read all Content from EEPROM or EFUSE.
for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
{
//value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
//*((u16 *)(&PROMContent[i])) = value16;
}
}
else
{
// Read EFUSE real map to shadow.
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
_rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
}
}
else
{//autoload fail
//RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n"));
pEEPROM->bautoload_fail_flag = _TRUE;
//update to default value 0xFF
if (_FALSE == pEEPROM->EepromOrEfuse)
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
}
#endif
}
static void
Hal_EfuseParsePIDVID_8188EU(
@ -2693,89 +2125,11 @@ Hal_CustomizeByCustomerID_8188EU(
IN struct adapter * padapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(padapter->MgntInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
// For customized behavior.
if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
pMgntInfo->CustomerID = RT_CID_819x_HP;
// Decide CustomerID according to VID/DID or EEPROM
switch(pHalData->EEPROMCustomerID)
{
case EEPROM_CID_DEFAULT:
if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pMgntInfo->CustomerID = RT_CID_DLINK;
else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pMgntInfo->CustomerID = RT_CID_DLINK;
else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pMgntInfo->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
padapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE;
pMgntInfo->keepAliveLevel = 0;
padapter->bUnloadDriverwhenS3S4 = FALSE;
break;
default:
pMgntInfo->CustomerID = RT_CID_DEFAULT;
break;
}
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pMgntInfo->CustomerID));
hal_CustomizedBehavior_8723U(padapter);
#endif
}
// Read HW power down mode selection
static void _ReadPSSetting(IN struct adapter *Adapter,IN u8*PROMContent,IN u8 AutoloadFail)
{
#if 0
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
if(AutoloadFail){
pwrctl->bHWPowerdown = _FALSE;
pwrctl->bSupportRemoteWakeup = _FALSE;
}
else {
//if(SUPPORT_HW_RADIO_DETECT(Adapter))
pwrctl->bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
//else
//pwrctl->bHWPwrPindetect = _FALSE;//dongle not support new
//hw power down mode selection , 0:rf-off / 1:power down
if(Adapter->registrypriv.hwpdn_mode==2)
pwrctl->bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
else
pwrctl->bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
// decide hw if support remote wakeup function
// if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
pwrctl->bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
//if(SUPPORT_HW_RADIO_DETECT(Adapter))
//Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ;
DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
pwrctl->bHWPwrPindetect,pwrctl->bHWPowerdown ,pwrctl->bSupportRemoteWakeup);
DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
}
#endif
}
#ifdef CONFIG_EFUSE_CONFIG_FILE
@ -3955,30 +3309,13 @@ _func_enter_;
}
break;
case HW_VAR_RESP_SIFS:
{
#if 0
// SIFS for OFDM Data ACK
rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]);
// SIFS for OFDM consecutive tx like CTS data!
rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]);
rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]);
rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]);
// 20100719 Joseph: Revise SIFS setting due to Hardware register definition change.
rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]);
rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]);
#else
//SIFS_Timer = 0x0a0a0808;
//RESP_SIFS for CCK
rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
//RESP_SIFS for OFDM
rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
#endif
}
//SIFS_Timer = 0x0a0a0808;
//RESP_SIFS for CCK
rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
//RESP_SIFS for OFDM
rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
break;
case HW_VAR_ACK_PREAMBLE:
{
@ -4368,32 +3705,18 @@ _func_enter_;
#ifdef CONFIG_CONCURRENT_MODE
{
int i;
#if 0 //for Miracast source PKT lost issue
u8 RetryLimit = 0x01;
rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
#endif
for(i=0;i<1000;i++)
{
if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204))
{
//DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(Adapter, 0x204), rtw_read32(Adapter, 0x200), i);
for(i=0;i<1000;i++) {
if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204)) {
rtw_msleep_os(10);
}
else
{
} else {
DBG_871X("no packet in tx packet buffer (%d)\n", i);
break;
}
}
#if 0 //for Miracast source PKT lost issue
RetryLimit = 0x30;
rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
#endif
}
#endif
break;
case HW_VAR_APFM_ON_MAC:
pHalData->bMacPwrCtrlOn = *val;
DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn);

121
hal/usb_ops_linux.c
View file

@ -114,14 +114,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
_rtw_memcpy( pIo_buf, pdata, len);
}
#if 0
//timeout test for firmware downloading
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len
, (value == FW_8188E_START_ADDRESS) ?RTW_USB_CONTROL_MSG_TIMEOUT_TEST : RTW_USB_CONTROL_MSG_TIMEOUT
);
#else
status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
#endif
if ( status == len) // Success this control transfer.
{
@ -393,21 +386,6 @@ void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pbuf)
_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
#if 0 //DBG
{
u32 hisr=0 ,hisr_ex=0;
_rtw_memcpy(&hisr,&(pHalData->IntArray[0]),4);
hisr = le32_to_cpu(hisr);
_rtw_memcpy(&hisr_ex,&(pHalData->IntArray[1]),4);
hisr_ex = le32_to_cpu(hisr_ex);
if((hisr != 0) || (hisr_ex!=0))
DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x \n",__FUNCTION__,hisr,hisr_ex);
}
#endif
#ifdef CONFIG_LPS_LCLK
if( pHalData->IntArray[0] & IMR_CPWM_88E )
{
@ -430,15 +408,6 @@ void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pbuf)
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0
if(pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__);
if(pHalData->IntArray[0] & IMR_TBDOK_88E)
DBG_8192C("%s: HISR_TXBCNOK\n", __func__);
if(pHalData->IntArray[0] & IMR_TBDER_88E)
DBG_8192C("%s: HISR_TXBCNERR\n", __func__);
#endif
if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
@ -612,84 +581,9 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta
}
else // Handle BC/MC Packets
{
u8 clone = _TRUE;
#if 0
u8 type, subtype, *paddr2, *paddr3;
type = GetFrameType(pbuf);
subtype = GetFrameSubType(pbuf); //bit(7)~bit(2)
switch (type)
{
case WIFI_MGT_TYPE: //Handle BC/MC mgnt Packets
if(subtype == WIFI_BEACON)
{
paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data);
if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) &&
_rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
{
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
if(check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) &&
_rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN))
{
if(clone==_FALSE)
{
clone = _TRUE;
}
else
{
clone = _FALSE;
}
precvframe->u.hdr.adapter = primary_padapter;
}
if(check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) ||
check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING))
{
clone = _TRUE;
precvframe->u.hdr.adapter = primary_padapter;
}
}
else if(subtype == WIFI_PROBEREQ)
{
//probe req frame is only for interface2
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
break;
case WIFI_CTRL_TYPE: // Handle BC/MC ctrl Packets
break;
case WIFI_DATA_TYPE: //Handle BC/MC data Packets
//Notes: AP MODE never rx BC/MC data packets
paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data);
if(_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
{
//change to secondary interface
precvframe->u.hdr.adapter = secondary_padapter;
clone = _FALSE;
}
break;
default:
break;
}
#endif
if(_TRUE == clone)
{
if(_TRUE == clone) {
//clone/copy to if2
u8 shift_sz = 0;
u32 alloc_sz, skb_len;
@ -802,13 +696,6 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
#if 0 //temp remove when disable usb rx aggregation
if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
{
return _FAIL;
}
#endif
do{
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
@ -1199,12 +1086,6 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb)
prxstat = (struct recv_stat *)pbuf;
pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
#if 0 //temp remove when disable usb rx aggregation
if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
{
return _FAIL;
}
#endif
do{
RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",