mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2025-06-23 08:34:20 +00:00
rtl8188eu: Remove dead code inside #if 0
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
2d60bad9ad
commit
b6b121512b
56 changed files with 121 additions and 6115 deletions
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@ -495,12 +495,7 @@ phy_RFSerialRead(
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u32 NewOffset;
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u32 tmplong,tmplong2;
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u8 RfPiEnable=0;
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#if 0
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if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
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return retValue;
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if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
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return retValue;
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#endif
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//
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// Make sure RF register offset is correct
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//
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@ -617,28 +612,8 @@ phy_RFSerialWrite(
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BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
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u32 NewOffset;
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#if 0
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//<Roger_TODO> We should check valid regs for RF_6052 case.
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if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
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return;
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if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
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return;
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#endif
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// 2009/06/17 MH We can not execute IO for power save or other accident mode.
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//if(RT_CANNOT_IO(Adapter))
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//{
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// RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
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// return;
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//}
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Offset &= 0xff;
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//
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// Shadow Update
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//
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//PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
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//
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// Switch page for 8256 RF IC
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//
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@ -647,18 +622,14 @@ phy_RFSerialWrite(
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//
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// Put write addr in [5:0] and write data in [31:16]
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//
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//DataAndAddr = (Data<<16) | (NewOffset&0x3f);
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DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
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//
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// Write Operation
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//
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PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
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//RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
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}
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/**
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* Function: PHY_QueryRFReg
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*
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@ -1374,43 +1345,13 @@ phy_ConfigBBWithPgHeaderFile(
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PHY_REGArrayPGLen = Rtl8188E_PHY_REG_Array_PGLength;
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Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8188E_PHY_REG_Array_PG;
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if(ConfigType == CONFIG_BB_PHY_REG)
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{
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for(i=0;i<PHY_REGArrayPGLen;i=i+3)
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{
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#if 0 //without IO, no delay is neeeded...
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if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
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#ifdef CONFIG_LONG_DELAY_ISSUE
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rtw_msleep_os(50);
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#else
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rtw_mdelay_os(50);
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#endif
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}
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else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
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rtw_mdelay_os(5);
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else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
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rtw_mdelay_os(1);
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else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
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rtw_udelay_os(50);
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else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
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rtw_udelay_os(5);
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else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
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rtw_udelay_os(1);
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//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
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#endif
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if(ConfigType == CONFIG_BB_PHY_REG) {
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for(i=0;i<PHY_REGArrayPGLen;i=i+3) {
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storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
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Rtl819XPHY_REGArray_Table_PG[i+1],
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Rtl819XPHY_REGArray_Table_PG[i+2]);
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//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
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//RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
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}
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}
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else
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{
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//RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != CONFIG_BB_PHY_REG\n"));
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}
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return _SUCCESS;
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@ -1424,16 +1365,6 @@ phy_BB8192C_Config_1T(
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IN struct adapter *Adapter
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)
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{
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#if 0
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//for path - A
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PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
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PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
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PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
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PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
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PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
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PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
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PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
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#endif
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//for path - B
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PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
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PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
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@ -1622,27 +1553,6 @@ PHY_RFConfig8188E(
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// RF config
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//
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rtStatus = PHY_RF6052_Config8188E(Adapter);
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#if 0
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switch(pHalData->rf_chip)
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{
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case RF_6052:
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rtStatus = PHY_RF6052_Config(Adapter);
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break;
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case RF_8225:
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rtStatus = PHY_RF8225_Config(Adapter);
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break;
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case RF_8256:
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rtStatus = PHY_RF8256_Config(Adapter);
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break;
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case RF_8258:
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break;
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case RF_PSEUDO_11N:
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rtStatus = PHY_RF8225_Config(Adapter);
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break;
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default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
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break;
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}
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#endif
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return rtStatus;
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}
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@ -2161,37 +2071,6 @@ PHY_GetTxPowerLevel8188E(
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*powerlevel = TxPwrDbm;
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}
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#if 0
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static void getTxPowerIndex(
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IN struct adapter * Adapter,
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IN u8 channel,
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IN OUT u8* cckPowerLevel,
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IN OUT u8* ofdmPowerLevel
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)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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u8 index = (channel -1);
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// 1. CCK
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cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
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cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
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// 2. OFDM for 1S or 2S
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if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
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{
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// Read HT 40 OFDM TX power
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ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
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ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
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}
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else if (GET_RF_TYPE(Adapter) == RF_2T2R)
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{
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// Read HT 40 OFDM TX power
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ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
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ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
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}
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//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
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}
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#endif
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void getTxPowerIndex88E(
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IN struct adapter * Adapter,
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IN u8 channel,
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@ -2288,41 +2167,6 @@ void getTxPowerIndex88E(
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{
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}
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}
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#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
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switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){
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case 1: // 100%
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break;
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case 2: // 70%
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cckPowerLevel[0] -= 3;
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cckPowerLevel[1] -= 3;
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ofdmPowerLevel[0] -=3;
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ofdmPowerLevel[1] -= 3;
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break;
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case 3: // 50%
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cckPowerLevel[0] -= 6;
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cckPowerLevel[1] -= 6;
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ofdmPowerLevel[0] -=6;
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ofdmPowerLevel[1] -= 6;
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break;
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case 4: // 35%
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cckPowerLevel[0] -= 9;
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cckPowerLevel[1] -= 9;
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ofdmPowerLevel[0] -=9;
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ofdmPowerLevel[1] -= 9;
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break;
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case 5: // 15%
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cckPowerLevel[0] -= 17;
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cckPowerLevel[1] -= 17;
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ofdmPowerLevel[0] -=17;
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ofdmPowerLevel[1] -= 17;
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break;
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default:
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break;
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}
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#endif
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//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
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}
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void phy_PowerIndexCheck88E(
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@ -2336,70 +2180,13 @@ void phy_PowerIndexCheck88E(
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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#if 0 // (CCX_SUPPORT == 1)
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PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
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PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
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//
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// CCX 2 S31, AP control of client transmit power:
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// 1. We shall not exceed Cell Power Limit as possible as we can.
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// 2. Tolerance is +/- 5dB.
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// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
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//
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// TODO:
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// 1. 802.11h power contraint
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//
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// 071011, by rcnjko.
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//
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if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
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pMgntInfo->mAssoc &&
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pCcxInfo->bUpdateCcxPwr &&
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pCcxInfo->bWithCcxCellPwr &&
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channel == pMgntInfo->dot11CurrentChannelNumber)
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{
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u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
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u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
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u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
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RT_TRACE(COMP_TXAGC, DBG_LOUD,
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("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
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pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
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RT_TRACE(COMP_TXAGC, DBG_LOUD,
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("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
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channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
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// CCK
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if(cckPowerLevel[0] > CckCellPwrIdx)
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cckPowerLevel[0] = CckCellPwrIdx;
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// Legacy OFDM, HT OFDM
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if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
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{
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if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
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{
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ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
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}
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else
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{
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ofdmPowerLevel[0] = 0;
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}
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}
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RT_TRACE(COMP_TXAGC, DBG_LOUD,
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("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
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cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
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}
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#else
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// Add or not ???
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#endif
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pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
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pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
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pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
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pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
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//DBG_871X("PHY_SetTxPowerLevel8188E(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x, CurrentBW2024GTxPwrIdx: 0x%dx, CurrentBW4024GTxPwrIdx: 0x%x \n",
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// pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx, pHalData->CurrentBW2024GTxPwrIdx, pHalData->CurrentBW4024GTxPwrIdx);
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}
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/*-----------------------------------------------------------------------------
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* Function: SetTxPowerLevel8190()
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*
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@ -2448,30 +2235,6 @@ PHY_SetTxPowerLevel8188E(
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rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
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rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel);
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#if 0
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switch(pHalData->rf_chip)
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{
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case RF_8225:
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PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
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PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
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break;
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case RF_8256:
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PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
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PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
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break;
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case RF_6052:
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PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
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PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
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break;
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case RF_8258:
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break;
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}
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#endif
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}
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@ -2545,30 +2308,6 @@ PHY_ScanOperationBackup8188E(
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IN u8 Operation
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)
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{
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#if 0
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IO_TYPE IoType;
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if(!Adapter->bDriverStopped)
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{
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switch(Operation)
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{
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case SCAN_OPT_BACKUP:
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IoType = IO_CMD_PAUSE_DM_BY_SCAN;
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rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
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break;
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case SCAN_OPT_RESTORE:
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IoType = IO_CMD_RESUME_DM_BY_SCAN;
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rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
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break;
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default:
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RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
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break;
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}
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}
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#endif
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}
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/*-----------------------------------------------------------------------------
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@ -2787,31 +2526,12 @@ PHY_SetBWMode8188E(
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pHalData->CurrentChannelBW = Bandwidth;
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#if 0
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if(Offset==HT_EXTCHNL_OFFSET_LOWER)
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pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
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else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
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pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
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else
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pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
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#else
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pHalData->nCur40MhzPrimeSC = Offset;
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#endif
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if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
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{
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#if 0
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//PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
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#else
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_PHY_SetBWMode92C(Adapter);
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#endif
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}
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else
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{
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//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
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//pHalData->SetBWModeInProgress= FALSE;
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pHalData->CurrentChannelBW = tmpBW;
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}
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}
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@ -2919,11 +2639,7 @@ PHY_SwChnl8188E( // Call after initialization
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if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
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{
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#if 0
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//PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
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#else
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_PHY_SwChnl8192C(Adapter, channel);
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#endif
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if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
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||||
phy_SpurCalibration_8188E( Adapter);
|
||||
if(bResult)
|
||||
|
|
@ -2962,154 +2678,6 @@ phy_SwChnlStepByStep(
|
|||
OUT u32 *delay
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
|
||||
SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
|
||||
u4Byte PreCommonCmdCnt;
|
||||
SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
|
||||
u4Byte PostCommonCmdCnt;
|
||||
SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
|
||||
u4Byte RfDependCmdCnt;
|
||||
SwChnlCmd *CurrentCmd;
|
||||
u1Byte eRFPath;
|
||||
u4Byte RfTXPowerCtrl;
|
||||
BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
|
||||
|
||||
|
||||
RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
|
||||
#if(MP_DRIVER != 1)
|
||||
RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
|
||||
#endif
|
||||
RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
|
||||
|
||||
pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
|
||||
RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
|
||||
|
||||
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
//{
|
||||
// <1> Fill up pre common command.
|
||||
PreCommonCmdCnt = 0;
|
||||
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
|
||||
CmdID_SetTxPowerLevel, 0, 0, 0);
|
||||
phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
|
||||
CmdID_End, 0, 0, 0);
|
||||
|
||||
// <2> Fill up post common command.
|
||||
PostCommonCmdCnt = 0;
|
||||
|
||||
phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
|
||||
CmdID_End, 0, 0, 0);
|
||||
|
||||
// <3> Fill up RF dependent command.
|
||||
RfDependCmdCnt = 0;
|
||||
switch( pHalData->RFChipID )
|
||||
{
|
||||
case RF_8225:
|
||||
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
|
||||
// 2008/09/04 MH Change channel.
|
||||
if(channel==14) channel++;
|
||||
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
||||
CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
|
||||
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
||||
CmdID_End, 0, 0, 0);
|
||||
break;
|
||||
|
||||
case RF_8256:
|
||||
// TEST!! This is not the table for 8256!!
|
||||
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
|
||||
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
||||
CmdID_RF_WriteReg, rRfChannel, channel, 10);
|
||||
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
||||
CmdID_End, 0, 0, 0);
|
||||
break;
|
||||
|
||||
case RF_6052:
|
||||
RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
|
||||
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
||||
CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
|
||||
phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
|
||||
CmdID_End, 0, 0, 0);
|
||||
|
||||
break;
|
||||
|
||||
case RF_8258:
|
||||
break;
|
||||
|
||||
// For FPGA two MAC verification
|
||||
case RF_PSEUDO_11N:
|
||||
return TRUE;
|
||||
default:
|
||||
RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
|
||||
return FALSE;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
do{
|
||||
switch(*stage)
|
||||
{
|
||||
case 0:
|
||||
CurrentCmd=&PreCommonCmd[*step];
|
||||
break;
|
||||
case 1:
|
||||
CurrentCmd=&RfDependCmd[*step];
|
||||
break;
|
||||
case 2:
|
||||
CurrentCmd=&PostCommonCmd[*step];
|
||||
break;
|
||||
}
|
||||
|
||||
if(CurrentCmd->CmdID==CmdID_End)
|
||||
{
|
||||
if((*stage)==2)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*stage)++;
|
||||
(*step)=0;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
switch(CurrentCmd->CmdID)
|
||||
{
|
||||
case CmdID_SetTxPowerLevel:
|
||||
PHY_SetTxPowerLevel8192C(Adapter,channel);
|
||||
break;
|
||||
case CmdID_WritePortUlong:
|
||||
PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
|
||||
break;
|
||||
case CmdID_WritePortUshort:
|
||||
PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
|
||||
break;
|
||||
case CmdID_WritePortUchar:
|
||||
PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
|
||||
break;
|
||||
case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
|
||||
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
{
|
||||
#if 1
|
||||
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
|
||||
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
|
||||
#else
|
||||
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
}while(TRUE);
|
||||
//cosa }/*for(Number of RF paths)*/
|
||||
|
||||
(*delay)=CurrentCmd->msDelay;
|
||||
(*step)++;
|
||||
return FALSE;
|
||||
#endif
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
|
@ -3156,20 +2724,8 @@ phy_FinishSwChnlNow( // We should not call this function directly
|
|||
IN u8 channel
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
u32 delay;
|
||||
|
||||
while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
|
||||
{
|
||||
if(delay>0)
|
||||
rtw_mdelay_os(delay);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Description:
|
||||
// Switch channel synchronously. Called by SwChnlByDelayHandler.
|
||||
|
|
@ -3231,30 +2787,6 @@ PHY_SetMonitorMode8192C(
|
|||
IN BOOLEAN bEnableMonitorMode
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
|
||||
BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
|
||||
|
||||
//2 Note: we may need to stop antenna diversity.
|
||||
if(bEnableMonitorMode)
|
||||
{
|
||||
bFilterOutNonAssociatedBSSID = FALSE;
|
||||
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
|
||||
|
||||
pHalData->bInMonitorMode = TRUE;
|
||||
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
|
||||
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
|
||||
}
|
||||
else
|
||||
{
|
||||
bFilterOutNonAssociatedBSSID = TRUE;
|
||||
RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
|
||||
|
||||
pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
|
||||
pHalData->bInMonitorMode = FALSE;
|
||||
rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3280,20 +2812,9 @@ PHY_CheckIsLegalRfPath8192C(
|
|||
IN struct adapter *pAdapter,
|
||||
IN u32 eRFPath)
|
||||
{
|
||||
// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
|
||||
BOOLEAN rtValue = _TRUE;
|
||||
|
||||
// NOt check RF Path now.!
|
||||
#if 0
|
||||
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
|
||||
{
|
||||
rtValue = FALSE;
|
||||
}
|
||||
if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
|
||||
{
|
||||
|
||||
}
|
||||
#endif
|
||||
return rtValue;
|
||||
|
||||
} /* PHY_CheckIsLegalRfPath8192C */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue