mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Remove dead code inside #if 0
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
2d60bad9ad
commit
b6b121512b
56 changed files with 121 additions and 6115 deletions
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@ -97,50 +97,6 @@ void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
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IN u16 DataRate)
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{
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// We do not support gain table change inACUT now !!!! Delete later !!!
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#if 0//(RTL92SE_FPGA_VERIFY == 0)
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static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
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static u4Byte tx_gain_tbl1[6]
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= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
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static u4Byte tx_gain_tbl2[6]
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= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
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u1Byte i;
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if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
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{
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// Set TX SYNC power G2G3 loop filter
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
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// Change TX AGC gain table
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for (i = 0; i < 6; i++)
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
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// Set PA to high value
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
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}
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else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
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{
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// Set TX SYNC power G2G3 loop filter
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
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// Change TX AGC gain table
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for (i = 0; i < 6; i++)
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
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// Set PA low gain
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PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
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RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
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}
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#endif
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} /* RF_ChangeTxPath */
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@ -328,54 +284,8 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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*/
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} /* PHY_RF6052SetCckTxPower */
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#if 0
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//
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// powerbase0 for OFDM rates
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// powerbase1 for HT MCS rates
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//
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static void getPowerBase(
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IN struct adapter *Adapter,
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IN u8* pPowerLevel,
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IN u8 Channel,
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IN OUT u32* OfdmBase,
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IN OUT u32* MCSBase
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)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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u32 powerBase0, powerBase1;
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u8 Legacy_pwrdiff=0, HT20_pwrdiff=0;
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u8 i, powerlevel[2];
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for(i=0; i<2; i++)
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{
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powerlevel[i] = pPowerLevel[i];
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Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
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powerBase0 = powerlevel[i] + Legacy_pwrdiff;
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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*(OfdmBase+i) = powerBase0;
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//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
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}
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for(i=0; i<2; i++)
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{
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//Check HT20 to HT40 diff
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if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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{
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HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
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powerlevel[i] += HT20_pwrdiff;
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}
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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*(MCSBase+i) = powerBase1;
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//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
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}
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}
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#endif
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//
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// powerbase0 for OFDM rates
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// powerbase1 for HT MCS rates
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//
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void getPowerBase88E(
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IN struct adapter *Adapter,
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IN u8* pPowerLevelOFDM,
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@ -418,139 +328,7 @@ void getPowerBase88E(
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//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
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}
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}
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#if 0
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static void getTxPowerWriteValByRegulatory(
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IN struct adapter *Adapter,
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IN u8 Channel,
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IN u8 index,
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IN u32* powerBase0,
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IN u32* powerBase1,
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OUT u32* pOutWriteVal
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)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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u8 i, chnlGroup, pwr_diff_limit[4];
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u32 writeVal, customer_limit, rf;
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//
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// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
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//
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for(rf=0; rf<2; rf++)
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{
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switch(pHalData->EEPROMRegulatory)
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{
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case 0: // Realtek better performance
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// increase power diff defined by Realtek for large power
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chnlGroup = 0;
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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case 1: // Realtek regulatory
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// increase power diff defined by Realtek for regulatory
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{
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if(pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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if(pHalData->pwrGroupCnt >= 3)
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{
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if(Channel <= 3)
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chnlGroup = 0;
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else if(Channel >= 4 && Channel <= 9)
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chnlGroup = 1;
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else if(Channel > 9)
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chnlGroup = 2;
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if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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chnlGroup++;
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else
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chnlGroup+=4;
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}
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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}
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break;
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case 2: // Better regulatory
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// don't increase any power diff
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writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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case 3: // Customer defined power diff.
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// increase power diff defined by customer.
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chnlGroup = 0;
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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{
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//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
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// ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
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}
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else
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{
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//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
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// ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
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}
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for (i=0; i<4; i++)
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{
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pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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{
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if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
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pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
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}
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else
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{
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if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
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pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
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}
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}
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customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
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(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
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writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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default:
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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}
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// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
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// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
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// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
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if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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writeVal = 0x14141414;
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else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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writeVal = 0x00000000;
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// 20100628 Joseph: High power mode for BT-Coexist mechanism.
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// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
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if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
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{
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//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
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writeVal = writeVal - 0x06060606;
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}
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else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
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{
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//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
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writeVal = writeVal;
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}
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*(pOutWriteVal+rf) = writeVal;
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}
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}
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#endif
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void getTxPowerWriteValByRegulatory88E(
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IN struct adapter *Adapter,
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IN u8 Channel,
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@ -571,15 +349,8 @@ void getTxPowerWriteValByRegulatory88E(
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//
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// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
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//
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#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
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if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
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Regulatory = 2;
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#endif
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for(rf=0; rf<2; rf++)
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{
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switch(Regulatory)
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{
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for(rf=0; rf<2; rf++) {
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switch(Regulatory) {
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case 0: // Realtek better performance
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// increase power diff defined by Realtek for large power
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chnlGroup = 0;
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@ -1012,30 +783,7 @@ PHY_RF6052_Config8188E(
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// Config BB and RF
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//
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rtStatus = phy_RF6052_Config_ParaFile(Adapter);
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#if 0
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switch( Adapter->MgntInfo.bRegHwParaFile )
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{
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case 0:
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phy_RF6052_Config_HardCode(Adapter);
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break;
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case 1:
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rtStatus = phy_RF6052_Config_ParaFile(Adapter);
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break;
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case 2:
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// Partial Modify.
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phy_RF6052_Config_HardCode(Adapter);
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phy_RF6052_Config_ParaFile(Adapter);
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break;
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default:
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phy_RF6052_Config_HardCode(Adapter);
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break;
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}
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#endif
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return rtStatus;
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}
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