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rtl8188eu: Replace p1byte with u8

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2014-12-30 17:50:44 -06:00
parent 8aad1f53ce
commit b77dd7b8df
31 changed files with 633 additions and 635 deletions
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110
hal/Hal8188ERateAdaptive.c
View file

@ -19,7 +19,7 @@ Major Change History:
// Rate adaptive parameters
static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0
static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0
{6,5,4,3,0,4},//86 , idx=1
{6,5,4,2,0,4},//81 , idx=2
{8,7,6,4,0,6},//75 , idx=3
@ -43,24 +43,24 @@ static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0
{49,22,18,14,0,48},//6 , idx=0x15
{49,16,16,0,0,48}};//3 //3, idx=0x16
static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up
static u8 RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up
static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
static u8 PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
// wilson modify
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SS<TH
0x0b,0x0c,0x0d,0x0e,0x0f,0x11,0x13,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, // SS>TH
static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, // SS>TH
0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
static u8 RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
0,0,0,0,0,0x24,0x26,0x2a,
0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};
@ -73,11 +73,11 @@ static u16 N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8,
12,18,24,36,48,72,96,108,
30,40,50,80,120,200,280,320,
150,160,240,360,500,600,800,1000};
static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
static u8 TRYING_NECESSARY[RATESIZE] = {2,2,2,2,
2,2,3,3,4,4,5,7,
4,4,7,10,10,12,12,18,
5,7,7,8,11,18,36,60}; // 0329 // 1207
static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
static u8 DROPING_NECESSARY[RATESIZE] = {1,1,1,1,
1,2,3,4,5,6,7,8,
1,2,3,4,5,6,7,8,
5,6,7,8,9,10,11,12};
@ -98,7 +98,7 @@ static u32 INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode
0, // 14:
0, // 15:
};
static u1Byte PendingForRateUpFail[5]={2,10,24,40,60};
static u8 PendingForRateUpFail[5]={2,10,24,40,60};
static u16 DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms
// End Rate adaptive parameters
@ -107,10 +107,10 @@ static void
odm_SetTxRPTTiming_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo,
IN u1Byte extend
IN u8 extend
)
{
u1Byte idx = 0;
u8 idx = 0;
for(idx=0; idx<5; idx++)
if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
@ -138,8 +138,8 @@ odm_RateDown_8188E(
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID, LowestRate, HighestRate;
u1Byte i;
u8 RateID, LowestRate, HighestRate;
u8 i;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n"));
if(NULL == pRaInfo)
@ -211,8 +211,8 @@ odm_RateUp_8188E(
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID, HighestRate;
u1Byte i;
u8 RateID, HighestRate;
u8 i;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E() \n"));
if(NULL == pRaInfo)
@ -274,7 +274,7 @@ RateUpfinish:
}
static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){
u1Byte RateID;
u8 RateID;
RateID=pRaInfo->DecisionRate;
pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1;
pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1;
@ -286,9 +286,9 @@ odm_RateDecision_8188E(
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
//u32 pool_retry;
static u1Byte DynamicTxRPTTimingCounter=0;
static u8 DynamicTxRPTTimingCounter=0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n"));
@ -541,12 +541,12 @@ odm_PTDecision_8188E(
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte stage_BUF;
u1Byte j;
u1Byte temp_stage;
u8 stage_BUF;
u8 j;
u8 temp_stage;
u32 numsc;
u32 num_total;
u1Byte stage_id;
u8 stage_id;
stage_BUF=pRaInfo->PTStage;
numsc = 0;
@ -616,13 +616,13 @@ ODM_RASupport_Init(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
#if 1
u1Byte WirelessMode=0xFF; //invalid value
u1Byte max_rate_idx = 0x13; //MCS7
u8 WirelessMode=0xFF; //invalid value
u8 max_rate_idx = 0x13; //MCS7
if(pDM_Odm->pWirelessMode!=NULL){
WirelessMode=*(pDM_Odm->pWirelessMode);
}
@ -690,7 +690,7 @@ ODM_RAInfo_Init_all(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte MacID = 0;
u8 MacID = 0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n"));
pDM_Odm->CurrminRptTime = 0;
@ -702,10 +702,10 @@ ODM_RAInfo_Init_all(
}
u1Byte
u8
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
@ -715,13 +715,13 @@ ODM_RA_GetShortGI_8188E(
return pDM_Odm->RAInfo[MacID].RateSGI;
}
u1Byte
u8
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
u1Byte DecisionRate = 0;
u8 DecisionRate = 0;
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return 0;
@ -731,13 +731,13 @@ ODM_RA_GetDecisionRate_8188E(
return DecisionRate;
}
u1Byte
u8
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
u1Byte PTStage = 5;
u8 PTStage = 5;
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return 0;
PTStage = (pDM_Odm->RAInfo[MacID].PTStage);
@ -749,10 +749,10 @@ ODM_RA_GetHwPwrStatus_8188E(
void
ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u8 MacID,
IN u8 RateID,
IN u32 RateMask,
IN u1Byte SGIEnable
IN u8 SGIEnable
)
{
PODM_RA_INFO_T pRaInfo = NULL;
@ -773,8 +773,8 @@ ODM_RA_UpdateRateInfo_8188E(
void
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
IN u8 MacID,
IN u8 Rssi
)
{
PODM_RA_INFO_T pRaInfo = NULL;
@ -801,15 +801,15 @@ ODM_RA_Set_TxRPT_Time(
void
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u8 * TxRPT_Buf,
IN u16 TxRPT_Len,
IN u32 MacIDValidEntry0,
IN u32 MacIDValidEntry1
)
{
PODM_RA_INFO_T pRAInfo = NULL;
u1Byte MacId = 0;
pu1Byte pBuffer = NULL;
u8 MacId = 0;
u8 * pBuffer = NULL;
u32 valid = 0, ItemNum = 0;
u16 minRptTime = 0x927c;
@ -937,7 +937,7 @@ ODM_RASupport_Init(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
return 0;
@ -951,27 +951,27 @@ ODM_RAInfo_Init_all(
return 0;
}
u1Byte
u8
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
return 0;
}
u1Byte
u8
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
return 0;
}
u1Byte
u8
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
)
{
return 0;
@ -980,10 +980,10 @@ ODM_RA_GetHwPwrStatus_8188E(
void
ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u8 MacID,
IN u8 RateID,
IN u32 RateMask,
IN u1Byte SGIEnable
IN u8 SGIEnable
)
{
return;
@ -992,8 +992,8 @@ ODM_RA_UpdateRateInfo_8188E(
void
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
IN u8 MacID,
IN u8 Rssi
)
{
return;
@ -1011,7 +1011,7 @@ ODM_RA_Set_TxRPT_Time(
void
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u8 * TxRPT_Buf,
IN u16 TxRPT_Len,
IN u32 MacIDValidEntry0,
IN u32 MacIDValidEntry1

26
hal/Hal8188ERateAdaptive.h
View file

@ -51,46 +51,46 @@ ODM_RAInfo_Init_all(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
);
u1Byte
u8
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
);
u1Byte
u8
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
);
u1Byte
u8
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN u8 MacID
);
void
ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u8 MacID,
IN u8 RateID,
IN u32 RateMask,
IN u1Byte SGIEnable
IN u8 SGIEnable
);
void
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
IN u8 MacID,
IN u8 Rssi
);
void
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u8 * TxRPT_Buf,
IN u16 TxRPT_Len,
IN u32 MacIDValidEntry0,
IN u32 MacIDValidEntry1

30
hal/HalHWImg8188E_BB.c
View file

@ -338,9 +338,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u32);
u32 * Array = Array_AGC_TAB_1T_8188E;
BOOLEAN biol = FALSE;
@ -608,9 +608,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 _interface = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MP_8188E_AGC_TAB_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_AGC_TAB_1T_ICUT;
@ -900,9 +900,9 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u32);
u32 * Array = Array_PHY_REG_1T_8188E;
BOOLEAN biol = FALSE;
@ -1309,9 +1309,9 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 _interface = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MP_8188E_PHY_REG_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_PHY_REG_1T_ICUT;
@ -1392,9 +1392,9 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u32);
u32 * Array = Array_PHY_REG_PG_8188E;
BOOLEAN biol = FALSE;

26
hal/HalHWImg8188E_MAC.c
View file

@ -166,9 +166,9 @@ ODM_ReadAndConfig_MAC_REG_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MAC_REG_8188E)/sizeof(u32);
u32 * Array = Array_MAC_REG_8188E;
BOOLEAN biol = FALSE;
@ -215,7 +215,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WB_cmd(pxmit_frame,(u16)v1, (u1Byte)v2,0xFF);
rtw_IOL_append_WB_cmd(pxmit_frame,(u16)v1, (u8)v2,0xFF);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
cmpdata[cmpdata_idx].addr = v1;
cmpdata[cmpdata_idx].value= v2;
@ -225,7 +225,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
else
#endif //endif CONFIG_IOL_IOREG_CFG
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
}
continue;
}
@ -253,7 +253,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
if(biol){
if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WB_cmd(pxmit_frame,(u16)v1, (u1Byte)v2,0xFF);
rtw_IOL_append_WB_cmd(pxmit_frame,(u16)v1, (u8)v2,0xFF);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
cmpdata[cmpdata_idx].addr = v1;
cmpdata[cmpdata_idx].value= v2;
@ -263,7 +263,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
}
READ_NEXT_PAIR(v1, v2, i);
@ -289,7 +289,7 @@ ODM_ReadAndConfig_MAC_REG_8188E(
//compare writed data
{
u32 idx;
u1Byte cdata;
u8 cdata;
// HAL_STATUS_FAILURE;
printk(" MAC data compare => array_len:%d \n",cmpdata_idx);
for(idx=0;idx< cmpdata_idx;idx++)
@ -438,9 +438,9 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 _interface = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MP_8188E_MAC_REG_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_MAC_REG_ICUT;
@ -459,7 +459,7 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
continue;
}
else
@ -482,7 +482,7 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
READ_NEXT_PAIR(v1, v2, i);
}

12
hal/HalHWImg8188E_RF.c
View file

@ -187,9 +187,9 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte interfaceValue = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 interfaceValue = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u32);
u32 * Array = Array_RadioA_1T_8188E;
BOOLEAN biol = FALSE;
@ -504,9 +504,9 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u1Byte platform = pDM_Odm->SupportPlatform;
u1Byte _interface = pDM_Odm->SupportInterface;
u1Byte board = pDM_Odm->BoardType;
u8 platform = pDM_Odm->SupportPlatform;
u8 _interface = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MP_8188E_RadioA_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_RadioA_1T_ICUT;

8
hal/HalPhyRf.c
View file

@ -29,7 +29,7 @@ ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte i;
u8 i;
struct adapter *Adapter = pDM_Odm->Adapter;
if (!IS_HARDWARE_TYPE_8192D(Adapter))
@ -56,11 +56,11 @@ ODM_ResetIQKResult(
}
}
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
u8 ODM_GetRightChnlPlaceforIQK(u8 chnl)
{
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
u1Byte place = chnl;
u8 place = chnl;
if(chnl > 14)

2
hal/HalPhyRf.h
View file

@ -24,7 +24,7 @@
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void ODM_ResetIQKResult(PDM_ODM_T pDM_Odm );
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl);
u8 ODM_GetRightChnlPlaceforIQK(u8 chnl);
#endif // #ifndef __HAL_PHY_RF_H__

84
hal/HalPhyRf_8188e.c
View file

@ -47,8 +47,8 @@
//3============================================================
void setIqkMatrix(
PDM_ODM_T pDM_Odm,
u1Byte OFDM_index,
u1Byte RFPath,
u8 OFDM_index,
u8 RFPath,
s4Byte IqkResult_X,
s4Byte IqkResult_Y
)
@ -133,9 +133,9 @@ void setIqkMatrix(
void doIQK(
PDM_ODM_T pDM_Odm,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -168,12 +168,12 @@ void doIQK(
void
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
u8 Type, // 0 = OFDM, 1 = CCK
u8 * pDirection, // 1 = +(increase) 2 = -(decrease)
u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
)
{
u1Byte pwr_value = 0;
u8 pwr_value = 0;
//
// Tx power tracking BB swing table.
// The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB
@ -252,14 +252,14 @@ void
odm_TxPwrTrackSetPwr88E(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
u8 RFPath,
u8 ChannelMappedIndex
)
{
if (Method == TXAGC) {
u1Byte cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];
u1Byte BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT];
u1Byte rf = 0;
u8 cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];
u8 BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT];
u8 rf = 0;
u32 pwr = 0, TxAGC = 0;
struct adapter *Adapter = pDM_Odm->Adapter;
//printk("odm_TxPwrTrackSetPwr88E CH=%d, modify TXAGC \n", *(pDM_Odm->pChannel));
@ -345,8 +345,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
u1Byte ThermalValue_AVG_count = 0;
u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
u8 ThermalValue_AVG_count = 0;
u32 ThermalValue_AVG = 0;
s4Byte ele_A=0, ele_D, TempCCk, X, value32;
s4Byte Y, ele_C=0;
@ -356,8 +356,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
BOOLEAN is2T = FALSE;
BOOLEAN bInteralPA = FALSE;
u1Byte OFDM_min_index = 6, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
u8 OFDM_min_index = 6, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
u8 Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
enum _POWER_DEC_INC { POWER_DEC, POWER_INC };
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
@ -367,7 +367,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
// {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}}
{0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,-1,-2,-3,-4,-4,-4,-4,-5,-7,-8,-9,-9,-10}
};
u1Byte thermalThreshold[2][index_mapping_NUM_88E]={
u8 thermalThreshold[2][index_mapping_NUM_88E]={
// {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}}
{0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25}
};
@ -383,7 +383,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase));
ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); //0x42: RF Reg[15:10] 88E
ThermalValue = (u8)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); //0x42: RF Reg[15:10] 88E
if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
return;
@ -418,7 +418,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
if(ThermalValue_AVG_count)
{
ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue));
}
@ -566,14 +566,14 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 //ms
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_IQK_8188E(
IN struct adapter *pAdapter,
IN BOOLEAN configPathB
)
{
u32 regEAC, regE94, regE9C, regEA4;
u1Byte result = 0x00;
u8 result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
@ -619,14 +619,14 @@ phy_PathA_IQK_8188E(
return result;
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK(
IN struct adapter *pAdapter,
IN BOOLEAN configPathB
)
{
u32 regEAC, regE94, regE9C, regEA4, u4tmp;
u1Byte result = 0x00;
u8 result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));
@ -756,13 +756,13 @@ phy_PathA_RxIQK(
return result;
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathB_IQK_8188E(
IN struct adapter *pAdapter
)
{
u32 regEAC, regEB4, regEBC, regEC4, regECC;
u1Byte result = 0x00;
u8 result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
@ -813,7 +813,7 @@ _PHY_PathAFillIQKMatrix(
IN struct adapter *pAdapter,
IN BOOLEAN bIQKOK,
IN s4Byte result[][8],
IN u1Byte final_candidate,
IN u8 final_candidate,
IN BOOLEAN bTxOnly
)
{
@ -873,7 +873,7 @@ _PHY_PathBFillIQKMatrix(
IN struct adapter *pAdapter,
IN BOOLEAN bIQKOK,
IN s4Byte result[][8],
IN u1Byte final_candidate,
IN u8 final_candidate,
IN BOOLEAN bTxOnly //do Tx only
)
{
@ -1008,7 +1008,7 @@ _PHY_ReloadMACRegisters(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);
ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)MACBackup[i]);
}
ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
}
@ -1060,9 +1060,9 @@ _PHY_MACSettingCalibration(
ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));
ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
}
ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5)));
ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
}
@ -1102,14 +1102,14 @@ BOOLEAN
phy_SimularityCompare_8188E(
IN struct adapter *pAdapter,
IN s4Byte result[][8],
IN u1Byte c1,
IN u1Byte c2
IN u8 c1,
IN u8 c2
)
{
u32 i, j, diff, SimularityBitMap, bound = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
u8 final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
BOOLEAN bResult = TRUE;
BOOLEAN is2T;
s4Byte tmp1 = 0,tmp2 = 0;
@ -1226,14 +1226,14 @@ void
phy_IQCalibrate_8188E(
IN struct adapter *pAdapter,
IN s4Byte result[][8],
IN u1Byte t,
IN u8 t,
IN BOOLEAN is2T
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
u32 i;
u1Byte PathAOK, PathBOK;
u8 PathAOK, PathBOK;
u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
@ -1281,7 +1281,7 @@ else
_PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
if(t==0) {
pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u8)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
}
if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
@ -1422,7 +1422,7 @@ phy_LCCalibrate_8188E(
IN BOOLEAN is2T
)
{
u1Byte tmpReg;
u8 tmpReg;
u32 RF_Amode=0, RF_Bmode=0, LC_Cal;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
@ -1496,7 +1496,7 @@ phy_APCalibrate_8188E(
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
u32 regD[PATH_NUM];
u32 tmpReg, index, offset, apkbound;
u1Byte path, i, pathbound = PATH_NUM;
u8 path, i, pathbound = PATH_NUM;
u32 BB_backup[APK_BB_REG_NUM];
u32 BB_REG[APK_BB_REG_NUM] = {
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
@ -1941,8 +1941,8 @@ PHY_IQCalibrate_8188E(
#endif//(MP_DRIVER == 1)
s4Byte result[4][8]; //last is final result
u1Byte i, final_candidate, Indexforchannel;
u1Byte channelToIQK = 7;
u8 i, final_candidate, Indexforchannel;
u8 channelToIQK = 7;
BOOLEAN bPathAOK, bPathBOK;
s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
BOOLEAN is12simular, is13simular, is23simular;
@ -2217,7 +2217,7 @@ void phy_SetRFPathSwitch_8188E(
if(pAdapter->hw_init_completed == false)
{
u1Byte u1bTmp;
u8 u1bTmp;
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
//ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);

4
hal/HalPhyRf_8188e.h
View file

@ -36,8 +36,8 @@ typedef enum _PWRTRACK_CONTROL_METHOD {
void
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
u8 Type, // 0 = OFDM, 1 = CCK
u8 * pDirection, // 1 = +(increase) 2 = -(decrease)
u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
);

206
hal/odm.c
View file

@ -37,7 +37,7 @@ const u16 dB_Invert_Table[8][12] = {
{ 17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}};
// 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test.
//u1Byte tmpNumBssDesc;
//u8 tmpNumBssDesc;
//RT_WLAN_BSS tmpbssDesc[MAX_BSS_DESC];
//============================================================
@ -111,7 +111,7 @@ u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
};
u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
@ -148,7 +148,7 @@ u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
};
u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
@ -315,7 +315,7 @@ odm_AdaptivityInit(
void
odm_Adaptivity(
IN PDM_ODM_T pDM_Odm,
IN u1Byte IGI
IN u8 IGI
);
//END---------BB POWER SAVE-----------------------//
@ -357,7 +357,7 @@ odm_DynamicTxPowerSavePowerIndex(
void
odm_DynamicTxPowerWritePowerIndex(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Value);
IN u8 Value);
void
odm_DynamicTxPower_92C(
@ -418,13 +418,13 @@ odm_SwAntDivInit_NIC(
void
odm_SwAntDivChkAntSwitch(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
IN u8 Step
);
void
odm_SwAntDivChkAntSwitchNIC(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
IN u8 Step
);
@ -512,13 +512,13 @@ odm_StaDefAntSel(
IN u32 OFDM_Ant2_Cnt,
IN u32 CCK_Ant1_Cnt,
IN u32 CCK_Ant2_Cnt,
OUT u1Byte *pDefAnt
OUT u8 *pDefAnt
);
void
odm_SetRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant,
IN u8 Ant,
IN BOOLEAN bDualPath
);
@ -676,15 +676,15 @@ ODM_CmnInfoInit(
pDM_Odm->SupportAbility = (u32)Value;
break;
case ODM_CMNINFO_PLATFORM:
pDM_Odm->SupportPlatform = (u1Byte)Value;
pDM_Odm->SupportPlatform = (u8)Value;
break;
case ODM_CMNINFO_INTERFACE:
pDM_Odm->SupportInterface = (u1Byte)Value;
pDM_Odm->SupportInterface = (u8)Value;
break;
case ODM_CMNINFO_MP_TEST_CHIP:
pDM_Odm->bIsMPChip= (u1Byte)Value;
pDM_Odm->bIsMPChip= (u8)Value;
break;
case ODM_CMNINFO_IC_TYPE:
@ -692,38 +692,38 @@ ODM_CmnInfoInit(
break;
case ODM_CMNINFO_CUT_VER:
pDM_Odm->CutVersion = (u1Byte)Value;
pDM_Odm->CutVersion = (u8)Value;
break;
case ODM_CMNINFO_FAB_VER:
pDM_Odm->FabVersion = (u1Byte)Value;
pDM_Odm->FabVersion = (u8)Value;
break;
case ODM_CMNINFO_RF_TYPE:
pDM_Odm->RFType = (u1Byte)Value;
pDM_Odm->RFType = (u8)Value;
break;
case ODM_CMNINFO_RF_ANTENNA_TYPE:
pDM_Odm->AntDivType= (u1Byte)Value;
pDM_Odm->AntDivType= (u8)Value;
break;
case ODM_CMNINFO_BOARD_TYPE:
pDM_Odm->BoardType = (u1Byte)Value;
pDM_Odm->BoardType = (u8)Value;
break;
case ODM_CMNINFO_EXT_LNA:
pDM_Odm->ExtLNA = (u1Byte)Value;
pDM_Odm->ExtLNA = (u8)Value;
break;
case ODM_CMNINFO_EXT_PA:
pDM_Odm->ExtPA = (u1Byte)Value;
pDM_Odm->ExtPA = (u8)Value;
break;
case ODM_CMNINFO_EXT_TRSW:
pDM_Odm->ExtTRSW = (u1Byte)Value;
pDM_Odm->ExtTRSW = (u8)Value;
break;
case ODM_CMNINFO_PATCH_ID:
pDM_Odm->PatchID = (u1Byte)Value;
pDM_Odm->PatchID = (u8)Value;
break;
case ODM_CMNINFO_BINHCT_TEST:
pDM_Odm->bInHctTest = (BOOLEAN)Value;
@ -763,7 +763,7 @@ ODM_CmnInfoHook(
// Dynamic call by reference pointer.
//
case ODM_CMNINFO_MAC_PHY_MODE:
pDM_Odm->pMacPhyMode = (u1Byte *)pValue;
pDM_Odm->pMacPhyMode = (u8 *)pValue;
break;
case ODM_CMNINFO_TX_UNI:
@ -775,27 +775,27 @@ ODM_CmnInfoHook(
break;
case ODM_CMNINFO_WM_MODE:
pDM_Odm->pWirelessMode = (u1Byte *)pValue;
pDM_Odm->pWirelessMode = (u8 *)pValue;
break;
case ODM_CMNINFO_BAND:
pDM_Odm->pBandType = (u1Byte *)pValue;
pDM_Odm->pBandType = (u8 *)pValue;
break;
case ODM_CMNINFO_SEC_CHNL_OFFSET:
pDM_Odm->pSecChOffset = (u1Byte *)pValue;
pDM_Odm->pSecChOffset = (u8 *)pValue;
break;
case ODM_CMNINFO_SEC_MODE:
pDM_Odm->pSecurity = (u1Byte *)pValue;
pDM_Odm->pSecurity = (u8 *)pValue;
break;
case ODM_CMNINFO_BW:
pDM_Odm->pBandWidth = (u1Byte *)pValue;
pDM_Odm->pBandWidth = (u8 *)pValue;
break;
case ODM_CMNINFO_CHNL:
pDM_Odm->pChannel = (u1Byte *)pValue;
pDM_Odm->pChannel = (u8 *)pValue;
break;
case ODM_CMNINFO_DMSP_GET_VALUE:
@ -819,7 +819,7 @@ ODM_CmnInfoHook(
break;
case ODM_CMNINFO_ONE_PATH_CCA:
pDM_Odm->pOnePathCCA = (u1Byte *)pValue;
pDM_Odm->pOnePathCCA = (u8 *)pValue;
break;
case ODM_CMNINFO_DRV_STOP:
@ -835,14 +835,14 @@ ODM_CmnInfoHook(
break;
case ODM_CMNINFO_ANT_TEST:
pDM_Odm->pAntennaTest = (u1Byte *)pValue;
pDM_Odm->pAntennaTest = (u8 *)pValue;
break;
case ODM_CMNINFO_NET_CLOSED:
pDM_Odm->pbNet_closed = (BOOLEAN *)pValue;
break;
case ODM_CMNINFO_MP_MODE:
pDM_Odm->mp_mode = (u1Byte *)pValue;
pDM_Odm->mp_mode = (u8 *)pValue;
break;
//case ODM_CMNINFO_BT_COEXIST:
@ -917,7 +917,7 @@ ODM_CmnInfoUpdate(
break;
case ODM_CMNINFO_RF_TYPE:
pDM_Odm->RFType = (u1Byte)Value;
pDM_Odm->RFType = (u8)Value;
break;
case ODM_CMNINFO_WIFI_DIRECT:
@ -935,7 +935,7 @@ ODM_CmnInfoUpdate(
pDM_Odm->bsta_state = (BOOLEAN)Value;
break;
case ODM_CMNINFO_RSSI_MIN:
pDM_Odm->RSSI_Min= (u1Byte)Value;
pDM_Odm->RSSI_Min= (u8)Value;
break;
case ODM_CMNINFO_DBG_COMP:
@ -946,11 +946,11 @@ ODM_CmnInfoUpdate(
pDM_Odm->DebugLevel = (u32)Value;
break;
case ODM_CMNINFO_RA_THRESHOLD_HIGH:
pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
break;
case ODM_CMNINFO_RA_THRESHOLD_LOW:
pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value;
pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
break;
#if(BT_30_SUPPORT == 1)
// The following is for BT HS mode and BT coexist mechanism.
@ -963,7 +963,7 @@ ODM_CmnInfoUpdate(
break;
case ODM_CMNINFO_BT_DIG:
pDM_Odm->btHsDigVal = (u1Byte)Value;
pDM_Odm->btHsDigVal = (u8)Value;
break;
case ODM_CMNINFO_BT_BUSY:
@ -986,7 +986,7 @@ odm_CommonInfoSelfInit(
)
{
pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
{
#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
@ -1006,8 +1006,8 @@ odm_CommonInfoSelfUpdate(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte EntryCnt=0;
u1Byte i;
u8 EntryCnt=0;
u8 i;
PSTA_INFO_T pEntry;
if(*(pDM_Odm->pBandWidth) == ODM_BW40M) {
@ -1133,19 +1133,19 @@ ODM_ChangeDynamicInitGainThresh(
{
if(DM_Value > 30)
DM_Value = 30;
pDM_DigTable->BackoffVal = (u1Byte)DM_Value;
pDM_DigTable->BackoffVal = (u8)DM_Value;
}
else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
{
if(DM_Value == 0)
DM_Value = 0x1;
pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value;
pDM_DigTable->rx_gain_range_min = (u8)DM_Value;
}
else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
{
if(DM_Value > 0x50)
DM_Value = 0x50;
pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value;
pDM_DigTable->rx_gain_range_max = (u8)DM_Value;
}
} /* DM_ChangeDynamicInitGainThresh */
@ -1167,7 +1167,7 @@ int getIGIForDiff(int value_IGI)
void
ODM_Write_DIG(
IN PDM_ODM_T pDM_Odm,
IN u1Byte CurrentIGI
IN u8 CurrentIGI
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
@ -1222,9 +1222,9 @@ odm_DIGbyRSSI_LPS(
struct adapter * pAdapter =pDM_Odm->Adapter;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
u1Byte bFwCurrentInPSMode = FALSE;
u1Byte CurrentIGI=pDM_Odm->RSSI_Min;
u8 RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
u8 bFwCurrentInPSMode = FALSE;
u8 CurrentIGI=pDM_Odm->RSSI_Min;
if(! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E)))
return;
@ -1304,7 +1304,7 @@ IN PDM_ODM_T pDM_Odm
void
odm_Adaptivity(
IN PDM_ODM_T pDM_Odm,
IN u1Byte IGI
IN u8 IGI
)
{
s1Byte TH_L2H_dmc, TH_H2L_dmc;
@ -1355,7 +1355,7 @@ odm_Adaptivity(
IGI_target = pDM_Odm->IGI_Base;
}
pDM_Odm->IGI_target = (u1Byte) IGI_target;
pDM_Odm->IGI_target = (u8) IGI_target;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
(*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State));
@ -1377,11 +1377,11 @@ odm_Adaptivity(
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u8)TH_H2L_dmc);
}
else
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u8)TH_H2L_dmc<<8) | (u8)TH_L2H_dmc);
}
#if 1
@ -1394,7 +1394,7 @@ odm_DIGInit(
//pDM_DigTable->Dig_Enable_Flag = TRUE;
//pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
//pDM_DigTable->PreIGValue = 0x0;
//pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
//pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
@ -1448,12 +1448,12 @@ odm_DIG(
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
u1Byte DIG_Dynamic_MIN;
u1Byte DIG_MaxOfMin;
u8 DIG_Dynamic_MIN;
u8 DIG_MaxOfMin;
BOOLEAN FirstConnect, FirstDisConnect;
u1Byte dm_dig_max, dm_dig_min, offset;
u1Byte CurrentIGI = pDM_DigTable->CurIGValue;
u1Byte Adap_IGI_Upper = pDM_Odm->IGI_target + 30 + (u1Byte) pDM_Odm->TH_L2H_ini -(u1Byte) pDM_Odm->TH_EDCCA_HL_diff;
u8 dm_dig_max, dm_dig_min, offset;
u8 CurrentIGI = pDM_DigTable->CurIGValue;
u8 Adap_IGI_Upper = pDM_Odm->IGI_target + 30 + (u8) pDM_Odm->TH_L2H_ini -(u8) pDM_Odm->TH_EDCCA_HL_diff;
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0))
@ -1651,7 +1651,7 @@ odm_DIG(
{
if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV))
{
DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
}
}
@ -1692,7 +1692,7 @@ odm_DIG(
pDM_DigTable->LargeFAHit++;
if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)
{
pDM_DigTable->ForbiddenIGI = (u1Byte)CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
pDM_DigTable->ForbiddenIGI = (u8)CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
pDM_DigTable->LargeFAHit = 1;
}
@ -1846,7 +1846,7 @@ odm_DIG(
CurrentIGI = Adap_IGI_Upper;
if(CurrentIGI > (pDM_Odm->IGI_target + 4))
CurrentIGI = (u1Byte)pDM_Odm->IGI_target + 4;
CurrentIGI = (u8)pDM_Odm->IGI_target + 4;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
@ -1918,7 +1918,7 @@ odm_DIGInit(
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
pDM_DigTable->FALowThresh = DMfalseALARM_THRESH_LOW;
@ -1961,11 +1961,11 @@ odm_DIG(
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
u1Byte DIG_Dynamic_MIN;
u1Byte DIG_MaxOfMin;
u8 DIG_Dynamic_MIN;
u8 DIG_MaxOfMin;
BOOLEAN FirstConnect, FirstDisConnect;
u1Byte dm_dig_max, dm_dig_min;
u1Byte CurrentIGI = pDM_DigTable->CurIGValue;
u8 dm_dig_max, dm_dig_min;
u8 CurrentIGI = pDM_DigTable->CurIGValue;
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0))
@ -2139,7 +2139,7 @@ odm_DIG(
{
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
}
}
@ -2430,7 +2430,7 @@ odm_CCKPacketDetectionThresh(
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
u1Byte CurCCK_CCAThres;
u8 CurCCK_CCAThres;
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
@ -2467,7 +2467,7 @@ odm_CCKPacketDetectionThresh(
void
ODM_Write_CCK_CCA_Thres(
IN PDM_ODM_T pDM_Odm,
IN u1Byte CurCCK_CCAThres
IN u8 CurCCK_CCAThres
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
@ -2584,12 +2584,12 @@ odm_1R_CCA(
void
ODM_RF_Saving(
IN PDM_ODM_T pDM_Odm,
IN u1Byte bForceInNormal
IN u8 bForceInNormal
)
{
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
u1Byte Rssi_Up_bound = 30 ;
u1Byte Rssi_Low_bound = 25;
u8 Rssi_Up_bound = 30 ;
u8 Rssi_Low_bound = 25;
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
{
Rssi_Up_bound = 50 ;
@ -2697,12 +2697,12 @@ u32 ODM_Get_Rate_Bitmap(
IN PDM_ODM_T pDM_Odm,
IN u32 macid,
IN u32 ra_mask,
IN u1Byte rssi_level)
IN u8 rssi_level)
{
PSTA_INFO_T pEntry;
u32 rate_bitmap = 0x0fffffff;
u1Byte WirelessMode;
//u1Byte WirelessMode =*(pDM_Odm->pWirelessMode);
u8 WirelessMode;
//u8 WirelessMode =*(pDM_Odm->pWirelessMode);
pEntry = pDM_Odm->pODM_StaInfo[macid];
@ -2853,7 +2853,7 @@ odm_RefreshRateAdaptiveMaskCE(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte i;
u8 i;
struct adapter *pAdapter = pDM_Odm->Adapter;
if(pAdapter->bDriverStopped)
@ -2896,14 +2896,14 @@ ODM_RAStateCheck(
IN PDM_ODM_T pDM_Odm,
IN s4Byte RSSI,
IN BOOLEAN bForceUpdate,
OUT pu1Byte pRATRState
OUT u8 * pRATRState
)
{
PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive;
const u1Byte GoUpGap = 5;
u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh;
u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh;
u1Byte RATRState;
const u8 GoUpGap = 5;
u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
u8 RATRState;
// Threshold Adjustment:
// when RSSI state trends to go up one or two levels, make sure RSSI is high enough.
@ -2973,7 +2973,7 @@ odm_DynamicTxPowerSavePowerIndex(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte index;
u8 index;
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
struct adapter *Adapter = pDM_Odm->Adapter;
@ -2988,7 +2988,7 @@ odm_DynamicTxPowerRestorePowerIndex(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte index;
u8 index;
struct adapter * Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -3001,10 +3001,10 @@ odm_DynamicTxPowerRestorePowerIndex(
void
odm_DynamicTxPowerWritePowerIndex(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Value)
IN u8 Value)
{
u1Byte index;
u8 index;
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for(index = 0; index< 6; index++)
@ -3521,7 +3521,7 @@ ODM_SwAntDivRestAfterLink(
void
ODM_SwAntDivChkPerPktRssi(
IN PDM_ODM_T pDM_Odm,
IN u1Byte StationID,
IN u8 StationID,
IN PODM_PHY_INFO_T pPhyInfo
)
{
@ -3552,7 +3552,7 @@ ODM_SwAntDivChkPerPktRssi(
void
odm_SwAntDivChkAntSwitch(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
IN u8 Step
)
{
//
@ -3595,7 +3595,7 @@ odm_SwAntDivChkAntSwitch(
void
ODM_SetAntenna(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Antenna)
IN u8 Antenna)
{
ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna);
}
@ -3606,7 +3606,7 @@ ODM_SetAntenna(
void
odm_SwAntDivChkAntSwitchNIC(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
IN u8 Step
)
{
}
@ -3629,12 +3629,12 @@ void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
void odm_SwAntDivInit( IN PDM_ODM_T pDM_Odm ) {}
void ODM_SwAntDivChkPerPktRssi(
IN PDM_ODM_T pDM_Odm,
IN u1Byte StationID,
IN u8 StationID,
IN PODM_PHY_INFO_T pPhyInfo
) {}
void odm_SwAntDivChkAntSwitch(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Step
IN u8 Step
) {}
void ODM_SwAntDivResetBeforeLink( IN PDM_ODM_T pDM_Odm ){}
void ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm ){}
@ -3653,8 +3653,8 @@ odm_InitHybridAntDiv_88C_92D(
)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u1Byte bTxPathSel=0; //0:Path-A 1:Path-B
u1Byte i;
u8 bTxPathSel=0; //0:Path-A 1:Path-B
u8 i;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n"));
@ -3742,7 +3742,7 @@ odm_StaDefAntSel(
IN u32 OFDM_Ant2_Cnt,
IN u32 CCK_Ant1_Cnt,
IN u32 CCK_Ant2_Cnt,
OUT u1Byte *pDefAnt
OUT u8 *pDefAnt
)
{
@ -3783,7 +3783,7 @@ odm_StaDefAntSel(
#endif
//u32 antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
//(*pDefAnt)= (u1Byte) antsel;
//(*pDefAnt)= (u8) antsel;
@ -3799,7 +3799,7 @@ odm_StaDefAntSel(
void
odm_SetRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant,
IN u8 Ant,
IN BOOLEAN bDualPath
)
{
@ -3833,7 +3833,7 @@ odm_SetRxIdleAnt(
void
ODM_AntselStatistics_88C(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacId,
IN u8 MacId,
IN u32 PWDBAll,
IN BOOLEAN isCCKrate
)
@ -3878,7 +3878,7 @@ odm_HwAntDiv_92C_92D(
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u32 RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
u1Byte RxIdleAnt, i;
u8 RxIdleAnt, i;
BOOLEAN bRet=FALSE;
PSTA_INFO_T pEntry;
@ -4143,7 +4143,7 @@ u32
GetPSDData(
IN PDM_ODM_T pDM_Odm,
unsigned int point,
u1Byte initial_gain_psd)
u8 initial_gain_psd)
{
//unsigned int val, rfval;
//int psd_report;
@ -4169,8 +4169,8 @@ u32
ConvertTo_dB(
u32 Value)
{
u1Byte i;
u1Byte j;
u8 i;
u8 j;
u32 dB;
Value = Value & 0xFFFF;
@ -4268,7 +4268,7 @@ odm_PHY_ReloadAFERegisters(
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PDM_ODM_T pDM_Odm,
IN u1Byte mode
IN u8 mode
)
{
@ -4276,9 +4276,9 @@ ODM_SingleDualAntennaDetection(
//PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u32 CurrentChannel,RfLoopReg;
u1Byte n;
u8 n;
u32 Reg88c, Regc08, Reg874, Regc50;
u1Byte initial_gain = 0x5a;
u8 initial_gain = 0x5a;
u32 PSD_report_tmp;
u32 AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
BOOLEAN bResult = TRUE;

400
hal/odm.h
View file

@ -126,14 +126,14 @@
// We need to remove to other position???
//
typedef struct rtl8192cd_priv {
u1Byte temp;
u8 temp;
}rtl8192cd_priv, *prtl8192cd_priv;
typedef struct _Dynamic_Initial_Gain_Threshold_
{
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
u8 Dig_Enable_Flag;
u8 Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
@ -141,33 +141,33 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
u32 FALowThresh;
u32 FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
u1Byte CurMultiSTAConnectState;
u8 CurSTAConnectState;
u8 PreSTAConnectState;
u8 CurMultiSTAConnectState;
u1Byte PreIGValue;
u1Byte CurIGValue;
u1Byte BT30_CurIGI;
u1Byte BackupIGValue;
u8 PreIGValue;
u8 CurIGValue;
u8 BT30_CurIGI;
u8 BackupIGValue;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
u1Byte rx_gain_range_max;
u1Byte rx_gain_range_min;
u1Byte Rssi_val_min;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
u8 Rssi_val_min;
u1Byte PreCCK_CCAThres;
u1Byte CurCCK_CCAThres;
u1Byte PreCCKPDState;
u1Byte CurCCKPDState;
u8 PreCCK_CCAThres;
u8 CurCCK_CCAThres;
u8 PreCCKPDState;
u8 CurCCKPDState;
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u8 LargeFAHit;
u8 ForbiddenIGI;
u32 Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
u8 DIG_Dynamic_MIN_0;
u8 DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
@ -177,15 +177,15 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
typedef struct _Dynamic_Power_Saving_
{
u1Byte PreCCAState;
u1Byte CurCCAState;
u8 PreCCAState;
u8 CurCCAState;
u1Byte PreRFState;
u1Byte CurRFState;
u8 PreRFState;
u8 CurRFState;
int Rssi_val_min;
u1Byte initialize;
u8 initialize;
u32 Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
@ -208,25 +208,25 @@ typedef struct false_ALARM_STATISTICS{
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef struct _Dynamic_Primary_CCA{
u1Byte PriCCA_flag;
u1Byte intf_flag;
u1Byte intf_type;
u1Byte DupRTS_flag;
u1Byte Monitor_flag;
u8 PriCCA_flag;
u8 intf_flag;
u8 intf_type;
u8 DupRTS_flag;
u8 Monitor_flag;
}Pri_CCA_T, *pPri_CCA_T;
typedef struct _RX_High_Power_
{
u1Byte RXHP_flag;
u1Byte PSD_func_trigger;
u1Byte PSD_bitmap_RXHP[80];
u1Byte Pre_IGI;
u1Byte Cur_IGI;
u1Byte Pre_pw_th;
u1Byte Cur_pw_th;
u8 RXHP_flag;
u8 PSD_func_trigger;
u8 PSD_bitmap_RXHP[80];
u8 Pre_IGI;
u8 Cur_IGI;
u8 Pre_pw_th;
u8 Cur_pw_th;
BOOLEAN First_time_enter;
BOOLEAN RXHP_enable;
u1Byte TP_Mode;
u8 TP_Mode;
RT_TIMER PSDTimer;
}RXHP_T, *pRXHP_T;
@ -248,18 +248,18 @@ typedef struct _RX_High_Power_
typedef struct _SW_Antenna_Switch_
{
u1Byte try_flag;
u8 try_flag;
s4Byte PreRSSI;
u1Byte CurAntenna;
u1Byte PreAntenna;
u1Byte RSSI_Trying;
u1Byte TestMode;
u1Byte bTriggerAntennaSwitch;
u1Byte SelectAntennaMap;
u1Byte RSSI_target;
u8 CurAntenna;
u8 PreAntenna;
u8 RSSI_Trying;
u8 TestMode;
u8 bTriggerAntennaSwitch;
u8 SelectAntennaMap;
u8 RSSI_target;
// Before link Antenna Switch check
u1Byte SWAS_NoLink_State;
u8 SWAS_NoLink_State;
u32 SWAS_NoLink_BK_Reg860;
BOOLEAN ANTA_ON; //To indicate Ant A is or not
BOOLEAN ANTB_ON; //To indicate Ant B is on or not
@ -275,7 +275,7 @@ typedef struct _SW_Antenna_Switch_
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte TrafficLoad;
u8 TrafficLoad;
RT_TIMER SwAntennaSwitchTimer;
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
@ -285,10 +285,10 @@ typedef struct _SW_Antenna_Switch_
u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
u1Byte TxAnt[ASSOCIATE_ENTRY_NUM];
u1Byte TargetSTA;
u1Byte antsel;
u1Byte RxIdleAnt;
u8 TxAnt[ASSOCIATE_ENTRY_NUM];
u8 TargetSTA;
u8 antsel;
u8 RxIdleAnt;
#endif
}SWAT_T, *pSWAT_T;
@ -302,10 +302,10 @@ typedef struct _EDCA_TURBO_ {
typedef struct _ODM_RATE_ADAPTIVE
{
u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
u8 Type; // DM_Type_ByFW/DM_Type_ByDriver
u8 HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u8 LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u8 RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
u32 LastRATR; // RATR Register Content
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
@ -336,16 +336,16 @@ typedef struct _ODM_RATE_ADAPTIVE
typedef struct _ODM_Phy_Status_Info_
{
u1Byte RxPWDBAll;
u1Byte SignalQuality; // in 0-100 index.
u1Byte RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
u1Byte RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index
u8 RxPWDBAll;
u8 SignalQuality; // in 0-100 index.
u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index
s1Byte RxPower; // in dBm Translate from PWdB
s1Byte RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
u1Byte BTRxRSSIPercentage;
u1Byte SignalStrength; // in 0-100 index.
u1Byte RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
u1Byte RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
u8 BTRxRSSIPercentage;
u8 SignalStrength; // in 0-100 index.
u8 RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
u8 RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
@ -356,7 +356,7 @@ typedef struct _ODM_Phy_Dbg_Info_
u8Byte NumQryPhyStatus;
u8Byte NumQryPhyStatusCCK;
u8Byte NumQryPhyStatusOFDM;
u1Byte NumQryBeaconPkt;
u8 NumQryBeaconPkt;
//Others
s4Byte RxEVM[MAX_PATH_NUM_92CS];
@ -365,8 +365,8 @@ typedef struct _ODM_Phy_Dbg_Info_
typedef struct _ODM_Per_Pkt_Info_
{
u1Byte Rate;
u1Byte StationID;
u8 Rate;
u8 StationID;
BOOLEAN bPacketMatchBSSID;
BOOLEAN bPacketToSelf;
BOOLEAN bPacketBeacon;
@ -374,7 +374,7 @@ typedef struct _ODM_Per_Pkt_Info_
typedef struct _ODM_Mac_Status_Info_
{
u1Byte test;
u8 test;
}ODM_MAC_INFO;
@ -403,15 +403,15 @@ typedef enum tag_Dynamic_ODM_Support_Ability_Type
typedef struct _ODM_STA_INFO{
// Driver Write
BOOLEAN bUsed; // record the sta status link or not?
//u1Byte WirelessMode; //
u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E
//u8 WirelessMode; //
u8 IOTPeer; // Enum value. HT_IOT_PEER_E
// ODM Write
//1 PHY_STATUS_INFO
u1Byte RSSI_Path[4]; //
u1Byte RSSI_Ave;
u1Byte RXEVM[4];
u1Byte RXSNR[4];
u8 RSSI_Path[4]; //
u8 RSSI_Ave;
u8 RXEVM[4];
u8 RXSNR[4];
} ODM_STA_INFO_T, *PODM_STA_INFO_T;
//
@ -485,9 +485,9 @@ typedef enum _ODM_Common_Info_Definition
ODM_CMNINFO_RSSI_MIN,
ODM_CMNINFO_DBG_COMP, // u8Byte
ODM_CMNINFO_DBG_LEVEL, // u32
ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte
ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte
ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte
ODM_CMNINFO_RA_THRESHOLD_HIGH, // u8
ODM_CMNINFO_RA_THRESHOLD_LOW, // u8
ODM_CMNINFO_RF_ANTENNA_TYPE, // u8
ODM_CMNINFO_BT_DISABLED,
ODM_CMNINFO_BT_OPERATION,
ODM_CMNINFO_BT_DIG,
@ -757,37 +757,37 @@ typedef enum tag_CCA_Path
typedef struct _ODM_RA_Info_
{
u1Byte RateID;
u8 RateID;
u32 RateMask;
u32 RAUseRate;
u1Byte RateSGI;
u1Byte RssiStaRA;
u1Byte PreRssiStaRA;
u1Byte SGIEnable;
u1Byte DecisionRate;
u1Byte PreRate;
u1Byte HighestRate;
u1Byte LowestRate;
u8 RateSGI;
u8 RssiStaRA;
u8 PreRssiStaRA;
u8 SGIEnable;
u8 DecisionRate;
u8 PreRate;
u8 HighestRate;
u8 LowestRate;
u32 NscUp;
u32 NscDown;
u16 RTY[5];
u32 TOTAL;
u16 DROP;//Retry over or drop
u16 DROP1;//LifeTime over
u1Byte Active;
u8 Active;
u16 RptTime;
u1Byte RAWaitingCounter;
u1Byte RAPendingCounter;
u8 RAWaitingCounter;
u8 RAPendingCounter;
#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
u1Byte PTActive; // on or off
u1Byte PTTryState; // 0 trying state, 1 for decision state
u1Byte PTStage; // 0~6
u1Byte PTStopCount; //Stop PT counter
u1Byte PTPreRate; // if rate change do PT
u1Byte PTPreRssi; // if RSSI change 5% do PT
u1Byte PTModeSS; // decide whitch rate should do PT
u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
u1Byte PTSmoothFactor;
u8 PTActive; // on or off
u8 PTTryState; // 0 trying state, 1 for decision state
u8 PTStage; // 0~6
u8 PTStopCount; //Stop PT counter
u8 PTPreRate; // if rate change do PT
u8 PTPreRssi; // if RSSI change 5% do PT
u8 PTModeSS; // decide whitch rate should do PT
u8 RAstage; // StageRA, decide how many times RA will be done between PT
u8 PTSmoothFactor;
#endif
} ODM_RA_INFO_T,*PODM_RA_INFO_T;
@ -806,47 +806,47 @@ typedef struct ODM_RF_Calibration_Structure
s4Byte RegEB4;
s4Byte RegEBC;
//u1Byte bTXPowerTracking;
u1Byte TXPowercount;
//u8 bTXPowerTracking;
u8 TXPowercount;
BOOLEAN bTXPowerTrackingInit;
BOOLEAN bTXPowerTracking;
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u1Byte TM_Trigger;
u1Byte InternalPA5G[2]; //pathA / pathB
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
u8 InternalPA5G[2]; //pathA / pathB
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u1Byte ThermalValue;
u1Byte ThermalValue_LCK;
u1Byte ThermalValue_IQK;
u1Byte ThermalValue_DPK;
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
u1Byte ThermalValue_AVG_index;
u1Byte ThermalValue_RxGain;
u1Byte ThermalValue_Crystal;
u1Byte ThermalValue_DPKstore;
u1Byte ThermalValue_DPKtrack;
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u8 ThermalValue;
u8 ThermalValue_LCK;
u8 ThermalValue_IQK;
u8 ThermalValue_DPK;
u8 ThermalValue_AVG[AVG_THERMAL_NUM];
u8 ThermalValue_AVG_index;
u8 ThermalValue_RxGain;
u8 ThermalValue_Crystal;
u8 ThermalValue_DPKstore;
u8 ThermalValue_DPKtrack;
BOOLEAN TxPowerTrackingInProgress;
BOOLEAN bDPKenable;
BOOLEAN bReloadtxpowerindex;
u1Byte bRfPiEnable;
u8 bRfPiEnable;
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
u1Byte bCCKinCH14;
u1Byte CCK_index;
u1Byte OFDM_index[2];
u8 bCCKinCH14;
u8 CCK_index;
u8 OFDM_index[2];
BOOLEAN bDoneTxpower;
s1Byte PowerIndexOffset;
s1Byte DeltaPowerIndex;
s1Byte DeltaPowerIndexLast;
BOOLEAN bTxPowerChanged;
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
u8 ThermalValue_HP[HP_THERMAL_NUM];
u8 ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
u1Byte Delta_IQK;
u1Byte Delta_LCK;
u8 Delta_IQK;
u8 Delta_LCK;
//for IQK
u32 RegC04;
@ -868,11 +868,11 @@ typedef struct ODM_RF_Calibration_Structure
//for APK
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
//
// ODM Dynamic common info value definition
@ -880,23 +880,23 @@ typedef struct ODM_RF_Calibration_Structure
typedef struct _FAST_ANTENNA_TRAINNING_
{
u1Byte Bssid[6];
u1Byte antsel_rx_keep_0;
u1Byte antsel_rx_keep_1;
u1Byte antsel_rx_keep_2;
u8 Bssid[6];
u8 antsel_rx_keep_0;
u8 antsel_rx_keep_1;
u8 antsel_rx_keep_2;
u32 antSumRSSI[7];
u32 antRSSIcnt[7];
u32 antAveRSSI[7];
u1Byte FAT_State;
u8 FAT_State;
u32 TrainIdx;
u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte RxIdleAnt;
u8 RxIdleAnt;
BOOLEAN bBecomeLinked;
}FAT_T,*pFAT_T;
@ -950,15 +950,15 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
BOOLEAN bCckHighPower;
u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
u1Byte ControlChannel;
u8 RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
u8 ControlChannel;
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
//--------REMOVED COMMON INFO----------//
//u1Byte PseudoMacPhyMode;
//u8 PseudoMacPhyMode;
//BOOLEAN *BTCoexist;
//BOOLEAN PseudoBtCoexist;
//u1Byte OPMode;
//u8 OPMode;
//BOOLEAN bAPMode;
//BOOLEAN bClientMode;
//BOOLEAN bAdHocMode;
@ -973,34 +973,34 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//
//-----------HOOK BEFORE REG INIT-----------//
// ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
u1Byte SupportPlatform;
u8 SupportPlatform;
// ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
u32 SupportAbility;
// ODM PCIE/USB/SDIO/GSPI = 0/1/2/3
u1Byte SupportInterface;
u8 SupportInterface;
// ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
u32 SupportICType;
// Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
u1Byte CutVersion;
u8 CutVersion;
// Fab Version TSMC/UMC = 0/1
u1Byte FabVersion;
u8 FabVersion;
// RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...
u1Byte RFType;
u8 RFType;
// Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...
u1Byte BoardType;
u8 BoardType;
// with external LNA NO/Yes = 0/1
u1Byte ExtLNA;
u8 ExtLNA;
// with external PA NO/Yes = 0/1
u1Byte ExtPA;
u8 ExtPA;
// with external TRSW NO/Yes = 0/1
u1Byte ExtTRSW;
u1Byte PatchID; //Customer ID
u8 ExtTRSW;
u8 PatchID; //Customer ID
BOOLEAN bInHctTest;
BOOLEAN bWIFITest;
BOOLEAN bDualMacSmartConcurrent;
u32 BK_SupportAbility;
u1Byte AntDivType;
u8 AntDivType;
//-----------HOOK BEFORE REG INIT-----------//
//
@ -1008,28 +1008,28 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//
//--------- POINTER REFERENCE-----------//
u1Byte u1Byte_temp;
u8 u8_temp;
BOOLEAN BOOLEAN_temp;
struct adapter *_temp;
// MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2
u1Byte *pMacPhyMode;
u8 *pMacPhyMode;
//TX Unicast byte count
u8Byte *pNumTxBytesUnicast;
//RX Unicast byte count
u8Byte *pNumRxBytesUnicast;
// Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3
u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E
u8 *pWirelessMode; //ODM_WIRELESS_MODE_E
// Frequence band 2.4G/5G = 0/1
u1Byte *pBandType;
u8 *pBandType;
// Secondary channel offset don't_care/below/above = 0/1/2
u1Byte *pSecChOffset;
u8 *pSecChOffset;
// Security mode Open/WEP/AES/TKIP = 0/1/2/3
u1Byte *pSecurity;
u8 *pSecurity;
// BW info 20M/40M/80M = 0/1/2
u1Byte *pBandWidth;
u8 *pBandWidth;
// Central channel location Ch1/Ch2/....
u1Byte *pChannel; //central channel number
u8 *pChannel; //central channel number
// Common info for 92D DMSP
BOOLEAN *pbGetValueFromOtherMac;
@ -1039,9 +1039,9 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
BOOLEAN *pbScanInProcess;
BOOLEAN *pbPowerSaving;
// CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.
u1Byte *pOnePathCCA;
u8 *pOnePathCCA;
//pMgntInfo->AntennaTest
u1Byte *pAntennaTest;
u8 *pAntennaTest;
BOOLEAN *pbNet_closed;
//--------- POINTER REFERENCE-----------//
//
@ -1051,31 +1051,31 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
BOOLEAN bWIFI_Display;
BOOLEAN bLinked;
BOOLEAN bsta_state;
u1Byte RSSI_Min;
u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
u8 RSSI_Min;
u8 InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
BOOLEAN bIsMPChip;
BOOLEAN bOneEntryOnly;
// Common info for BTDM
BOOLEAN bBtDisabled; // BT is disabled
BOOLEAN bBtConnectProcess; // BT HS is under connection progress.
u1Byte btHsRssi; // BT HS mode wifi rssi value.
u8 btHsRssi; // BT HS mode wifi rssi value.
BOOLEAN bBtHsOperation; // BT HS mode is under progress
u1Byte btHsDigVal; // use BT rssi to decide the DIG value
u8 btHsDigVal; // use BT rssi to decide the DIG value
BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
BOOLEAN bBtLimitedDig; // BT is busy.
//------------CALL BY VALUE-------------//
u1Byte RSSI_A;
u1Byte RSSI_B;
u8 RSSI_A;
u8 RSSI_B;
u8Byte RSSI_TRSW;
u8Byte RSSI_TRSW_H;
u8Byte RSSI_TRSW_L;
u8Byte RSSI_TRSW_iso;
u1Byte RxRate;
u8 RxRate;
BOOLEAN StopDIG;
u1Byte TxRate;
u1Byte LinkedInterval;
u1Byte preChannel;
u8 TxRate;
u8 LinkedInterval;
u8 preChannel;
u32 TxagcOffsetValueA;
BOOLEAN IsTxagcOffsetPositiveA;
u32 TxagcOffsetValueB;
@ -1091,13 +1091,13 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
u32 IGI_Base;
u32 IGI_target;
BOOLEAN ForceEDCCA;
u1Byte AdapEn_RSSI;
u1Byte AntType;
u1Byte antdiv_rssi;
u1Byte antdiv_period;
u8 AdapEn_RSSI;
u8 AntType;
u8 antdiv_rssi;
u8 antdiv_period;
u32 Force_TH_H;
u32 Force_TH_L;
u1Byte IGI_LowerBound;
u8 IGI_LowerBound;
//2 Define STA info.
// _ODM_STA_INFO
@ -1158,12 +1158,12 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//PSD
BOOLEAN bUserAssignLevel;
RT_TIMER PSDTimer;
u1Byte RSSI_BT; //come from BT
u8 RSSI_BT; //come from BT
BOOLEAN bPSDinProcess;
BOOLEAN bDMInitialGainEnable;
//for rate adaptive, in fact, 88c/92c fw will handle this
u1Byte bUseRAMask;
u8 bUseRAMask;
ODM_RATE_ADAPTIVE RateAdaptive;
@ -1173,19 +1173,19 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//
// TX power tracking
//
u1Byte BbSwingIdxOfdm;
u1Byte BbSwingIdxOfdmCurrent;
u1Byte BbSwingIdxOfdmBase;
u8 BbSwingIdxOfdm;
u8 BbSwingIdxOfdmCurrent;
u8 BbSwingIdxOfdmBase;
BOOLEAN BbSwingFlagOfdm;
u1Byte BbSwingIdxCck;
u1Byte BbSwingIdxCckCurrent;
u1Byte BbSwingIdxCckBase;
u1Byte DefaultOfdmIndex;
u1Byte DefaultCckIndex;
u8 BbSwingIdxCck;
u8 BbSwingIdxCckCurrent;
u8 BbSwingIdxCckBase;
u8 DefaultOfdmIndex;
u8 DefaultCckIndex;
BOOLEAN BbSwingFlagCck;
u1Byte *mp_mode;
u8 *mp_mode;
//
// ODM system resource.
//
@ -1413,8 +1413,8 @@ typedef enum tag_SW_Antenna_Switch_Definition
#define CCK_TABLE_SIZE 33
extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
@ -1431,18 +1431,18 @@ extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
void ODM_Write_DIG(PDM_ODM_T pDM_Odm, u1Byte CurrentIGI);
void ODM_Write_CCK_CCA_Thres(PDM_ODM_T pDM_Odm, u1Byte CurCCK_CCAThres);
void ODM_Write_DIG(PDM_ODM_T pDM_Odm, u8 CurrentIGI);
void ODM_Write_CCK_CCA_Thres(PDM_ODM_T pDM_Odm, u8 CurCCK_CCAThres);
void
ODM_SetAntenna(
PDM_ODM_T pDM_Odm,
u1Byte Antenna);
u8 Antenna);
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving( PDM_ODM_T pDM_Odm,
u1Byte bForceInNormal );
u8 bForceInNormal );
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm);
@ -1458,13 +1458,13 @@ ODM_RAStateCheck(
PDM_ODM_T pDM_Odm,
s4Byte RSSI,
BOOLEAN bForceUpdate,
OUT pu1Byte pRATRState
OUT u8 * pRATRState
);
#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
void ODM_SwAntDivChkPerPktRssi(
PDM_ODM_T pDM_Odm,
u1Byte StationID,
u8 StationID,
PODM_PHY_INFO_T pPhyInfo
);
@ -1474,7 +1474,7 @@ u32
GetPSDData(
PDM_ODM_T pDM_Odm,
unsigned int point,
u1Byte initial_gain_psd);
u8 initial_gain_psd);
void
odm_DIGbyRSSI_LPS(
@ -1485,7 +1485,7 @@ u32 ODM_Get_Rate_Bitmap(
PDM_ODM_T pDM_Odm,
u32 macid,
u32 ra_mask,
u1Byte rssi_level);
u8 rssi_level);
void ODM_DMInit(PDM_ODM_T pDM_Odm);
@ -1546,7 +1546,7 @@ ODM_ResetIQKResult(
void
ODM_AntselStatistics_88C(
PDM_ODM_T pDM_Odm,
u1Byte MacId,
u8 MacId,
u32 PWDBAll,
BOOLEAN isCCKrate
);
@ -1559,7 +1559,7 @@ ODM_SingleDualAntennaDefaultSetting(
BOOLEAN
ODM_SingleDualAntennaDetection(
PDM_ODM_T pDM_Odm,
u1Byte mode
u8 mode
);

70
hal/odm_HWConfig.c
View file

@ -40,7 +40,7 @@
#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm))
#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm))
u1Byte
u8
odm_QueryRxPwrPercentage(
IN s1Byte AntPower
)
@ -203,19 +203,19 @@ odm_SignalScaleMapping(
}
//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
static u8 odm_SQ_process_patch_RT_CID_819x_Lenovo(
IN PDM_ODM_T pDM_Odm,
IN u1Byte isCCKrate,
IN u1Byte PWDB_ALL,
IN u1Byte path,
IN u1Byte RSSI
IN u8 isCCKrate,
IN u8 PWDB_ALL,
IN u8 path,
IN u8 RSSI
)
{
u1Byte SQ;
u8 SQ;
return SQ;
}
static u1Byte
static u8
odm_EVMdbToPercentage(
IN s1Byte Value
)
@ -250,19 +250,19 @@ void
odm_RxPhyStatus92CSeries_Parsing(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN u8 * pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u1Byte i, Max_spatial_stream;
u8 i, Max_spatial_stream;
s1Byte rx_pwr[4], rx_pwr_all=0;
u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT;
u1Byte RSSI, total_rssi=0;
u1Byte isCCKrate=0;
u1Byte rf_rx_num = 0;
u1Byte cck_highpwr = 0;
u1Byte LNA_idx, VGA_idx;
u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT;
u8 RSSI, total_rssi=0;
u8 isCCKrate=0;
u8 rf_rx_num = 0;
u8 cck_highpwr = 0;
u8 LNA_idx, VGA_idx;
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
@ -274,8 +274,8 @@ odm_RxPhyStatus92CSeries_Parsing(
if(isCCKrate)
{
u1Byte report;
u1Byte cck_agc_rpt;
u8 report;
u8 cck_agc_rpt;
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
//
@ -432,7 +432,7 @@ odm_RxPhyStatus92CSeries_Parsing(
//
if(pPktinfo->bPacketMatchBSSID)
{
u1Byte SQ,SQ_rpt;
u8 SQ,SQ_rpt;
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0);
@ -495,7 +495,7 @@ odm_RxPhyStatus92CSeries_Parsing(
RSSI -= 4;
}
pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI;
pPhyInfo->RxMIMOSignalStrength[i] =(u8) RSSI;
//Get Rx snr value in DB
pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2);
@ -550,9 +550,9 @@ odm_RxPhyStatus92CSeries_Parsing(
{
if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only
{
pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff);
pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
}
pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff);
pPhyInfo->RxMIMOSignalQuality[i] = (u8)(EVM & 0xff);
}
}
}
@ -562,13 +562,13 @@ odm_RxPhyStatus92CSeries_Parsing(
//It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().
if(isCCKrate)
{
pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL;
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL;
}
else
{
if (rf_rx_num != 0)
{
pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num));
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num));
}
}
@ -599,8 +599,8 @@ odm_Process_RSSIForDM(
{
s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave;
u1Byte isCCKrate=0;
u1Byte RSSI_max, RSSI_min, i;
u8 isCCKrate=0;
u8 RSSI_max, RSSI_min, i;
u32 OFDM_pkt=0;
u32 Weighting=0;
@ -633,7 +633,7 @@ odm_Process_RSSIForDM(
//-----------------Smart Antenna Debug Message------------------//
if(pDM_Odm->SupportICType == ODM_RTL8188E)
{
u1Byte antsel_tr_mux;
u8 antsel_tr_mux;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
@ -737,7 +737,7 @@ odm_Process_RSSIForDM(
else
{
RSSI_Ave = pPhyInfo->RxPWDBAll;
pDM_Odm->RSSI_A = (u1Byte) pPhyInfo->RxPWDBAll;
pDM_Odm->RSSI_A = (u8) pPhyInfo->RxPWDBAll;
pDM_Odm->RSSI_B = 0xFF;
//1 Process CCK RSSI
@ -773,7 +773,7 @@ odm_Process_RSSIForDM(
pEntry->rssi_stat.ValidBit++;
for(i=0; i<pEntry->rssi_stat.ValidBit; i++)
OFDM_pkt += (u1Byte)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
if(pEntry->rssi_stat.ValidBit == 64)
{
@ -808,7 +808,7 @@ void
ODM_PhyStatusQuery_92CSeries(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN u8 * pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -836,7 +836,7 @@ void
ODM_PhyStatusQuery_JaguarSeries(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN u8 * pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -848,7 +848,7 @@ void
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN u8 * pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -859,8 +859,8 @@ ODM_PhyStatusQuery(
void
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN u8 * pMacStatus,
IN u8 MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
@ -936,7 +936,7 @@ ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
)
{
u1Byte result = HAL_STATUS_SUCCESS;
u8 result = HAL_STATUS_SUCCESS;
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))

106
hal/odm_HWConfig.h
View file

@ -71,48 +71,48 @@
typedef struct _Phy_Rx_AGC_Info
{
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain:7,trsw:1;
u8 gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
u8 trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
u8 ch_corr[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;//ch_corr_msb;
u8 noise_power_db_msb;
u8 path_cfotail[2];
u8 pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
u8 path_rxsnr[2];
u8 noise_power_db_lsb;
u8 rsvd_2[3];
u8 stream_csi[2];
u8 stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
u8 rsvd_3;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
u8 antsel_rx_keep_2:1; //ex_intf_flg:1;
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 ant_sel_b:1;
u8 ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u8 ant_sel:1;
u8 ant_sel_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
@ -120,30 +120,30 @@ typedef struct _Phy_Status_Rpt_8192cd
typedef struct _Phy_Status_Rpt_8195
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
u8 ch_num[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_bb_pwr_ofdm_cfosho_b;
u8 cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u8 rsvd_1;
u8 path_cfotail[2];
u8 pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
u8 path_rxsnr[2];
u8 rsvd_2[2];
u8 stream_snr[2];
u8 stream_csi[2];
u8 rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
u8 rsvd_4;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
u8 antidx_anta:3;
u8 antidx_antb:3;
u8 rsvd_5:2;
#else // _BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
u8 rsvd_5:2;
u8 antidx_antb:3;
u8 antidx_anta:3;
#endif
} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
@ -157,15 +157,15 @@ void
ODM_PhyStatusQuery(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
pu1Byte pPhyStatus,
u8 * pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
);
void
ODM_MacStatusQuery(
PDM_ODM_T pDM_Odm,
pu1Byte pMacStatus,
u1Byte MacID,
u8 * pMacStatus,
u8 MacID,
BOOLEAN bPacketMatchBSSID,
BOOLEAN bPacketToSelf,
BOOLEAN bPacketBeacon

30
hal/odm_RTL8188E.c
View file

@ -33,7 +33,7 @@ ODM_DIG_LowerBound_88E(
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
}
//If only one Entry connected
@ -275,7 +275,7 @@ ODM_AntennaDiversityInit_88E(
void
ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u8 Ant)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u32 DefaultAnt, OptionalAnt;
@ -315,10 +315,10 @@ ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
void
odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u32 MacId)
odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u8 Ant, IN u32 MacId)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u1Byte TargetAnt;
u8 TargetAnt;
if(Ant == MAIN_ANT)
TargetAnt = MAIN_ANT_CG_TRX;
@ -338,8 +338,8 @@ odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u32 MacId)
void
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
IN u8 * pDesc,
IN u8 macId
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
@ -357,9 +357,9 @@ ODM_SetTxAntByTxInfo_88E(
void
ODM_AntselStatistics_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u8 antsel_tr_mux,
IN u32 MacId,
IN u1Byte RxPWDBAll
IN u8 RxPWDBAll
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
@ -403,7 +403,7 @@ odm_HWAntDiv(
{
u32 i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
u32 Main_RSSI, Aux_RSSI;
u1Byte RxIdleAnt=0, TargetAnt=7;
u8 RxIdleAnt=0, TargetAnt=7;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
BOOLEAN bMatchBSSID;
@ -552,8 +552,8 @@ ODM_AntennaDiversity_88E(
void
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
IN u8 * pDesc,
IN u8 macId
)
{
}
@ -597,15 +597,15 @@ odm_DynamicPrimaryCCA(
BOOLEAN Is40MHz;
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW
BOOLEAN bConnected = FALSE; // connected or not
static u1Byte Client_40MHz_pre = 0;
static u8 Client_40MHz_pre = 0;
static u8Byte lastTxOkCnt = 0;
static u8Byte lastRxOkCnt = 0;
static u32 Counter = 0;
static u1Byte Delay = 1;
static u8 Delay = 1;
u8Byte curTxOkCnt;
u8Byte curRxOkCnt;
u1Byte SecCHOffset;
u1Byte i;
u8 SecCHOffset;
u8 i;
return;
}

6
hal/odm_RTL8188E.h
View file

@ -34,11 +34,11 @@ void ODM_AntennaDiversityInit_88E(PDM_ODM_T pDM_Odm);
void ODM_AntennaDiversity_88E(PDM_ODM_T pDM_Odm);
void ODM_SetTxAntByTxInfo_88E(PDM_ODM_T pDM_Odm, pu1Byte pDesc, u1Byte macId);
void ODM_SetTxAntByTxInfo_88E(PDM_ODM_T pDM_Odm, u8 * pDesc, u8 macId);
void ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant);
void ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u8 Ant);
void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm, u1Byte antsel_tr_mux, u32 MacId, u1Byte RxPWDBAll);
void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll);
void odm_FastAntTraining(PDM_ODM_T pDM_Odm);

2
hal/odm_RegConfig8188E.c
View file

@ -101,7 +101,7 @@ void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u32 Addr,
IN u1Byte Data
IN u8 Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);

2
hal/odm_RegConfig8188E.h
View file

@ -47,7 +47,7 @@ void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u32 Addr,
IN u1Byte Data
IN u8 Data
);
void

2
hal/odm_debug.h
View file

@ -142,7 +142,7 @@
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
u8 * __ptr = (u8 *)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \

10
hal/odm_interface.c
View file

@ -27,7 +27,7 @@
// ODM IO Relative API.
//
u1Byte
u8
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u32 RegAddr
@ -62,7 +62,7 @@ void
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u32 RegAddr,
IN u1Byte Data
IN u8 Data
)
{
struct adapter * Adapter = pDM_Odm->Adapter;
@ -345,13 +345,13 @@ ODM_ReleaseTimer(
//
u32
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u8 * pH2CBuffer,
IN u32 H2CBufferLen,
IN u32 CmdNum,
IN u32 * pElementID,
IN u32 * pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
IN u8 ** pCmbBuffer,
IN u8 * CmdStartSeq
)
{
return TRUE;

10
hal/odm_interface.h
View file

@ -91,7 +91,7 @@ typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext);
//
u1Byte
u8
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u32 RegAddr
@ -113,7 +113,7 @@ void
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u32 RegAddr,
IN u1Byte Data
IN u8 Data
);
void
@ -309,13 +309,13 @@ ODM_ReleaseTimer(
//
u32
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u8 * pH2CBuffer,
IN u32 H2CBufferLen,
IN u32 CmdNum,
IN u32 * pElementID,
IN u32 * pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
IN u8 ** pCmbBuffer,
IN u8 * CmdStartSeq
);
#endif // __ODM_INTERFACE_H__

3
hal/odm_types.h
View file

@ -53,8 +53,7 @@ typedef enum _RT_SPINLOCK_TYPE{
#include <basic_types.h>
#define u1Byte u8
#define pu1Byte u8*
#define u8 u8
#define u8Byte u64
#define pu8Byte u64*

12
hal/rtl8188e_dm.c
View file

@ -257,18 +257,18 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp));
//================= only for 8192D =================
/*
//pHalData->CurrentBandType92D
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u8_temp));
//================= only for 8192D =================
// driver havn't those variable now
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u8_temp));
*/
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));

12
hal/rtl8188e_hal_init.c
View file

@ -271,7 +271,7 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
//
// 5. Calculate Efuse utilization.
//
efuse_usage = (u1Byte)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN_88E);
efuse_usage = (u8)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN_88E);
//Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized);
exit:
@ -1364,7 +1364,7 @@ Hal_EfuseReadEFuse88E(
//
// 5. Calculate Efuse utilization.
//
efuse_usage = (u1Byte)((eFuse_Addr*100)/EFUSE_REAL_CONTENT_LEN_88E);
efuse_usage = (u8)((eFuse_Addr*100)/EFUSE_REAL_CONTENT_LEN_88E);
rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
exit:
@ -1524,8 +1524,8 @@ rtl8188e_ReadEFuse(
void
Hal_EFUSEGetEfuseDefinition88E(
IN struct adapter *pAdapter,
IN u1Byte efuseType,
IN u1Byte type,
IN u8 efuseType,
IN u8 type,
OUT void * pOut
)
{
@ -1602,7 +1602,7 @@ Hal_EFUSEGetEfuseDefinition_Pseudo88E(
case TYPE_EFUSE_MAX_SECTION:
{
u8* pMax_section;
pMax_section = (pu1Byte)pOut;
pMax_section = (u8 *)pOut;
*pMax_section = EFUSE_MAX_SECTION_88E;
}
break;
@ -3547,7 +3547,7 @@ Hal_ReadThermalMeter_88E(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte tempval;
u8 tempval;
//
// ThermalMeter from EEPROM

16
hal/rtl8188e_phycfg.c
View file

@ -159,11 +159,11 @@ sic_Read4Byte(
//RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD));
#endif
rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));
//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));
//RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));
//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));
//RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u8)(offset&0xff)));
rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));
//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));
//RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8)));
//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));
//RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)));
rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ);
//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ);
//RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ));
@ -672,7 +672,7 @@ rtl8188e_PHY_SetRFReg(
{
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
//u1Byte RFWaitCounter = 0;
//u8 RFWaitCounter = 0;
u32 Original_Value, BitShift;
//_irqL irqL;
@ -1000,7 +1000,7 @@ phy_ConfigBBExternalPA(
* Read/Write
*
* Input: struct adapter * Adapter
* u1Byte ConfigType 0 => PHY_CONFIG
* u8 ConfigType 0 => PHY_CONFIG
* 1 =>AGC_TAB
*
* Output: NONE
@ -2166,7 +2166,7 @@ void phy_PowerIndexCheck88E(
* We must consider RF path later!!!!!!!
*
* Input: struct adapter * Adapter
* u1Byte channel
* u8 channel
*
* Output: NONE
*
@ -2341,7 +2341,7 @@ _PHY_SetBWMode92C(
regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
//regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);
//regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(u8 *)&regBwOpMode);
switch(pHalData->CurrentChannelBW)
{

6
hal/rtl8188e_rf6052.c
View file

@ -341,10 +341,10 @@ void getTxPowerWriteValByRegulatory88E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
u8 i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
s1Byte pwr_diff=0;
u32 writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory;
u8 Regulatory = pHalData->EEPROMRegulatory;
//
// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
@ -451,7 +451,7 @@ void getTxPowerWriteValByRegulatory88E(
for (i=0; i<4; i++)
{
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if(pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff;

4
hal/rtl8188e_xmit.c
View file

@ -130,11 +130,11 @@ struct EMInfo{
void
InsertEMContent_8188E(
struct EMInfo *pEMInfo,
IN pu1Byte VirtualAddress)
IN u8 * VirtualAddress)
{
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
u1Byte index=0;
u8 index=0;
u32 dwtmp=0;
#endif

2
hal/usb_halinit.c
View file

@ -2100,7 +2100,7 @@ Hal_EfuseParseMACAddr_8188EU(
if (AutoLoadFail)
{
// sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
// sMacAddr[5] = (u8)GetRandomNumber(1, 254);
for (i=0; i<6; i++)
pEEPROM->mac_addr[i] = sMacAddr[i];
}

4
include/basic_types.h
View file

@ -216,11 +216,11 @@
//pclint
#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
{ \
*((pu1Byte)(__pStart)) = \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
| \
((u1Byte)__Value) \
((u8)__Value) \
); \
}

4
include/rtl8188e_hal.h
View file

@ -234,8 +234,8 @@ typedef struct _TxPowerInfo
} TxPowerInfo, *PTxPowerInfo;
typedef struct _TxPowerInfo24G{
u1Byte IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
u1Byte IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1];
u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1];
//If only one tx, only BW20 and OFDM are used.
s1Byte CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s1Byte OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];

46
include/rtw_bt_mp.h
View file

@ -46,16 +46,16 @@ typedef enum _MP_BT_MODE{
// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER
typedef struct _BT_TXRX_PARAMETERS{
u1Byte txrxChannel;
u8 txrxChannel;
u32 txrxTxPktCnt;
u1Byte txrxTxPktInterval;
u1Byte txrxPayloadType;
u1Byte txrxPktType;
u8 txrxTxPktInterval;
u8 txrxPayloadType;
u8 txrxPktType;
u16 txrxPayloadLen;
u32 txrxPktHeader;
u1Byte txrxWhitenCoeff;
u1Byte txrxBdaddr[6];
u1Byte txrxTxGainIndex;
u8 txrxWhitenCoeff;
u8 txrxBdaddr[6];
u8 txrxTxGainIndex;
} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
// txrxPktType
@ -197,10 +197,10 @@ typedef enum _BT_REPORT_TYPE{
void
MPTBT_Test(
IN struct adapter *Adapter,
IN u1Byte opCode,
IN u1Byte byte1,
IN u1Byte byte2,
IN u1Byte byte3
IN u8 opCode,
IN u8 byte1,
IN u8 byte2,
IN u8 byte3
);
NDIS_STATUS
@ -215,8 +215,8 @@ MPTBT_SendOidBT(
void
MPTBT_FwC2hBtMpCtrl(
struct adapter *Adapter,
pu1Byte tmpBuf,
u1Byte length
u8 * tmpBuf,
u8 length
);
void MPh2c_timeout_handle(void *FunctionContext);
@ -244,21 +244,21 @@ typedef struct _BT_RSP_CMD{
typedef struct _BT_H2C{
u1Byte opCodeVer:4;
u1Byte reqNum:4;
u1Byte opCode;
u1Byte buf[100];
u8 opCodeVer:4;
u8 reqNum:4;
u8 opCode;
u8 buf[100];
}BT_H2C, *PBT_H2C;
typedef struct _BT_EXT_C2H{
u1Byte extendId;
u1Byte statusCode:4;
u1Byte retLen:4;
u1Byte opCodeVer:4;
u1Byte reqNum:4;
u1Byte buf[100];
u8 extendId;
u8 statusCode:4;
u8 retLen:4;
u8 opCodeVer:4;
u8 reqNum:4;
u8 buf[100];
}BT_EXT_C2H, *PBT_EXT_C2H;
typedef enum _BT_OPCODE_STATUS{

13
include/rtw_mp.h
View file

@ -159,12 +159,11 @@ struct mp_tx
#define MP_MAX_LINES 1000
#define MP_MAX_LINES_BYTES 256
#define u1Byte u8
#define u8 u8
#define s1Byte s8
#define u32 u32
#define s4Byte s32
#define u1Byte u8
#define pu1Byte u8*
#define u8 u8
#define u8Byte u64
#define pu8Byte u64*
@ -282,12 +281,12 @@ typedef struct _MPT_CONTEXT
u8 backup0x52_RF_A;
u8 backup0x52_RF_B;
u1Byte h2cReqNum;
u1Byte c2hBuf[20];
u8 h2cReqNum;
u8 c2hBuf[20];
u1Byte btInBuf[100];
u8 btInBuf[100];
ULONG mptOutLen;
u1Byte mptOutBuf[100];
u8 mptOutBuf[100];
}MPT_CONTEXT, *PMPT_CONTEXT;