skyfall/rtl8188eu
1
0
Fork 0
mirror of https://github.com/lwfinger/rtl8188eu.git synced 2025-05-06 21:43:06 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

rtl8188eu: More cleanups of code

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-05-25 15:45:50 -05:00
parent 3535ad59e3
commit d597e07a9e
62 changed files with 1765 additions and 1768 deletions
Download patch file Download diff file Expand all files Collapse all files

118
include/Hal8188EPhyCfg.h
View file

@ -214,128 +214,128 @@ typedef struct _R_ANTENNA_SELECT_CCK{
//
// BB and RF register read/write
//
u32 rtl8188e_PHY_QueryBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8188e_PHY_QueryRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8188e_PHY_QueryBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask );
void rtl8188e_PHY_SetBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8188e_PHY_QueryRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask );
void rtl8188e_PHY_SetRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(IN PADAPTER Adapter );
int PHY_BBConfig8188E(IN PADAPTER Adapter );
int PHY_RFConfig8188E(IN PADAPTER Adapter );
int PHY_MACConfig8188E( PADAPTER Adapter );
int PHY_BBConfig8188E( PADAPTER Adapter );
int PHY_RFConfig8188E( PADAPTER Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
void rtl8192c_PHY_GetHWRegOriginalValue( PADAPTER Adapter );
//
// RF Power setting
//
//extern bool PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//extern bool PHY_SetRFPowerState( PADAPTER Adapter,
// RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8188E( IN PADAPTER Adapter,
void PHY_GetTxPowerLevel8188E( PADAPTER Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8188E( IN PADAPTER Adapter,
IN u8 channel );
bool PHY_UpdateTxPowerDbm8188E( IN PADAPTER Adapter,
IN int powerInDbm );
void PHY_SetTxPowerLevel8188E( PADAPTER Adapter,
u8 channel );
bool PHY_UpdateTxPowerDbm8188E( PADAPTER Adapter,
int powerInDbm );
//
void
PHY_ScanOperationBackup8188E(IN PADAPTER Adapter,
IN u8 Operation );
PHY_ScanOperationBackup8188E( PADAPTER Adapter,
u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8188E( IN PADAPTER pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//extern void PHY_SetBWModeCallback8192C( PRT_TIMER pTimer );
void PHY_SetBWMode8188E( PADAPTER pAdapter,
HT_CHANNEL_WIDTH ChnlWidth,
unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern bool HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//extern bool HalSetIO8192C( PADAPTER Adapter,
// IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
extern void FillA2Entry8192C( PADAPTER Adapter,
u8 index,
u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8188E( IN PADAPTER pAdapter,
IN u8 channel );
//extern void PHY_SwChnlCallback8192C( PRT_TIMER pTimer );
void PHY_SwChnl8188E( PADAPTER pAdapter,
u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
IN u8 channel );
void PHY_SwChnlPhy8192C( PADAPTER pAdapter,
u8 channel );
void ChkFwCmdIoDone( IN PADAPTER Adapter);
void ChkFwCmdIoDone( PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN bool bEnableMonitorMode );
void PHY_SetMonitorMode8192C( PADAPTER pAdapter,
bool bEnableMonitorMode );
bool PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
IN u32 eRFPath );
bool PHY_CheckIsLegalRfPath8192C( PADAPTER pAdapter,
u32 eRFPath );
void PHY_SetRFPathSwitch_8188E(IN PADAPTER pAdapter, IN bool bMain);
void PHY_SetRFPathSwitch_8188E( PADAPTER pAdapter, bool bMain);
extern void
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
PADAPTER Adapter
);
extern void
PHY_EnableHostClkReq(
IN PADAPTER Adapter
PADAPTER Adapter
);
bool
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
PADAPTER Adapter,
u8 DefaultAnt
);
#ifdef CONFIG_PHY_SETTING_WITH_ODM
void
storePwrIndexDiffRateOffset(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
#endif //CONFIG_PHY_SETTING_WITH_ODM
/*--------------------------Exported Function prototype---------------------*/

38
include/Hal8188ERateAdaptive.h
View file

@ -42,7 +42,7 @@ Major Change History:
void
ODM_RASupport_Init(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
int
@ -52,26 +52,26 @@ ODM_RAInfo_Init_all(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
PDM_ODM_T pDM_Odm,
u1Byte MacID
);
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
PDM_ODM_T pDM_Odm,
u1Byte MacID
);
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
PDM_ODM_T pDM_Odm,
u1Byte MacID
);
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
PDM_ODM_T pDM_Odm,
u1Byte MacID
);
void
ODM_RA_UpdateRateInfo_8188E(
@ -84,24 +84,24 @@ ODM_RA_UpdateRateInfo_8188E(
void
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
PDM_ODM_T pDM_Odm,
u1Byte MacID,
u1Byte Rssi
);
void
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u2Byte TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
PDM_ODM_T pDM_Odm,
pu1Byte TxRPT_Buf,
u2Byte TxRPT_Len,
u4Byte MacIDValidEntry0,
u4Byte MacIDValidEntry1
);
void
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
PDM_ODM_T pDM_Odm,
u2Byte minRptTime
);
#endif

126
include/Hal8192CPhyCfg.h
View file

@ -250,133 +250,133 @@ typedef struct _R_ANTENNA_SELECT_CCK{
//
// BB and RF register read/write
//
u32 rtl8192c_PHY_QueryBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8192c_PHY_SetBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8192c_PHY_QueryRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8192c_PHY_SetRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8192c_PHY_QueryBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask );
void rtl8192c_PHY_SetBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8192c_PHY_QueryRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask );
void rtl8192c_PHY_SetRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8192C( IN PADAPTER Adapter );
int PHY_BBConfig8192C( IN PADAPTER Adapter );
int PHY_RFConfig8192C( IN PADAPTER Adapter );
int PHY_MACConfig8192C( PADAPTER Adapter );
int PHY_BBConfig8192C( PADAPTER Adapter );
int PHY_RFConfig8192C( PADAPTER Adapter );
/* RF config */
int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithParaFile( PADAPTER Adapter,
u8* pFileName,
RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath);
/* BB/RF readback check for making sure init OK */
int rtl8192c_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
IN HW90_BLOCK_E CheckBlock,
IN RF_RADIO_PATH_E eRFPath );
int rtl8192c_PHY_CheckBBAndRFOK( PADAPTER Adapter,
HW90_BLOCK_E CheckBlock,
RF_RADIO_PATH_E eRFPath );
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
void rtl8192c_PHY_GetHWRegOriginalValue( PADAPTER Adapter );
//
// RF Power setting
//
//extern bool PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//extern bool PHY_SetRFPowerState( PADAPTER Adapter,
// RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter,
void PHY_GetTxPowerLevel8192C( PADAPTER Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter,
IN u8 channel );
bool PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter,
IN int powerInDbm );
void PHY_SetTxPowerLevel8192C( PADAPTER Adapter,
u8 channel );
bool PHY_UpdateTxPowerDbm8192C( PADAPTER Adapter,
int powerInDbm );
//
void
PHY_ScanOperationBackup8192C(IN PADAPTER Adapter,
IN u8 Operation );
PHY_ScanOperationBackup8192C( PADAPTER Adapter,
u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8192C( IN PADAPTER pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//extern void PHY_SetBWModeCallback8192C( PRT_TIMER pTimer );
void PHY_SetBWMode8192C( PADAPTER pAdapter,
HT_CHANNEL_WIDTH ChnlWidth,
unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern bool HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//extern bool HalSetIO8192C( PADAPTER Adapter,
// IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
extern void FillA2Entry8192C( PADAPTER Adapter,
u8 index,
u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8192C( IN PADAPTER pAdapter,
IN u8 channel );
//extern void PHY_SwChnlCallback8192C( PRT_TIMER pTimer );
void PHY_SwChnl8192C( PADAPTER pAdapter,
u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
IN u8 channel );
void PHY_SwChnlPhy8192C( PADAPTER pAdapter,
u8 channel );
void ChkFwCmdIoDone( IN PADAPTER Adapter);
void ChkFwCmdIoDone( PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN bool bEnableMonitorMode );
void PHY_SetMonitorMode8192C( PADAPTER pAdapter,
bool bEnableMonitorMode );
bool PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
IN u32 eRFPath );
bool PHY_CheckIsLegalRfPath8192C( PADAPTER pAdapter,
u32 eRFPath );
void rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN bool bMain);
void rtl8192c_PHY_SetRFPathSwitch( PADAPTER pAdapter, bool bMain);
//
// Modify the value of the hw register when beacon interval be changed.
//
void
rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
rtl8192c_PHY_SetBeaconHwReg( PADAPTER Adapter,
u16 BeaconInterval );
extern void
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
PADAPTER Adapter
);
extern void
PHY_EnableHostClkReq(
IN PADAPTER Adapter
PADAPTER Adapter
);
bool
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
PADAPTER Adapter,
u8 DefaultAnt
);
#ifdef RTL8192C_RECONFIG_TO_1T1R

144
include/Hal8192DPhyCfg.h
View file

@ -299,136 +299,136 @@ typedef struct _R_ANTENNA_SELECT_CCK{
//
// BB and RF register read/write
//
void rtl8192d_PHY_SetBBReg1Byte( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8192d_PHY_QueryBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8192d_PHY_SetBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8192d_PHY_QueryRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8192d_PHY_SetRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
void rtl8192d_PHY_SetBBReg1Byte( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8192d_PHY_QueryBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask );
void rtl8192d_PHY_SetBBReg( PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data );
u32 rtl8192d_PHY_QueryRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask );
void rtl8192d_PHY_SetRFReg( PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
extern int PHY_MACConfig8192D( IN PADAPTER Adapter );
extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
extern int PHY_MACConfig8192D( PADAPTER Adapter );
extern int PHY_BBConfig8192D( PADAPTER Adapter );
extern int PHY_RFConfig8192D( PADAPTER Adapter );
/* RF config */
int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_CONTENT Content,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithParaFile( PADAPTER Adapter,
u8* pFileName,
RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
RF_CONTENT Content,
RF_RADIO_PATH_E eRFPath);
/* BB/RF readback check for making sure init OK */
int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
IN HW90_BLOCK_E CheckBlock,
IN RF_RADIO_PATH_E eRFPath );
int rtl8192d_PHY_CheckBBAndRFOK( PADAPTER Adapter,
HW90_BLOCK_E CheckBlock,
RF_RADIO_PATH_E eRFPath );
/* Read initi reg value for tx power setting. */
void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
void rtl8192d_PHY_GetHWRegOriginalValue( PADAPTER Adapter );
//
// RF Power setting
//
//extern bool PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//extern bool PHY_SetRFPowerState( PADAPTER Adapter,
// RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
void PHY_GetTxPowerLevel8192D( PADAPTER Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
IN u8 channel );
bool PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
IN int powerInDbm );
void PHY_SetTxPowerLevel8192D( PADAPTER Adapter,
u8 channel );
bool PHY_UpdateTxPowerDbm8192D( PADAPTER Adapter,
int powerInDbm );
//
void
PHY_ScanOperationBackup8192D(IN PADAPTER Adapter,
IN u8 Operation );
PHY_ScanOperationBackup8192D( PADAPTER Adapter,
u8 Operation );
//
// Switch bandwidth for 8192S
//
//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8192D( IN PADAPTER pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//void PHY_SetBWModeCallback8192C( PRT_TIMER pTimer );
void PHY_SetBWMode8192D( PADAPTER pAdapter,
HT_CHANNEL_WIDTH ChnlWidth,
unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern bool HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//extern bool HalSetIO8192C( PADAPTER Adapter,
// IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
extern void FillA2Entry8192C( PADAPTER Adapter,
u8 index,
u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8192D( IN PADAPTER pAdapter,
IN u8 channel );
//extern void PHY_SwChnlCallback8192C( PRT_TIMER pTimer );
void PHY_SwChnl8192D( PADAPTER pAdapter,
u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192D( IN PADAPTER pAdapter,
IN u8 channel );
void PHY_SwChnlPhy8192D( PADAPTER pAdapter,
u8 channel );
extern void ChkFwCmdIoDone( IN PADAPTER Adapter);
extern void ChkFwCmdIoDone( PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter,
IN bool bEnableMonitorMode );
void PHY_SetMonitorMode8192D( PADAPTER pAdapter,
bool bEnableMonitorMode );
bool PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter,
IN u32 eRFPath );
bool PHY_CheckIsLegalRfPath8192D( PADAPTER pAdapter,
u32 eRFPath );
//
// Modify the value of the hw register when beacon interval be changed.
//
void
rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
rtl8192d_PHY_SetBeaconHwReg( PADAPTER Adapter,
u16 BeaconInterval );
extern void
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
PADAPTER Adapter
);
extern void
PHY_EnableHostClkReq(
IN PADAPTER Adapter
PADAPTER Adapter
);
bool
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
PADAPTER Adapter,
u8 DefaultAnt
);
void
@ -456,21 +456,21 @@ void PHY_ConfigMacCoexist_RFPage92D(
void
rtl8192d_PHY_InitRxSetting(
IN PADAPTER Adapter
PADAPTER Adapter
);
void
rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN bool bMain);
rtl8192d_PHY_SetRFPathSwitch( PADAPTER pAdapter, bool bMain);
void
HalChangeCCKStatus8192D(
IN PADAPTER Adapter,
IN bool bCCKDisable
PADAPTER Adapter,
bool bCCKDisable
);
void
PHY_InitPABias92D(IN PADAPTER Adapter);
PHY_InitPABias92D( PADAPTER Adapter);
/*--------------------------Exported Function prototype---------------------*/

4
include/Hal8723APhyCfg.h
View file

@ -22,8 +22,8 @@
#include <Hal8192CPhyCfg.h>
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A( IN PADAPTER Adapter );
int PHY_RFConfig8723A( IN PADAPTER Adapter );
int PHY_BBConfig8723A( PADAPTER Adapter );
int PHY_RFConfig8723A( PADAPTER Adapter );
s32 PHY_MACConfig8723A(PADAPTER padapter);
#endif

14
include/HalPhyRf.h
View file

@ -29,28 +29,28 @@
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN bool bEnableMonitorMode );
void PHY_SetMonitorMode8192C( PADAPTER pAdapter,
bool bEnableMonitorMode );
//
// IQ calibrate
//
void
PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
IN bool bReCovery);
PHY_IQCalibrate_8192C( PADAPTER pAdapter,
bool bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
PHY_LCCalibrate_8192C( PADAPTER pAdapter);
//
// AP calibrate
//
void
PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
IN s1Byte delta);
PHY_APCalibrate_8192C( PADAPTER pAdapter,
s1Byte delta);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59

34
include/HalPhyRf_8188e.h
View file

@ -55,7 +55,7 @@ PHY_IQCalibrate_8188E(
#else
IN PADAPTER Adapter,
#endif
IN bool bReCovery);
bool bReCovery);
//
@ -66,7 +66,7 @@ PHY_LCCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
PADAPTER pAdapter
#endif
);
@ -78,11 +78,11 @@ PHY_APCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
PADAPTER pAdapter,
#endif
IN s1Byte delta);
s1Byte delta);
void
PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter);
PHY_DigitalPredistortion_8188E( PADAPTER pAdapter);
void
@ -90,11 +90,11 @@ _PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
pu4Byte ADDAReg,
pu4Byte ADDABackup,
u4Byte RegisterNum
);
void
@ -102,11 +102,11 @@ _PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN bool isPathAOn,
IN bool is2T
pu4Byte ADDAReg,
bool isPathAOn,
bool is2T
);
void
@ -114,10 +114,10 @@ _PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
pu4Byte MACReg,
pu4Byte MACBackup
);
@ -126,7 +126,7 @@ _PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
PADAPTER pAdapter
#endif
);

20
include/hal_com.h
View file

@ -140,9 +140,9 @@
#define DESC_RATEMCS15_SG 0x1c
#define DESC_RATEMCS32 0x20
#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU)
#define REG_NOA_DESC_SEL 0x05CF
#define REG_NOA_DESC_DURATION 0x05E0
#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU)
#define REG_NOA_DESC_SEL 0x05CF
#define REG_NOA_DESC_DURATION 0x05E0
#define REG_NOA_DESC_INTERVAL 0x05E4
#define REG_NOA_DESC_START 0x05E8
#define REG_NOA_DESC_COUNT 0x05EC
@ -153,11 +153,11 @@ void dump_chip_info(HAL_VERSION ChipVersion);
u8 //return the final channel plan decision
hal_com_get_channel_plan(
IN PADAPTER padapter,
IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
IN u8 sw_channel_plan, //channel plan from SW (registry/module param)
IN u8 def_channel_plan, //channel plan used when the former two is invalid
IN bool AutoLoadFail
PADAPTER padapter,
u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
u8 sw_channel_plan, //channel plan from SW (registry/module param)
u8 def_channel_plan, //channel plan used when the former two is invalid
bool AutoLoadFail
);
u8 MRateToHwRate(u8 rate);
@ -169,8 +169,8 @@ void HalSetBrateCfg(
bool
Hal_MappingOutPipe(
IN PADAPTER pAdapter,
IN u8 NumOutPipe
PADAPTER pAdapter,
u8 NumOutPipe
);
void hal_init_macaddr(_adapter *adapter);

2
include/mp_custom_oid.h
View file

@ -206,7 +206,7 @@
#define OID_CE_USB_READ_REGISTRY 0xFF0111C2
#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3
#define OID_RT_PRO_SET_INITIAL_GA 0xFF0111C3
#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4
#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5
#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6

152
include/odm.h
View file

@ -75,7 +75,7 @@
#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD
#define MODE_40M 0 //0:20M, 1:40M
#define PSD_TH2 3
#define PSD_CHMIN 20 // Minimum channel number for BT AFH
#define PSD_CHM 20 // Minimum channel number for BT AFH
#define SIR_STEP_SIZE 3
#define Smooth_Size_1 5
#define Smooth_TH_1 3
@ -627,7 +627,7 @@ typedef enum _ODM_Support_Ability_Definition
ODM_BB_CCK_PD = BIT5,
ODM_BB_ANT_DIV = BIT6,
ODM_BB_PWR_SAVE = BIT7,
ODM_BB_PWR_TRAIN = BIT8,
ODM_BB_PWR_TRA = BIT8,
ODM_BB_RATE_ADAPTIVE = BIT9,
ODM_BB_PATH_DIV = BIT10,
ODM_BB_PSD = BIT11,
@ -1556,34 +1556,34 @@ extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
void ODM_Write_DIG(IN PDM_ODM_T pDM_Odm, IN u1Byte CurrentIGI);
void ODM_Write_CCK_CCA_Thres(IN PDM_ODM_T pDM_Odm, IN u1Byte CurCCK_CCAThres);
void ODM_Write_DIG( PDM_ODM_T pDM_Odm, u1Byte CurrentIGI);
void ODM_Write_CCK_CCA_Thres( PDM_ODM_T pDM_Odm, u1Byte CurCCK_CCAThres);
void
ODM_SetAntenna(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Antenna);
PDM_ODM_T pDM_Odm,
u1Byte Antenna);
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving( IN PDM_ODM_T pDM_Odm,
IN u1Byte bForceInNormal );
void ODM_RF_Saving( PDM_ODM_T pDM_Odm,
u1Byte bForceInNormal );
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
void ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm);
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm);
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
void
ODM_TXPowerTrackingCheck(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
bool
ODM_RAStateCheck(
IN PDM_ODM_T pDM_Odm,
IN s4Byte RSSI,
IN bool bForceUpdate,
OUT pu1Byte pRATRState
PDM_ODM_T pDM_Odm,
s4Byte RSSI,
bool bForceUpdate,
pu1Byte pRATRState
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_AP|ODM_ADSL))
@ -1591,27 +1591,27 @@ ODM_RAStateCheck(
// function prototype
//============================================================
//#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,
// IN INT32 DM_Type,
// IN INT32 DM_Value);
//void ODM_ChangeDynamicInitGainThresh( PADAPTER pAdapter,
// INT32 DM_Type,
// INT32 DM_Value);
void
ODM_ChangeDynamicInitGainThresh(
IN PDM_ODM_T pDM_Odm,
IN u4Byte DM_Type,
IN u4Byte DM_Value
PDM_ODM_T pDM_Odm,
u4Byte DM_Type,
u4Byte DM_Value
);
bool
ODM_CheckPowerStatus(
IN PADAPTER Adapter
PADAPTER Adapter
);
#if (DM_ODM_SUPPORT_TYPE != ODM_ADSL)
void
ODM_RateAdaptiveStateApInit(
IN PADAPTER Adapter ,
IN PRT_WLAN_STA pEntry
PADAPTER Adapter ,
PRT_WLAN_STA pEntry
);
#endif
#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
@ -1621,15 +1621,15 @@ ODM_RateAdaptiveStateApInit(
#ifdef WIFI_WMM
void
ODM_IotEdcaSwitch(
IN PDM_ODM_T pDM_Odm,
IN unsigned char enable
PDM_ODM_T pDM_Odm,
unsigned char enable
);
#endif
bool
ODM_ChooseIotMainSTA(
IN PDM_ODM_T pDM_Odm,
IN PSTA_INFO_T pstat
PDM_ODM_T pDM_Odm,
PSTA_INFO_T pstat
);
#endif
@ -1637,20 +1637,20 @@ ODM_ChooseIotMainSTA(
#ifdef HW_ANT_SWITCH
u1Byte
ODM_Diversity_AntennaSelect(
IN PDM_ODM_T pDM_Odm,
IN u1Byte *data
PDM_ODM_T pDM_Odm,
u1Byte *data
);
#endif
#endif
#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink
void ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm);
void ODM_SwAntDivResetBeforeLink( PDM_ODM_T pDM_Odm);
//#define SwAntDivCheckBeforeLink8192C ODM_SwAntDivCheckBeforeLink8192C
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink8192C
bool
ODM_SwAntDivCheckBeforeLink8192C(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
@ -1679,14 +1679,14 @@ GetPSDData(
void
odm_DIGbyRSSI_LPS(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
u4Byte ODM_Get_Rate_Bitmap(
IN PDM_ODM_T pDM_Odm,
IN u4Byte macid,
IN u4Byte ra_mask,
IN u1Byte rssi_level);
PDM_ODM_T pDM_Odm,
u4Byte macid,
u4Byte ra_mask,
u1Byte rssi_level);
#endif
@ -1702,62 +1702,62 @@ odm_PSDMonitorWorkItemCallback(
void
PatchDCTone(
IN PDM_ODM_T pDM_Odm,
PDM_ODM_T pDM_Odm,
pu4Byte PSD_report,
u1Byte initial_gain_psd
);
void
ODM_PSDMonitor(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
void odm_PSD_Monitor(PDM_ODM_T pDM_Odm);
void odm_PSDMonitorInit(PDM_ODM_T pDM_Odm);
void
ODM_PSDDbgControl(
IN PADAPTER Adapter,
IN u4Byte mode,
IN u4Byte btRssi
PADAPTER Adapter,
u4Byte mode,
u4Byte btRssi
);
#endif // DM_ODM_SUPPORT_TYPE
void ODM_DMInit( IN PDM_ODM_T pDM_Odm);
void ODM_DMInit( PDM_ODM_T pDM_Odm);
void
ODM_DMWatchdog(
IN PDM_ODM_T pDM_Odm // For common use in the future
PDM_ODM_T pDM_Odm // For common use in the future
);
void
ODM_CmnInfoInit(
IN PDM_ODM_T pDM_Odm,
IN ODM_CMNINFO_E CmnInfo,
IN u4Byte Value
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
u4Byte Value
);
void
ODM_CmnInfoHook(
IN PDM_ODM_T pDM_Odm,
IN ODM_CMNINFO_E CmnInfo,
IN void * pValue
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
void * pValue
);
void
ODM_CmnInfoPtrArrayHook(
IN PDM_ODM_T pDM_Odm,
IN ODM_CMNINFO_E CmnInfo,
IN u2Byte Index,
IN void * pValue
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
u2Byte Index,
void * pValue
);
void
ODM_CmnInfoUpdate(
IN PDM_ODM_T pDM_Odm,
IN u4Byte CmnInfo,
IN u8Byte Value
PDM_ODM_T pDM_Odm,
u4Byte CmnInfo,
u8Byte Value
);
void
@ -1787,7 +1787,7 @@ void ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm );
void odm_PathDivChkAntSwitch(PDM_ODM_T pDM_Odm);
void ODM_PathDivRestAfterLink(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
@ -1806,7 +1806,7 @@ void ODM_PathDivRestAfterLink(
//void odm_PathDivChkAntSwitch(PADAPTER Adapter,u1Byte Step);
void ODM_PathDivRestAfterLink(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
@ -1838,14 +1838,14 @@ PlatformDivision64(
#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
bool
ODM_PathDiversityBeforeLink92C(
//IN PADAPTER Adapter
IN PDM_ODM_T pDM_Odm
// PADAPTER Adapter
PDM_ODM_T pDM_Odm
);
#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter,
// IN INT32 DM_Type,
// IN INT32 DM_Value);
//void ODM_ChangeDynamicInitGainThresh( PADAPTER pAdapter,
// INT32 DM_Type,
// INT32 DM_Value);
//
@ -1873,9 +1873,9 @@ typedef enum tag_DIG_Connect_Definition
void
ODM_FillTXPathInTXDESC(
IN PADAPTER Adapter,
IN PRT_TCB pTcb,
IN pu1Byte pDesc
PADAPTER Adapter,
PRT_TCB pTcb,
pu1Byte pDesc
);
@ -1902,30 +1902,30 @@ ODM_FillTXPathInTXDESC(
void
ODM_SetTxAntByTxInfo_88C_92D(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
PDM_ODM_T pDM_Odm,
pu1Byte pDesc,
u1Byte macId
);
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
void
ODM_AntselStatistics_88C(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacId,
IN u4Byte PWDBAll,
IN bool isCCKrate
PDM_ODM_T pDM_Odm,
u1Byte MacId,
u4Byte PWDBAll,
bool isCCKrate
);
#if ( DM_ODM_SUPPORT_TYPE & (ODM_MP |ODM_CE))
void
ODM_SingleDualAntennaDefaultSetting(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
bool
ODM_SingleDualAntennaDetection(
IN PDM_ODM_T pDM_Odm,
IN u1Byte mode
PDM_ODM_T pDM_Odm,
u1Byte mode
);
#endif // #if ((DM_ODM_SUPPORT_TYPE==ODM_MP)||(DM_ODM_SUPPORT_TYPE==ODM_CE))

34
include/odm_HWConfig.h
View file

@ -150,43 +150,43 @@ typedef struct _Phy_Status_Rpt_8195
void
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
void
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
pu1Byte pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
);
void
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN bool bPacketMatchBSSID,
IN bool bPacketToSelf,
IN bool bPacketBeacon
PDM_ODM_T pDM_Odm,
pu1Byte pMacStatus,
u1Byte MacID,
bool bPacketMatchBSSID,
bool bPacketToSelf,
bool bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP))
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E Content,
ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
PDM_ODM_T pDM_Odm,
ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#endif

36
include/odm_RTL8188E.h
View file

@ -29,37 +29,37 @@
void
ODM_DIG_LowerBound_88E(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
void
odm_FastAntTrainingInit(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#endif
void
ODM_AntennaDiversityInit_88E(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
void
ODM_AntennaDiversity_88E
(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
void
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
PDM_ODM_T pDM_Odm,
pu1Byte pDesc,
u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
void
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#endif
@ -71,38 +71,38 @@ ODM_UpdateRxIdleAnt_88E(
void
ODM_AntselStatistics_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u1Byte RxPWDBAll
PDM_ODM_T pDM_Odm,
u1Byte antsel_tr_mux,
u4Byte MacId,
u1Byte RxPWDBAll
);
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
void
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
void
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
void
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
PDM_ODM_T pDM_Odm
);
#endif
void
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm);
PDM_ODM_T pDM_Odm);
bool
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm);
PDM_ODM_T pDM_Odm);
void
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm);
PDM_ODM_T pDM_Odm);
#endif

50
include/odm_RegConfig8188E.h
View file

@ -24,56 +24,56 @@
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
u4Byte RegAddr
);
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Data
);
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Data
);
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u1Byte Data
);
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
);
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
);
#endif
#endif // end of SUPPORT

2
include/odm_debug.h
View file

@ -78,7 +78,7 @@
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_PWR_TRA BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11

172
include/odm_interface.h
View file

@ -99,88 +99,88 @@ typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext);
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
);
void
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u1Byte Data
);
void
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u2Byte Data
);
void
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte Data
);
void
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask
);
void
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask
);
void
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
u4Byte RegAddr,
u4Byte BitMask
);
@ -189,22 +189,22 @@ ODM_GetRFReg(
//
void
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT void * *pPtr,
IN u4Byte length
PDM_ODM_T pDM_Odm,
void * *pPtr,
u4Byte length
);
void
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT void * pPtr,
IN u4Byte length
PDM_ODM_T pDM_Odm,
void * pPtr,
u4Byte length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN void * pBuf1,
IN void * pBuf2,
IN u4Byte length
PDM_ODM_T pDM_Odm,
void * pBuf1,
void * pBuf2,
u4Byte length
);
//
@ -212,14 +212,14 @@ s4Byte ODM_CompareMemory(
//
void
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
PDM_ODM_T pDM_Odm,
RT_SPINLOCK_TYPE type
);
void
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
PDM_ODM_T pDM_Odm,
RT_SPINLOCK_TYPE type
);
@ -228,36 +228,36 @@ ODM_ReleaseSpinLock(
//
void
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN void * pContext,
IN const char* szID
PDM_ODM_T pDM_Odm,
PRT_WORK_ITEM pRtWorkItem,
RT_WORKITEM_CALL_BACK RtWorkItemCallback,
void * pContext,
const char* szID
);
void
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
PRT_WORK_ITEM pRtWorkItem
);
void
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
PRT_WORK_ITEM pRtWorkItem
);
void
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
PRT_WORK_ITEM pRtWorkItem
);
void
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
PRT_WORK_ITEM pRtWorkItem
);
void
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
PRT_WORK_ITEM pRtWorkItem
);
//
@ -265,7 +265,7 @@ ODM_IsWorkItemScheduled(
//
void
ODM_StallExecution(
IN u4Byte usDelay
u4Byte usDelay
);
void
@ -283,30 +283,30 @@ ODM_sleep_us(IN u4Byte us);
void
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
PDM_ODM_T pDM_Odm,
PRT_TIMER pTimer,
u4Byte msDelay
);
void
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN void * pContext,
IN const char* szID
PDM_ODM_T pDM_Odm,
PRT_TIMER pTimer,
RT_TIMER_CALL_BACK CallBackFunc,
void * pContext,
const char* szID
);
void
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
PDM_ODM_T pDM_Odm,
PRT_TIMER pTimer
);
void
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
PDM_ODM_T pDM_Odm,
PRT_TIMER pTimer
);
@ -316,21 +316,21 @@ ODM_ReleaseTimer(
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
void
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
PADAPTER Adapter,
u1Byte ElementID,
u4Byte CmdLen,
pu1Byte pCmdBuffer
);
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
pu1Byte pH2CBuffer,
u4Byte H2CBufferLen,
u4Byte CmdNum,
pu4Byte pElementID,
pu4Byte pCmdLen,
pu1Byte* pCmbBuffer,
pu1Byte CmdStartSeq
);
#endif
#endif // __ODM_INTERFACE_H__

2
include/rtl8188e_hal.h
View file

@ -275,7 +275,7 @@ enum ChannelPlan
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_SPA = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,

24
include/rtl8188e_rf.h
View file

@ -25,20 +25,20 @@
#define RF6052_MAX_PATH 2
int PHY_RF6052_Config8188E( IN PADAPTER Adapter );
void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
int PHY_RF6052_Config8188E( PADAPTER Adapter );
void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
u16 DataRate);
void rtl8188e_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
PADAPTER Adapter,
HT_CHANNEL_WIDTH Bandwidth);
void rtl8188e_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
PADAPTER Adapter,
u8* pPowerlevel);
void rtl8188e_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevelOFDM,
IN u8* pPowerLevelBW20,
IN u8* pPowerLevelBW40,
IN u8 Channel);
PADAPTER Adapter,
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
u8* pPowerLevelBW40,
u8 Channel);
#endif//__RTL8188E_RF_H__

6
include/rtl8188e_spec.h
View file

@ -1419,7 +1419,7 @@ Current IOREG MAP
#define SDIO_HISR_HSISR_IND BIT20
#define SDIO_HISR_GTINT3_IND BIT21
#define SDIO_HISR_GTINT4_IND BIT22
#define SDIO_HISR_PSTIMEOUT BIT23
#define SDIO_HISR_PSTIME BIT23
#define SDIO_HISR_OCPINT BIT24
#define SDIO_HISR_ATIMEND BIT25
#define SDIO_HISR_ATIMEND_E BIT26
@ -1623,13 +1623,13 @@ Current IOREG MAP
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_SPA 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_NCC 0xB
#define EEPROM_USB_OPTIONAL1 0xE

2
include/rtl8192c_dm.h
View file

@ -256,7 +256,7 @@ void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir);
void rtl8192c_init_dm_priv(IN PADAPTER Adapter);
void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192c_InitHalDm( IN PADAPTER Adapter);
void rtl8192c_InitHalDm( PADAPTER Adapter);
void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
#endif //__HAL8190PCIDM_H__

2
include/rtl8192c_hal.h
View file

@ -355,7 +355,7 @@ enum ChannelPlan{
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_SPA = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,

20
include/rtl8192c_rf.h
View file

@ -71,19 +71,19 @@
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192c_RF_ChangeTxPath( PADAPTER Adapter,
u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
PADAPTER Adapter,
HT_CHANNEL_WIDTH Bandwidth);
void rtl8192c_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
PADAPTER Adapter,
u8* pPowerlevel);
void rtl8192c_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN PADAPTER Adapter );
PADAPTER Adapter,
u8* pPowerLevel,
u8 Channel);
int PHY_RF6052_Config8192C( PADAPTER Adapter );
/*--------------------------Exported Function prototype---------------------*/

14
include/rtl8192c_spec.h
View file

@ -474,8 +474,8 @@
//----------------------------------------------------------------------------
// 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
//----------------------------------------------------------------------------
#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
#define GPIO_ REG_GPIO_PIN_CTRL // GPIO pins input value
#define GPIO_ (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
@ -593,7 +593,7 @@ Default: 00b.
#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_PSTIME BIT14 // Power save time out interrupt
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
@ -666,13 +666,13 @@ Default: 00b.
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_SPA 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_NCC 0xB
#define EEPROM_USB_OPTIONAL1 0xE
@ -1755,8 +1755,8 @@ Current IOREG MAP
//----------------------------------------------------------------------------
// 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
//----------------------------------------------------------------------------
#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
#define GPIO_ REG_GPIO_PIN_CTRL // GPIO pins input value
#define GPIO_ (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)

2
include/rtl8192d_hal.h
View file

@ -378,7 +378,7 @@ enum ChannelPlan{
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_SPA = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,

22
include/rtl8192d_rf.h
View file

@ -71,21 +71,21 @@
//
// RF RL6052 Series API
//
void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192d_RF_ChangeTxPath( PADAPTER Adapter,
u16 DataRate);
void rtl8192d_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
PADAPTER Adapter,
HT_CHANNEL_WIDTH Bandwidth);
void rtl8192d_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
PADAPTER Adapter,
u8* pPowerlevel);
void rtl8192d_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192D( IN PADAPTER Adapter );
PADAPTER Adapter,
u8* pPowerLevel,
u8 Channel);
int PHY_RF6052_Config8192D( PADAPTER Adapter );
bool rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN bool bMac0);
bool rtl8192d_PHY_EnableAnotherPHY( PADAPTER Adapter, bool bMac0);
void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN bool bMac0);

10
include/rtl8192d_spec.h
View file

@ -489,8 +489,8 @@
//----------------------------------------------------------------------------
// 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
//----------------------------------------------------------------------------
#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value
#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
#define GPIO_ REG_GPIO_PIN_CTRL // GPIO pins input value
#define GPIO_ (REG_GPIO_PIN_CTRL+1) // GPIO pins output value
#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
@ -611,7 +611,7 @@ Default: 00b.
#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_PSTIME BIT14 // Power save time out interrupt
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
@ -692,13 +692,13 @@ Default: 00b.
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_SPA 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_NCC 0xB
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80

32
include/rtl8723a_bt-coexist.h
View file

@ -167,11 +167,11 @@ typedef enum _HCI_STATUS
HCI_STATUS_UNKNOW_HCI_CMD =0x01, //Unknown HCI Command
HCI_STATUS_UNKNOW_CONNECT_ID =0X02, //Unknown Connection Identifier
HCI_STATUS_HW_FAIL =0X03, //Hardware Failure
HCI_STATUS_PAGE_TIMEOUT =0X04, //Page Timeout
HCI_STATUS_PAGE_TIME =0X04, //Page Timeout
HCI_STATUS_AUTH_FAIL =0X05, //Authentication Failure
HCI_STATUS_PIN_OR_KEY_MISSING =0X06, //PIN or Key Missing
HCI_STATUS_MEM_CAP_EXCEED =0X07, //Memory Capacity Exceeded
HCI_STATUS_CONNECT_TIMEOUT =0X08, //Connection Timeout
HCI_STATUS_CONNECT_TIME =0X08, //Connection Timeout
HCI_STATUS_CONNECT_LIMIT =0X09, //Connection Limit Exceeded
HCI_STATUS_SYN_CONNECT_LIMIT =0X0a, //Synchronous Connection Limit To A Device Exceeded
HCI_STATUS_ACL_CONNECT_EXISTS =0X0b, //ACL Connection Already Exists
@ -179,7 +179,7 @@ typedef enum _HCI_STATUS
HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE =0X0d, //Connection Rejected due to Limited Resources
HCI_STATUS_CONNECT_RJT_SEC_REASON =0X0e, //Connection Rejected Due To Security Reasons
HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR =0X0f, //Connection Rejected due to Unacceptable BD_ADDR
HCI_STATUS_CONNECT_ACCEPT_TIMEOUT =0X10, //Connection Accept Timeout Exceeded
HCI_STATUS_CONNECT_ACCEPT_TIME =0X10, //Connection Accept Timeout Exceeded
HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE =0X11, //Unsupported Feature or Parameter Value
HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE =0X12, //Invalid HCI Command Parameters
HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT =0X13, //Remote User Terminated Connection
@ -197,7 +197,7 @@ typedef enum _HCI_STATUS
HCI_STATUS_UNSPECIFIC_ERROR =0X1f, //Unspecified Error
HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE =0X20, //Unsupported LMP Parameter Value
HCI_STATUS_ROLE_CHANGE_NOT_ALLOW =0X21, //Role Change Not Allowed
HCI_STATUS_LMP_RESPONSE_TIMEOUT =0X22, //LMP Response Timeout
HCI_STATUS_LMP_RESPONSE_TIME =0X22, //LMP Response Timeout
HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION =0X23, //LMP Error Transaction Collision
HCI_STATUS_LMP_PDU_NOT_ALLOW =0X24, //LMP PDU Not Allowed
HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW =0X25, //Encryption Mode Not Acceptable
@ -318,10 +318,10 @@ typedef enum _SET_EVENT_MASK_COMMAND
HCI_DELETE_STORED_LINK_KEY =0x0012,
HCI_WRITE_LOCAL_NAME =0x0013,
HCI_READ_LOCAL_NAME =0x0014,
HCI_READ_CONNECTION_ACCEPT_TIMEOUT =0x0015,
HCI_WRITE_CONNECTION_ACCEPT_TIMEOUT =0x0016,
HCI_READ_PAGE_TIMEOUT =0x0017,
HCI_WRITE_PAGE_TIMEOUT =0x0018,
HCI_READ_CONNECTION_ACCEPT_TIME =0x0015,
HCI_WRITE_CONNECTION_ACCEPT_TIME =0x0016,
HCI_READ_PAGE_TIME =0x0017,
HCI_WRITE_PAGE_TIME =0x0018,
HCI_READ_SCAN_ENABLE =0x0019,
HCI_WRITE_SCAN_ENABLE =0x001a,
HCI_READ_PAGE_SCAN_ACTIVITY =0x001b,
@ -334,8 +334,8 @@ typedef enum _SET_EVENT_MASK_COMMAND
HCI_WRITE_CLASS_OF_DEVICE =0x0024,
HCI_READ_VOICE_SETTING =0x0025,
HCI_WRITE_VOICE_SETTING =0x0026,
HCI_READ_AUTOMATIC_FLUSH_TIMEOUT =0x0027,
HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT =0x0028,
HCI_READ_AUTOMATIC_FLUSH_TIME =0x0027,
HCI_WRITE_AUTOMATIC_FLUSH_TIME =0x0028,
HCI_READ_NUM_BROADCAST_RETRANSMISSIONS =0x0029,
HCI_WRITE_NUM_BROADCAST_RETRANSMISSIONS =0x002a,
HCI_READ_HOLD_MODE_ACTIVITY =0x002b,
@ -345,8 +345,8 @@ typedef enum _SET_EVENT_MASK_COMMAND
HCI_SET_CONTROLLER_TO_HOST_FLOW_CONTROL =0x0031,
HCI_HOST_BUFFER_SIZE =0x0033,
HCI_HOST_NUMBER_OF_COMPLETED_PACKETS =0x0035,
HCI_READ_LINK_SUPERVISION_TIMEOUT =0x0036,
HCI_WRITE_LINK_SUPERVISION_TIMEOUT =0x0037,
HCI_READ_LINK_SUPERVISION_TIME =0x0036,
HCI_WRITE_LINK_SUPERVISION_TIME =0x0037,
HCI_READ_NUMBER_OF_SUPPORTED_IAC =0x0038,
HCI_READ_CURRENT_IAC_LAP =0x0039,
HCI_WRITE_CURRENT_IAC_LAP =0x003a,
@ -373,16 +373,16 @@ typedef enum _SET_EVENT_MASK_COMMAND
HCI_WRITE_DEFAULT_ERRONEOUS_DATA_REPORTING =0x005b,
HCI_ENHANCED_FLUSH =0x005f,
HCI_SEND_KEYPRESS_NOTIFICATION =0x0060,
HCI_READ_LOGICAL_LINK_ACCEPT_TIMEOUT =0x0061,
HCI_WRITE_LOGICAL_LINK_ACCEPT_TIMEOUT =0x0062,
HCI_READ_LOGICAL_LINK_ACCEPT_TIME =0x0061,
HCI_WRITE_LOGICAL_LINK_ACCEPT_TIME =0x0062,
HCI_SET_EVENT_MASK_PAGE_2 =0x0063,
HCI_READ_LOCATION_DATA =0x0064,
HCI_WRITE_LOCATION_DATA =0x0065,
HCI_READ_FLOW_CONTROL_MODE =0x0066,
HCI_WRITE_FLOW_CONTROL_MODE =0x0067,
HCI_READ_ENHANCE_TRANSMIT_POWER_LEVEL =0x0068,
HCI_READ_BEST_EFFORT_FLUSH_TIMEOUT =0x0069,
HCI_WRITE_BEST_EFFORT_FLUSH_TIMEOUT =0x006a,
HCI_READ_BEST_EFFORT_FLUSH_TIME =0x0069,
HCI_WRITE_BEST_EFFORT_FLUSH_TIME =0x006a,
HCI_SHORT_RANGE_MODE =0x006b
}SET_EVENT_MASK_COMMAND,*PSET_EVENT_MASK_COMMAND;

2
include/rtl8723a_hal.h
View file

@ -316,7 +316,7 @@ enum ChannelPlan
CHPL_FCC = 0,
CHPL_IC = 1,
CHPL_ETSI = 2,
CHPL_SPAIN = 3,
CHPL_SPA = 3,
CHPL_FRANCE = 4,
CHPL_MKK = 5,
CHPL_MKK1 = 6,

2
include/rtl8723a_rf.h
View file

@ -21,6 +21,6 @@
#define __RTL8723A_RF_H__
#include "rtl8192c_rf.h"
int PHY_RF6052_Config8723A( IN PADAPTER Adapter );
int PHY_RF6052_Config8723A( PADAPTER Adapter );
#endif

4
include/rtl8723a_spec.h
View file

@ -411,7 +411,7 @@
#define SDIO_HISR_HSISR_IND BIT20
#define SDIO_HISR_GTINT3_IND BIT21
#define SDIO_HISR_GTINT4_IND BIT22
#define SDIO_HISR_PSTIMEOUT BIT23
#define SDIO_HISR_PSTIME BIT23
#define SDIO_HISR_OCPINT BIT24
#define SDIO_HISR_ATIMEND BIT25
#define SDIO_HISR_ATIMEND_E BIT26
@ -459,7 +459,7 @@
//-----------------------------------------------------------------------------
#define UHIMR_TIMEOUT2 BIT31
#define UHIMR_TIMEOUT1 BIT30
#define UHIMR_PSTIMEOUT BIT29
#define UHIMR_PSTIME BIT29
#define UHIMR_GTINT4 BIT28
#define UHIMR_GTINT3 BIT27
#define UHIMR_TXBCNERR BIT26

24
include/rtw_bt_mp.h
View file

@ -112,7 +112,7 @@ typedef enum _BT_CTRL_STATUS{
BT_STATUS_SUCCESS = 0x00, // Success
BT_STATUS_BT_OP_SUCCESS = 0x01, // bt fw op execution success
BT_STATUS_H2C_SUCCESS = 0x02, // H2c success
BT_STATUS_H2C_TIMTOUT = 0x03, // H2c timeout
BT_STATUS_H2C_TIMT = 0x03, // H2c timeout
BT_STATUS_H2C_BT_NO_RSP = 0x04, // H2c sent, bt no rsp
BT_STATUS_C2H_SUCCESS = 0x05, // C2h success
BT_STATUS_C2H_REQNUM_MISMATCH = 0x06, // bt fw wrong rsp
@ -182,20 +182,20 @@ typedef enum _BT_REPORT_TYPE{
void
MPTBT_Test(
IN PADAPTER Adapter,
IN u1Byte opCode,
IN u1Byte byte1,
IN u1Byte byte2,
IN u1Byte byte3
PADAPTER Adapter,
u1Byte opCode,
u1Byte byte1,
u1Byte byte2,
u1Byte byte3
);
NDIS_STATUS
MPTBT_SendOidBT(
IN PADAPTER pAdapter,
IN void * InformationBuffer,
IN ULONG InformationBufferLength,
OUT PULONG BytesRead,
OUT PULONG BytesNeeded
PADAPTER pAdapter,
void * InformationBuffer,
ULONG InformationBufferLength,
PULONG BytesRead,
PULONG BytesNeeded
);
void
@ -264,7 +264,7 @@ typedef enum _BT_CTRL_OPCODE_LOWER{
BT_LO_OP_RESET = 0x01,
BT_LO_OP_TEST_CTRL = 0x02,
BT_LO_OP_SET_BT_MODE = 0x03,
BT_LO_OP_SET_CHNL_TX_GAIN = 0x04,
BT_LO_OP_SET_CHNL_TX_GA = 0x04,
BT_LO_OP_SET_PKT_TYPE_LEN = 0x05,
BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,

4
include/rtw_eeprom.h
View file

@ -56,8 +56,8 @@
#define EEPROM_CID_CAMEO 0X8
#define EEPROM_CID_SITECOM 0x9
#define EEPROM_CID_COREGA 0xB
#define EEPROM_CID_EDIMAX_BELKIN 0xC
#define EEPROM_CID_SERCOMM_BELKIN 0xE
#define EEPROM_CID_EDIMAX_BELK 0xC
#define EEPROM_CID_SERCOMM_BELK 0xE
#define EEPROM_CID_CAMEO1 0xF
#define EEPROM_CID_WNC_COREGA 0x12
#define EEPROM_CID_CLEVO 0x13

24
include/rtw_ioctl.h
View file

@ -248,21 +248,21 @@ extern struct iw_handler_def rtw_handlers_def;
#endif
extern NDIS_STATUS drv_query_info(
IN _nic_hdl MiniportAdapterContext,
IN NDIS_OID Oid,
IN void * InformationBuffer,
IN u32 InformationBufferLength,
OUT u32* BytesWritten,
OUT u32* BytesNeeded
_nic_hdl MiniportAdapterContext,
NDIS_OID Oid,
void * InformationBuffer,
u32 InformationBufferLength,
u32* BytesWritten,
u32* BytesNeeded
);
extern NDIS_STATUS drv_set_info(
IN _nic_hdl MiniportAdapterContext,
IN NDIS_OID Oid,
IN void * InformationBuffer,
IN u32 InformationBufferLength,
OUT u32* BytesRead,
OUT u32* BytesNeeded
_nic_hdl MiniportAdapterContext,
NDIS_OID Oid,
void * InformationBuffer,
u32 InformationBufferLength,
u32* BytesRead,
u32* BytesNeeded
);
#endif // #ifndef __INC_CEINFO_

20
include/rtw_mlme.h
View file

@ -31,8 +31,8 @@
#endif
#define MAX_BSS_CNT 128
//#define MAX_JOIN_TIMEOUT 2000
//#define MAX_JOIN_TIMEOUT 2500
//#define MAX_JOIN_TIME 2000
//#define MAX_JOIN_TIME 2500
#define MAX_JOIN_TIMEOUT 6500
// Commented by Albert 20101105
@ -601,17 +601,17 @@ void rtw_indicate_wx_disassoc_event(_adapter *padapter);
extern thread_return event_thread(void *context);
extern void rtw_join_timeout_handler (
IN void * SystemSpecific1,
IN void * FunctionContext,
IN void * SystemSpecific2,
IN void * SystemSpecific3
void * SystemSpecific1,
void * FunctionContext,
void * SystemSpecific2,
void * SystemSpecific3
);
extern void _rtw_scan_timeout_handler (
IN void * SystemSpecific1,
IN void * FunctionContext,
IN void * SystemSpecific2,
IN void * SystemSpecific3
void * SystemSpecific1,
void * FunctionContext,
void * SystemSpecific2,
void * SystemSpecific3
);
#endif

2
include/rtw_mlme_ext.h
View file

@ -72,7 +72,7 @@
#define DYNAMIC_BB_CCK_PD BIT(5)
#define DYNAMIC_BB_ANT_DIV BIT(6)
#define DYNAMIC_BB_PWR_SAVE BIT(7)
#define DYNAMIC_BB_PWR_TRAIN BIT(8)
#define DYNAMIC_BB_PWR_TRA BIT(8)
#define DYNAMIC_BB_RATE_ADAPTIVE BIT(9)
#define DYNAMIC_BB_PATH_DIV BIT(10)
#define DYNAMIC_BB_PSD BIT(11)

24
include/rtw_pwrctrl.h
View file

@ -52,17 +52,17 @@
enum Power_Mgnt
{
PS_MODE_ACTIVE = 0 ,
PS_MODE_MIN ,
PS_MODE_MAX ,
PS_MODE_DTIM ,
PS_MODE_VOIP ,
PS_MODE_UAPSD_WMM ,
PS_MODE_UAPSD ,
PS_MODE_IBSS ,
PS_MODE_WWLAN ,
PM_Radio_Off ,
PM_Card_Disable ,
PS_MODE_ACTIVE = 0,
PS_MODE_MIN,
PS_MODE_MAX,
PS_MODE_DTIM,
PS_MODE_VOIP,
PS_MODE_UAPSD_WMM,
PS_MODE_UAPSD,
PS_MODE_IBSS,
PS_MODE_WWLAN,
PM_Radio_Off,
PM_Card_Disable ,
PS_MODE_NUM
};
@ -342,7 +342,7 @@ void rtw_ps_processor(_adapter*padapter);
int autoresume_enter(_adapter* padapter);
#endif
#ifdef SUPPORT_HW_RFOFF_DETECTED
rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter );
rt_rf_power_state RfOnOffDetect( PADAPTER pAdapter );
#endif

8
include/rtw_security.h
View file

@ -430,10 +430,10 @@ int tdls_verify_mic(u8 *kck, u8 trans_seq,
#ifdef PLATFORM_WINDOWS
void rtw_use_tkipkey_handler (
IN void * SystemSpecific1,
IN void * FunctionContext,
IN void * SystemSpecific2,
IN void * SystemSpecific3
void * SystemSpecific1,
void * FunctionContext,
void * SystemSpecific2,
void * SystemSpecific3
);
#endif
#ifdef PLATFORM_LINUX

2
include/rtw_tdls.h
View file

@ -39,7 +39,7 @@
#define TPK_RESEND_COUNT 301
#define CH_SWITCH_TIME 10
#define CH_SWITCH_TIMEOUT 30
#define CH_SWITCH_TIME 30
#define TDLS_STAY_TIME 500
#define TDLS_SIGNAL_THRESH 0x20
#define TDLS_WATCHDOG_PERIOD 10 //Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec

2
include/usb_ops_linux.h
View file

@ -32,7 +32,7 @@
#define MAX_USBCTRL_VENDORREQ_TIMES 1
#endif
#define RTW_USB_BULKOUT_TIMEOUT 5000//ms
#define RTW_USB_BULKOUT_TIME 5000//ms
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb)

14
include/wifi.h
View file

@ -229,7 +229,7 @@ enum WIFI_REG_DOMAIN {
DOMAIN_FCC = 1,
DOMAIN_IC = 2,
DOMAIN_ETSI = 3,
DOMAIN_SPAIN = 4,
DOMAIN_SPA = 4,
DOMAIN_FRANCE = 5,
DOMAIN_MKK = 6,
DOMAIN_ISRAEL = 7,
@ -993,7 +993,7 @@ typedef enum _HT_CAP_AMPDU_FACTOR {
#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER
// Value of Device Password ID
#define WPS_DPID_PIN 0x0000
#define WPS_DPID_P 0x0000
#define WPS_DPID_USER_SPEC 0x0001
#define WPS_DPID_MACHINE_SPEC 0x0002
#define WPS_DPID_REKEY 0x0003
@ -1111,12 +1111,12 @@ typedef enum _HT_CAP_AMPDU_FACTOR {
#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX
#define P2P_PROVISION_TIMEOUT 5000 // 5 seconds timeout for sending the provision discovery request
#define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 // 3 seconds timeout for sending the provision discovery request under concurrent mode
#define P2P_CONCURRENT_PROVISION_TIME 3000 // 3 seconds timeout for sending the provision discovery request under concurrent mode
#define P2P_GO_NEGO_TIMEOUT 5000 // 5 seconds timeout for receiving the group negotation response
#define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 // 3 seconds timeout for sending the negotiation request under concurrent mode
#define P2P_CONCURRENT_GO_NEGO_TIME 3000 // 3 seconds timeout for sending the negotiation request under concurrent mode
#define P2P_TX_PRESCAN_TIMEOUT 100 // 100ms
#define P2P_INVITE_TIMEOUT 5000 // 5 seconds timeout for sending the invitation request
#define P2P_CONCURRENT_INVITE_TIMEOUT 3000 // 3 seconds timeout for sending the invitation request under concurrent mode
#define P2P_CONCURRENT_INVITE_TIME 3000 // 3 seconds timeout for sending the invitation request under concurrent mode
#define P2P_RESET_SCAN_CH 25000 // 25 seconds timeout to reset the scan channel ( based on channel plan )
#define P2P_MAX_INTENT 15
@ -1133,8 +1133,8 @@ typedef enum _HT_CAP_AMPDU_FACTOR {
#define WPS_CM_KEYPAD 0x0100
#define WPS_CM_SW_PUHS_BUTTON 0x0280
#define WPS_CM_HW_PUHS_BUTTON 0x0480
#define WPS_CM_SW_DISPLAY_PIN 0x2008
#define WPS_CM_LCD_DISPLAY_PIN 0x4008
#define WPS_CM_SW_DISPLAY_P 0x2008
#define WPS_CM_LCD_DISPLAY_P 0x4008
enum P2P_ROLE {
P2P_ROLE_DISABLE = 0,