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rtl8188eu: Remove trailing white space from all source files

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-05-18 23:28:07 -05:00
parent 77e736c66a
commit f5f3863bc5
205 changed files with 55371 additions and 55581 deletions
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57
include/Hal8188EFWImg_CE.h
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@ -1,29 +1,28 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188E_FW_IMG_H
#define __INC_HAL8188E_FW_IMG_H
//V10(1641)
#define Rtl8188EFWImgArrayLength 13904
extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
#endif //__INC_HAL8188E_FW_IMG_H
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188E_FW_IMG_H
#define __INC_HAL8188E_FW_IMG_H
//V10(1641)
#define Rtl8188EFWImgArrayLength 13904
extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
#endif //__INC_HAL8188E_FW_IMG_H

853
include/Hal8188EPhyCfg.h
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@ -1,427 +1,426 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188EPHYCFG_H__
#define __INC_HAL8188EPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
typedef enum _HW90_BLOCK{
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define MAX_PG_GROUP 13
#define RF_PATH_MAX 2
#define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT 4 //path numbers
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups
#define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
u32 rtl8188e_PHY_QueryBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8188e_PHY_QueryRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(IN PADAPTER Adapter );
int PHY_BBConfig8188E(IN PADAPTER Adapter );
int PHY_RFConfig8188E(IN PADAPTER Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8188E( IN PADAPTER Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8188E( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8188E( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8188E(IN PADAPTER Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8188E( IN PADAPTER pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8188E( IN PADAPTER pAdapter,
IN u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
IN u32 eRFPath );
VOID PHY_SetRFPathSwitch_8188E(IN PADAPTER pAdapter, IN BOOLEAN bMain);
extern VOID
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
);
#ifdef CONFIG_PHY_SETTING_WITH_ODM
VOID
storePwrIndexDiffRateOffset(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
#endif //CONFIG_PHY_SETTING_WITH_ODM
/*--------------------------Exported Function prototype---------------------*/
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8188e_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8188e_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8188e_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8188e_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
//extern s32 PHY_MACConfig8723(PADAPTER padapter);
//s32 PHY_BBConfig8723(PADAPTER padapter);
//s32 PHY_RFConfig8723(PADAPTER padapter);
//==================================================================
// Note: If SIC_ENABLE under PCIE, because of the slow operation
// you should
// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
// 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
//
#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
#define SIC_ENABLE 1
#define SIC_HW_SUPPORT 1
#else
#define SIC_ENABLE 0
#define SIC_HW_SUPPORT 0
#endif
//==================================================================
#define SIC_MAX_POLL_CNT 5
#if (SIC_HW_SUPPORT == 1)
#define SIC_CMD_READY 0
#define SIC_CMD_PREWRITE 0x1
#if (RTL8188E_SUPPORT == 1)
#define SIC_CMD_WRITE 0x40
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x80
#define SIC_CMD_INIT 0xf0
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1EC // 1b0~1b3
#else
#define SIC_CMD_WRITE 0x11
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x12
#define SIC_CMD_INIT 0x1f
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1b6 // 1byte
#define SIC_ADDR_REG 0x1b4 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1b0 // 1b0~1b3
#endif
#else
#define SIC_CMD_READY 0
#define SIC_CMD_WRITE 1
#define SIC_CMD_READ 2
#if (RTL8188E_SUPPORT == 1)
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1EC // 1bc~1bf
#else
#define SIC_CMD_REG 0x1b8 // 1byte
#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1bc // 1bc~1bf
#endif
#endif
#if (SIC_ENABLE == 1)
VOID SIC_Init(IN PADAPTER Adapter);
#endif
#endif // __INC_HAL8192CPHYCFG_H
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188EPHYCFG_H__
#define __INC_HAL8188EPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
typedef enum _HW90_BLOCK{
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define MAX_PG_GROUP 13
#define RF_PATH_MAX 2
#define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT 4 //path numbers
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups
#define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
u32 rtl8188e_PHY_QueryBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetBBReg( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8188e_PHY_QueryRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetRFReg( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(IN PADAPTER Adapter );
int PHY_BBConfig8188E(IN PADAPTER Adapter );
int PHY_RFConfig8188E(IN PADAPTER Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8188E( IN PADAPTER Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8188E( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8188E( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8188E(IN PADAPTER Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8188E( IN PADAPTER pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8188E( IN PADAPTER pAdapter,
IN u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
IN u32 eRFPath );
VOID PHY_SetRFPathSwitch_8188E(IN PADAPTER pAdapter, IN BOOLEAN bMain);
extern VOID
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
);
#ifdef CONFIG_PHY_SETTING_WITH_ODM
VOID
storePwrIndexDiffRateOffset(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
#endif //CONFIG_PHY_SETTING_WITH_ODM
/*--------------------------Exported Function prototype---------------------*/
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8188e_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8188e_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8188e_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8188e_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
//extern s32 PHY_MACConfig8723(PADAPTER padapter);
//s32 PHY_BBConfig8723(PADAPTER padapter);
//s32 PHY_RFConfig8723(PADAPTER padapter);
//==================================================================
// Note: If SIC_ENABLE under PCIE, because of the slow operation
// you should
// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
// 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
//
#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
#define SIC_ENABLE 1
#define SIC_HW_SUPPORT 1
#else
#define SIC_ENABLE 0
#define SIC_HW_SUPPORT 0
#endif
//==================================================================
#define SIC_MAX_POLL_CNT 5
#if (SIC_HW_SUPPORT == 1)
#define SIC_CMD_READY 0
#define SIC_CMD_PREWRITE 0x1
#if (RTL8188E_SUPPORT == 1)
#define SIC_CMD_WRITE 0x40
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x80
#define SIC_CMD_INIT 0xf0
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1EC // 1b0~1b3
#else
#define SIC_CMD_WRITE 0x11
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x12
#define SIC_CMD_INIT 0x1f
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1b6 // 1byte
#define SIC_ADDR_REG 0x1b4 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1b0 // 1b0~1b3
#endif
#else
#define SIC_CMD_READY 0
#define SIC_CMD_WRITE 1
#define SIC_CMD_READ 2
#if (RTL8188E_SUPPORT == 1)
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1EC // 1bc~1bf
#else
#define SIC_CMD_REG 0x1b8 // 1byte
#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1bc // 1bc~1bf
#endif
#endif
#if (SIC_ENABLE == 1)
VOID SIC_Init(IN PADAPTER Adapter);
#endif
#endif // __INC_HAL8192CPHYCFG_H

2221
include/Hal8188EPhyReg.h
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353
include/Hal8188EPwrSeq.h
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@ -1,177 +1,176 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL8188EPWRSEQ_H__
#define __HAL8188EPWRSEQ_H__
#include "HalPwrSeqCmd.h"
/*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8188E_PwrSeq_V09.h
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8188E_TRANS_END_STEPS 1
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step
#define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif //__HAL8188EPWRSEQ_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL8188EPWRSEQ_H__
#define __HAL8188EPWRSEQ_H__
#include "HalPwrSeqCmd.h"
/*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8188E_PwrSeq_V09.h
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8188E_TRANS_END_STEPS 1
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step
#define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif //__HAL8188EPWRSEQ_H__

215
include/Hal8188ERateAdaptive.h
View file

@ -1,108 +1,107 @@
#ifndef __INC_RA_H
#define __INC_RA_H
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
RateAdaptive.h
Abstract:
Prototype of RA and related data structure.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-08-12 Page Create.
--*/
// Rate adaptive define
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
//
// TX report 2 format in Rx desc
//
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16)
#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8)
#endif
// End rate adaptive define
VOID
ODM_RASupport_Init(
IN PDM_ODM_T pDM_Odm
);
int
ODM_RAInfo_Init_all(
IN PDM_ODM_T pDM_Odm
);
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
VOID
ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u4Byte RateMask,
IN u1Byte SGIEnable
);
VOID
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
);
VOID
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u2Byte TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
);
VOID
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
);
#endif
#ifndef __INC_RA_H
#define __INC_RA_H
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
RateAdaptive.h
Abstract:
Prototype of RA and related data structure.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-08-12 Page Create.
--*/
// Rate adaptive define
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
//
// TX report 2 format in Rx desc
//
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16)
#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8)
#endif
// End rate adaptive define
VOID
ODM_RASupport_Init(
IN PDM_ODM_T pDM_Odm
);
int
ODM_RAInfo_Init_all(
IN PDM_ODM_T pDM_Odm
);
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
VOID
ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u4Byte RateMask,
IN u1Byte SGIEnable
);
VOID
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
);
VOID
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u2Byte TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
);
VOID
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
);
#endif

93
include/Hal8188EReg.h
View file

@ -1,47 +1,46 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: Hal8188EReg.h
//
// Description:
//
// This file is for RTL8188E register definition.
//
//
//============================================================
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
//
// Register Definition
//
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
//
// Bitmap Definition
//
#define BIT_FA_RESET_8188E BIT0
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: Hal8188EReg.h
//
// Description:
//
// This file is for RTL8188E register definition.
//
//
//============================================================
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
//
// Register Definition
//
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
//
// Bitmap Definition
//
#define BIT_FA_RESET_8188E BIT0
#endif

127
include/Hal8192CPhyCfg.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -21,18 +21,18 @@
* Module: __INC_HAL8192CPHYCFG_H
*
*
* Note:
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192CPHYCFG_H
@ -79,7 +79,7 @@
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
@ -112,7 +112,7 @@ typedef enum _RF_RADIO_PATH{
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define RF_PATH_MAX 2
@ -122,12 +122,12 @@ typedef enum _RF_RADIO_PATH{
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
@ -152,75 +152,75 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
@ -230,12 +230,12 @@ typedef struct _R_ANTENNA_SELECT_OFDM{
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
@ -276,7 +276,7 @@ int PHY_BBConfig8192C( IN PADAPTER Adapter );
int PHY_RFConfig8192C( IN PADAPTER Adapter );
/* RF config */
int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
@ -291,21 +291,21 @@ void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
VOID
PHY_ScanOperationBackup8192C(IN PADAPTER Adapter,
IN u8 Operation );
@ -342,7 +342,7 @@ void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
@ -358,7 +358,7 @@ VOID rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
//
// Modify the value of the hw register when beacon interval be changed.
//
void
void
rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
@ -376,7 +376,7 @@ PHY_EnableHostClkReq(
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
IN u8 DefaultAnt
);
#ifdef RTL8192C_RECONFIG_TO_1T1R
@ -392,4 +392,3 @@ extern void PHY_Reconfig_To_1T1R(_adapter *padapter);
#define PHY_SetMacReg PHY_SetBBReg
#endif // __INC_HAL8192CPHYCFG_H

451
include/Hal8192CPhyReg.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -27,18 +27,18 @@
* 3. PMAC/BB register bit mask.
* 4. RF reg bit mask.
* 5. Other BB/RF relative definition.
*
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
* 09/25/2008 MH 1. Add RL6052 register definition
*
*
*****************************************************************************/
#ifndef __INC_HAL8192CPHYREG_H
#define __INC_HAL8192CPHYREG_H
@ -179,8 +179,8 @@
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxHP 0xa14
@ -191,20 +191,20 @@
#define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rConfig_Pmpd_AntB 0xb98
#define rAPK 0xbd8
@ -218,16 +218,16 @@
#define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
@ -255,7 +255,7 @@
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c
#define rOFDM0_XCTxIQImbalance 0xc90
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxIQImbalance 0xc98
#define rOFDM0_XDTxAFE 0xc9c
@ -298,8 +298,8 @@
#define rOFDM_LongCFOCD 0xdb8
#define rOFDM_TailCFOAB 0xdbc
#define rOFDM_TailCFOCD 0xdc0
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_BWReport 0xdcc
#define rOFDM_AGCReport 0xdd0
#define rOFDM_RxSNR 0xdd4
@ -324,7 +324,7 @@
#define rTx_IQK_PI_A 0xe38
#define rRx_IQK_PI_A 0xe3c
#define rTx_IQK 0xe40
#define rTx_IQK 0xe40
#define rRx_IQK 0xe44
#define rIQK_AGC_Pts 0xe48
#define rIQK_AGC_Rsp 0xe4c
@ -361,10 +361,10 @@
#define rRx_Power_After_IQK_B_2 0xecc
#define rRx_OFDM 0xed0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rPMPD_ANAEN 0xeec
//
@ -398,56 +398,56 @@
//
// RL6052 Register definition
//
#define RF_AC 0x00 //
#define RF_AC 0x00 //
#define RF_IQADJ_G1 0x01 //
#define RF_IQADJ_G2 0x02 //
#define RF_IQADJ_G1 0x01 //
#define RF_IQADJ_G2 0x02 //
#define RF_BS_PA_APSET_G1_G4 0x03
#define RF_BS_PA_APSET_G5_G8 0x04
#define RF_POW_TRSW 0x05 //
#define RF_POW_TRSW 0x05 //
#define RF_GAIN_RX 0x06 //
#define RF_GAIN_TX 0x07 //
#define RF_GAIN_RX 0x06 //
#define RF_GAIN_TX 0x07 //
#define RF_TXM_IDAC 0x08 //
#define RF_IPA_G 0x09 //
#define RF_TXM_IDAC 0x08 //
#define RF_IPA_G 0x09 //
#define RF_TXBIAS_G 0x0A
#define RF_TXPA_AG 0x0B
#define RF_IPA_A 0x0C //
#define RF_IPA_A 0x0C //
#define RF_TXBIAS_A 0x0D
#define RF_BS_PA_APSET_G9_G11 0x0E
#define RF_BS_IQGEN 0x0F //
#define RF_BS_IQGEN 0x0F //
#define RF_MODE1 0x10 //
#define RF_MODE2 0x11 //
#define RF_MODE1 0x10 //
#define RF_MODE2 0x11 //
#define RF_RX_AGC_HP 0x12 //
#define RF_TX_AGC 0x13 //
#define RF_BIAS 0x14 //
#define RF_IPA 0x15 //
#define RF_RX_AGC_HP 0x12 //
#define RF_TX_AGC 0x13 //
#define RF_BIAS 0x14 //
#define RF_IPA 0x15 //
#define RF_TXBIAS 0x16 //
#define RF_POW_ABILITY 0x17 //
#define RF_MODE_AG 0x18 //
#define RF_POW_ABILITY 0x17 //
#define RF_MODE_AG 0x18 //
#define rRfChannel 0x18 // RF channel and BW switch
#define RF_CHNLBW 0x18 // RF channel and BW switch
#define RF_TOP 0x19 //
#define RF_TOP 0x19 //
#define RF_RX_G1 0x1A //
#define RF_RX_G2 0x1B //
#define RF_RX_G1 0x1A //
#define RF_RX_G2 0x1B //
#define RF_RX_BB2 0x1C //
#define RF_RX_BB1 0x1D //
#define RF_RX_BB2 0x1C //
#define RF_RX_BB1 0x1D //
#define RF_RCK1 0x1E //
#define RF_RCK2 0x1F //
#define RF_RCK1 0x1E //
#define RF_RCK2 0x1F //
#define RF_TX_G1 0x20 //
#define RF_TX_G2 0x21 //
#define RF_TX_G3 0x22 //
#define RF_TX_G1 0x20 //
#define RF_TX_G2 0x21 //
#define RF_TX_G3 0x22 //
#define RF_TX_BB1 0x23 //
#define RF_TX_BB1 0x23 //
#define RF_T_METER 0x24 //
#define RF_T_METER 0x24 //
#define RF_SYN_G1 0x25 // RF TX Power control
#define RF_SYN_G2 0x26 // RF TX Power control
@ -513,7 +513,7 @@
#define bCCKTxStatus 0x1
#define bOFDMTxStatus 0x2
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
@ -522,157 +522,157 @@
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bAntennaSelect 0x0300
#define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bLSSIReadBackData 0xfffff // T65 RF
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000
#define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
// 3. Page9(0x900)
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
// 4. PageA(0xA00)
#define bCCKBBMode 0x3 // Useless
@ -716,7 +716,7 @@
#define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly
#define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300
@ -748,9 +748,9 @@
#define bCCKRxFACounterLower 0xff
#define bCCKRxFACounterUpper 0xff000000
#define bCCKRxHPAGCStart 0xe000
#define bCCKRxHPAGCFinal 0x1c00
#define bCCKRxHPAGCFinal 0x1c00
#define bCCKRxFalseAlarmEnable 0x8000
#define bCCKFACounterFreeze 0x4000
#define bCCKFACounterFreeze 0x4000
#define bCCKTxPathSel 0x10000000
#define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000
@ -902,16 +902,16 @@
#define bRxSGI_TH 0xc0000000
#define bDFSCnt0 0xff
#define bDFSCnt1 0xff00
#define bDFSFlag 0xf0000
#define bDFSFlag 0xf0000
#define bMFWeightSum 0x300000
#define bMinIdxTH 0x7f000000
#define bDAFormat 0x40000
#define bTxChEmuEnable 0x01000000
#define bMinIdxTH 0x7f000000
#define bDAFormat 0x40000
#define bTxChEmuEnable 0x01000000
#define bTRSWIsolation_A 0x7f
#define bTRSWIsolation_B 0x7f00
#define bTRSWIsolation_C 0x7f0000
#define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00
#define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00
// 6. PageE(0xE00)
#define bSTBCEn 0x4 // Useless
@ -948,7 +948,7 @@
#define bLongCFOFLength 11
#define bTailCFO 0x1fff
#define bTailCFOTLength 13
#define bTailCFOFLength 12
#define bTailCFOFLength 12
#define bmax_en_pwdB 0xffff
#define bCC_power_dB 0xffff0000
#define bnoise_pwdB 0xffff
@ -956,27 +956,27 @@
#define bPowerMeasFLength 3
#define bRx_HT_BW 0x1
#define bRxSC 0x6
#define bRx_HT 0x8
#define bRx_HT 0x8
#define bNB_intf_det_on 0x1
#define bIntf_win_len_cfg 0x30
#define bNB_Intf_TH_cfg 0x1c0
#define bNB_Intf_TH_cfg 0x1c0
#define bRFGain 0x3f
#define bTableSel 0x40
#define bTRSW 0x80
#define bTRSW 0x80
#define bRxSNR_A 0xff
#define bRxSNR_B 0xff00
#define bRxSNR_C 0xff0000
#define bRxSNR_D 0xff000000
#define bSNREVMTLength 8
#define bSNREVMFLength 1
#define bSNREVMFLength 1
#define bCSI1st 0xff
#define bCSI2nd 0xff00
#define bRxEVM1st 0xff0000
#define bRxEVM2nd 0xff000000
#define bRxEVM2nd 0xff000000
#define bSIGEVM 0xff
#define bPWDB 0xff00
#define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless
#define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00
@ -987,7 +987,7 @@
#define bSFactorQAM8 0xf000000
#define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless
#define bChSmooth 0x4
#define bChSmoothCfg1 0x38
@ -996,7 +996,7 @@
#define bChSmoothCfg4 0x7000
#define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless
#define bUpdCFO 0x40
#define bUpdCFOOffData 0x80
@ -1070,24 +1070,24 @@
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
#define bMask12Bits 0xfff
#define bMaskH4Bits 0xf0000000
#define bMaskH4Bits 0xf0000000
#define bMaskOFDM_D 0xffc00000
#define bMaskCCK 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff
#define bRFRegOffsetMask 0xfffff
#define bEnable 0x1 // Useless
#define bDisable 0x0
#define LeftAntenna 0x0 // Useless
#define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless
#define tUpdateRxCounter 100 //100ms
#define rateCCK 0 // Useless
#define rateOFDM 1
#define rateHT 2
@ -1110,7 +1110,7 @@
#define bPMACControl 0x0 // Useless
#define bWMACControl 0x1
#define bWNICControl 0x2
#define PathA 0x0 // Useless
#define PathB 0x1
#define PathC 0x2
@ -1120,4 +1120,3 @@
#endif //__INC_HAL8192SPHYREG_H

129
include/Hal8192DPhyCfg.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,18 +22,18 @@
* Module: __INC_HAL8192DPHYCFG_H
*
*
* Note:
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192DPHYCFG_H
@ -74,7 +74,7 @@
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
@ -115,7 +115,7 @@ typedef enum _RF_RADIO_PATH{
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define RF_PATH_MAX 2
@ -150,8 +150,8 @@ typedef enum _WIRELESS_MODE {
#if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1)
typedef enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0,
BaseBand_Config_AGC_TAB = 1,
BaseBand_Config_PHY_REG = 0,
BaseBand_Config_AGC_TAB = 1,
BaseBand_Config_AGC_TAB_2G = 2,
BaseBand_Config_AGC_TAB_5G = 3,
}BaseBand_Config_Type, *PBaseBand_Config_Type;
@ -166,7 +166,7 @@ typedef enum _BaseBand_Config_Type{
typedef enum _MACPHY_MODE_8192D{
SINGLEMAC_SINGLEPHY, //SMSP
DUALMAC_DUALPHY, //DMDP
DUALMAC_SINGLEPHY, //DMSP
DUALMAC_SINGLEPHY, //DMSP
}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
typedef enum _MACPHY_MODE_CHANGE_ACTION{
@ -180,7 +180,7 @@ typedef enum _MACPHY_MODE_CHANGE_ACTION{
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
typedef enum _BAND_TYPE{
BAND_ON_2_4G = 1,
BAND_ON_2_4G = 1,
BAND_ON_5G = 2,
BAND_ON_BOTH,
BANDMAX
@ -201,77 +201,77 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
@ -281,12 +281,12 @@ typedef struct _R_ANTENNA_SELECT_OFDM{
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
@ -329,7 +329,7 @@ extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
/* RF config */
int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_CONTENT Content,
@ -344,21 +344,21 @@ void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
VOID
PHY_ScanOperationBackup8192D(IN PADAPTER Adapter,
IN u8 Operation );
@ -396,7 +396,7 @@ void PHY_SwChnlPhy8192D( IN PADAPTER pAdapter,
extern void ChkFwCmdIoDone( IN PADAPTER Adapter);
//
// BB/MAC/RF other monitor API
//
@ -410,7 +410,7 @@ BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter,
//
// Modify the value of the hw register when beacon interval be changed.
//
void
void
rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
@ -428,7 +428,7 @@ PHY_EnableHostClkReq(
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
IN u8 DefaultAnt
);
VOID
@ -439,7 +439,7 @@ PHY_UpdateBBRFConfiguration8192D(
VOID PHY_ReadMacPhyMode92D(
IN PADAPTER Adapter,
IN BOOLEAN AutoloadFail
IN BOOLEAN AutoloadFail
);
VOID PHY_ConfigMacPhyMode92D(
@ -460,7 +460,7 @@ rtl8192d_PHY_InitRxSetting(
);
VOID
VOID
rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
VOID
@ -469,7 +469,7 @@ HalChangeCCKStatus8192D(
IN BOOLEAN bCCKDisable
);
VOID
VOID
PHY_InitPABias92D(IN PADAPTER Adapter);
/*--------------------------Exported Function prototype---------------------*/
@ -483,4 +483,3 @@ PHY_InitPABias92D(IN PADAPTER Adapter);
#define PHY_SetMacReg PHY_SetBBReg
#endif // __INC_HAL8192SPHYCFG_H

2309
include/Hal8192DPhyReg.h
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File diff suppressed because it is too large Load diff

59
include/Hal8723APhyCfg.h
View file

@ -1,30 +1,29 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723PHYCFG_H__
#define __INC_HAL8723PHYCFG_H__
#include <Hal8192CPhyCfg.h>
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A( IN PADAPTER Adapter );
int PHY_RFConfig8723A( IN PADAPTER Adapter );
s32 PHY_MACConfig8723A(PADAPTER padapter);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723PHYCFG_H__
#define __INC_HAL8723PHYCFG_H__
#include <Hal8192CPhyCfg.h>
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A( IN PADAPTER Adapter );
int PHY_RFConfig8723A( IN PADAPTER Adapter );
s32 PHY_MACConfig8723A(PADAPTER padapter);
#endif

147
include/Hal8723APhyReg.h
View file

@ -1,74 +1,73 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723APHYREG_H__
#define __INC_HAL8723APHYREG_H__
#include <Hal8192CPhyReg.h>
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723APHYREG_H__
#define __INC_HAL8723APHYREG_H__
#include <Hal8192CPhyReg.h>
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#endif

341
include/Hal8723PwrSeq.h
View file

@ -1,171 +1,170 @@
#ifndef __HAL8723PWRSEQ_H__
#define __HAL8723PWRSEQ_H__
/*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#include "HalPwrSeqCmd.h"
#include "rtl8723a_spec.h"
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8723A_TRANS_END_STEPS 1
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8723A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8723A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
#endif
#ifndef __HAL8723PWRSEQ_H__
#define __HAL8723PWRSEQ_H__
/*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#include "HalPwrSeqCmd.h"
#include "rtl8723a_spec.h"
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8723A_TRANS_END_STEPS 1
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8723A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8723A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
#endif

111
include/HalHWImg8188E_BB.h
View file

@ -1,56 +1,55 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* AGC_TAB_1T.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_AGC_TAB_1T_8188E(
IN PDM_ODM_T pDM_Odm
);
/******************************************************************************
* PHY_REG_1T.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_PHY_REG_1T_8188E(
IN PDM_ODM_T pDM_Odm
);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif // end of HWIMG_SUPPORT
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* AGC_TAB_1T.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_AGC_TAB_1T_8188E(
IN PDM_ODM_T pDM_Odm
);
/******************************************************************************
* PHY_REG_1T.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_PHY_REG_1T_8188E(
IN PDM_ODM_T pDM_Odm
);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif // end of HWIMG_SUPPORT

92
include/HalHWImg8188E_FW.h
View file

@ -1,46 +1,46 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_FW_8188E_HW_IMG_H
#define __INC_FW_8188E_HW_IMG_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
void
ODM_ReadFirmware_8188E_FW_AP(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#else
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
#define ArrayLength_8188E_FW_WoWLAN 15764
extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
#endif
#endif
#endif // end of HWIMG_SUPPORT
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_FW_8188E_HW_IMG_H
#define __INC_FW_8188E_HW_IMG_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
void
ODM_ReadFirmware_8188E_FW_AP(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#else
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
#define ArrayLength_8188E_FW_WoWLAN 15764
extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
#endif
#endif
#endif // end of HWIMG_SUPPORT

75
include/HalHWImg8188E_MAC.h
View file

@ -1,38 +1,37 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_MAC_REG_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif // end of HWIMG_SUPPORT
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_MAC_REG_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif // end of HWIMG_SUPPORT

75
include/HalHWImg8188E_RF.h
View file

@ -1,38 +1,37 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_RadioA_1T_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif // end of HWIMG_SUPPORT
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H
//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_RadioA_1T_8188E(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif // end of HWIMG_SUPPORT

27
include/HalPhyRf.h
View file

@ -17,40 +17,40 @@
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 //ms
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
//
// IQ calibrate
//
void
PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
IN BOOLEAN bReCovery);
void
PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
void
PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
//
// AP calibrate
//
void
void
PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
IN s1Byte delta);
IN s1Byte delta);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59
@ -58,13 +58,12 @@ PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
);
u1Byte
u1Byte
ODM_GetRightChnlPlaceforIQK(
IN u1Byte chnl
);
#endif // #ifndef __HAL_PHY_RF_H__

269
include/HalPhyRf_8188e.h
View file

@ -1,135 +1,134 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 //ms
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
VOID
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
);
VOID
odm_TXPowerTrackingCallback_ThermalMeter_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
#endif
);
//1 7. IQK
void
PHY_IQCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
//
// AP calibrate
//
void
PHY_APCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter);
VOID
_PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 //ms
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
VOID
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
);
VOID
odm_TXPowerTrackingCallback_ThermalMeter_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
#endif
);
//1 7. IQK
void
PHY_IQCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
//
// AP calibrate
//
void
PHY_APCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter);
VOID
_PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

275
include/HalPwrSeqCmd.h
View file

@ -1,138 +1,137 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include <drv_types.h>
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if ( (Read(offset) & msk) == (value & msk) )
// break;
// } while (not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================
// Prototype of protected function.
//================================================================================
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrCfgCmd[]);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include <drv_types.h>
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if ( (Read(offset) & msk) == (value & msk) )
// break;
// } while (not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================
// Prototype of protected function.
//================================================================================
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrCfgCmd[]);
#endif

57
include/HalVerDef.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -20,56 +20,56 @@
#ifndef __HAL_VERSION_DEF_H__
#define __HAL_VERSION_DEF_H__
#define TRUE _TRUE
#define TRUE _TRUE
#define FALSE _FALSE
// HAL_IC_TYPE_E
typedef enum tag_HAL_IC_Type_Definition
{
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
}HAL_IC_TYPE_E;
//HAL_CHIP_TYPE_E
typedef enum tag_HAL_CHIP_Type_Definition
{
TEST_CHIP = 0,
NORMAL_CHIP = 1,
TEST_CHIP = 0,
NORMAL_CHIP = 1,
FPGA = 2,
}HAL_CHIP_TYPE_E;
//HAL_CUT_VERSION_E
typedef enum tag_HAL_Cut_Version_Definition
{
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
}HAL_CUT_VERSION_E;
// HAL_Manufacturer
typedef enum tag_HAL_Manufacturer_Version_Definition
{
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
}HAL_VENDOR_E;
typedef enum tag_HAL_RF_Type_Definition
{
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_2T2R = 2,
RF_TYPE_2T3R = 3,
RF_TYPE_2T4R = 4,
@ -84,7 +84,7 @@ typedef struct tag_HAL_VERSION
HAL_CHIP_TYPE_E ChipType;
HAL_CUT_VERSION_E CUTVersion;
HAL_VENDOR_E VendorType;
HAL_RF_TYPE_E RFType;
HAL_RF_TYPE_E RFType;
u8 ROMVer;
}HAL_VERSION,*PHAL_VERSION;
@ -137,7 +137,7 @@ typedef struct tag_HAL_VERSION
//----------------------------------------------------------------------------
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
@ -153,4 +153,3 @@ typedef struct tag_HAL_VERSION
#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE)
#endif

151
include/autoconf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,24 +33,24 @@
#define RTL871X_MODULE_NAME "88EU"
#define DRV_NAME "rtl8188eu"
#define CONFIG_USB_HCI
#define CONFIG_USB_HCI
#define CONFIG_RTL8188E
#define CONFIG_RTL8188E
#define PLATFORM_LINUX
#define PLATFORM_LINUX
//#define CONFIG_IOCTL_CFG80211
//#define CONFIG_IOCTL_CFG80211
#if defined( CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
#ifndef CONFIG_IOCTL_CFG80211
#define CONFIG_IOCTL_CFG80211
#ifndef CONFIG_IOCTL_CFG80211
#define CONFIG_IOCTL_CFG80211
#endif
#endif
#ifdef CONFIG_IOCTL_CFG80211
//#define RTW_USE_CFG80211_STA_EVENT /* Opne this for Android 4.1's wpa_supplicant */
#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
//#define CONFIG_DEBUG_CFG80211
//#define CONFIG_DEBUG_CFG80211
//#define CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2
#define CONFIG_SET_SCAN_DENY_TIMER
@ -62,38 +62,38 @@
//#define CONFIG_H2CLBK
#define CONFIG_EMBEDDED_FWIMG
#define CONFIG_EMBEDDED_FWIMG
//#define CONFIG_FILE_FWIMG
#define CONFIG_XMIT_ACK
#ifdef CONFIG_XMIT_ACK
#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
#endif
#define CONFIG_80211N_HT
#define CONFIG_80211N_HT
#define CONFIG_RECV_REORDERING_CTRL
#define CONFIG_RECV_REORDERING_CTRL
//#define CONFIG_TCP_CSUM_OFFLOAD_RX
//#define CONFIG_TCP_CSUM_OFFLOAD_RX
//#define CONFIG_DRVEXT_MODULE
//#define CONFIG_DRVEXT_MODULE
#define CONFIG_SUPPORT_USB_INT
#ifdef CONFIG_SUPPORT_USB_INT
//#define CONFIG_USB_INTERRUPT_IN_PIPE
//#define CONFIG_USB_INTERRUPT_IN_PIPE
#endif
//#ifndef CONFIG_MP_INCLUDED
#define CONFIG_IPS
#define CONFIG_IPS
#ifdef CONFIG_IPS
//#define CONFIG_IPS_LEVEL_2 //enable this to set default IPS mode to IPS_LEVEL_2
#endif
#define SUPPORT_HW_RFOFF_DETECTED
#define SUPPORT_HW_RFOFF_DETECTED
#define CONFIG_LPS
#define CONFIG_LPS
#if defined(CONFIG_LPS) && defined(CONFIG_SUPPORT_USB_INT)
//#define CONFIG_LPS_LCLK
//#define CONFIG_LPS_LCLK
#endif
#ifdef CONFIG_LPS_LCLK
@ -104,23 +104,23 @@
#define CONFIG_ANTENNA_DIVERSITY
//after link
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#endif
//#define CONFIG_CONCURRENT_MODE
//#define CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
//#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#endif
#define CONFIG_IOL
//#else //#ifndef CONFIG_MP_INCLUDED
//#endif //#ifndef CONFIG_MP_INCLUDED
//#else //#ifndef CONFIG_MP_INCLUDED
#define CONFIG_AP_MODE
//#endif //#ifndef CONFIG_MP_INCLUDED
#define CONFIG_AP_MODE
#ifdef CONFIG_AP_MODE
//#define CONFIG_INTERRUPT_BASED_TXBCN // Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs
#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN)
@ -128,22 +128,22 @@
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
//#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#endif
#define CONFIG_NATIVEAP_MLME
#ifndef CONFIG_NATIVEAP_MLME
#define CONFIG_HOSTAPD_MLME
#endif
#define CONFIG_FIND_BEST_CHANNEL
//#define CONFIG_NO_WIRELESS_HANDLERS
#define CONFIG_HOSTAPD_MLME
#endif
#define CONFIG_FIND_BEST_CHANNEL
//#define CONFIG_NO_WIRELESS_HANDLERS
#endif
#define CONFIG_P2P
#define CONFIG_P2P
#ifdef CONFIG_P2P
//The CONFIG_WFD is for supporting the Wi-Fi display
//#define CONFIG_WFD
//#define CONFIG_WFD
#ifndef CONFIG_WIFI_TEST
#define CONFIG_P2P_REMOVE_GROUP_INFO
#endif
@ -154,13 +154,13 @@
#endif
// Added by Kurt 20110511
//#define CONFIG_TDLS
//#define CONFIG_TDLS
#ifdef CONFIG_TDLS
// #ifndef CONFIG_WFD
// #define CONFIG_WFD
// #define CONFIG_WFD
// #endif
// #define CONFIG_TDLS_AUTOSETUP
// #define CONFIG_TDLS_AUTOCHECKALIVE
// #define CONFIG_TDLS_AUTOSETUP
// #define CONFIG_TDLS_AUTOCHECKALIVE
#endif
@ -179,9 +179,9 @@
#define CONFIG_IOL_READ_EFUSE_MAP
//#define DBG_IOL_READ_EFUSE_MAP
#define CONFIG_IOL_LLT
#define CONFIG_IOL_EFUSE_PATCH
#define CONFIG_IOL_EFUSE_PATCH
#define CONFIG_IOL_IOREG_CFG
//#define CONFIG_IOL_IOREG_CFG_DBG
//#define CONFIG_IOL_IOREG_CFG_DBG
#endif
@ -204,35 +204,35 @@
#endif // CONFIG_BR_EXT
#define CONFIG_TX_MCAST2UNI // Support IP multicast->unicast
//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs.
//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs.
/*
* Interface Related Config
/*
* Interface Related Config
*/
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#define CONFIG_USB_TX_AGGREGATION
#define CONFIG_USB_RX_AGGREGATION
#define CONFIG_USB_TX_AGGREGATION
#define CONFIG_USB_RX_AGGREGATION
#endif
#define CONFIG_PREALLOC_RECV_SKB
#define CONFIG_PREALLOC_RECV_SKB
//#define CONFIG_REDUCE_USB_TX_INT // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms.
//#define CONFIG_EASY_REPLACEMENT
//#define CONFIG_EASY_REPLACEMENT
/*
/*
* CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now!
*/
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
#ifdef CONFIG_PLATFORM_ARM_SUNxI
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
#define CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif
#endif
/*
/*
* USB VENDOR REQ BUFFER ALLOCATION METHOD
* if not set we'll use function local variable (stack memory)
*/
@ -242,7 +242,7 @@
#define CONFIG_USB_VENDOR_REQ_MUTEX
#define CONFIG_VENDOR_REQ_RETRY
//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
/*
@ -261,7 +261,7 @@
#define ENABLE_USB_DROP_INCORRECT_OUT 0
//#define RTL8192CU_ADHOC_WORKAROUND_SETTING
//#define RTL8192CU_ADHOC_WORKAROUND_SETTING
#define DISABLE_BB_RF 0
@ -269,7 +269,7 @@
#ifdef CONFIG_MP_INCLUDED
#define MP_DRIVER 1
#define CONFIG_MP_IWPRIV_SUPPORT
#define CONFIG_MP_IWPRIV_SUPPORT
//#undef CONFIG_USB_TX_AGGREGATION
//#undef CONFIG_USB_RX_AGGREGATION
#else
@ -282,8 +282,8 @@
*/
#ifdef CONFIG_PLATFORM_MN10300
#define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#if defined (CONFIG_SW_ANTENNA_DIVERSITY)
#undef CONFIG_SW_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
@ -292,18 +292,18 @@
#if defined (CONFIG_POWER_SAVING)
#undef CONFIG_POWER_SAVING
#endif
#endif//CONFIG_PLATFORM_MN10300
#ifdef CONFIG_PLATFORM_TI_DM365
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif
#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
#ifdef CONFIG_USB_TX_AGGREGATION
#ifdef CONFIG_USB_TX_AGGREGATION
#undef CONFIG_USB_TX_AGGREGATION
#endif
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
@ -319,20 +319,20 @@
* Outsource Related Config
*/
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8188EE_SUPPORT 0
#define RTL8188EU_SUPPORT 1
@ -340,13 +340,13 @@
#define RTL8188E_SUPPORT (RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT)
#define RTL8188E_FOR_TEST_CHIP 0
//#if (RTL8188E_SUPPORT==1)
#define RATE_ADAPTIVE_SUPPORT 1
#define RATE_ADAPTIVE_SUPPORT 1
#define POWER_TRAINING_ACTIVE 1
//#endif
#ifdef CONFIG_USB_TX_AGGREGATION
//#define CONFIG_TX_EARLY_MODE
//#define CONFIG_TX_EARLY_MODE
#endif
#ifdef CONFIG_TX_EARLY_MODE
@ -391,10 +391,9 @@
//#define DBG_HAL_INIT_PROFILING
//#define DBG_MEMORY_LEAK
//#define DBG_MEMORY_LEAK
//TX use 1 urb
//#define CONFIG_SINGLE_XMIT_BUF
//RX use 1 urb
//#define CONFIG_SINGLE_RECV_BUF

59
include/basic_types.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -29,13 +29,13 @@
#ifndef TRUE
#define _TRUE 1
#else
#define _TRUE TRUE
#define _TRUE TRUE
#endif
#ifndef FALSE
#ifndef FALSE
#define _FALSE 0
#else
#define _FALSE FALSE
#define _FALSE FALSE
#endif
#ifdef PLATFORM_WINDOWS
@ -48,7 +48,7 @@
typedef signed long s32;
typedef unsigned long u32;
typedef unsigned int uint;
typedef signed int sint;
@ -57,7 +57,7 @@
typedef unsigned long long u64;
#ifdef NDIS50_MINIPORT
#define NDIS_MAJOR_VERSION 5
#define NDIS_MINOR_VERSION 0
@ -96,14 +96,14 @@
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#define ULONG u32
typedef void (*proc_t)(void*);
typedef __kernel_size_t SIZE_T;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#endif
@ -117,7 +117,7 @@
typedef signed int s32;
typedef unsigned int u32;
typedef unsigned int uint;
typedef signed int sint;
typedef long atomic_t;
@ -129,7 +129,7 @@
#define VOID void
#define NDIS_OID uint
#define NDIS_STATUS uint
#ifndef PVOID
typedef void * PVOID;
//#define PVOID (void *)
@ -138,17 +138,17 @@
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#define ULONG u32
typedef void (*proc_t)(void*);
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef __kernel_size_t SIZE_T;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#endif
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
@ -170,8 +170,8 @@
//
// Byte Swapping routine.
//
#define EF1Byte
#define EF2Byte le16_to_cpu
#define EF1Byte
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
@ -186,7 +186,7 @@
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
//
// Example:
@ -203,7 +203,7 @@
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
//
// Description:
@ -227,7 +227,7 @@
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
@ -239,7 +239,7 @@
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
@ -249,23 +249,23 @@
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
@ -280,7 +280,7 @@
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
@ -335,4 +335,3 @@
typedef unsigned char BOOLEAN,*PBOOLEAN;
#endif //__BASIC_TYPES_H__

3
include/circ_buf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -25,4 +25,3 @@
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
#endif //_CIRC_BUF_H_

3
include/cmd_osdep.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,4 +33,3 @@ extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj);
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
#endif

4
include/drv_conf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -67,7 +67,7 @@
#endif
//About USB VENDOR REQ
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif

21
include/drv_types.h
View file

@ -128,7 +128,7 @@ struct registry_priv
u8 network_mode; //infra, ad-hoc, auto
u8 channel;//ad-hoc support requirement
u8 wireless_mode;//A, B, G, auto
u8 scan_mode;//active, passive
u8 scan_mode;//active, passive
u8 radio_enable;
u8 preamble;//long, short, auto
u8 vrtl_carrier_sense;//Enable, Disable, Auto
@ -166,7 +166,7 @@ struct registry_priv
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;//for tx
u8 rx_stbc;
u8 rx_stbc;
u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted
#endif
u8 lowrate_two_xmit;
@ -353,10 +353,10 @@ struct dvobj_priv
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
// pci-e bridge */
u8 const_hostpci_aspm_setting;
u8 const_hostpci_aspm_setting;
// pci-e device */
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_backdoor;
u8 bdma64;
#endif//PLATFORM_LINUX
@ -453,7 +453,7 @@ struct _ADAPTER{
int DriverState;// for disable driver using module, use dongle to replace module.
int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd
int bDongle;//build-in module or external dongle
u16 chip_type;
u16 chip_type;
u16 HardwareType;
u16 interface_type;//USB,SDIO,SPI,PCI
@ -463,20 +463,20 @@ struct _ADAPTER{
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
//struct io_queue *pio_queue;
struct io_priv iopriv;
struct io_priv iopriv;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
struct registry_priv registrypriv;
struct pwrctrl_priv pwrctrlpriv;
struct eeprom_priv eeprompriv;
struct eeprom_priv eeprompriv;
struct led_priv ledpriv;
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
//Check BT status for BT Hung.
struct workqueue_struct *priv_checkbt_wq;
struct delayed_work checkbt_work;
#endif
#endif
#ifdef CONFIG_MP_INCLUDED
struct mp_priv mppriv;
#endif
@ -663,4 +663,3 @@ __inline static u8 *myid(struct eeprom_priv *peepriv)
#endif //__DRV_TYPES_H__

7
include/drv_types_ce.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -49,7 +49,7 @@ typedef struct _MP_REG_ENTRY
u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
uint FieldOffset; // offset to MP_ADAPTER field
uint FieldSize; // size (in bytes) of the field
#ifdef UNDER_AMD64
u64 Default;
#else
@ -64,7 +64,7 @@ typedef struct _MP_REG_ENTRY
typedef struct _USB_EXTENSION {
LPCUSB_FUNCS _lpUsbFuncs;
USB_HANDLE _hDevice;
PVOID pAdapter;
PVOID pAdapter;
} USB_EXTENSION, *PUSB_EXTENSION;
#endif
@ -79,4 +79,3 @@ typedef struct _OCTET_STRING{
#endif

97
include/drv_types_gspi.h
View file

@ -1,49 +1,48 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_GSPI_H__
#define __DRV_TYPES_GSPI_H__
#include <drv_conf.h>
#include <basic_types.h>
// SPI Header Files
#ifdef PLATFORM_LINUX
#include <linux/spi/spi.h>
#endif
typedef struct gspi_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct spi_device *func;
struct workqueue_struct *priv_wq;
struct delayed_work irq_work;
#endif
} GSPI_DATA, *PGSPI_DATA;
#endif // #ifndef __DRV_TYPES_GSPI_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_GSPI_H__
#define __DRV_TYPES_GSPI_H__
#include <drv_conf.h>
#include <basic_types.h>
// SPI Header Files
#ifdef PLATFORM_LINUX
#include <linux/spi/spi.h>
#endif
typedef struct gspi_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct spi_device *func;
struct workqueue_struct *priv_wq;
struct delayed_work irq_work;
#endif
} GSPI_DATA, *PGSPI_DATA;
#endif // #ifndef __DRV_TYPES_GSPI_H__

3
include/drv_types_linux.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,4 +22,3 @@
#endif

141
include/drv_types_sdio.h
View file

@ -1,71 +1,70 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_SDIO_H__
#define __DRV_TYPES_SDIO_H__
#include <drv_conf.h>
#include <basic_types.h>
// SDIO Header Files
#ifdef PLATFORM_LINUX
#include <linux/mmc/sdio_func.h>
#endif
#ifdef PLATFORM_OS_XP
#include <wdm.h>
#include <ntddsd.h>
#endif
#ifdef PLATFORM_OS_CE
#include <sdcardddk.h>
#endif
typedef struct sdio_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct sdio_func *func;
_thread_hdl_ sys_sdio_irq_thd;
#endif
#ifdef PLATFORM_OS_XP
PDEVICE_OBJECT pphysdevobj;
PDEVICE_OBJECT pfuncdevobj;
PDEVICE_OBJECT pnextdevobj;
SDBUS_INTERFACE_STANDARD sdbusinft;
u8 nextdevstacksz;
#endif
#ifdef PLATFORM_OS_CE
SD_DEVICE_HANDLE hDevice;
SD_CARD_RCA sd_rca;
SD_CARD_INTERFACE card_intf;
BOOLEAN enableIsarWithStatus;
WCHAR active_path[MAX_ACTIVE_REG_PATH];
SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap;
#endif
} SDIO_DATA, *PSDIO_DATA;
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_SDIO_H__
#define __DRV_TYPES_SDIO_H__
#include <drv_conf.h>
#include <basic_types.h>
// SDIO Header Files
#ifdef PLATFORM_LINUX
#include <linux/mmc/sdio_func.h>
#endif
#ifdef PLATFORM_OS_XP
#include <wdm.h>
#include <ntddsd.h>
#endif
#ifdef PLATFORM_OS_CE
#include <sdcardddk.h>
#endif
typedef struct sdio_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct sdio_func *func;
_thread_hdl_ sys_sdio_irq_thd;
#endif
#ifdef PLATFORM_OS_XP
PDEVICE_OBJECT pphysdevobj;
PDEVICE_OBJECT pfuncdevobj;
PDEVICE_OBJECT pnextdevobj;
SDBUS_INTERFACE_STANDARD sdbusinft;
u8 nextdevstacksz;
#endif
#ifdef PLATFORM_OS_CE
SD_DEVICE_HANDLE hDevice;
SD_CARD_RCA sd_rca;
SD_CARD_INTERFACE card_intf;
BOOLEAN enableIsarWithStatus;
WCHAR active_path[MAX_ACTIVE_REG_PATH];
SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap;
#endif
} SDIO_DATA, *PSDIO_DATA;
#endif

5
include/drv_types_xp.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -70,7 +70,7 @@ typedef struct _MP_REG_ENTRY
u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
uint FieldOffset; // offset to MP_ADAPTER field
uint FieldSize; // size (in bytes) of the field
#ifdef UNDER_AMD64
u64 Default;
#else
@ -92,4 +92,3 @@ typedef struct _OCTET_STRING{
#endif

7
include/ethernet.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -17,7 +17,7 @@
*
*
******************************************************************************/
/*! \file */
/*! \file */
#ifndef __INC_ETHERNET_H
#define __INC_ETHERNET_H
@ -30,7 +30,7 @@
#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address?
#define RT_ETH_IS_BROADCAST(_pAddr) ( \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[1]==0xff && \
((UCHAR *)(_pAddr))[2]==0xff && \
((UCHAR *)(_pAddr))[3]==0xff && \
@ -39,4 +39,3 @@
#endif // #ifndef __INC_ETHERNET_H

3
include/h2clbk.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,4 +33,3 @@ void _lbk_rsp(PADAPTER Adapter);
void _lbk_evt(IN PADAPTER Adapter);
void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);

17
include/hal_com.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -28,7 +28,7 @@
#define RATR_2M 0x00000002
#define RATR_55M 0x00000004
#define RATR_11M 0x00000008
//OFDM
//OFDM
#define RATR_6M 0x00000010
#define RATR_9M 0x00000020
#define RATR_12M 0x00000040
@ -37,7 +37,7 @@
#define RATR_36M 0x00000200
#define RATR_48M 0x00000400
#define RATR_54M 0x00000800
//MCS 1 Spatial Stream
//MCS 1 Spatial Stream
#define RATR_MCS0 0x00001000
#define RATR_MCS1 0x00002000
#define RATR_MCS2 0x00004000
@ -61,7 +61,7 @@
#define RATE_2M BIT(1)
#define RATE_5_5M BIT(2)
#define RATE_11M BIT(3)
//OFDM
//OFDM
#define RATE_6M BIT(4)
#define RATE_9M BIT(5)
#define RATE_12M BIT(6)
@ -90,15 +90,15 @@
#define RATE_MCS15 BIT(27)
// ALL CCK Rate
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
RATR_36M|RATR_48M|RATR_54M
RATR_36M|RATR_48M|RATR_54M
#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
/*------------------------------ Tx Desc definition Macro ------------------------*/
/*------------------------------ Tx Desc definition Macro ------------------------*/
//#pragma mark -- Tx Desc related definition. --
//----------------------------------------------------------------------------
//-----------------------------------------------------------
@ -179,4 +179,3 @@ void c2h_evt_clear(_adapter *adapter);
s32 c2h_evt_read(_adapter *adapter, u8 *buf);
#endif //__HAL_COMMON_H__

41
include/hal_intf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -31,8 +31,8 @@
enum RTL871X_HCI_TYPE {
RTW_PCIE = BIT0,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_GSPI = BIT3,
};
@ -43,7 +43,7 @@ enum _CHIP_TYPE {
RTL8188C_8192C,
RTL8192D,
RTL8723A,
RTL8188E,
RTL8188E,
MAX_CHIP_TYPE
};
@ -98,7 +98,7 @@ typedef enum _HW_VARIABLES{
HW_VAR_INITIAL_GAIN,
HW_VAR_TRIGGER_GPIO_0,
HW_VAR_BT_SET_COEXIST,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_CURRENT_ANTENNA,
HW_VAR_ANTENNA_DIVERSITY_LINK,
HW_VAR_ANTENNA_DIVERSITY_SELECT,
@ -117,7 +117,7 @@ typedef enum _HW_VARIABLES{
#endif
HW_VAR_NAV_UPPER,
HW_VAR_RPT_TIMER_SETTING,
HW_VAR_TX_RPT_MAX_MACID,
HW_VAR_TX_RPT_MAX_MACID,
HW_VAR_H2C_MEDIA_STATUS_RPT,
HW_VAR_CHK_HI_QUEUE_EMPTY,
}HW_VARIABLES;
@ -142,7 +142,7 @@ typedef enum _HAL_DEF_VARIABLE{
}HAL_DEF_VARIABLE;
typedef enum _HAL_ODM_VARIABLE{
HAL_ODM_STA_INFO,
HAL_ODM_STA_INFO,
HAL_ODM_P2P_STATE,
HAL_ODM_WIFI_DISPLAY_STATE,
}HAL_ODM_VARIABLE;
@ -205,7 +205,7 @@ struct hal_ops {
void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
void (*Add_RateATid)(_adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level);
#ifdef CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
void (*clone_haldata)(_adapter *dst_padapter, _adapter *src_padapter);
#endif
void (*run_thread)(_adapter *padapter);
@ -233,14 +233,14 @@ struct hal_ops {
void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
u16 (*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
u8 (*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
BOOLEAN (*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
#ifdef DBG_CONFIG_ERROR_DETECT
void (*sreset_init_value)(_adapter *padapter);
void (*sreset_reset_value)(_adapter *padapter);
void (*sreset_reset_value)(_adapter *padapter);
void (*silentreset)(_adapter *padapter);
void (*sreset_xmit_status_check)(_adapter *padapter);
void (*sreset_linked_status_check) (_adapter *padapter);
@ -262,8 +262,8 @@ struct hal_ops {
void (*hal_init_checkbthang_workqueue)(_adapter * padapter);
void (*hal_free_checkbthang_workqueue)(_adapter * padapter);
void (*hal_cancel_checkbthang_workqueue)(_adapter * padapter);
void (*hal_checke_bt_hang)(_adapter * padapter);
#endif
void (*hal_checke_bt_hang)(_adapter * padapter);
#endif
};
typedef enum _RT_EEPROM_TYPE{
@ -275,10 +275,10 @@ typedef enum _RT_EEPROM_TYPE{
#define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
typedef enum _HARDWARE_TYPE{
HARDWARE_TYPE_RTL8180,
@ -400,7 +400,7 @@ u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pVa
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
void rtw_hal_enable_interrupt(_adapter *padapter);
void rtw_hal_disable_interrupt(_adapter *padapter);
@ -448,7 +448,7 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#ifdef DBG_CONFIG_ERROR_DETECT
void rtw_hal_sreset_init(_adapter *padapter);
void rtw_hal_sreset_reset(_adapter *padapter);
void rtw_hal_sreset_reset(_adapter *padapter);
void rtw_hal_sreset_reset_value(_adapter *padapter);
void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
void rtw_hal_sreset_linked_status_check (_adapter *padapter);
@ -470,4 +470,3 @@ s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter);
#endif //__HAL_INTF_H__

55
include/ieee80211.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -35,7 +35,7 @@
#include <linux/wireless.h>
#endif
#else
#include <list.h>
#endif
@ -127,11 +127,11 @@ enum {
#define IEEE_CRYPT_ALG_NAME_LEN 16
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_WEP104 BIT(2)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
@ -183,8 +183,8 @@ enum NETWORK_TYPE
WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only
WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck
WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only
//WIRELESS_AUTO = BIT(5),
WIRELESS_AC = BIT(6),
//WIRELESS_AUTO = BIT(5),
WIRELESS_AC = BIT(6),
//Combination
WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm
@ -210,7 +210,7 @@ enum NETWORK_TYPE
#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)
#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE)
#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE)
#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE)
typedef struct ieee_param {
@ -228,7 +228,7 @@ typedef struct ieee_param {
} wpa_ie;
struct{
int command;
int reason_code;
int reason_code;
} mlme;
struct {
u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
@ -244,7 +244,7 @@ typedef struct ieee_param {
u16 aid;
u16 capability;
int flags;
u8 tx_supp_rates[16];
u8 tx_supp_rates[16];
struct rtw_ieee80211_ht_cap ht_cap;
} add_sta;
struct {
@ -253,7 +253,7 @@ typedef struct ieee_param {
} bcn_ie;
#endif
} u;
} u;
}ieee_param;
#ifdef CONFIG_AP_MODE
@ -268,7 +268,7 @@ struct sta_data{
u16 capability;
int flags;
u32 sta_set;
u8 tx_supp_rates[16];
u8 tx_supp_rates[16];
u32 tx_supp_rates_len;
struct rtw_ieee80211_ht_cap ht_cap;
u64 rx_pkts;
@ -315,7 +315,7 @@ struct ieee_ibss_seq {
_list list;
};
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)||defined(PLATFORM_FREEBSD)
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)||defined(PLATFORM_FREEBSD)
struct rtw_ieee80211_hdr {
u16 frame_ctl;
@ -452,7 +452,7 @@ enum eap_type {
/* management */
#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020
#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030
#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040
@ -665,7 +665,7 @@ struct ieee80211_snap_hdr {
#define IEEE80211_24GHZ_BAND (1<<0)
#define IEEE80211_52GHZ_BAND (1<<1)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_NUM_OFDM_RATESLEN 8
@ -673,7 +673,7 @@ struct ieee80211_snap_hdr {
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
@ -1101,7 +1101,7 @@ enum ieee80211_state {
/* the card is not linked at all */
IEEE80211_NOLINK = 0,
/* IEEE80211_ASSOCIATING* are for BSS client mode
* the driver shall not perform RX filtering unless
* the state is LINKED.
@ -1109,31 +1109,31 @@ enum ieee80211_state {
* defaults to NOLINK for ALL the other states (including
* LINKED_SCANNING)
*/
/* the association procedure will start (wq scheduling)*/
IEEE80211_ASSOCIATING,
IEEE80211_ASSOCIATING_RETRY,
/* the association procedure is sending AUTH request*/
IEEE80211_ASSOCIATING_AUTHENTICATING,
/* the association procedure has successfully authentcated
* and is sending association request
*/
IEEE80211_ASSOCIATING_AUTHENTICATED,
/* the link is ok. the card associated to a BSS or linked
* to a ibss cell or acting as an AP and creating the bss
*/
IEEE80211_LINKED,
/* same as LINKED, but the driver shall apply RX filter
* rules as we are in NO_LINK mode. As the card is still
* logically linked, but it is doing a syncro site survey
* then it will be back to LINKED state.
*/
IEEE80211_LINKED_SCANNING,
};
#endif //PLATFORM_FREEBSD
@ -1325,7 +1325,7 @@ enum rtw_ieee80211_back_parties {
RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
};
#define RTW_IEEE80211_CHAN_NO_HT40 \
(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
@ -1342,7 +1342,7 @@ struct rtw_ieee80211_channel {
//u32 orig_flags;
//int orig_mag;
//int orig_mpwr;
};
};
#define CHAN_FMT \
/*"band:%d, "*/ \
@ -1355,7 +1355,7 @@ struct rtw_ieee80211_channel {
/*"beacon_found:%u\n"*/ \
/*"orig_flags:0x%08x\n"*/ \
/*"orig_mag:%d\n"*/ \
/*"orig_mpwr:%d\n"*/
/*"orig_mpwr:%d\n"*/
#define CHAN_ARG(channel) \
/*(channel)->band*/ \
@ -1511,4 +1511,3 @@ int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *act
const char *action_public_str(u8 action);
#endif /* IEEE80211_H */

813
include/ieee80211_ext.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,409 +16,408 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IEEE80211_EXT_H
#define __IEEE80211_EXT_H
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define WMM_OUI_TYPE 2
#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WMM_VERSION 1
#define WPA_PROTO_WPA BIT(0)
#define WPA_PROTO_RSN BIT(1)
#define WPA_KEY_MGMT_IEEE8021X BIT(0)
#define WPA_KEY_MGMT_PSK BIT(1)
#define WPA_KEY_MGMT_NONE BIT(2)
#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
#define WPA_KEY_MGMT_WPA_NONE BIT(4)
#define WPA_CAPABILITY_PREAUTH BIT(0)
#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
#define PMKID_LEN 16
#ifdef PLATFORM_LINUX
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct wme_ac_parameter {
#if defined(__LITTLE_ENDIAN)
/* byte 1 */
u8 aifsn:4,
acm:1,
aci:2,
reserved:1;
/* byte 2 */
u8 eCWmin:4,
eCWmax:4;
#elif defined(__BIG_ENDIAN)
/* byte 1 */
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
/* byte 2 */
u8 eCWmax:4,
eCWmin:4;
#else
#error "Please fix <endian.h>"
#endif
/* bytes 3 & 4 */
u16 txopLimit;
} __attribute__ ((packed));
struct wme_parameter_element {
/* required fields for WME version 1 */
u8 oui[3];
u8 oui_type;
u8 oui_subtype;
u8 version;
u8 acInfo;
u8 reserved;
struct wme_ac_parameter ac[4];
} __attribute__ ((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
};
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
};
#pragma pack()
#endif
#define WPA_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define WPA_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define WPA_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val))
/* Action category code */
enum ieee80211_category {
WLAN_CATEGORY_SPECTRUM_MGMT = 0,
WLAN_CATEGORY_QOS = 1,
WLAN_CATEGORY_DLS = 2,
WLAN_CATEGORY_BACK = 3,
WLAN_CATEGORY_HT = 7,
WLAN_CATEGORY_WMM = 17,
};
/* SPECTRUM_MGMT action code */
enum ieee80211_spectrum_mgmt_actioncode {
WLAN_ACTION_SPCT_MSR_REQ = 0,
WLAN_ACTION_SPCT_MSR_RPRT = 1,
WLAN_ACTION_SPCT_TPC_REQ = 2,
WLAN_ACTION_SPCT_TPC_RPRT = 3,
WLAN_ACTION_SPCT_CHL_SWITCH = 4,
WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
};
/* BACK action code */
enum ieee80211_back_actioncode {
WLAN_ACTION_ADDBA_REQ = 0,
WLAN_ACTION_ADDBA_RESP = 1,
WLAN_ACTION_DELBA = 2,
};
/* HT features action code */
enum ieee80211_ht_actioncode {
WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
WLAN_ACTION_SM_PS = 1,
WLAN_ACTION_PSPM = 2,
WLAN_ACTION_PCO_PHASE = 3,
WLAN_ACTION_MIMO_CSI_MX = 4,
WLAN_ACTION_MIMO_NONCP_BF = 5,
WLAN_ACTION_MIMP_CP_BF = 6,
WLAN_ACTION_ASEL_INDICATES_FB = 7,
WLAN_ACTION_HI_INFO_EXCHG = 8,
};
/* BACK (block-ack) parties */
enum ieee80211_back_parties {
WLAN_BACK_RECIPIENT = 0,
WLAN_BACK_INITIATOR = 1,
WLAN_BACK_TIMER = 2,
};
#ifdef PLATFORM_LINUX
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} __attribute__ ((packed)) auth;
struct {
u16 reason_code;
} __attribute__ ((packed)) deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) reassoc_req;
struct {
u16 reason_code;
} __attribute__ ((packed)) disassoc;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} __attribute__ ((packed)) beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} __attribute__ ((packed)) probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} __attribute__ ((packed)) probe_resp;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} __attribute__ ((packed)) addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} __attribute__ ((packed)) addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} __attribute__ ((packed)) delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __attribute__ ((packed)) plink_action;
struct{
u8 action_code;
u8 variable[0];
} __attribute__ ((packed)) mesh_action;
} __attribute__ ((packed)) u;
} __attribute__ ((packed)) action;
} __attribute__ ((packed)) u;
}__attribute__ ((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} auth;
struct {
u16 reason_code;
} deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} reassoc_req;
struct {
u16 reason_code;
} disassoc;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} wme_action;
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} plink_action;
struct{
u8 action_code;
u8 variable[0];
} mesh_action;
} u;
} action;
} u;
} ;
#pragma pack()
#endif
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
#endif
******************************************************************************/
#ifndef __IEEE80211_EXT_H
#define __IEEE80211_EXT_H
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define WMM_OUI_TYPE 2
#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WMM_VERSION 1
#define WPA_PROTO_WPA BIT(0)
#define WPA_PROTO_RSN BIT(1)
#define WPA_KEY_MGMT_IEEE8021X BIT(0)
#define WPA_KEY_MGMT_PSK BIT(1)
#define WPA_KEY_MGMT_NONE BIT(2)
#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
#define WPA_KEY_MGMT_WPA_NONE BIT(4)
#define WPA_CAPABILITY_PREAUTH BIT(0)
#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
#define PMKID_LEN 16
#ifdef PLATFORM_LINUX
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct wme_ac_parameter {
#if defined(__LITTLE_ENDIAN)
/* byte 1 */
u8 aifsn:4,
acm:1,
aci:2,
reserved:1;
/* byte 2 */
u8 eCWmin:4,
eCWmax:4;
#elif defined(__BIG_ENDIAN)
/* byte 1 */
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
/* byte 2 */
u8 eCWmax:4,
eCWmin:4;
#else
#error "Please fix <endian.h>"
#endif
/* bytes 3 & 4 */
u16 txopLimit;
} __attribute__ ((packed));
struct wme_parameter_element {
/* required fields for WME version 1 */
u8 oui[3];
u8 oui_type;
u8 oui_subtype;
u8 version;
u8 acInfo;
u8 reserved;
struct wme_ac_parameter ac[4];
} __attribute__ ((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
};
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
};
#pragma pack()
#endif
#define WPA_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define WPA_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define WPA_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val))
/* Action category code */
enum ieee80211_category {
WLAN_CATEGORY_SPECTRUM_MGMT = 0,
WLAN_CATEGORY_QOS = 1,
WLAN_CATEGORY_DLS = 2,
WLAN_CATEGORY_BACK = 3,
WLAN_CATEGORY_HT = 7,
WLAN_CATEGORY_WMM = 17,
};
/* SPECTRUM_MGMT action code */
enum ieee80211_spectrum_mgmt_actioncode {
WLAN_ACTION_SPCT_MSR_REQ = 0,
WLAN_ACTION_SPCT_MSR_RPRT = 1,
WLAN_ACTION_SPCT_TPC_REQ = 2,
WLAN_ACTION_SPCT_TPC_RPRT = 3,
WLAN_ACTION_SPCT_CHL_SWITCH = 4,
WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
};
/* BACK action code */
enum ieee80211_back_actioncode {
WLAN_ACTION_ADDBA_REQ = 0,
WLAN_ACTION_ADDBA_RESP = 1,
WLAN_ACTION_DELBA = 2,
};
/* HT features action code */
enum ieee80211_ht_actioncode {
WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
WLAN_ACTION_SM_PS = 1,
WLAN_ACTION_PSPM = 2,
WLAN_ACTION_PCO_PHASE = 3,
WLAN_ACTION_MIMO_CSI_MX = 4,
WLAN_ACTION_MIMO_NONCP_BF = 5,
WLAN_ACTION_MIMP_CP_BF = 6,
WLAN_ACTION_ASEL_INDICATES_FB = 7,
WLAN_ACTION_HI_INFO_EXCHG = 8,
};
/* BACK (block-ack) parties */
enum ieee80211_back_parties {
WLAN_BACK_RECIPIENT = 0,
WLAN_BACK_INITIATOR = 1,
WLAN_BACK_TIMER = 2,
};
#ifdef PLATFORM_LINUX
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} __attribute__ ((packed)) auth;
struct {
u16 reason_code;
} __attribute__ ((packed)) deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) reassoc_req;
struct {
u16 reason_code;
} __attribute__ ((packed)) disassoc;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} __attribute__ ((packed)) beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} __attribute__ ((packed)) probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} __attribute__ ((packed)) probe_resp;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} __attribute__ ((packed)) addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} __attribute__ ((packed)) addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} __attribute__ ((packed)) delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __attribute__ ((packed)) plink_action;
struct{
u8 action_code;
u8 variable[0];
} __attribute__ ((packed)) mesh_action;
} __attribute__ ((packed)) u;
} __attribute__ ((packed)) action;
} __attribute__ ((packed)) u;
}__attribute__ ((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} auth;
struct {
u16 reason_code;
} deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} reassoc_req;
struct {
u16 reason_code;
} disassoc;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} wme_action;
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} plink_action;
struct{
u8 action_code;
u8 variable[0];
} mesh_action;
} u;
} action;
} u;
} ;
#pragma pack()
#endif
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
#endif

19
include/if_ether.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -17,13 +17,13 @@
*
*
******************************************************************************/
#ifndef _LINUX_IF_ETHER_H
#define _LINUX_IF_ETHER_H
/*
* IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble
* and FCS/CRC (frame check sequence).
* and FCS/CRC (frame check sequence).
*/
#define ETH_ALEN 6 /* Octets in one ethernet addr */
@ -69,18 +69,18 @@
/*
* Non DIX types. Won't clash for 1500 types.
*/
#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */
#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */
#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_SNAP 0x0005 /* Internal only */
#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */
#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/
#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */
#define ETH_P_CONTROL 0x0016 /* Card specific control frames */
#define ETH_P_IRDA 0x0017 /* Linux-IrDA */
@ -89,8 +89,8 @@
/*
* This is an Ethernet frame header.
*/
struct ethhdr
struct ethhdr
{
unsigned char h_dest[ETH_ALEN]; /* destination eth addr */
unsigned char h_source[ETH_ALEN]; /* source ether addr */
@ -110,4 +110,3 @@ struct _vlan {
#endif /* _LINUX_IF_ETHER_H */

229
include/ioctl_cfg80211.h
View file

@ -1,115 +1,114 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
#if defined(RTW_USE_CFG80211_STA_EVENT)
#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
#endif
struct rtw_wdev_invit_info {
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_priv
{
struct wireless_dev *rtw_wdev;
_adapter *padapter;
struct cfg80211_scan_request *scan_request;
_lock scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
u8 bandroid_scan;
bool block;
bool power_mgmt;
#ifdef CONFIG_CONCURRENT_MODE
ATOMIC_T ro_ch_to;
ATOMIC_T switch_ch_to;
#endif
};
#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w)))
#define wiphy_to_adapter(x) (_adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter)
#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev)
int rtw_wdev_alloc(_adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(_adapter *padapter);
void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
void rtw_cfg80211_indicate_connect(_adapter *padapter);
void rtw_cfg80211_indicate_disconnect(_adapter *padapter);
void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted);
#ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE
void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(dev, freq, buf, len, gfp)
#define rtw_cfg80211_send_rx_assoc(dev, bss, buf, len) cfg80211_send_rx_assoc(dev, buf, len)
#else
#define rtw_cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp)
#define rtw_cfg80211_send_rx_assoc(dev, bss, buf, len) cfg80211_send_rx_assoc(dev, bss, buf, len)
#endif
#endif //__IOCTL_CFG80211_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
#if defined(RTW_USE_CFG80211_STA_EVENT)
#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
#endif
struct rtw_wdev_invit_info {
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_priv
{
struct wireless_dev *rtw_wdev;
_adapter *padapter;
struct cfg80211_scan_request *scan_request;
_lock scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
u8 bandroid_scan;
bool block;
bool power_mgmt;
#ifdef CONFIG_CONCURRENT_MODE
ATOMIC_T ro_ch_to;
ATOMIC_T switch_ch_to;
#endif
};
#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w)))
#define wiphy_to_adapter(x) (_adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter)
#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev)
int rtw_wdev_alloc(_adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(_adapter *padapter);
void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
void rtw_cfg80211_indicate_connect(_adapter *padapter);
void rtw_cfg80211_indicate_disconnect(_adapter *padapter);
void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted);
#ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE
void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(dev, freq, buf, len, gfp)
#define rtw_cfg80211_send_rx_assoc(dev, bss, buf, len) cfg80211_send_rx_assoc(dev, buf, len)
#else
#define rtw_cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp)
#define rtw_cfg80211_send_rx_assoc(dev, bss, buf, len) cfg80211_send_rx_assoc(dev, bss, buf, len)
#endif
#endif //__IOCTL_CFG80211_H__

7
include/ip.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -102,7 +102,7 @@ struct ip_options {
is_data:1, /* Options in __data, rather than skb */
is_strictroute:1, /* Strict source route */
srr_is_hit:1, /* Packet destination addr was our one */
is_changed:1, /* IP checksum more not valid */
is_changed:1, /* IP checksum more not valid */
rr_needaddr:1, /* Need to record addr of outgoing dev */
ts_needtime:1, /* Need to record timestamp */
ts_needaddr:1; /* Need to record addr of outgoing dev */
@ -121,7 +121,7 @@ struct iphdr {
version:4;
#elif defined (__BIG_ENDIAN_BITFIELD)
__u8 version:4,
ihl:4;
ihl:4;
#else
#error "Please fix <asm/byteorder.h>"
#endif
@ -138,4 +138,3 @@ struct iphdr {
};
#endif /* _LINUX_IP_H */

3
include/mlme_osdep.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -37,4 +37,3 @@ extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie);
void rtw_reset_securitypriv( _adapter *adapter );
#endif //_MLME_OSDEP_H_

35
include/mp_custom_oid.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -38,7 +38,7 @@
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
@ -71,7 +71,7 @@
#define OID_RT_PRO_READ_EEPROM 0xFF818022
#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
@ -84,7 +84,7 @@
#define OID_RT_PRO_SET_MODULATION 0xFF81802F
//
//Sean
//Sean
#define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082
@ -114,15 +114,15 @@
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
//
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188
@ -239,8 +239,8 @@
#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S
@ -283,9 +283,9 @@
#define OID_RT_PRO_READ_TSSI 0xFF871123//S
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S
//Method 2 , using workitem
#define OID_RT_SET_READ_REG 0xFF871181 //S
@ -299,7 +299,7 @@
//For SDIO INTERFACE only
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
//For USB INTERFACE only
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S
@ -314,8 +314,8 @@
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S
@ -327,7 +327,7 @@
#define OID_RT_SET_BANDWIDTH 0xFF871209 //S
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q
@ -351,4 +351,3 @@
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S
#endif //#ifndef __CUSTOM_OID_H

5
include/nic_spec.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,7 +16,7 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
******************************************************************************/
#ifndef __NIC_SPEC_H__
@ -44,4 +44,3 @@
#endif // __RTL8711_SPEC_H__

3875
include/odm.h
View file

File diff suppressed because it is too large Load diff

389
include/odm_HWConfig.h
View file

@ -1,195 +1,194 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
//============================================================
// Definition
//============================================================
//
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
#define DESC92C_RATE1M 0x00
#define DESC92C_RATE2M 0x01
#define DESC92C_RATE5_5M 0x02
#define DESC92C_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define DESC92C_RATE6M 0x04
#define DESC92C_RATE9M 0x05
#define DESC92C_RATE12M 0x06
#define DESC92C_RATE18M 0x07
#define DESC92C_RATE24M 0x08
#define DESC92C_RATE36M 0x09
#define DESC92C_RATE48M 0x0a
#define DESC92C_RATE54M 0x0b
// MCS Rates, TxHT = 1
#define DESC92C_RATEMCS0 0x0c
#define DESC92C_RATEMCS1 0x0d
#define DESC92C_RATEMCS2 0x0e
#define DESC92C_RATEMCS3 0x0f
#define DESC92C_RATEMCS4 0x10
#define DESC92C_RATEMCS5 0x11
#define DESC92C_RATEMCS6 0x12
#define DESC92C_RATEMCS7 0x13
#define DESC92C_RATEMCS8 0x14
#define DESC92C_RATEMCS9 0x15
#define DESC92C_RATEMCS10 0x16
#define DESC92C_RATEMCS11 0x17
#define DESC92C_RATEMCS12 0x18
#define DESC92C_RATEMCS13 0x19
#define DESC92C_RATEMCS14 0x1a
#define DESC92C_RATEMCS15 0x1b
#define DESC92C_RATEMCS15_SG 0x1c
#define DESC92C_RATEMCS32 0x20
//============================================================
// structure and define
//============================================================
typedef struct _Phy_Rx_AGC_Info
{
#ifdef __LITTLE_ENDIAN
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#ifdef __LITTLE_ENDIAN
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8195
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
#ifdef __LITTLE_ENDIAN
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // __BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP))
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
//============================================================
// Definition
//============================================================
//
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
#define DESC92C_RATE1M 0x00
#define DESC92C_RATE2M 0x01
#define DESC92C_RATE5_5M 0x02
#define DESC92C_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define DESC92C_RATE6M 0x04
#define DESC92C_RATE9M 0x05
#define DESC92C_RATE12M 0x06
#define DESC92C_RATE18M 0x07
#define DESC92C_RATE24M 0x08
#define DESC92C_RATE36M 0x09
#define DESC92C_RATE48M 0x0a
#define DESC92C_RATE54M 0x0b
// MCS Rates, TxHT = 1
#define DESC92C_RATEMCS0 0x0c
#define DESC92C_RATEMCS1 0x0d
#define DESC92C_RATEMCS2 0x0e
#define DESC92C_RATEMCS3 0x0f
#define DESC92C_RATEMCS4 0x10
#define DESC92C_RATEMCS5 0x11
#define DESC92C_RATEMCS6 0x12
#define DESC92C_RATEMCS7 0x13
#define DESC92C_RATEMCS8 0x14
#define DESC92C_RATEMCS9 0x15
#define DESC92C_RATEMCS10 0x16
#define DESC92C_RATEMCS11 0x17
#define DESC92C_RATEMCS12 0x18
#define DESC92C_RATEMCS13 0x19
#define DESC92C_RATEMCS14 0x1a
#define DESC92C_RATEMCS15 0x1b
#define DESC92C_RATEMCS15_SG 0x1c
#define DESC92C_RATEMCS32 0x20
//============================================================
// structure and define
//============================================================
typedef struct _Phy_Rx_AGC_Info
{
#ifdef __LITTLE_ENDIAN
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#ifdef __LITTLE_ENDIAN
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8195
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
#ifdef __LITTLE_ENDIAN
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // __BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE|ODM_AP))
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif

217
include/odm_RTL8188E.h
View file

@ -1,109 +1,108 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#define MAIN_ANT 0
#define AUX_ANT 1
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
VOID
ODM_DIG_LowerBound_88E(
IN PDM_ODM_T pDM_Odm
);
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTrainingInit(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
ODM_AntennaDiversityInit_88E(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntennaDiversity_88E
(
IN PDM_ODM_T pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
VOID
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
ODM_UpdateRxIdleAnt_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
ODM_AntselStatistics_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u1Byte RxPWDBAll
);
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm);
BOOLEAN
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm);
VOID
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#define MAIN_ANT 0
#define AUX_ANT 1
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
VOID
ODM_DIG_LowerBound_88E(
IN PDM_ODM_T pDM_Odm
);
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTrainingInit(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
ODM_AntennaDiversityInit_88E(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntennaDiversity_88E
(
IN PDM_ODM_T pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
VOID
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
ODM_UpdateRxIdleAnt_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
VOID
ODM_AntselStatistics_88E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u1Byte RxPWDBAll
);
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm);
BOOLEAN
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm);
VOID
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm);
#endif

65
include/odm_RegConfig8188E.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -19,62 +19,61 @@
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
);
void
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
void
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
#endif
#endif // end of SUPPORT

109
include/odm_RegDefine11AC.h
View file

@ -1,55 +1,54 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
//2 BB REG LIST
//PAGE 8
//PAGE 9
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
//PAGE A
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE C
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
#define ODM_REG_IGI_B_11AC 0xE50
//PAGE F
#define ODM_REG_OFDM_FA_11AC 0xF48
//2 MAC REG LIST
//DIG Related
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
//2 BB REG LIST
//PAGE 8
//PAGE 9
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
//PAGE A
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE C
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
#define ODM_REG_IGI_B_11AC 0xE50
//PAGE F
#define ODM_REG_OFDM_FA_11AC 0xF48
//2 MAC REG LIST
//DIG Related
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#endif

343
include/odm_RegDefine11N.h
View file

@ -1,172 +1,171 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
//2 BB REG LIST
//PAGE 8
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
//PAGE 9
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
//PAGE A
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
//PAGE E
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
//2 MAC REG LIST
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
#define ODM_BIT_IGI_11N 0x0000007F
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
//2 BB REG LIST
//PAGE 8
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
//PAGE 9
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
//PAGE A
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
//PAGE E
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
//2 MAC REG LIST
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
#define ODM_BIT_IGI_11N 0x0000007F
#endif

346
include/odm_debug.h
View file

@ -1,173 +1,173 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __func__, ## args);
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __func__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
if (pDM_Odm->SupportICType == ODM_RTL8192C) \
DbgPrint("[ODM-92C] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8192D) \
DbgPrint("[ODM-92D] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8723A) \
DbgPrint("[ODM-8723A] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8188E) \
DbgPrint("[ODM-8188E] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8812) \
DbgPrint("[ODM-8812] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8821) \
DbgPrint("[ODM-8821] "); \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if (!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__func__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for ( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
#endif // __ODM_DBG_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __func__, ## args);
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __func__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
if (pDM_Odm->SupportICType == ODM_RTL8192C) \
DbgPrint("[ODM-92C] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8192D) \
DbgPrint("[ODM-92D] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8723A) \
DbgPrint("[ODM-8723A] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8188E) \
DbgPrint("[ODM-8188E] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8812) \
DbgPrint("[ODM-8812] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8821) \
DbgPrint("[ODM-8821] "); \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if (!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__func__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for ( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
#endif // __ODM_DBG_H__

673
include/odm_interface.h
View file

@ -1,337 +1,336 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
//
// =========== Constant/Structure/Enum/... Define
//
//
// =========== Macro Define
//
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES.
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
typedef enum _ODM_H2C_CMD
{
ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT=1,
ODM_H2C_PathDiv = 2,
ODM_MAX_H2CCMD
}ODM_H2C_CMD;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#endif
//
// =========== Extern Variable ??? It should be forbidden.
//
//
// =========== EXtern Function Prototype
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
);
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
);
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
);
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
//
// Memory Relative Function.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
);
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
);
//
// ODM MISC-spin lock relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
//
// ODM MISC-workitem relative API.
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
);
VOID
ODM_delay_ms(IN u4Byte ms);
VOID
ODM_delay_us(IN u4Byte us);
VOID
ODM_sleep_ms(IN u4Byte ms);
VOID
ODM_sleep_us(IN u4Byte us);
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
);
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
//
// ODM FW relative API.
//
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
);
#endif
#endif // __ODM_INTERFACE_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
//
// =========== Constant/Structure/Enum/... Define
//
//
// =========== Macro Define
//
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES.
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
typedef enum _ODM_H2C_CMD
{
ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT=1,
ODM_H2C_PathDiv = 2,
ODM_MAX_H2CCMD
}ODM_H2C_CMD;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#endif
//
// =========== Extern Variable ??? It should be forbidden.
//
//
// =========== EXtern Function Prototype
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
);
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
);
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
);
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
//
// Memory Relative Function.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
);
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
);
//
// ODM MISC-spin lock relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
//
// ODM MISC-workitem relative API.
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
);
VOID
ODM_delay_ms(IN u4Byte ms);
VOID
ODM_delay_us(IN u4Byte us);
VOID
ODM_sleep_ms(IN u4Byte ms);
VOID
ODM_sleep_us(IN u4Byte us);
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
);
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
//
// ODM FW relative API.
//
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
);
#endif
#endif // __ODM_INTERFACE_H__

347
include/odm_precomp.h
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@ -1,174 +1,173 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "odm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// Flags
#include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags.
#include "../odm_inc.h" // OUTSRC needs some extra flags.
// Data Structure
#include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
#include "../8192cd.h" // OUTSRC needs basic ADSL struct definition.
#include "../8192cd_util.h" // OUTSRC needs basic I/O function.
#ifdef ADSL_AP_BUILD_WORKAROUND
// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <hal_intf.h>
#elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
#include "Mp_Precomp.h"
#endif
//2 Hardware Parameter Files
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/Hal8192CEFWImg_AP.h"
#include "rtl8192c/Hal8192CEPHYImg_AP.h"
#include "rtl8192c/Hal8192CEMACImg_AP.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "Hal8188EFWImg_CE.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
#endif
//2 OutSrc Header Files
#include "odm.h"
#include "odm_HWConfig.h"
#include "odm_debug.h"
#include "odm_RegDefine11AC.h"
#include "odm_RegDefine11N.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_AP.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "HalPhyRf.h"
#include "HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e_hal.h"
#endif
#include "odm_interface.h"
#include "odm_reg.h"
#if (RTL8192C_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192c/Hal8192CHWImg_MAC.h"
#include "rtl8192c/Hal8192CHWImg_RF.h"
#include "rtl8192c/Hal8192CHWImg_BB.h"
#include "rtl8192c/Hal8192CHWImg_FW.h"
#endif
#include "rtl8192c/odm_RTL8192C.h"
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/odm_RTL8192D.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8723a/HalHWImg8723A_MAC.h"
#include "rtl8723a/HalHWImg8723A_RF.h"
#include "rtl8723a/HalHWImg8723A_BB.h"
#include "rtl8723a/HalHWImg8723A_FW.h"
#include "rtl8723a/odm_RegConfig8723A.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "HalHWImg8188E_MAC.h"
#include "HalHWImg8188E_RF.h"
#include "HalHWImg8188E_BB.h"
#include "Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#include "HalPhyRf_8188e.h"
#endif
#if (RTL8188E_FOR_TEST_CHIP >= 1)
#include "HalHWImg8188E_TestChip_MAC.h"
#include "HalHWImg8188E_TestChip_RF.h"
#include "HalHWImg8188E_TestChip_BB.h"
#endif
#ifdef CONFIG_WOWLAN
#if (RTL8188E_SUPPORT==1)
#include "HalHWImg8188E_FW.h"
#endif
#endif //CONFIG_WOWLAN
#include "odm_RegConfig8188E.h"
#include "odm_RTL8188E.h"
#endif
#endif // __ODM_PRECOMP_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "odm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// Flags
#include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags.
#include "../odm_inc.h" // OUTSRC needs some extra flags.
// Data Structure
#include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
#include "../8192cd.h" // OUTSRC needs basic ADSL struct definition.
#include "../8192cd_util.h" // OUTSRC needs basic I/O function.
#ifdef ADSL_AP_BUILD_WORKAROUND
// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <hal_intf.h>
#elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
#include "Mp_Precomp.h"
#endif
//2 Hardware Parameter Files
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/Hal8192CEFWImg_AP.h"
#include "rtl8192c/Hal8192CEPHYImg_AP.h"
#include "rtl8192c/Hal8192CEMACImg_AP.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "Hal8188EFWImg_CE.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
#endif
//2 OutSrc Header Files
#include "odm.h"
#include "odm_HWConfig.h"
#include "odm_debug.h"
#include "odm_RegDefine11AC.h"
#include "odm_RegDefine11N.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_AP.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "HalPhyRf.h"
#include "HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e_hal.h"
#endif
#include "odm_interface.h"
#include "odm_reg.h"
#if (RTL8192C_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192c/Hal8192CHWImg_MAC.h"
#include "rtl8192c/Hal8192CHWImg_RF.h"
#include "rtl8192c/Hal8192CHWImg_BB.h"
#include "rtl8192c/Hal8192CHWImg_FW.h"
#endif
#include "rtl8192c/odm_RTL8192C.h"
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/odm_RTL8192D.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8723a/HalHWImg8723A_MAC.h"
#include "rtl8723a/HalHWImg8723A_RF.h"
#include "rtl8723a/HalHWImg8723A_BB.h"
#include "rtl8723a/HalHWImg8723A_FW.h"
#include "rtl8723a/odm_RegConfig8723A.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "HalHWImg8188E_MAC.h"
#include "HalHWImg8188E_RF.h"
#include "HalHWImg8188E_BB.h"
#include "Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#include "HalPhyRf_8188e.h"
#endif
#if (RTL8188E_FOR_TEST_CHIP >= 1)
#include "HalHWImg8188E_TestChip_MAC.h"
#include "HalHWImg8188E_TestChip_RF.h"
#include "HalHWImg8188E_TestChip_BB.h"
#endif
#ifdef CONFIG_WOWLAN
#if (RTL8188E_SUPPORT==1)
#include "HalHWImg8188E_FW.h"
#endif
#endif //CONFIG_WOWLAN
#include "odm_RegConfig8188E.h"
#include "odm_RTL8188E.h"
#endif
#endif // __ODM_PRECOMP_H__

239
include/odm_reg.h
View file

@ -1,120 +1,119 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
//MAC REG
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
//Ant Detect Reg
#define ODM_DPDT 0x300
//PSD Init
#define ODM_PSDREG 0x808
//92D Path Div
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
#define BIT_FA_RESET BIT0
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
//MAC REG
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
//Ant Detect Reg
#define ODM_DPDT 0x300
//PSD Init
#define ODM_PSDREG 0x808
//92D Path Div
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
#define BIT_FA_RESET BIT0
#endif

95
include/odm_types.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -23,17 +23,17 @@
//
// Define Different SW team support
//
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_MP 0x08 //BIT3
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_MP 0x08 //BIT3
#define DM_ODM_SUPPORT_TYPE ODM_CE
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#endif
typedef enum _HAL_STATUS{
@ -64,7 +64,7 @@ typedef enum _RT_SPINLOCK_TYPE{
RT_RM_SPINLOCK = 3,
RT_CAM_SPINLOCK = 4,
RT_SCAN_SPINLOCK = 5,
RT_LOG_SPINLOCK = 7,
RT_LOG_SPINLOCK = 7,
RT_BW_SPINLOCK = 8,
RT_CHNLOP_SPINLOCK = 9,
RT_RF_OPERATE_SPINLOCK = 10,
@ -77,7 +77,7 @@ typedef enum _RT_SPINLOCK_TYPE{
//Shall we define Ndis 6.2 SpinLock Here ?
RT_PORT_SPINLOCK=16,
RT_VNIC_SPINLOCK=17,
RT_HVL_SPINLOCK=18,
RT_HVL_SPINLOCK=18,
RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
RT_BTData_SPINLOCK=25,
@ -85,7 +85,7 @@ typedef enum _RT_SPINLOCK_TYPE{
RT_WAPI_OPTION_SPINLOCK=26,
RT_WAPI_RX_SPINLOCK=27,
// add for 92D CCK control issue
// add for 92D CCK control issue
RT_CCK_PAGEA_SPINLOCK = 28,
RT_BUFFER_SPINLOCK = 29,
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
@ -104,8 +104,8 @@ typedef enum _RT_SPINLOCK_TYPE{
#define PSTA_INFO_T PRT_WLAN_STA
// typedef unsigned long u4Byte,*pu4Byte;
#define CONFIG_HW_ANTENNA_DIVERSITY
#define CONFIG_SW_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#define CONFIG_SW_ANTENNA_DIVERSITY
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
@ -133,12 +133,12 @@ typedef enum _RT_SPINLOCK_TYPE{
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
@ -160,71 +160,70 @@ typedef enum _RT_SPINLOCK_TYPE{
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <basic_types.h>
#define u1Byte u8
#define pu1Byte u8*
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#define s8Byte s64
#define ps8Byte s64*
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#endif
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define STA_INFO_T struct sta_info
#define PSTA_INFO_T struct sta_info *
#define TRUE _TRUE
#define TRUE _TRUE
#define FALSE _FALSE
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
//define useless flag to avoid compile warning
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define BT_30_SUPPORT 0
#define FPGA_TWO_MAC_VERIFICATION 0
#endif
#endif // __ODM_TYPES_H__

307
include/osdep_ce_service.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,156 +16,155 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
typedef NDIS_MINIPORT_TIMER _timer;
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define thread_exit() ExitThread(STATUS_SUCCESS); return 0;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
{
NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx);
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
NdisMSetTimer(ptimer,delay_time);
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
NdisMCancelTimer(ptimer,bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
#endif
******************************************************************************/
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
typedef NDIS_MINIPORT_TIMER _timer;
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define thread_exit() ExitThread(STATUS_SUCCESS); return 0;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
{
NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx);
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
NdisMSetTimer(ptimer,delay_time);
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
NdisMCancelTimer(ptimer,bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
#endif

29
include/osdep_intf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -26,9 +26,9 @@
#include <drv_types.h>
struct intf_priv {
u8 *intf_dev;
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_xmitsz; //USB2.0: unlimited, SDIO:512
u32 max_recvsz; //USB2.0: unlimited, SDIO:512
@ -36,9 +36,9 @@ struct intf_priv {
volatile u8 *allocated_io_rwmem;
u32 io_wsz; //unit: 4bytes
u32 io_rsz;//unit: 4bytes
u8 intf_status;
void (*_bus_io)(u8 *priv);
u8 intf_status;
void (*_bus_io)(u8 *priv);
/*
Under Sync. IRP (SDIO/USB)
@ -50,11 +50,11 @@ The protection mechanism is through the pending queue.
_mutex ioctl_mutex;
#ifdef PLATFORM_LINUX
#ifdef CONFIG_USB_HCI
#ifdef PLATFORM_LINUX
#ifdef CONFIG_USB_HCI
// when in USB, IO is through interrupt in/out endpoints
struct usb_device *udev;
struct usb_device *udev;
PURB piorw_urb;
u8 io_irp_cnt;
u8 bio_irp_pending;
@ -67,7 +67,7 @@ The protection mechanism is through the pending queue.
#ifdef PLATFORM_OS_XP
#ifdef CONFIG_SDIO_HCI
// below is for io_rwmem...
// below is for io_rwmem...
PMDL pmdl;
PSDBUS_REQUEST_PACKET sdrp;
PSDBUS_REQUEST_PACKET recv_sdrp;
@ -81,11 +81,11 @@ The protection mechanism is through the pending queue.
PIRP piorw_irp;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
#endif
_sema io_retevt;
#endif
#endif
};
};
#ifdef CONFIG_R871X_TEST
@ -147,4 +147,3 @@ void rtw_drv_if2_stop(_adapter *if2);
#endif
#endif //_OSDEP_INTF_H_

158
include/osdep_service.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -32,7 +32,7 @@
#undef _FALSE
#define _FALSE 0
#ifdef PLATFORM_FREEBSD
#include <sys/cdefs.h>
@ -89,31 +89,31 @@
#if 1 //Baron porting from linux, it's all temp solution, needs to check again
#include <sys/sema.h>
#include <sys/pcpu.h> /* XXX for PCPU_GET */
// typedef struct semaphore _sema;
typedef struct sema _sema;
// typedef struct semaphore _sema;
typedef struct sema _sema;
// typedef spinlock_t _lock;
typedef struct mtx _lock;
typedef struct mtx _mutex;
typedef struct mtx _mutex;
typedef struct timer_list _timer;
struct list_head {
struct list_head *next, *prev;
};
struct __queue {
struct list_head queue;
struct list_head queue;
_lock lock;
};
//typedef struct sk_buff _pkt;
typedef struct mbuf _pkt;
typedef struct mbuf _buffer;
typedef struct __queue _queue;
typedef struct list_head _list;
typedef int _OS_STATUS;
//typedef u32 _irqL;
typedef unsigned long _irqL;
typedef struct ifnet * _nic_hdl;
typedef pid_t _thread_hdl_;
// typedef struct thread _thread_hdl_;
typedef void thread_return;
@ -139,7 +139,7 @@
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
/*
/*
* Linux timers are emulated using FreeBSD callout functions
* (and taskqueue functionality).
*
@ -153,11 +153,11 @@ struct timer_list {
/* FreeBSD callout related fields */
struct callout callout;
//timeout function
//timeout function
void (*function)(void*);
//argument
void *arg;
};
struct workqueue_struct;
struct work_struct;
@ -167,13 +167,13 @@ typedef enum work_state {
WORK_STATE_UNSET = 0,
WORK_STATE_CALLOUT_PENDING = 1,
WORK_STATE_TASK_PENDING = 2,
WORK_STATE_WORK_CANCELLED = 3
WORK_STATE_WORK_CANCELLED = 3
} work_state_t;
struct work_struct {
struct task task; /* FreeBSD task */
work_state_t state; /* the pending or otherwise state of work. */
work_func_t func;
work_func_t func;
};
#define spin_unlock_irqrestore mtx_unlock_irqrestore
#define spin_unlock_bh mtx_unlock_irqrestore
@ -201,10 +201,10 @@ typedef unsigned char *sk_buff_data_t;
typedef union ktime ktime_t; /* Kill this */
void rtw_mtx_lock(_lock *plock);
void rtw_mtx_unlock(_lock *plock);
/**
/**
* struct sk_buff - socket buffer
* @next: Next buffer in list
* @prev: Previous buffer in list
@ -233,7 +233,7 @@ void rtw_mtx_unlock(_lock *plock);
* @priority: Packet queueing priority
* @users: User count - see {datagram,tcp}.c
* @protocol: Packet protocol from driver
* @truesize: Buffer size
* @truesize: Buffer size
* @head: Head of buffer
* @data: Data head pointer
* @tail: Tail pointer
@ -496,7 +496,7 @@ void dev_kfree_skb_any(struct sk_buff *skb);
*
* These macros will use the SYSINIT framework to call a specified
* function (with no arguments) on module loading or unloading.
*
*
*/
void module_init_exit_wrapper(void *arg);
@ -513,13 +513,13 @@ void module_init_exit_wrapper(void *arg);
/*
* The usb_register and usb_deregister functions are used to register
* usb drivers with the usb subsystem.
* usb drivers with the usb subsystem.
*/
int usb_register(struct usb_driver *driver);
int usb_deregister(struct usb_driver *driver);
/*
* usb_get_dev and usb_put_dev - increment/decrement the reference count
* usb_get_dev and usb_put_dev - increment/decrement the reference count
* of the usb device structure.
*
* Original body of usb_get_dev:
@ -537,7 +537,7 @@ usb_get_dev(struct usb_device *dev)
return dev;
}
static inline void
static inline void
usb_put_dev(struct usb_device *dev)
{
return;
@ -615,18 +615,18 @@ typedef unsigned gfp_t;
__inline static _list *get_next(_list *list)
{
return list->next;
}
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
spin_lock_irqsave(plock, *pirqL);
@ -695,7 +695,7 @@ __inline static void _init_timer(_timer *ptimer,_nic_hdl padapter,void *pfunc,vo
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
{
// mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
if (ptimer->function && ptimer->arg){
rtw_mtx_lock(NULL);
@ -706,8 +706,8 @@ __inline static void _set_timer(_timer *ptimer,u32 delay_time)
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
// del_timer_sync(ptimer);
// *bcancelled= _TRUE;//TRUE ==1; FALSE==0
// del_timer_sync(ptimer);
// *bcancelled= _TRUE;//TRUE ==1; FALSE==0
rtw_mtx_lock(NULL);
callout_drain(&ptimer->callout);
rtw_mtx_unlock(NULL);
@ -780,10 +780,10 @@ __inline static void _set_workitem(_workitem *pwork)
#include <linux/kthread.h>
#ifdef CONFIG_IOCTL_CFG80211
// #include <linux/ieee80211.h>
#ifdef CONFIG_IOCTL_CFG80211
// #include <linux/ieee80211.h>
#include <net/ieee80211_radiotap.h>
#include <net/cfg80211.h>
#include <net/cfg80211.h>
#endif //CONFIG_IOCTL_CFG80211
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
@ -804,7 +804,7 @@ __inline static void _set_workitem(_workitem *pwork)
#include <linux/pci.h>
#endif
#ifdef CONFIG_USB_HCI
typedef struct urb * PURB;
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
@ -814,30 +814,30 @@ __inline static void _set_workitem(_workitem *pwork)
#endif
#endif
typedef struct semaphore _sema;
typedef struct semaphore _sema;
typedef spinlock_t _lock;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
typedef struct mutex _mutex;
typedef struct mutex _mutex;
#else
typedef struct semaphore _mutex;
#endif
typedef struct timer_list _timer;
struct __queue {
struct list_head queue;
struct list_head queue;
_lock lock;
};
typedef struct sk_buff _pkt;
typedef unsigned char _buffer;
typedef struct __queue _queue;
typedef struct list_head _list;
typedef int _OS_STATUS;
//typedef u32 _irqL;
typedef unsigned long _irqL;
typedef struct net_device * _nic_hdl;
typedef void* _thread_hdl_;
typedef int thread_return;
typedef void* thread_context;
@ -878,18 +878,18 @@ static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
__inline static _list *get_next(_list *list)
{
return list->next;
}
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
spin_lock_irqsave(plock, *pirqL);
@ -949,20 +949,20 @@ __inline static void rtw_list_delete(_list *plist)
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx)
{
//setup_timer(ptimer, pfunc,(u32)cntx);
//setup_timer(ptimer, pfunc,(u32)cntx);
ptimer->function = pfunc;
ptimer->data = (unsigned long)cntx;
init_timer(ptimer);
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
{
mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
del_timer_sync(ptimer);
del_timer_sync(ptimer);
*bcancelled= _TRUE;//TRUE ==1; FALSE==0
}
@ -1071,14 +1071,14 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
#include <usbdlib.h>
#endif
typedef KSEMAPHORE _sema;
typedef KSEMAPHORE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef KMUTEX _mutex;
typedef KMUTEX _mutex;
typedef KIRQL _irqL;
@ -1089,14 +1089,14 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
typedef NDIS_MINIPORT_TIMER _timer;
struct __queue {
LIST_ENTRY queue;
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef PKTHREAD _thread_hdl_;
typedef void thread_return;
typedef void* thread_context;
@ -1107,40 +1107,40 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
#define HZ 10000000
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
NdisAcquireSpinLock(plock);
}
__inline static _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
@ -1168,7 +1168,7 @@ __inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
InitializeListHead(plist);
}
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
@ -1177,8 +1177,8 @@ __inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVO
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
NdisMSetTimer(ptimer,delay_time);
{
NdisMSetTimer(ptimer,delay_time);
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
@ -1378,7 +1378,7 @@ extern void rtw_sleep_schedulable(int ms);
extern void rtw_msleep_os(int ms);
extern void rtw_usleep_os(int us);
extern u32 rtw_atoi(u8* s);
extern u32 rtw_atoi(u8* s);
#ifdef DBG_DELAY_OS
#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __func__, __LINE__)
@ -1404,9 +1404,9 @@ __inline static unsigned char _cancel_timer_ex(_timer *ptimer)
#endif
#ifdef PLATFORM_WINDOWS
u8 bcancelled;
_cancel_timer(ptimer, &bcancelled);
return bcancelled;
#endif
}
@ -1419,9 +1419,9 @@ static __inline void thread_enter(char *name)
allow_signal(SIGTERM);
}
__inline static void flush_signals_thread(void)
__inline static void flush_signals_thread(void)
{
if (signal_pending (current))
if (signal_pending (current))
flush_signals(current);
}
@ -1440,8 +1440,8 @@ __inline static _OS_STATUS res_to_status(sint res)
else
return NDIS_STATUS_FAILURE;
#endif
#endif
}
#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
@ -1453,7 +1453,7 @@ __inline static u32 _RND4(u32 sz)
u32 val;
val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2;
return val;
}
@ -1464,7 +1464,7 @@ __inline static u32 _RND8(u32 sz)
u32 val;
val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3;
return val;
}
@ -1475,7 +1475,7 @@ __inline static u32 _RND128(u32 sz)
u32 val;
val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7;
return val;
}
@ -1486,7 +1486,7 @@ __inline static u32 _RND256(u32 sz)
u32 val;
val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8;
return val;
}
@ -1497,7 +1497,7 @@ __inline static u32 _RND512(u32 sz)
u32 val;
val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9;
return val;
}
@ -1658,7 +1658,7 @@ extern u64 rtw_division64(u64 x, u64 y);
} while (0)
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
((u32) (a)[2]))
((u32) (a)[2]))
#define RTW_PUT_BE24(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \
@ -1667,7 +1667,7 @@ extern u64 rtw_division64(u64 x, u64 y);
} while (0)
#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
#define RTW_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
@ -1677,7 +1677,7 @@ extern u64 rtw_division64(u64 x, u64 y);
} while (0)
#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
#define RTW_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
@ -1689,7 +1689,7 @@ extern u64 rtw_division64(u64 x, u64 y);
#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
(((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
(((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
#define RTW_PUT_BE64(a, val) \
do { \
(a)[0] = (u8) (((u64) (val)) >> 56); \
@ -1725,5 +1725,3 @@ struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
void rtw_cbuf_free(struct rtw_cbuf *cbuf);
#endif

7
include/recv_osdep.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -29,13 +29,13 @@ extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
extern void _rtw_free_recv_priv (struct recv_priv *precvpriv);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup);
int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
void rtw_free_recv_priv (struct recv_priv *precvpriv);
@ -55,4 +55,3 @@ void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
#endif //

12
include/rtl8188e_cmd.h
View file

@ -25,8 +25,8 @@ typedef enum _RTL8188E_H2C_CMD_ID
//Class Common
H2C_COM_RSVD_PAGE =0x00,
H2C_COM_MEDIA_STATUS_RPT =0x01,
H2C_COM_SCAN =0x02,
H2C_COM_KEEP_ALIVE =0x03,
H2C_COM_SCAN =0x02,
H2C_COM_KEEP_ALIVE =0x03,
H2C_COM_DISCNT_DECISION =0x04,
#ifndef CONFIG_WOWLAN
H2C_COM_WWLAN =0x05,
@ -53,7 +53,7 @@ typedef enum _RTL8188E_H2C_CMD_ID
H2C_BT_COEX_GPIO_MODE =0x61,
H2C_BT_DAC_SWING_VAL =0x62,
H2C_BT_PSD_RST =0x63,
//Class Remote WakeUp
#ifdef CONFIG_WOWLAN
H2C_COM_WWLAN =0x80,
@ -61,10 +61,10 @@ typedef enum _RTL8188E_H2C_CMD_ID
H2C_COM_AOAC_GLOBAL_INFO =0x82,
#endif
//Class
//Class
H2C_RESET_TSF =0xc0,
}RTL8188E_H2C_CMD_ID;
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
@ -173,5 +173,3 @@ void rtl8188es_set_wowlan_cmd(_adapter* padapter, u8 enable);
void SetFwRelatedForWoWLAN8188ES(_adapter* padapter, u8 bHostIsGoingtoSleep);
#endif//CONFIG_WOWLAN
#endif//__RTL8188E_CMD_H__

4
include/rtl8188e_dm.h
View file

@ -21,7 +21,7 @@
#define __RTL8188E_DM_H__
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
//###### duplicate code,will move to ODM #########
#define IQK_MAC_REG_NUM 4
@ -29,7 +29,7 @@ enum{
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
//###### duplicate code,will move to ODM #########
struct dm_priv
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;

1415
include/rtl8188e_hal.h
View file

File diff suppressed because it is too large Load diff

73
include/rtl8188e_led.h
View file

@ -1,37 +1,36 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_LED_H__
#define __RTL8188E_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
void rtl8188eu_InitSwLeds(PADAPTER padapter);
void rtl8188eu_DeInitSwLeds(PADAPTER padapter);
void SwLedOn(_adapter *padapter, PLED_871x pLed);
void SwLedOff(_adapter *padapter, PLED_871x pLed);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_LED_H__
#define __RTL8188E_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
void rtl8188eu_InitSwLeds(PADAPTER padapter);
void rtl8188eu_DeInitSwLeds(PADAPTER padapter);
void SwLedOn(_adapter *padapter, PLED_871x pLed);
void SwLedOff(_adapter *padapter, PLED_871x pLed);
#endif

291
include/rtl8188e_recv.h
View file

@ -1,146 +1,145 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_RECV_H__
#define __RTL8188E_RECV_H__
#include <rtl8192c_recv.h>
#define TX_RPT1_PKT_LEN 8
typedef enum _RX_PACKET_TYPE{
NORMAL_RX,//Normal rx packet
TX_REPORT1,//CCX
TX_REPORT2,//TX RPT
HIS_REPORT,// USB HISR RPT
}RX_PACKET_TYPE, *PRX_PACKET_TYPE;
typedef struct rxreport_8188e
{
//Offset 0
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
//Offset 4
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
//Offset 8
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd0831:1;
//Offset 12
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rpt_sel:2;
u32 rsvd1216:13;
u32 pattern_match:1;
u32 unicastwake:1;
u32 magicwake:1;
//Offset 16
/*
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 rsvd1613:19;
*/
u32 rsvd16;
//Offset 20
u32 tsfl;
//Offset 24
u32 bassn:12;
u32 bavld:1;
u32 rsvd2413:19;
} RXREPORT, *PRXREPORT;
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_recv_priv(PADAPTER padapter);
void rtl8188es_free_recv_priv(PADAPTER padapter);
void rtl8188es_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
void rtl8188eu_free_recv_priv(PADAPTER padapter);
void rtl8188eu_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
void rtl8188eu_recv_tasklet(void *priv);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
void rtl8188ee_free_recv_priv(PADAPTER padapter);
#endif
void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8188e_process_phy_info(PADAPTER padapter, void *prframe);
void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status);
void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_RECV_H__
#define __RTL8188E_RECV_H__
#include <rtl8192c_recv.h>
#define TX_RPT1_PKT_LEN 8
typedef enum _RX_PACKET_TYPE{
NORMAL_RX,//Normal rx packet
TX_REPORT1,//CCX
TX_REPORT2,//TX RPT
HIS_REPORT,// USB HISR RPT
}RX_PACKET_TYPE, *PRX_PACKET_TYPE;
typedef struct rxreport_8188e
{
//Offset 0
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
//Offset 4
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
//Offset 8
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd0831:1;
//Offset 12
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rpt_sel:2;
u32 rsvd1216:13;
u32 pattern_match:1;
u32 unicastwake:1;
u32 magicwake:1;
//Offset 16
/*
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 rsvd1613:19;
*/
u32 rsvd16;
//Offset 20
u32 tsfl;
//Offset 24
u32 bassn:12;
u32 bavld:1;
u32 rsvd2413:19;
} RXREPORT, *PRXREPORT;
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_recv_priv(PADAPTER padapter);
void rtl8188es_free_recv_priv(PADAPTER padapter);
void rtl8188es_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
void rtl8188eu_free_recv_priv(PADAPTER padapter);
void rtl8188eu_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
void rtl8188eu_recv_tasklet(void *priv);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
void rtl8188ee_free_recv_priv(PADAPTER padapter);
#endif
void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8188e_process_phy_info(PADAPTER padapter, void *prframe);
void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status);
void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat);
#endif

9
include/rtl8188e_rf.h
View file

@ -26,11 +26,11 @@
int PHY_RF6052_Config8188E( IN PADAPTER Adapter );
void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter,
void rtl8188e_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8188e_PHY_RF6052SetBandwidth(
void rtl8188e_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8188e_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
@ -38,8 +38,7 @@ VOID rtl8188e_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevelOFDM,
IN u8* pPowerLevelBW20,
IN u8* pPowerLevelBW40,
IN u8* pPowerLevelBW40,
IN u8 Channel);
#endif//__RTL8188E_RF_H__

3292
include/rtl8188e_spec.h
View file

File diff suppressed because it is too large Load diff

3
include/rtl8188e_sreset.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -31,4 +31,3 @@ extern void rtl8188e_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8188e_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

617
include/rtl8188e_xmit.h
View file

@ -1,309 +1,308 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_XMIT_H__
#define __RTL8188E_XMIT_H__
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
//
// Queue Select Value in TxDesc
//
#define QSLT_BK 0x2//0x01
#define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4
#define QSLT_VO 0x7//0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
//For 88e early mode
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define QSEL_SHT 8
#define RATE_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define SEC_TYPE_SHT 22
#define PKT_OFFSET_SHT 26
//OFFSET 8
#define AGG_EN BIT(12)
#define AGG_BK BIT(16)
#define AMPDU_DENSITY_SHT 20
#define ANTSEL_A BIT(24)
#define ANTSEL_B BIT(25)
#define TX_ANT_CCK_SHT 26
#define TX_ANTL_SHT 28
#define TX_ANT_HT_SHT 30
//OFFSET 12
#define SEQ_SHT 16
#define EN_HWSEQ BIT(31)
//OFFSET 16
#define QOS BIT(6)
#define HW_SSN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define CTS_2_SELF BIT(11)
#define RTS_EN BIT(12)
#define HW_RTS_EN BIT(13)
#define DATA_SHORT BIT(24)
#define PWR_STATUS_SHT 15
#define DATA_SC_SHT 20
#define DATA_BW BIT(25)
//OFFSET 20
#define RTY_LMT_EN BIT(17)
enum TXDESC_SC{
SC_DONT_CARE = 0x00,
SC_UPPER= 0x01,
SC_LOWER=0x02,
SC_DUPLICATE=0x03
};
//OFFSET 20
#define SGI BIT(6)
#define USB_TXAGG_NUM_SHT 24
typedef struct txdesc_88e
{
//Offset 0
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
//Offset 4
u32 macid:6;
u32 rsvd0406:2;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
//Offset 8
u32 rts_rc:6;
u32 data_rc:6;
u32 agg_en:1;
u32 rd_en:1;
u32 bar_rty_th:2;
u32 bk:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
//Offset 12
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
//Offset 16
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 pwr_status:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
//Offset 20
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
//Offset 24
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
//Offset 28
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 sw0:8; /* offset 30 */
u32 sw1:4;
u32 mcs15_sgi_max_len:4;
}TXDESC, *PTXDESC;
#define txdesc_set_ccx_sw_88e(txdesc, value) \
do { \
((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
} while (0)
struct txrpt_ccx_88e {
/* offset 0 */
u8 tag1:1;
u8 pkt_num:3;
u8 txdma_underflow:1;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:6;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
void rtl8188e_fill_fake_txdesc(PADAPTER padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull);
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
void rtl8188es_free_xmit_priv(PADAPTER padapter);
s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
thread_return rtl8188es_xmit_thread(thread_context context);
s32 rtl8188es_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8188es_xmit_buf_handler
#ifdef CONFIG_SDIO_TX_TASKLET
void rtl8188es_xmit_tasklet(void *priv);
#endif
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8188eu_init_xmit_priv(PADAPTER padapter);
void rtl8188eu_free_xmit_priv(PADAPTER padapter);
s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8188eu_xmit_buf_handler
void rtl8188eu_xmit_tasklet(void *priv);
s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_xmit_priv(PADAPTER padapter);
void rtl8188ee_free_xmit_priv(PADAPTER padapter);
struct xmit_buf *rtl8188ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8188ee_xmitframe_resume(_adapter *padapter);
s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
void rtl8188ee_xmit_tasklet(void *priv);
#endif
#ifdef CONFIG_TX_EARLY_MODE
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf );
#endif
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_88e(void *buf);
void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);
#else
#define dump_txrpt_ccx_88e(buf) do {} while (0)
#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)
#endif //CONFIG_XMIT_ACK
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif //__RTL8188E_XMIT_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_XMIT_H__
#define __RTL8188E_XMIT_H__
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
//
// Queue Select Value in TxDesc
//
#define QSLT_BK 0x2//0x01
#define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4
#define QSLT_VO 0x7//0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
//For 88e early mode
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define QSEL_SHT 8
#define RATE_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define SEC_TYPE_SHT 22
#define PKT_OFFSET_SHT 26
//OFFSET 8
#define AGG_EN BIT(12)
#define AGG_BK BIT(16)
#define AMPDU_DENSITY_SHT 20
#define ANTSEL_A BIT(24)
#define ANTSEL_B BIT(25)
#define TX_ANT_CCK_SHT 26
#define TX_ANTL_SHT 28
#define TX_ANT_HT_SHT 30
//OFFSET 12
#define SEQ_SHT 16
#define EN_HWSEQ BIT(31)
//OFFSET 16
#define QOS BIT(6)
#define HW_SSN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define CTS_2_SELF BIT(11)
#define RTS_EN BIT(12)
#define HW_RTS_EN BIT(13)
#define DATA_SHORT BIT(24)
#define PWR_STATUS_SHT 15
#define DATA_SC_SHT 20
#define DATA_BW BIT(25)
//OFFSET 20
#define RTY_LMT_EN BIT(17)
enum TXDESC_SC{
SC_DONT_CARE = 0x00,
SC_UPPER= 0x01,
SC_LOWER=0x02,
SC_DUPLICATE=0x03
};
//OFFSET 20
#define SGI BIT(6)
#define USB_TXAGG_NUM_SHT 24
typedef struct txdesc_88e
{
//Offset 0
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
//Offset 4
u32 macid:6;
u32 rsvd0406:2;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
//Offset 8
u32 rts_rc:6;
u32 data_rc:6;
u32 agg_en:1;
u32 rd_en:1;
u32 bar_rty_th:2;
u32 bk:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
//Offset 12
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
//Offset 16
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 pwr_status:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
//Offset 20
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
//Offset 24
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
//Offset 28
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 sw0:8; /* offset 30 */
u32 sw1:4;
u32 mcs15_sgi_max_len:4;
}TXDESC, *PTXDESC;
#define txdesc_set_ccx_sw_88e(txdesc, value) \
do { \
((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
} while (0)
struct txrpt_ccx_88e {
/* offset 0 */
u8 tag1:1;
u8 pkt_num:3;
u8 txdma_underflow:1;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:6;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
void rtl8188e_fill_fake_txdesc(PADAPTER padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull);
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
void rtl8188es_free_xmit_priv(PADAPTER padapter);
s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
thread_return rtl8188es_xmit_thread(thread_context context);
s32 rtl8188es_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8188es_xmit_buf_handler
#ifdef CONFIG_SDIO_TX_TASKLET
void rtl8188es_xmit_tasklet(void *priv);
#endif
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8188eu_init_xmit_priv(PADAPTER padapter);
void rtl8188eu_free_xmit_priv(PADAPTER padapter);
s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8188eu_xmit_buf_handler
void rtl8188eu_xmit_tasklet(void *priv);
s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_xmit_priv(PADAPTER padapter);
void rtl8188ee_free_xmit_priv(PADAPTER padapter);
struct xmit_buf *rtl8188ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8188ee_xmitframe_resume(_adapter *padapter);
s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
void rtl8188ee_xmit_tasklet(void *priv);
#endif
#ifdef CONFIG_TX_EARLY_MODE
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf );
#endif
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_88e(void *buf);
void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);
#else
#define dump_txrpt_ccx_88e(buf) do {} while (0)
#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)
#endif //CONFIG_XMIT_ACK
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif //__RTL8188E_XMIT_H__

17
include/rtl8192c_cmd.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,7 +22,7 @@
enum cmd_msg_element_id
{
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID=0,
SET_PWRMODE_EID=1,
@ -49,13 +49,13 @@ struct cmd_msg_parm {
};
typedef struct _SETPWRMODE_PARM{
u8 Mode;
u8 SmartPS;
u8 Mode;
u8 SmartPS;
u8 BcnPassTime; // unit: 100ms
}SETPWRMODE_PARM, *PSETPWRMODE_PARM;
struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; // 1: on, 0:off
u8 ROFOn; // 1: on, 0:off
u16 gpio_period; // unit: 1024 us
}__attribute__ ((packed));
@ -65,8 +65,8 @@ typedef struct JOINBSSRPT_PARM{
}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
typedef struct _RSVDPAGE_LOC{
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
}RSVDPAGE_LOC, *PRSVDPAGE_LOC;
@ -98,7 +98,7 @@ void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
#ifdef CONFIG_IOL
typedef struct _IO_OFFLOAD_LOC{
u8 LocCmd;
u8 LocCmd;
}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC;
int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
#endif //CONFIG_IOL
@ -113,4 +113,3 @@ u8 rtl8192c_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
#endif // __RTL8192C_CMD_H_

31
include/rtl8192c_dm.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -34,15 +34,15 @@
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
typedef enum _BT_Ant_NUM{
Ant_x2 = 0,
Ant_x2 = 0,
Ant_x1 = 1
} BT_Ant_NUM, *PBT_Ant_NUM;
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR_BC4 = 3,
@ -51,12 +51,12 @@ typedef enum _BT_CoType{
} BT_CoType, *PBT_CoType;
typedef enum _BT_CurState{
BT_OFF = 0,
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
@ -69,7 +69,7 @@ typedef enum _BT_ServiceType{
} BT_ServiceType, *PBT_ServiceType;
typedef enum _BT_RadioShared{
BT_Radio_Shared = 0,
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
@ -116,7 +116,7 @@ struct btcoexist_priv {
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
//###### duplicate code,will move to ODM #########
struct dm_priv
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
@ -141,7 +141,7 @@ struct dm_priv
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
@ -150,11 +150,11 @@ struct dm_priv
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
@ -173,7 +173,7 @@ struct dm_priv
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
//for IQK
u32 RegC04;
u32 Reg874;
@ -221,10 +221,10 @@ struct dm_priv
//for Antenna diversity
#ifdef CONFIG_ANTENNA_DIVERSITY
// SWAT_T DM_SWAT_Table;
#endif
#endif
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
// _timer SwAntennaSwitchTimer;
/*
/*
u64 lastTxOkCnt;
u64 lastRxOkCnt;
u64 TXByteCnt_A;
@ -238,7 +238,7 @@ struct dm_priv
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
// u8 DIG_Dynamic_MIN ;
// u8 DIG_Dynamic_MIN ;
//###### duplicate code,will move to ODM #########
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
@ -260,4 +260,3 @@ void rtl8192c_InitHalDm( IN PADAPTER Adapter);
void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
#endif //__HAL8190PCIDM_H__

20
include/rtl8192c_event.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,13 +16,11 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_EVENT_H_
#define _RTL8192C_EVENT_H_
#endif
******************************************************************************/
#ifndef _RTL8192C_EVENT_H_
#define _RTL8192C_EVENT_H_
#endif

185
include/rtl8192c_hal.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -38,7 +38,7 @@
#ifdef CONFIG_PCI_HCI
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
@ -88,7 +88,7 @@
#define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
// #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
#define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
@ -99,34 +99,34 @@
#define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
#define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
#elif defined(CONFIG_USB_HCI)
@ -140,7 +140,7 @@
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
//#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
@ -148,7 +148,7 @@
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
@ -177,46 +177,46 @@
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength
#endif
@ -381,15 +381,15 @@ typedef struct _TxPowerInfo{
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
//
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 1byte|----8bytes----|1byte|--5bytes--|
// | 1byte|----8bytes----|1byte|--5bytes--|
// | | Reserved(14bytes) |
//
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_MAP_LEN_8723 256
@ -419,13 +419,13 @@ typedef enum _RT_MULTI_FUNC{
//
typedef enum _RT_POLARITY_CTL{
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
RT_POLARITY_HIGH_ACT = 1,
}RT_POLARITY_CTL,*PRT_POLARITY_CTL;
// For RTL8723 regulator mode. by tynli. 2011.01.14.
typedef enum _RT_REGULATOR_MODE{
RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1,
RT_LDO_REGULATOR = 1,
}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE;
enum c2h_id_8192c {
@ -460,7 +460,7 @@ struct hal_data_8192ce
u32 IntrMaskToSet[2];
u32 DisabledFunctions;
//current WIFI_PHY values
u32 ReceiveConfig;
u32 TransmitConfig;
@ -489,8 +489,8 @@ struct hal_data_8192ce
u16 EEPROMChannelPlan;
u16 EEPROMVersion;
u8 EEPROMChnlAreaTxPwrCCK[2][3];
u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
u8 EEPROMChnlAreaTxPwrCCK[2][3];
u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
u8 EEPROMPwrLimitHT20[3];
u8 EEPROMPwrLimitHT40[3];
@ -508,7 +508,7 @@ struct hal_data_8192ce
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -517,11 +517,11 @@ struct hal_data_8192ce
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
@ -545,7 +545,7 @@ struct hal_data_8192ce
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
//u32 TxPowerTrackControl;
u8 b1x1RecvCombine; // for 1T1R receive combining
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
//vivi, for tx power tracking, 20080407
@ -556,9 +556,9 @@ struct hal_data_8192ce
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
//RDG enable
BOOLEAN bRDGEnable;
@ -571,8 +571,8 @@ struct hal_data_8192ce
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 CurAntenna;
u8 CurAntenna;
//### ODM-DUPLICATE CODE ###
u8 AntDivCfg;
/*
@ -592,9 +592,9 @@ struct hal_data_8192ce
u32 OFDM_Ant2_Cnt;
#endif
*/
//### ODM-DUPLICATE CODE ###
//### ODM-DUPLICATE CODE ###
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 bDumpRxPkt;//for debug
#ifdef DBG_CONFIG_ERROR_DETECT
@ -607,7 +607,7 @@ struct hal_data_8192ce
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
u16 EfuseUsedBytes;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif //CONFIG_P2P
@ -682,7 +682,7 @@ struct hal_data_8192cu
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -737,19 +737,19 @@ struct hal_data_8192cu
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv srestpriv;
#endif
#endif
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
u8 CurAntenna;
u8 CurAntenna;
/*****ODM duplicate data********/
u8 AntDivCfg;
/*
@ -812,11 +812,11 @@ struct hal_data_8192cu
u16 EfuseUsedBytes;
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
@ -847,4 +847,3 @@ void rtl8192c_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter);
s32 c2h_id_filter_ccx_8192c(u8 id);
#endif

49
include/rtl8192c_led.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,27 +16,26 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_LED_H_
#define __RTL8192C_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192cu_InitSwLeds(_adapter *padapter);
void rtl8192cu_DeInitSwLeds(_adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192ce_gen_RefreshLedState(PADAPTER Adapter);
void rtl8192ce_InitSwLeds(_adapter *padapter);
void rtl8192ce_DeInitSwLeds(_adapter *padapter);
#endif
#endif
******************************************************************************/
#ifndef __RTL8192C_LED_H_
#define __RTL8192C_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192cu_InitSwLeds(_adapter *padapter);
void rtl8192cu_DeInitSwLeds(_adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192ce_gen_RefreshLedState(PADAPTER Adapter);
void rtl8192ce_InitSwLeds(_adapter *padapter);
void rtl8192ce_DeInitSwLeds(_adapter *padapter);
#endif
#endif

5
include/rtl8192c_recv.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -34,7 +34,7 @@
#if defined(CONFIG_GSPI_HCI)
#define NR_RECVBUFF (32)
#elif defined(CONFIG_SDIO_HCI)
#define NR_RECVBUFF (8)
#define NR_RECVBUFF (8)
#else
#ifdef CONFIG_SINGLE_RECV_BUF
#define NR_RECVBUFF (1)
@ -140,4 +140,3 @@ void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy
void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif

149
include/rtl8192c_rf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,77 +16,76 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192c_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192C_RF_H_
#define _RTL8192C_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192c_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN PADAPTER Adapter );
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192c_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192C_RF_H_
#define _RTL8192C_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192c_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN PADAPTER Adapter );
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

117
include/rtl8192c_spec.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -168,7 +168,7 @@
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG 0x0300
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
@ -284,7 +284,7 @@
#define REG_ATIMWND 0x055A
#define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_TSFTR 0x0560
#define REG_TSFTR1 0x0568
#define REG_INIT_TSFTR 0x0564
@ -453,14 +453,14 @@
#define InvalidBBRFValue 0x12345678
// Min Spacing related settings.
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
//----------------------------------------------------------------------------
// 8192C Cmd9346CR bits (Offset 0xA, 16bit)
//----------------------------------------------------------------------------
#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define Cmd9346CR_9356SEL BIT4
#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
#define AutoLoadEFUSE CmdEEPROM_En
@ -480,7 +480,7 @@
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
//----------------------------------------------------------------------------
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
//----------------------------------------------------------------------------
/*
Network Type
@ -508,16 +508,16 @@ Default: 00b.
#define RRSR_RSC_LOWSUBCHNL 0x200000
#define RRSR_SHORT 0x800000
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
@ -527,7 +527,7 @@ Default: 00b.
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define BRSR_AckShortPmb BIT23
#define BRSR_AckShortPmb BIT23
// CCK ACK: use Short Preamble or not
//----------------------------------------------------------------------------
@ -545,20 +545,20 @@ Default: 00b.
#define CAM_NOTVALID 0x0000
#define CAM_USEDK BIT5
#define CAM_CONTENT_COUNT 8
#define CAM_CONTENT_COUNT 8
#define CAM_NONE 0x0
#define CAM_WEP40 0x01
#define CAM_TKIP 0x02
#define CAM_AES 0x04
#define CAM_WEP104 0x05
#define TOTAL_CAM_ENTRY 32
#define HALF_CAM_ENTRY 16
#define HALF_CAM_ENTRY 16
#define CAM_CONFIG_USEDK _TRUE
#define CAM_CONFIG_NO_USEDK _FALSE
#define CAM_WRITE BIT16
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
@ -593,7 +593,7 @@ Default: 00b.
#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
@ -683,7 +683,7 @@ Default: 00b.
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#define EEPROM_CID_QMI 0x0D
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define RTL_EEPROM_ID 0x8129
@ -725,7 +725,7 @@ typedef enum _INTERFACE_SELECT_8192CPCIe{
#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
#define EEPROM_HT20_MAX_PWR_OFFSET 0x72
#define EEPROM_CHANNEL_PLAN 0x75
#define EEPROM_CHANNEL_PLAN 0x75
#define EEPROM_TSSI_A 0x76
#define EEPROM_TSSI_B 0x77
#define EEPROM_THERMAL_METER 0x78
@ -738,16 +738,16 @@ typedef enum _INTERFACE_SELECT_8192CPCIe{
#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5]
#endif
#endif
#ifdef CONFIG_USB_HCI
//should be renamed and moved to another file
typedef enum _BOARD_TYPE_8192CUSB{
BOARD_USB_DONGLE = 0, // USB dongle
BOARD_USB_High_PA = 1, // USB dongle with high power PA
BOARD_MINICARD = 2, // Minicard
BOARD_USB_SOLO = 3, // USB solo-Slim module
BOARD_USB_DONGLE = 0, // USB dongle
BOARD_USB_High_PA = 1, // USB dongle with high power PA
BOARD_MINICARD = 2, // Minicard
BOARD_USB_SOLO = 3, // USB solo-Slim module
BOARD_USB_COMBO = 4, // USB Combo-Slim module
} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB;
@ -817,7 +817,7 @@ typedef enum _BOARD_TYPE_8192CUSB{
#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power
// 2009/02/09 Cosa Add for SD3 requirement
// 2009/02/09 Cosa Add for SD3 requirement
#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference
#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
@ -897,7 +897,7 @@ typedef enum _BOARD_TYPE_8192CUSB{
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,
Here the register defines are for 92C. When the define is as same with 92C,
we will use the 92C's define for the consistency
So the following defines for 92C is not entire!!!!!!
=====================================================================
@ -934,23 +934,23 @@ Current IOREG MAP
#define RCR_ACF BIT12 //Accept control type frame
#define RCR_ADF BIT11 //Accept data type frame
#define RCR_AICV BIT9 //Accept ICV error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp)
#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data)
#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet
#define RCR_APWRMGT BIT5 //Accept power management packet
#define RCR_ADD3 BIT4 //Accept address 3 match packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_APM BIT1 //Accept physical match packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_MXDMA_OFFSET 8
#define RCR_FIFO_OFFSET 13
//============================================================================
// 8192c USB specific Regsiter Offset and Content definition,
// 8192c USB specific Regsiter Offset and Content definition,
// 2009.08.18, added by vivi. for merge 92c and 92C into one driver
//============================================================================
//#define APS_FSMCO 0x0004 same with 92Ce
@ -981,7 +981,7 @@ Current IOREG MAP
#define InvalidBBRFValue 0x12345678
//============================================================================
// 8192C Regsiter Bit and Content definition
// 8192C Regsiter Bit and Content definition
//============================================================================
//-----------------------------------------------------
//
@ -1072,16 +1072,16 @@ Current IOREG MAP
//2 9346CR
#define EEDO BIT(0)
#define EEDI BIT(1)
#define EESK BIT(2)
#define EECS BIT(3)
//#define EERPROMSEL BIT(4)
//#define EEPROM_EN BIT(5)
#define EEDO BIT(0)
#define EEDI BIT(1)
#define EESK BIT(2)
#define EECS BIT(3)
//#define EERPROMSEL BIT(4)
//#define EEPROM_EN BIT(5)
#define BOOT_FROM_EEPROM BIT(4)
#define EEPROM_EN BIT(5)
#define EEM0 BIT(6)
#define EEM1 BIT(7)
#define EEM0 BIT(6)
#define EEM1 BIT(7)
//2 AFE_MISC
@ -1194,7 +1194,7 @@ Current IOREG MAP
#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only.
#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only.
//2 PWR_DATA
//2 PWR_DATA
//2 CAL_TIMER
@ -1225,10 +1225,10 @@ Current IOREG MAP
//2 GPIO_INTM
//2 LEDCFG
#define LED0PL BIT(4)
#define LED0PL BIT(4)
#define LED0DIS BIT(7)
#define LED1DIS BIT(15)
#define LED1PL BIT(12)
#define LED1PL BIT(12)
#define SECCAM_CLR BIT(30)
@ -1281,7 +1281,7 @@ Current IOREG MAP
//2REG_GPIO_OUTSTS (For RTL8723 only)
#define EFS_HCI_SEL (BIT(0)|BIT(1))
#define PAD_HCI_SEL (BIT(2)|BIT(3))
#define HCI_SEL (BIT(4)|BIT(5))
#define HCI_SEL (BIT(4)|BIT(5))
#define PKG_SEL_HCI BIT(6)
#define FEN_GPS BIT(7)
#define FEN_BT BIT(8)
@ -1375,12 +1375,12 @@ Current IOREG MAP
#define HQSEL_HIQ BIT(5)
// For normal driver, 0x10C
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define QUEUE_LOW 1
#define QUEUE_NORMAL 2
@ -1765,4 +1765,3 @@ Current IOREG MAP
#include "basic_types.h"
#endif

33
include/rtl8192c_sreset.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,19 +16,18 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_SRESET_C_
#define _RTL8192C_SRESET_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8192c_silentreset_for_specific_platform(_adapter *padapter);
extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8192c_sreset_linked_status_check(_adapter *padapter);
#endif
#endif
******************************************************************************/
#ifndef _RTL8192C_SRESET_C_
#define _RTL8192C_SRESET_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8192c_silentreset_for_specific_platform(_adapter *padapter);
extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8192c_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

5
include/rtl8192c_xmit.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -32,7 +32,7 @@
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
#define OWN BIT(31)
//OFFSET 4
@ -162,4 +162,3 @@ s32 rtl8192ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#endif

8
include/rtl8192d_cmd.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,7 +22,7 @@
//--------------------------------------------
//3 Host Message Box
//3 Host Message Box
//--------------------------------------------
// User Define Message [31:8]
@ -63,7 +63,7 @@ struct P2P_PS_Offload_t {
// Description: Determine the types of H2C commands that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _RTL8192D_H2C_CMD
typedef enum _RTL8192D_H2C_CMD
{
H2C_AP_OFFLOAD = 0, /*0*/
H2C_SETPWRMODE = 1, /*1*/
@ -99,5 +99,3 @@ void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
#endif

31
include/rtl8192d_dm.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -28,7 +28,7 @@
//============================================================
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
@ -51,13 +51,13 @@ enum{
#define IQK_Matrix_REG_NUM 8
#define IQK_Matrix_Settings_NUM 1+24+21
//###### duplicate code,will move to ODM #########
struct dm_priv
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
u8 InitDMFlag;
u32 InitODMFlag;
//* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB;
int EntryMinUndecoratedSmoothedPWDB;
@ -73,22 +73,22 @@ struct dm_priv
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
*/
//for High Power
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
@ -111,7 +111,7 @@ struct dm_priv
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u32 RegA24;
//for IQK
u32 Reg874;
u32 RegC08;
@ -125,22 +125,22 @@ struct dm_priv
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 bCCKinCH14;
char CCK_index;
//u8 Record_CCK_20Mindex;
//u8 Record_CCK_40Mindex;
char OFDM_index[2];
BOOLEAN bDPKdone[2];
u8 PowerIndex_backup[6];
//for Antenna diversity
//#ifdef CONFIG_ANTENNA_DIVERSITY
//SWAT_T DM_SWAT_Table;
//#endif
//Neil Chen----2011--06--23-----
//3 Path Diversity
//3 Path Diversity
BOOLEAN bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19
BOOLEAN RSSI_test;
s32 RSSI_sum_A;
@ -152,7 +152,7 @@ struct dm_priv
//for TxPwrTracking
int RegE94;
int RegE9C;
int RegE9C;
int RegEB4;
int RegEBC;
#if MP_DRIVER == 1
@ -180,4 +180,3 @@ void rtl8192d_InitHalDm(IN PADAPTER Adapter);
void rtl8192d_HalDmWatchDog(IN PADAPTER Adapter);
#endif //__HAL8190PCIDM_H__

111
include/rtl8192d_hal.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,14 +33,14 @@
#include "../hal/OUTSRC/odm_precomp.h"
#ifdef CONFIG_PCI_HCI
#include <pci_ops.h>
#include <pci_ops.h>
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//---------------------------------------------------------------------
// RTL8192DE From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
@ -50,7 +50,7 @@
#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
@ -59,16 +59,16 @@
// RTL8192DE From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
@ -77,7 +77,7 @@
#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
@ -86,7 +86,7 @@
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
@ -98,7 +98,7 @@
#elif defined(CONFIG_USB_HCI)
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
//---------------------------------------------------------------------
@ -108,8 +108,8 @@
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
@ -124,16 +124,16 @@
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
@ -142,8 +142,8 @@
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
@ -151,14 +151,14 @@
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
@ -171,12 +171,12 @@
#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
@ -187,7 +187,7 @@
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
//
// Check if FW header exists. We do not consider the lower 4 bits in this case.
// Check if FW header exists. We do not consider the lower 4 bits in this case.
// By tynli. 2009.12.04.
//
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
@ -251,7 +251,7 @@ typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
#define BCN_DMA_ATIME_INT_TIME 0x02
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR = 3,
@ -260,12 +260,12 @@ typedef enum _BT_CoType{
} BT_CoType, *PBT_CoType;
typedef enum _BT_CurState{
BT_OFF = 0,
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
@ -277,7 +277,7 @@ typedef enum _BT_ServiceType{
} BT_ServiceType, *PBT_ServiceType;
typedef enum _BT_RadioShared{
BT_Radio_Shared = 0,
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
@ -289,7 +289,7 @@ typedef struct _BT_COEXIST_STR{
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_Service;
u8 BT_RadioSharedType;
u8 Ratio_Tx;
u8 Ratio_PRI;
@ -410,12 +410,12 @@ typedef struct _TxPowerInfo{
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 2byte|----8bytes----|1byte|--7bytes--| //92D
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
typedef enum _PA_MODE {
PA_MODE_EXTERNAL = 0x00,
PA_MODE_INTERNAL_SP3T = 0x01,
PA_MODE_INTERNAL_SPDT = 0x02
PA_MODE_INTERNAL_SPDT = 0x02
} PA_MODE;
/* Copy from rtl8192c */
@ -437,8 +437,8 @@ enum c2h_id_8192d {
#ifdef CONFIG_PCI_HCI
struct hal_data_8192de
{
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
MACPHY_MODE_8192D MacPhyMode92D;
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
BAND_TYPE BandSet92D;
@ -498,7 +498,7 @@ struct hal_data_8192de
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -543,7 +543,7 @@ struct hal_data_8192de
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
@ -568,7 +568,7 @@ struct hal_data_8192de
#else
//regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
#endif
//for host message to fw
@ -581,9 +581,9 @@ struct hal_data_8192de
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 RegCR_1;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 bInterruptMigration;
@ -595,8 +595,8 @@ struct hal_data_8192de
u16 RegRRSR;
u16 EfuseUsedBytes;
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
@ -630,7 +630,7 @@ VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
//should be renamed and moved to another file
typedef enum _INTERFACE_SELECT_8192DUSB{
INTF_SEL0_USB = 0, // USB
INTF_SEL0_USB = 0, // USB
INTF_SEL1_MINICARD = 1, // Minicard
INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary
INTF_SEL3_PRO = 3, // Customized proprietary
@ -640,9 +640,9 @@ typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB;
struct hal_data_8192du
{
HAL_VERSION VersionID;
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
// add for 92D Phy mode/mac/Band mode
MACPHY_MODE_8192D MacPhyMode92D;
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
BAND_TYPE BandSet92D;
@ -687,7 +687,7 @@ struct hal_data_8192du
u16 EEPROMSVID;
u16 EEPROMSDID;
u8 EEPROMCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMRegulatory;
u8 EEPROMThermalMeter;
@ -698,7 +698,7 @@ struct hal_data_8192du
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -743,7 +743,7 @@ struct hal_data_8192du
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
@ -769,7 +769,7 @@ struct hal_data_8192du
#else
//regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
#endif
//for host message to fw
@ -780,11 +780,11 @@ struct hal_data_8192du
u32 RegBcnCtrlVal;
u8 RegTxPause;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 RegReg542;
u8 RegCR_1;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
@ -820,8 +820,8 @@ struct hal_data_8192du
u16 RegRRSR;
u16 EfuseUsedBytes;
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
@ -852,4 +852,3 @@ void rtl8192d_free_hal_data(_adapter * padapter);
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
void rtl8192d_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter);
#endif

51
include/rtl8192d_led.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,28 +16,27 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_LED_H_
#define __RTL8192D_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192du_InitSwLeds(_adapter *padapter);
void rtl8192du_DeInitSwLeds(_adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192de_gen_RefreshLedState(PADAPTER Adapter);
void rtl8192de_InitSwLeds(_adapter *padapter);
void rtl8192de_DeInitSwLeds(_adapter *padapter);
#endif
#endif
******************************************************************************/
#ifndef __RTL8192D_LED_H_
#define __RTL8192D_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192du_InitSwLeds(_adapter *padapter);
void rtl8192du_DeInitSwLeds(_adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192de_gen_RefreshLedState(PADAPTER Adapter);
void rtl8192de_InitSwLeds(_adapter *padapter);
void rtl8192de_DeInitSwLeds(_adapter *padapter);
#endif
#endif

3
include/rtl8192d_recv.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -132,4 +132,3 @@ void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy
void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif

159
include/rtl8192d_rf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,82 +16,81 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192d_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192D_RF_H_
#define _RTL8192D_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192d_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192d_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192d_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192D( IN PADAPTER Adapter );
BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192d_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192D_RF_H_
#define _RTL8192D_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192d_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192d_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192d_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192D( IN PADAPTER Adapter );
BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

145
include/rtl8192d_spec.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -91,14 +91,14 @@
#define REG_SYS_CFG 0x00F0
#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
#define REG_MAC0 0x0081
#define REG_MAC1 0x0053
#define FW_MAC0_ready 0x18
#define FW_MAC1_ready 0x1A
#define MAC0_ON BIT7
#define MAC1_ON BIT0
#define mac0_ready BIT0
#define mac1_ready BIT0
#define REG_MAC0 0x0081
#define REG_MAC1 0x0053
#define FW_MAC0_ready 0x18
#define FW_MAC1_ready 0x1A
#define MAC0_ON BIT7
#define MAC1_ON BIT0
#define mac0_ready BIT0
#define mac1_ready BIT0
//-----------------------------------------------------
@ -177,7 +177,7 @@
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG 0x0300
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
@ -189,7 +189,7 @@
#define REG_DBI 0x0348 // Backdoor REG for Access Configuration
//sherry added for DBI Read/Write 20091126
#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration
#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration
#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
@ -300,7 +300,7 @@
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_TSFTR 0x0560
#define REG_TSFTR1 0x0568
#define REG_INIT_TSFTR 0x0564
@ -394,7 +394,7 @@
#define REG_USB_AGG_TO 0xFE5C
#define REG_USB_AGG_TH 0xFE5D
// for 92DU high_Queue low_Queue Normal_Queue select
// for 92DU high_Queue low_Queue Normal_Queue select
#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44
//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45
#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47
@ -443,7 +443,7 @@
#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053
#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055
#define PBP REG_PBP
#define PBP REG_PBP
// Redifine MACID register, to compatible prior ICs.
#define IDR0 MACIDR0
@ -463,20 +463,20 @@
#define UnusedRegister 0x1BF
#define DCAM UnusedRegister
#define PSR UnusedRegister
#define BBAddr UnusedRegister
#define BBAddr UnusedRegister
#define PhyDataR UnusedRegister
#define InvalidBBRFValue 0x12345678
// Min Spacing related settings.
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
//----------------------------------------------------------------------------
// 8192C Cmd9346CR bits (Offset 0xA, 16bit)
//----------------------------------------------------------------------------
#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define Cmd9346CR_9356SEL BIT4
#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
#define AutoLoadEFUSE CmdEEPROM_En
@ -496,7 +496,7 @@
//----------------------------------------------------------------------------
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
//----------------------------------------------------------------------------
/*
Network Type
@ -524,16 +524,16 @@ Default: 00b.
#define RRSR_RSC_LOWSUBCHNL 0x200000
#define RRSR_SHORT 0x800000
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
@ -543,7 +543,7 @@ Default: 00b.
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define BRSR_AckShortPmb BIT23
#define BRSR_AckShortPmb BIT23
// CCK ACK: use Short Preamble or not
//----------------------------------------------------------------------------
@ -561,7 +561,7 @@ Default: 00b.
#define CAM_NOTVALID 0x0000
#define CAM_USEDK BIT5
#define CAM_CONTENT_COUNT 8
#define CAM_CONTENT_COUNT 8
#define CAM_NONE 0x0
#define CAM_WEP40 0x01
@ -572,11 +572,11 @@ Default: 00b.
#define TOTAL_CAM_ENTRY 32
#define HALF_CAM_ENTRY 16
#define HALF_CAM_ENTRY 16
#define CAM_CONFIG_USEDK _TRUE
#define CAM_CONFIG_NO_USEDK _FALSE
#define CAM_WRITE BIT16
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
@ -611,7 +611,7 @@ Default: 00b.
#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
@ -651,10 +651,10 @@ Default: 00b.
// Default Value for EEPROM or EFUSE!!!
//
#define EEPROM_Default_TSSI 0x0
#define EEPROM_Default_TxPowerDiff 0x0
#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0
#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68)
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_TxPowerDiff 0x0
#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0
#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68)
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_HT2T_TxPwr 0x10
#define EEPROM_Default_LegacyHTTxPowerDiff 0x4
@ -666,17 +666,17 @@ Default: 00b.
#define EEPROM_Default_TxPowerLevel_5G 0x22
#define EEPROM_Default_HT40_2SDiff 0x0
#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 //OFDM Tx Power index diff
#define EEPROM_Default_HT40_PwrMaxOffset 0
#define EEPROM_Default_HT20_PwrMaxOffset 0
#define EEPROM_Default_HT40_PwrMaxOffset 0
#define EEPROM_Default_HT20_PwrMaxOffset 0
// For debug
#define EEPROM_Default_PID 0x1234
#define EEPROM_Default_VID 0x5678
#define EEPROM_Default_CustomerID 0xAB
#define EEPROM_Default_SubCustomerID 0xCD
#define EEPROM_Default_Version 0
#define EEPROM_Default_PID 0x1234
#define EEPROM_Default_VID 0x5678
#define EEPROM_Default_CustomerID 0xAB
#define EEPROM_Default_SubCustomerID 0xCD
#define EEPROM_Default_Version 0
#define EEPROM_Default_externalPA_C9 0x00
#define EEPROM_Default_externalPA_CC 0xFF
@ -704,11 +704,11 @@ Default: 00b.
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#define EEPROM_CID_QMI 0x0D
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define RTL8192_EEPROM_ID 0x8129
@ -767,7 +767,7 @@ Default: 00b.
#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_IQK_DELTA 0xBC
#define EEPROM_LCK_DELTA 0xBC
#define EEPROM_XTAL_K 0xBD //[7:5]
@ -792,7 +792,7 @@ Default: 00b.
#define EEPROM_DEF_PART_NO 0x3FD //Byte
#define EEPROME_CHIP_VERSION_L 0x3FF
#define EEPROME_CHIP_VERSION_H 0x3FE
#endif
#endif
#ifdef CONFIG_USB_HCI
#define RTL8190_EEPROM_ID 0x8129 // 0-1
@ -846,7 +846,7 @@ Default: 00b.
#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_TEST_CHANNEL_PLAN 0xBB
#define EEPROM_IQK_DELTA 0xBC
#define EEPROM_LCK_DELTA 0xBC
@ -934,7 +934,7 @@ Default: 00b.
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,
Here the register defines are for 92C. When the define is as same with 92C,
we will use the 92C's define for the consistency
So the following defines for 92C is not entire!!!!!!
=====================================================================
@ -970,23 +970,23 @@ Current IOREG MAP
#define RCR_ACF BIT12 //Accept control type frame
#define RCR_ADF BIT11 //Accept data type frame
#define RCR_AICV BIT9 //Accept ICV error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp)
#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data)
#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet
#define RCR_APWRMGT BIT5 //Accept power management packet
#define RCR_ADD3 BIT4 //Accept address 3 match packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_APM BIT1 //Accept physical match packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_MXDMA_OFFSET 8
#define RCR_FIFO_OFFSET 13
//============================================================================
// 8192c USB specific Regsiter Offset and Content definition,
// 8192c USB specific Regsiter Offset and Content definition,
// 2009.08.18, added by vivi. for merge 92c and 92C into one driver
//============================================================================
//#define APS_FSMCO 0x0004 same with 92Ce
@ -1017,7 +1017,7 @@ Current IOREG MAP
#define InvalidBBRFValue 0x12345678
//============================================================================
// 8192C Regsiter Bit and Content definition
// 8192C Regsiter Bit and Content definition
//============================================================================
//-----------------------------------------------------
//
@ -1207,11 +1207,11 @@ Current IOREG MAP
#define EF_PD BIT(19)
#define EF_FLAG BIT(31)
//2 EFUSE_TEST
//2 EFUSE_TEST
#define EF_TRPT BIT(7)
#define LDOE25_EN BIT(31)
//2 PWR_DATA
//2 PWR_DATA
//2 CAL_TIMER
@ -1241,8 +1241,8 @@ Current IOREG MAP
//2 GPIO_INTM
//2 LEDCFG
#define LED0PL BIT(4)
#define LED1PL BIT(12)
#define LED0PL BIT(4)
#define LED1PL BIT(12)
#define LED0DIS BIT(7)
#define SECCAM_CLR BIT(30)
@ -1364,12 +1364,12 @@ Current IOREG MAP
#define HQSEL_HIQ BIT(5)
// For normal driver, 0x10C
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define QUEUE_LOW 1
#define QUEUE_NORMAL 2
@ -1672,8 +1672,8 @@ Current IOREG MAP
#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
#define SCR_SKByA2 BIT(4) //Search kEY BY A2
#define SCR_NoSKMC BIT(5) //No Key Search Multicast
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
//vivi added for new cam search flow, 20091028
#ifdef HW_EN_DE_CRYPTION_FOR_NEW_CAM_SEARCH_FLOW
@ -1735,4 +1735,3 @@ Current IOREG MAP
#include "basic_types.h"
#endif

5
include/rtl8192d_xmit.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -32,7 +32,7 @@
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
#define OWN BIT(31)
//OFFSET 4
@ -178,4 +178,3 @@ s32 rtl8192de_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif

15
include/rtl8723a_bt-coexist.h
View file

@ -82,7 +82,7 @@ typedef struct _OCTET_STRING{
enum
{
AESCCMP_BLK_SIZE = 16, // # octets in an AES block
AESCCMP_MAX_PACKET = 4*512, // largest packet size
AESCCMP_MAX_PACKET = 4*512, // largest packet size
AESCCMP_N_RESERVED = 0, // reserved nonce octet value
AESCCMP_A_DATA = 0x40, // the Adata bit in the flags
AESCCMP_M_SHIFT = 3, // how much to shift the 3-bit M field
@ -159,7 +159,7 @@ typedef struct _CHNL_TXPOWER_TRIPLE
//=============================================
#define CAM_BT_START_INDEX (HALF_CAM_ENTRY - 4) // MAX_BT_ASOC_ENTRY_NUM : 4 !!!
#define BT_HWCAM_STAR CAM_BT_START_INDEX // We used HALF_CAM_ENTRY ~ HALF_CAM_ENTRY -MAX_BT_ASOC_ENTRY_NUM
#define BT_HWCAM_STAR CAM_BT_START_INDEX // We used HALF_CAM_ENTRY ~ HALF_CAM_ENTRY -MAX_BT_ASOC_ENTRY_NUM
typedef enum _HCI_STATUS
{
@ -442,7 +442,7 @@ typedef enum _HCI_EXTENSION_COMMANDS
HCI_EXTENSION_VERSION_NOTIFY =0x0100,
HCI_LINK_STATUS_NOTIFY =0x0101,
HCI_BT_OPERATION_NOTIFY =0x0102,
HCI_ENABLE_WIFI_SCAN_NOTIFY =0x0103,
HCI_ENABLE_WIFI_SCAN_NOTIFY =0x0103,
//The following is for IVT
@ -570,7 +570,7 @@ typedef enum _HCI_STATE_MACHINE
HCI_STATE_AUTHENTICATING =0x04,
HCI_STATE_CONNECTED =0x08,
HCI_STATE_DISCONNECTING =0x10,
HCI_STATE_DISCONNECTED =0x20
HCI_STATE_DISCONNECTED =0x20
} HCI_STATE_MACHINE, *PHCI_STATE_MACHINE;
typedef enum _AMP_ASSOC_STRUCTURE_TYPE
@ -713,7 +713,7 @@ typedef enum _BT_STATE_WPA_AUTH
} BT_STATE_WPA_AUTH, *PBT_STATE_WPA_AUTH;
#define BT_WPA_AUTH_TIMEOUT_PERIOD 1000
#define BTMaxWPAAuthReTransmitCoun 5
#define BTMaxWPAAuthReTransmitCoun 5
#define MAX_AMP_ASSOC_FRAG_LEN 248
#define TOTAL_ALLOCIATE_ASSOC_LEN 1000
@ -1330,7 +1330,7 @@ typedef struct _BTDM_8723A_2ANT
u8 bPreRfRxLpfShrink;
u8 bCurRfRxLpfShrink;
u8 bPreLowPenaltyRa;
u8 bPreLowPenaltyRa;
u8 bCurLowPenaltyRa;
u8 preBtRetryIndex;
@ -1344,7 +1344,7 @@ typedef struct _BTDM_8723A_2ANT
u8 bPreAdcBackOff;
u8 bCurAdcBackOff;
u8 bPreAgcTableEn;
u8 bPreAgcTableEn;
u8 bCurAgcTableEn;
u32 preVal0x6c0;
@ -1779,4 +1779,3 @@ extern u32 BTCoexDbgLevel;
#endif // __RTL8723A_BT_COEXIST_H__

11
include/rtl8723a_cmd.h
View file

@ -21,7 +21,7 @@
#define __RTL8723A_CMD_H__
#define H2C_BT_FW_PATCH_LEN 3
#define H2C_BT_FW_PATCH_LEN 3
#define H2C_BT_PWR_FORCE_LEN 3
enum cmd_msg_element_id
@ -54,7 +54,7 @@ enum cmd_msg_element_id
SCAN_EN_EID = 59,
LOWPWR_LPS_EID = 71,
H2C_RESET_TSF = 75,
MAX_CMDMSG_EID
MAX_CMDMSG_EID
};
struct cmd_msg_parm {
@ -114,10 +114,10 @@ typedef struct _B_TYPE_TDMA_PARM
{
#define B_TDMA_EN BIT(0)
#define B_TDMA_FIXANTINBT BIT(1)
#define B_TDMA_TXPSPOLL BIT(2)
#define B_TDMA_TXPSPOLL BIT(2)
#define B_TDMA_VAL870 BIT(3)
#define B_TDMA_AUTOWAKEUP BIT(4)
#define B_TDMA_NOPS BIT(5)
#define B_TDMA_NOPS BIT(5)
#define B_TDMA_WLANHIGHPRI BIT(6)
u8 option;
@ -135,7 +135,7 @@ typedef struct _SCAN_EN_PARM {
// BT_FW_PATCH
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) // SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
typedef struct _LOWPWR_LPS_PARM
{
@ -171,4 +171,3 @@ void CheckFwRsvdPageContent(PADAPTER padapter);
#ifdef CONFIG_TSF_RESET_OFFLOAD
u8 rtl8723c_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD

9
include/rtl8723a_dm.h
View file

@ -30,7 +30,7 @@
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
//============================================================
// structure and define
@ -157,7 +157,7 @@ struct dm_priv
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
// _timer SwAntennaSwitchTimer;
/*
/*
u64 lastTxOkCnt;
u64 lastRxOkCnt;
u64 TXByteCnt_A;
@ -171,7 +171,7 @@ struct dm_priv
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
// u8 DIG_Dynamic_MIN ;
// u8 DIG_Dynamic_MIN ;
//###### duplicate code,will move to ODM #########
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
@ -184,11 +184,10 @@ struct dm_priv
void rtl8723a_init_dm_priv(PADAPTER padapter);
void rtl8723a_deinit_dm_priv(PADAPTER padapter);
void rtl8723a_InitHalDm(PADAPTER padapter);
void rtl8723a_HalDmWatchDog(PADAPTER padapter);
#endif

1671
include/rtl8723a_hal.h
View file

File diff suppressed because it is too large Load diff

99
include/rtl8723a_led.h
View file

@ -1,50 +1,49 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_LED_H__
#define __RTL8723A_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8723au_InitSwLeds(PADAPTER padapter);
void rtl8723au_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8723ae_gen_RefreshLedState(PADAPTER Adapter);
void rtl8723ae_InitSwLeds(PADAPTER padapter);
void rtl8723ae_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8723as_InitSwLeds(PADAPTER padapter);
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_GSPI_HCI
void rtl8723as_InitSwLeds(PADAPTER padapter);
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_LED_H__
#define __RTL8723A_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8723au_InitSwLeds(PADAPTER padapter);
void rtl8723au_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8723ae_gen_RefreshLedState(PADAPTER Adapter);
void rtl8723ae_InitSwLeds(PADAPTER padapter);
void rtl8723ae_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8723as_InitSwLeds(PADAPTER padapter);
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_GSPI_HCI
void rtl8723as_InitSwLeds(PADAPTER padapter);
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
#endif
#endif

3
include/rtl8723a_pg.h
View file

@ -108,8 +108,7 @@ typedef enum _BT_CoType
typedef enum _BT_RadioShared
{
BT_Radio_Shared = 0,
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
#endif

81
include/rtl8723a_recv.h
View file

@ -1,41 +1,40 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_RECV_H__
#define __RTL8723A_RECV_H__
#include <rtl8192c_recv.h>
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifdef CONFIG_DIRECT_RECV
void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
s32 rtl8723as_init_recv_priv(PADAPTER padapter);
void rtl8723as_free_recv_priv(PADAPTER padapter);
#endif
void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8192c_process_phy_info(PADAPTER padapter, void *prframe);
#ifdef CONFIG_USB_HCI
void update_recvframe_attrib(union recv_frame *precvframe, struct recv_stat *prxstat);
void update_recvframe_phyinfo(union recv_frame *precvframe, struct phy_stat *pphy_info);
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_RECV_H__
#define __RTL8723A_RECV_H__
#include <rtl8192c_recv.h>
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifdef CONFIG_DIRECT_RECV
void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
s32 rtl8723as_init_recv_priv(PADAPTER padapter);
void rtl8723as_free_recv_priv(PADAPTER padapter);
#endif
void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8192c_process_phy_info(PADAPTER padapter, void *prframe);
#ifdef CONFIG_USB_HCI
void update_recvframe_attrib(union recv_frame *precvframe, struct recv_stat *prxstat);
void update_recvframe_phyinfo(union recv_frame *precvframe, struct phy_stat *pphy_info);
#endif
#endif

1
include/rtl8723a_rf.h
View file

@ -24,4 +24,3 @@
int PHY_RF6052_Config8723A( IN PADAPTER Adapter );
#endif

1061
include/rtl8723a_spec.h
View file

File diff suppressed because it is too large Load diff

3
include/rtl8723a_sreset.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -31,4 +31,3 @@ extern void rtl8723a_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8723a_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

471
include/rtl8723a_xmit.h
View file

@ -1,236 +1,235 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_XMIT_H__
#define __RTL8723A_XMIT_H__
#include <rtl8192c_xmit.h>
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
//OFFSET 8
#define AGG_EN BIT(29)
//OFFSET 12
#define SEQ_SHT 16
//OFFSET 16
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
//OFFSET 20
#define SGI BIT(6)
typedef struct txdesc_8723a
{
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
u32 macid:5;
u32 agg_en:1;
u32 bk:1;
u32 rd_en:1;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
u32 rts_rc:6;
u32 data_rc:6;
u32 rsvd0812:2;
u32 bar_rty_th:2;
u32 rsvd0816:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 rsvd1615:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 mcsg4_max_len:4;
u32 mcsg5_max_len:4;
u32 mcsg6_max_len:4;
u32 mcs15_sgi_max_len:4;
}TXDESC, *PTXDESC;
#define txdesc_set_ccx_sw_8723a(txdesc, value) \
do { \
((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \
} while (0)
struct txrpt_ccx_8723a {
/* offset 0 */
u8 tag1:1;
u8 rsvd:4;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:5;
u8 pkt_drop:1;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8723a(void *buf);
void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf);
#else
#define dump_txrpt_ccx_8723a(buf) do {} while (0)
#define handle_txrpt_ccx_8723a(adapter, buf) do {} while (0)
#endif //CONFIG_XMIT_ACK
void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8723a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8723as_init_xmit_priv(PADAPTER padapter);
void rtl8723as_free_xmit_priv(PADAPTER padapter);
s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8723as_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8723as_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8723as_xmit_thread(thread_context context);
#define hal_xmit_handler rtl8723as_xmit_buf_handler
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8723au_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8723au_xmit_buf_handler
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_XMIT_H__
#define __RTL8723A_XMIT_H__
#include <rtl8192c_xmit.h>
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
//OFFSET 8
#define AGG_EN BIT(29)
//OFFSET 12
#define SEQ_SHT 16
//OFFSET 16
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
//OFFSET 20
#define SGI BIT(6)
typedef struct txdesc_8723a
{
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
u32 macid:5;
u32 agg_en:1;
u32 bk:1;
u32 rd_en:1;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
u32 rts_rc:6;
u32 data_rc:6;
u32 rsvd0812:2;
u32 bar_rty_th:2;
u32 rsvd0816:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 rsvd1615:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 mcsg4_max_len:4;
u32 mcsg5_max_len:4;
u32 mcsg6_max_len:4;
u32 mcs15_sgi_max_len:4;
}TXDESC, *PTXDESC;
#define txdesc_set_ccx_sw_8723a(txdesc, value) \
do { \
((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \
} while (0)
struct txrpt_ccx_8723a {
/* offset 0 */
u8 tag1:1;
u8 rsvd:4;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:5;
u8 pkt_drop:1;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8723a(void *buf);
void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf);
#else
#define dump_txrpt_ccx_8723a(buf) do {} while (0)
#define handle_txrpt_ccx_8723a(adapter, buf) do {} while (0)
#endif //CONFIG_XMIT_ACK
void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8723a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8723as_init_xmit_priv(PADAPTER padapter);
void rtl8723as_free_xmit_priv(PADAPTER padapter);
s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8723as_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8723as_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8723as_xmit_thread(thread_context context);
#define hal_xmit_handler rtl8723as_xmit_buf_handler
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8723au_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8723au_xmit_buf_handler
#endif
#endif

33
include/rtw_android.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -17,7 +17,7 @@
*
*
******************************************************************************/
#ifndef __RTW_ANDROID_H__
#define __RTW_ANDROID_H__
@ -25,28 +25,28 @@
#include <linux/netdevice.h>
enum ANDROID_WIFI_CMD {
ANDROID_WIFI_CMD_START,
ANDROID_WIFI_CMD_STOP,
ANDROID_WIFI_CMD_START,
ANDROID_WIFI_CMD_STOP,
ANDROID_WIFI_CMD_SCAN_ACTIVE,
ANDROID_WIFI_CMD_SCAN_PASSIVE,
ANDROID_WIFI_CMD_RSSI,
ANDROID_WIFI_CMD_SCAN_PASSIVE,
ANDROID_WIFI_CMD_RSSI,
ANDROID_WIFI_CMD_LINKSPEED,
ANDROID_WIFI_CMD_RXFILTER_START,
ANDROID_WIFI_CMD_RXFILTER_STOP,
ANDROID_WIFI_CMD_RXFILTER_ADD,
ANDROID_WIFI_CMD_RXFILTER_STOP,
ANDROID_WIFI_CMD_RXFILTER_ADD,
ANDROID_WIFI_CMD_RXFILTER_REMOVE,
ANDROID_WIFI_CMD_BTCOEXSCAN_START,
ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
ANDROID_WIFI_CMD_BTCOEXMODE,
ANDROID_WIFI_CMD_SETSUSPENDOPT,
ANDROID_WIFI_CMD_P2P_DEV_ADDR,
ANDROID_WIFI_CMD_SETFWPATH,
ANDROID_WIFI_CMD_SETBAND,
ANDROID_WIFI_CMD_GETBAND,
ANDROID_WIFI_CMD_COUNTRY,
ANDROID_WIFI_CMD_P2P_DEV_ADDR,
ANDROID_WIFI_CMD_SETFWPATH,
ANDROID_WIFI_CMD_SETBAND,
ANDROID_WIFI_CMD_GETBAND,
ANDROID_WIFI_CMD_COUNTRY,
ANDROID_WIFI_CMD_P2P_SET_NOA,
ANDROID_WIFI_CMD_P2P_GET_NOA,
ANDROID_WIFI_CMD_P2P_SET_PS,
ANDROID_WIFI_CMD_P2P_GET_NOA,
ANDROID_WIFI_CMD_P2P_SET_PS,
ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
#ifdef PNO_SUPPORT
ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
@ -61,7 +61,7 @@ enum ANDROID_WIFI_CMD {
ANDROID_WIFI_CMD_WFD_ENABLE,
ANDROID_WIFI_CMD_WFD_DISABLE,
ANDROID_WIFI_CMD_WFD_SET_TCPPORT,
ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,
ANDROID_WIFI_CMD_WFD_SET_DEVTYPE,
@ -87,4 +87,3 @@ static void rtw_android_wifictrl_func_del(void) {}
#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
#endif //__RTW_ANDROID_H__

127
include/rtw_ap.h
View file

@ -1,64 +1,63 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_AP_H_
#define __RTW_AP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_AP_MODE
//external function
extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
void init_mlme_ap_info(_adapter *padapter);
void free_mlme_ap_info(_adapter *padapter);
//void update_BCNTIM(_adapter *padapter);
void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level);
void expire_timeout_chk(_adapter *padapter);
void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len);
void rtw_set_macaddr_acl(_adapter *padapter, int mode);
int rtw_acl_add_sta(_adapter *padapter, u8 *addr);
int rtw_acl_remove_sta(_adapter *padapter, u8 *addr);
#ifdef CONFIG_NATIVEAP_MLME
void associated_clients_update(_adapter *padapter, u8 updated);
void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
void sta_info_update(_adapter *padapter, struct sta_info *psta);
void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason);
int rtw_sta_flush(_adapter *padapter);
int rtw_ap_inform_ch_switch (_adapter *padapter, u8 new_ch, u8 ch_offset);
void start_ap_mode(_adapter *padapter);
void stop_ap_mode(_adapter *padapter);
#endif
#endif //end of CONFIG_AP_MODE
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_AP_H_
#define __RTW_AP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_AP_MODE
//external function
extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
void init_mlme_ap_info(_adapter *padapter);
void free_mlme_ap_info(_adapter *padapter);
//void update_BCNTIM(_adapter *padapter);
void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level);
void expire_timeout_chk(_adapter *padapter);
void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len);
void rtw_set_macaddr_acl(_adapter *padapter, int mode);
int rtw_acl_add_sta(_adapter *padapter, u8 *addr);
int rtw_acl_remove_sta(_adapter *padapter, u8 *addr);
#ifdef CONFIG_NATIVEAP_MLME
void associated_clients_update(_adapter *padapter, u8 updated);
void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
void sta_info_update(_adapter *padapter, struct sta_info *psta);
void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason);
int rtw_sta_flush(_adapter *padapter);
int rtw_ap_inform_ch_switch (_adapter *padapter, u8 new_ch, u8 ch_offset);
void start_ap_mode(_adapter *padapter);
void stop_ap_mode(_adapter *padapter);
#endif
#endif //end of CONFIG_AP_MODE
#endif

7
include/rtw_br_ext.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -21,7 +21,7 @@
#define _RTW_BR_EXT_H_
#if 1 // rtw_wifi_driver
#define CL_IPV6_PASS 1
#define CL_IPV6_PASS 1
#define MACADDRLEN 6
#define _DEBUG_ERR DBG_8192C
#define _DEBUG_INFO //DBG_8192C
@ -49,7 +49,7 @@ struct nat25_network_db_entry
atomic_t use_count;
unsigned char macAddr[6];
unsigned long ageing_timer;
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
};
enum NAT25_METHOD {
@ -73,4 +73,3 @@ struct br_ext_info {
void nat25_db_cleanup(_adapter *priv);
#endif // _RTW_BR_EXT_H_

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