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rtl8188eu: Remove trailing white space from all source files

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-05-18 23:28:07 -05:00
parent 77e736c66a
commit f5f3863bc5
205 changed files with 55371 additions and 55581 deletions
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13
core/rtw_ap.c
View file

@ -28,7 +28,7 @@
#ifdef CONFIG_AP_MODE
extern unsigned char RTW_WPA_OUI[];
extern unsigned char WMM_OUI[];
extern unsigned char WMM_OUI[];
extern unsigned char WPS_OUI[];
extern unsigned char P2P_OUI[];
extern unsigned char WFD_OUI[];
@ -1825,7 +1825,7 @@ static void update_bcn_vendor_spec_ie(_adapter *padapter, u8*oui)
else
{
DBG_871X("unknown OUI type!\n");
}
}
}
@ -2053,7 +2053,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_preamble++;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
(pmlmepriv->num_sta_no_short_preamble == 1))
(pmlmepriv->num_sta_no_short_preamble == 1))
{
beacon_updated = _TRUE;
update_beacon(padapter, 0xFF, NULL, _TRUE);
@ -2070,7 +2070,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_preamble--;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
(pmlmepriv->num_sta_no_short_preamble == 0))
(pmlmepriv->num_sta_no_short_preamble == 0))
{
beacon_updated = _TRUE;
update_beacon(padapter, 0xFF, NULL, _TRUE);
@ -2121,7 +2121,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_slot_time++;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
(pmlmepriv->num_sta_no_short_slot_time == 1))
(pmlmepriv->num_sta_no_short_slot_time == 1))
{
beacon_updated = _TRUE;
update_beacon(padapter, 0xFF, NULL, _TRUE);
@ -2138,7 +2138,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_slot_time--;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
(pmlmepriv->num_sta_no_short_slot_time == 0))
(pmlmepriv->num_sta_no_short_slot_time == 0))
{
beacon_updated = _TRUE;
update_beacon(padapter, 0xFF, NULL, _TRUE);
@ -2599,4 +2599,3 @@ void stop_ap_mode(_adapter *padapter)
#endif //CONFIG_NATIVEAP_MLME
#endif //CONFIG_AP_MODE

3
core/rtw_br_ext.c
View file

@ -1410,7 +1410,7 @@ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method)
}
/*---------------------------------------------------*/
/* Handle IPV6 frame */
/* Handle IPV6 frame */
/*---------------------------------------------------*/
#ifdef CL_IPV6_PASS
else if (protocol == __constant_htons(ETH_P_IPV6))
@ -1669,4 +1669,3 @@ void *scdb_findEntry(_adapter *priv, unsigned char *macAddr,
}
#endif // CONFIG_BR_EXT

55
core/rtw_cmd.c
View file

@ -648,7 +648,7 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action)
{
struct cmd_obj* ph2c;
struct usb_suspend_parm* psetusbsuspend;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 ret = _SUCCESS;
@ -691,7 +691,7 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num,
u8 res = _FAIL;
struct cmd_obj *ph2c;
struct sitesurvey_parm *psurveyPara;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
@ -869,7 +869,7 @@ u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch)
{
struct cmd_obj* ph2c;
struct setphy_parm* psetphypara;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
// struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
// struct registry_priv* pregistry_priv = &padapter->registrypriv;
u8 res=_SUCCESS;
@ -906,7 +906,7 @@ u8 rtw_setbbreg_cmd(_adapter*padapter, u8 offset, u8 val)
{
struct cmd_obj* ph2c;
struct writeBB_parm* pwritebbparm;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
@ -937,7 +937,7 @@ u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
{
struct cmd_obj* ph2c;
struct readBB_parm* prdbbparm;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
@ -972,7 +972,7 @@ u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val)
{
struct cmd_obj* ph2c;
struct writeRF_parm* pwriterfparm;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj));
@ -1003,7 +1003,7 @@ u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
{
struct cmd_obj* ph2c;
struct readRF_parm* prdrfparm;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
@ -1072,7 +1072,7 @@ _func_exit_;
u8 rtw_createbss_cmd(_adapter *padapter)
{
struct cmd_obj* pcmd;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network;
u8 res=_SUCCESS;
@ -1121,7 +1121,7 @@ _func_exit_;
u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz)
{
struct cmd_obj* pcmd;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
@ -1420,12 +1420,12 @@ u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key)
{
struct cmd_obj* ph2c;
struct set_stakey_parm *psetstakey_para;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct set_stakey_rsp *psetstakey_rsp = NULL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct sta_info* sta = (struct sta_info* )psta;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct sta_info* sta = (struct sta_info* )psta;
u8 res=_SUCCESS;
_func_enter_;
@ -1495,11 +1495,11 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, u8 *psta, u8 entry, u8 enqueue)
{
struct cmd_obj* ph2c;
struct set_stakey_parm *psetstakey_para;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct set_stakey_rsp *psetstakey_rsp = NULL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct sta_info* sta = (struct sta_info* )psta;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct sta_info* sta = (struct sta_info* )psta;
u8 res=_SUCCESS;
_func_enter_;
@ -1556,7 +1556,7 @@ u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table)
{
struct cmd_obj* ph2c;
struct setratable_parm * psetrttblparm;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
@ -1588,7 +1588,7 @@ u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval)
{
struct cmd_obj* ph2c;
struct getratable_parm * pgetrttblparm;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
u8 res=_SUCCESS;
_func_enter_;
@ -1625,7 +1625,7 @@ _func_exit_;
u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr)
{
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
struct cmd_obj* ph2c;
struct set_assocsta_parm *psetassocsta_para;
struct set_stakey_rsp *psetassocsta_rsp = NULL;
@ -1909,7 +1909,7 @@ u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no)
{
struct cmd_obj* pcmdobj;
struct SetChannelSwitch_param*setChannelSwitch_param;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res=_SUCCESS;
@ -1947,7 +1947,7 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
{
struct cmd_obj* pcmdobj;
struct TDLSoption_param *TDLSoption;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res=_SUCCESS;
@ -2340,7 +2340,7 @@ u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue)
struct cmd_obj *ph2c;
struct drvextra_cmd_parm *pdrvextra_cmd_parm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 bSupportAntDiv = _FALSE;
u8 bSupportAntDiv = _FALSE;
u8 res = _SUCCESS;
_func_enter_;
@ -2731,7 +2731,7 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
void rtw_survey_cmd_callback(_adapter* padapter , struct cmd_obj *pcmd)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
_func_enter_;
@ -2754,7 +2754,7 @@ _func_exit_;
void rtw_disassoc_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd)
{
_irqL irqL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
_func_enter_;
@ -2784,7 +2784,7 @@ _func_exit_;
void rtw_joinbss_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
_func_enter_;
@ -2811,7 +2811,7 @@ void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd)
u8 timer_cancelled;
struct sta_info *psta = NULL;
struct wlan_network *pwlan = NULL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)pcmd->parmbuf;
struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
@ -2828,7 +2828,7 @@ _func_enter_;
#ifdef CONFIG_FW_MLMLE
//endian_convert
pnetwork->Length = le32_to_cpu(pnetwork->Length);
pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
pnetwork->Privacy =le32_to_cpu(pnetwork->Privacy);
pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi);
pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse);
@ -2890,7 +2890,7 @@ _func_enter_;
//rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);
// copy pdev_network information to pmlmepriv->cur_network
// copy pdev_network information to pmlmepriv->cur_network
_rtw_memcpy(&tgt_network->network, pnetwork, (get_WLAN_BSSID_EX_sz(pnetwork)));
// reset DSConfig
@ -2986,4 +2986,3 @@ _func_enter_;
_func_exit_;
}

7
core/rtw_debug.c
View file

@ -469,7 +469,7 @@ int proc_get_bb_reg_dump1(char *page, char **start,
len += snprintf(page + len, count - len, "\n======= BB REG =======\n");
for (i=0x800;i<0xB00;i+=4)
{
if (j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
if (j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
if ((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
}
@ -489,7 +489,7 @@ int proc_get_bb_reg_dump2(char *page, char **start,
len += snprintf(page + len, count - len, "\n======= BB REG =======\n");
for (i=0xB00;i<0xE00;i+=4)
{
if (j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
if (j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
if ((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
}
@ -509,7 +509,7 @@ int proc_get_bb_reg_dump3(char *page, char **start,
len += snprintf(page + len, count - len, "\n======= BB REG =======\n");
for (i=0xE00;i<0x1000;i+=4)
{
if (j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
if (j%4==1) len += snprintf(page + len, count - len,"0x%02x",i);
len += snprintf(page + len, count - len," 0x%08x ",rtw_read32(padapter,i));
if ((j++)%4 == 0) len += snprintf(page + len, count - len,"\n");
}
@ -1166,4 +1166,3 @@ int proc_set_btcoex_dbg(struct file *file, const char __user *buffer,
#endif /* CONFIG_BT_COEXIST */
#endif

52
core/rtw_efuse.c
View file

@ -77,12 +77,12 @@ BOOLEAN
Efuse_Write1ByteToFakeContent(
IN PADAPTER pAdapter,
IN u16 Offset,
IN u8 Value );
IN u8 Value );
BOOLEAN
Efuse_Write1ByteToFakeContent(
IN PADAPTER pAdapter,
IN u16 Offset,
IN u8 Value )
IN u8 Value )
{
if (Offset >= EFUSE_MAX_HW_SIZE)
{
@ -112,7 +112,7 @@ Efuse_Write1ByteToFakeContent(
*
* Revised History:
* When Who Remark
* 11/17/2008 MHC Create Version 0.
* 11/17/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
VOID
@ -137,7 +137,7 @@ Efuse_PowerSwitch(
*
* Revised History:
* When Who Remark
* 11/16/2008 MHC Create Version 0.
* 11/16/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
u16
@ -179,8 +179,8 @@ Efuse_CalculateWordCnts(IN u8 word_en)
VOID
ReadEFuseByte(
PADAPTER Adapter,
u16 _offset,
u8 *pbuf,
u16 _offset,
u8 *pbuf,
IN BOOLEAN bPseudoTest)
{
u32 value32;
@ -238,7 +238,7 @@ ReadEFuseByte(
//
// Created by Roger, 2008.10.21.
//
// 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description.
// 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description.
// 2. Add efuse utilization collect.
// 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1
// write addr must be after sec5.
@ -249,8 +249,8 @@ efuse_ReadEFuse(
PADAPTER Adapter,
u8 efuseType,
u16 _offset,
u16 _size_byte,
u8 *pbuf,
u16 _size_byte,
u8 *pbuf,
IN BOOLEAN bPseudoTest
);
VOID
@ -258,8 +258,8 @@ efuse_ReadEFuse(
PADAPTER Adapter,
u8 efuseType,
u16 _offset,
u16 _size_byte,
u8 *pbuf,
u16 _size_byte,
u8 *pbuf,
IN BOOLEAN bPseudoTest
)
{
@ -291,7 +291,7 @@ EFUSE_GetEfuseDefinition(
*
* Revised History:
* When Who Remark
* 09/23/2008 MHC Copy from WMAC.
* 09/23/2008 MHC Copy from WMAC.
*
*---------------------------------------------------------------------------*/
u8
@ -355,7 +355,7 @@ EFUSE_Read1Byte(
*
* Revised History:
* When Who Remark
* 09/23/2008 MHC Copy from WMAC.
* 09/23/2008 MHC Copy from WMAC.
*
*---------------------------------------------------------------------------*/
@ -512,7 +512,7 @@ Efuse_PgPacketRead( IN PADAPTER pAdapter,
int
Efuse_PgPacketWrite(IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *data,
IN BOOLEAN bPseudoTest)
@ -527,7 +527,7 @@ Efuse_PgPacketWrite(IN PADAPTER pAdapter,
int
Efuse_PgPacketWrite_BT(IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *data,
IN BOOLEAN bPseudoTest)
@ -552,8 +552,8 @@ Efuse_PgPacketWrite_BT(IN PADAPTER pAdapter,
*
* Revised History:
* When Who Remark
* 11/16/2008 MHC Create Version 0.
* 11/21/2008 MHC Fix Write bug when we only enable late word.
* 11/16/2008 MHC Create Version 0.
* 11/21/2008 MHC Fix Write bug when we only enable late word.
*
*---------------------------------------------------------------------------*/
void
@ -911,7 +911,7 @@ exit:
*
* Revised History:
* When Who Remark
* 11/11/2008 MHC Create Version 0.
* 11/11/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
VOID
@ -953,7 +953,7 @@ Efuse_ReadAllMap(
*
* Revised History:
* When Who Remark
* 11/12/2008 MHC Create Version 0.
* 11/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
static VOID
@ -1014,7 +1014,7 @@ efuse_ShadowRead4Byte(
*
* Revised History:
* When Who Remark
* 11/12/2008 MHC Create Version 0.
* 11/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
#ifdef PLATFORM
@ -1022,13 +1022,13 @@ static VOID
efuse_ShadowWrite1Byte(
IN PADAPTER pAdapter,
IN u16 Offset,
IN u8 Value);
IN u8 Value);
#endif //PLATFORM
static VOID
efuse_ShadowWrite1Byte(
IN PADAPTER pAdapter,
IN u16 Offset,
IN u8 Value)
IN u8 Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
@ -1041,7 +1041,7 @@ static VOID
efuse_ShadowWrite2Byte(
IN PADAPTER pAdapter,
IN u16 Offset,
IN u16 Value)
IN u16 Value)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
@ -1079,7 +1079,7 @@ efuse_ShadowWrite4Byte(
*
* Revised History:
* When Who Remark
* 11/13/2008 MHC Create Version 0.
* 11/13/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void EFUSE_ShadowMapUpdate(
@ -1128,7 +1128,7 @@ void EFUSE_ShadowMapUpdate(
*
* Revised History:
* When Who Remark
* 11/12/2008 MHC Create Version 0.
* 11/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void
@ -1160,7 +1160,7 @@ EFUSE_ShadowRead(
*
* Revised History:
* When Who Remark
* 11/12/2008 MHC Create Version 0.
* 11/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
VOID

19
core/rtw_ieee80211.c
View file

@ -50,13 +50,13 @@ u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 };
// for adhoc-master to generate ie and provide supported-rate to fw
//-----------------------------------------------------------
static u8 WIFI_CCKRATES[] =
static u8 WIFI_CCKRATES[] =
{(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),
(IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),
(IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),
(IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)};
static u8 WIFI_OFDMRATES[] =
static u8 WIFI_OFDMRATES[] =
{(IEEE80211_OFDM_RATE_6MB),
(IEEE80211_OFDM_RATE_9MB),
(IEEE80211_OFDM_RATE_12MB),
@ -128,7 +128,7 @@ int rtw_check_network_type(unsigned char *rate, int ratelen, int channel)
if ((rtw_is_cckratesonly_included(rate)) == _TRUE)
return WIRELESS_11B;
else if ((rtw_is_cckrates_included(rate)) == _TRUE)
return WIRELESS_11BG;
return WIRELESS_11BG;
else
return WIRELESS_11G;
}
@ -406,7 +406,7 @@ _func_exit_;
int rtw_generate_ie(struct registry_priv *pregistrypriv)
{
u8 wireless_mode;
int sz = 0, rateLen;
int sz = 0, rateLen;
WLAN_BSSID_EX* pdev_network = &pregistrypriv->dev_network;
u8* ie = pdev_network->IEs;
@ -644,7 +644,7 @@ int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis
if (count == 0 || left < count * WPA_SELECTOR_LEN) {
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), "
"count %u left %u", __func__, count, left));
"count %u left %u", __func__, count, left));
return _FAIL;
}
@ -722,7 +722,7 @@ int rtw_parse_wpa2_ie(u8* rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwi
if (count == 0 || left < count * RSN_SELECTOR_LEN) {
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), "
"count %u left %u", __func__, count, left));
"count %u left %u", __func__, count, left));
return _FAIL;
}
@ -760,7 +760,7 @@ int rtw_parse_wpa2_ie(u8* rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwi
int rtw_get_wapi_ie(u8 *in_ie,uint in_len,u8 *wapi_ie,u16 *wapi_len)
{
u8 authmode, i;
uint cnt;
uint cnt;
u8 wapi_oui1[4]={0x0,0x14,0x72,0x01};
u8 wapi_oui2[4]={0x0,0x14,0x72,0x02};
@ -772,7 +772,7 @@ _func_enter_;
//if (authmode==_WAPI_IE_)
if (authmode==_WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt+6], wapi_oui1,4)==_TRUE ||
_rtw_memcmp(&in_ie[cnt+6], wapi_oui2,4)==_TRUE))
_rtw_memcmp(&in_ie[cnt+6], wapi_oui2,4)==_TRUE))
{
if (wapi_ie) {
_rtw_memcpy(wapi_ie, &in_ie[cnt],in_ie[cnt+1]+2);
@ -804,7 +804,7 @@ int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16
{
u8 authmode, sec_idx, i;
u8 wpa_oui[4]={0x0,0x50,0xf2,0x01};
uint cnt;
uint cnt;
_func_enter_;
@ -1992,4 +1992,3 @@ const char *action_public_str(u8 action)
action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;
return _action_public_str[action];
}

38
core/rtw_io.c
View file

@ -75,12 +75,12 @@ jackson@realtek.com.tw
#endif
#ifdef CONFIG_SDIO_HCI
#define rtw_le16_to_cpu(val) val
#define rtw_le16_to_cpu(val) val
#define rtw_le32_to_cpu(val) val
#define rtw_cpu_to_le16(val) val
#define rtw_cpu_to_le32(val) val
#else
#define rtw_le16_to_cpu(val) le16_to_cpu(val)
#define rtw_le16_to_cpu(val) le16_to_cpu(val)
#define rtw_le32_to_cpu(val) le32_to_cpu(val)
#define rtw_cpu_to_le16(val) cpu_to_le16(val)
#define rtw_cpu_to_le32(val) cpu_to_le32(val)
@ -90,7 +90,7 @@ jackson@realtek.com.tw
u8 _rtw_read8(_adapter *adapter, u32 addr)
{
u8 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
@ -105,10 +105,10 @@ u8 _rtw_read8(_adapter *adapter, u32 addr)
u16 _rtw_read16(_adapter *adapter, u32 addr)
{
u16 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read16 = pintfhdl->io_ops._read16;
@ -120,10 +120,10 @@ u16 _rtw_read16(_adapter *adapter, u32 addr)
u32 _rtw_read32(_adapter *adapter, u32 addr)
{
u32 r_val;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
_func_enter_;
_read32 = pintfhdl->io_ops._read32;
@ -135,7 +135,7 @@ u32 _rtw_read32(_adapter *adapter, u32 addr)
int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
@ -150,7 +150,7 @@ int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
}
int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
@ -166,7 +166,7 @@ int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
}
int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
@ -183,7 +183,7 @@ int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata);
@ -198,7 +198,7 @@ int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
}
int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
@ -213,7 +213,7 @@ int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
}
int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
@ -228,7 +228,7 @@ int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
}
int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
@ -245,7 +245,7 @@ int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
@ -268,7 +268,7 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
@ -285,7 +285,7 @@ void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
@ -321,7 +321,7 @@ void _rtw_read_port_cancel(_adapter *adapter)
u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 ret = _SUCCESS;
@ -479,5 +479,3 @@ int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const cha
return _rtw_writeN(adapter, addr, length, data);
}
#endif

3
core/rtw_ioctl_query.c
View file

@ -61,7 +61,7 @@ query_802_11_capability(
pCap->Length = sizeof(NDIS_802_11_CAPABILITY);
if (ulNumOfPairSupported > 1 )
pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
pCap->Version = 2;
pCap->NoOfPMKIDs = NUM_PMKID_CACHE;
@ -193,4 +193,3 @@ _func_exit_;
return _TRUE;
}
#endif

7
core/rtw_ioctl_set.c
View file

@ -147,7 +147,7 @@ _func_enter_;
{
// submit createbss_cmd to change to a ADHOC_MASTER
//pmlmepriv->lock has been acquired by caller...
//pmlmepriv->lock has been acquired by caller...
WLAN_BSSID_EX *pdev_network = &(padapter->registrypriv.dev_network);
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
@ -168,7 +168,7 @@ _func_enter_;
goto exit;
}
pmlmepriv->to_join = _FALSE;
pmlmepriv->to_join = _FALSE;
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode***\n "));
@ -415,7 +415,7 @@ u8 rtw_set_802_11_ssid(_adapter* padapter, NDIS_802_11_SSID *ssid)
_func_enter_;
DBG_871X_LEVEL(_drv_always_, "set ssid [%s] fw_state=0x%08x\n",
ssid->Ssid, get_fwstate(pmlmepriv));
ssid->Ssid, get_fwstate(pmlmepriv));
if (padapter->hw_init_completed==_FALSE){
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
@ -1434,4 +1434,3 @@ int rtw_set_country(_adapter *adapter, const char *country_code)
return rtw_set_channel_plan(adapter, channel_plan);
}

1
core/rtw_iol.c
View file

@ -400,4 +400,3 @@ int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
#endif //CONFIG_IOL

73
core/rtw_led.c
View file

@ -268,7 +268,7 @@ SwLedBlink1(
#endif
struct led_priv *ledpriv = &(padapter->ledpriv);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
PLED_871x pLed1 = &(ledpriv->SwLed1);
PLED_871x pLed1 = &(ledpriv->SwLed1);
u8 bStopBlinking = _FALSE;
#ifndef CONFIG_LED_REMOVE_HAL
@ -656,7 +656,7 @@ SwLedBlink3(
}
else
{
if ( pLed->bLedOn )
if ( pLed->bLedOn )
pLed->BlinkingLedState = RTW_LED_OFF;
else
pLed->BlinkingLedState = RTW_LED_ON;
@ -770,7 +770,7 @@ SwLedBlink4(
_adapter *padapter = pLed->padapter;
struct led_priv *ledpriv = &(padapter->ledpriv);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
PLED_871x pLed1 = &(ledpriv->SwLed1);
PLED_871x pLed1 = &(ledpriv->SwLed1);
u8 bStopBlinking = _FALSE;
// Change LED according to BlinkingLedState specified.
@ -1252,11 +1252,11 @@ SwLedControlMode1(
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedLinkBlinkInProgress = _FALSE;
}
if (pLed->bLedBlinkInProgress ==_TRUE)
if (pLed->bLedBlinkInProgress ==_TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedBlinkInProgress = _FALSE;
}
}
pLed->bLedNoLinkBlinkInProgress = _TRUE;
pLed->CurrLedState = LED_BLINK_SLOWLY;
@ -1284,7 +1284,7 @@ SwLedControlMode1(
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedBlinkInProgress = _FALSE;
}
}
pLed->bLedLinkBlinkInProgress = _TRUE;
pLed->CurrLedState = LED_BLINK_NORMAL;
if ( pLed->bLedOn )
@ -1297,13 +1297,13 @@ SwLedControlMode1(
case LED_CTL_SITE_SURVEY:
if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
;
;
else if (pLed->bLedScanBlinkInProgress ==_FALSE)
{
if (IS_LED_WPS_BLINKING(pLed))
if (IS_LED_WPS_BLINKING(pLed))
return;
if (pLed->bLedNoLinkBlinkInProgress == _TRUE)
if (pLed->bLedNoLinkBlinkInProgress == _TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedNoLinkBlinkInProgress = _FALSE;
@ -1313,7 +1313,7 @@ SwLedControlMode1(
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedLinkBlinkInProgress = _FALSE;
}
if (pLed->bLedBlinkInProgress ==_TRUE)
if (pLed->bLedBlinkInProgress ==_TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedBlinkInProgress = _FALSE;
@ -1501,19 +1501,19 @@ SwLedControlMode2(
{
struct led_priv *ledpriv = &(padapter->ledpriv);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
PLED_871x pLed = &(ledpriv->SwLed0);
PLED_871x pLed = &(ledpriv->SwLed0);
switch (LedAction)
{
case LED_CTL_SITE_SURVEY:
if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
;
;
else if (pLed->bLedScanBlinkInProgress ==_FALSE)
{
if (IS_LED_WPS_BLINKING(pLed))
if (IS_LED_WPS_BLINKING(pLed))
return;
if (pLed->bLedBlinkInProgress ==_TRUE)
if (pLed->bLedBlinkInProgress ==_TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedBlinkInProgress = _FALSE;
@ -1531,9 +1531,9 @@ SwLedControlMode2(
case LED_CTL_TX:
case LED_CTL_RX:
if ((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
{
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
if ((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
{
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
{
return;
}
@ -1696,9 +1696,9 @@ SwLedControlMode2(
case LED_CTL_TX:
case LED_CTL_RX:
if ((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
{
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
if ((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
{
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
{
return;
}
@ -1869,16 +1869,16 @@ SwLedControlMode4(
{
return;
}
if (pLed->bLedBlinkInProgress ==_TRUE)
if (pLed->bLedBlinkInProgress ==_TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedBlinkInProgress = _FALSE;
}
if (pLed->bLedNoLinkBlinkInProgress ==_TRUE)
}
if (pLed->bLedNoLinkBlinkInProgress ==_TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedNoLinkBlinkInProgress = _FALSE;
}
}
pLed->bLedStartToLinkBlinkInProgress = _TRUE;
pLed->CurrLedState = LED_BLINK_StartToBlink;
@ -1919,11 +1919,11 @@ SwLedControlMode4(
{
return;
}
if (pLed->bLedBlinkInProgress ==_TRUE)
if (pLed->bLedBlinkInProgress ==_TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedBlinkInProgress = _FALSE;
}
}
pLed->bLedNoLinkBlinkInProgress = _TRUE;
pLed->CurrLedState = LED_BLINK_SLOWLY;
@ -1966,13 +1966,13 @@ SwLedControlMode4(
case LED_CTL_TX:
case LED_CTL_RX:
if (pLed->bLedBlinkInProgress ==_FALSE)
{
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
if (pLed->bLedBlinkInProgress ==_FALSE)
{
if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
{
return;
}
if (pLed->bLedNoLinkBlinkInProgress == _TRUE)
if (pLed->bLedNoLinkBlinkInProgress == _TRUE)
{
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedNoLinkBlinkInProgress = _FALSE;
@ -2191,7 +2191,7 @@ SwLedControlMode5(
{
case LED_CTL_POWER_ON:
case LED_CTL_NO_LINK:
case LED_CTL_LINK: //solid blue
case LED_CTL_LINK: //solid blue
pLed->CurrLedState = RTW_LED_ON;
pLed->BlinkingLedState = RTW_LED_ON;
@ -2221,9 +2221,9 @@ SwLedControlMode5(
case LED_CTL_TX:
case LED_CTL_RX:
if (pLed->bLedBlinkInProgress ==_FALSE)
{
if (pLed->CurrLedState == LED_BLINK_SCAN)
if (pLed->bLedBlinkInProgress ==_FALSE)
{
if (pLed->CurrLedState == LED_BLINK_SCAN)
{
return;
}
@ -2356,7 +2356,7 @@ LedControl871x(
struct led_priv *ledpriv = &(padapter->ledpriv);
if ( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)
||(padapter->hw_init_completed == _FALSE) )
||(padapter->hw_init_completed == _FALSE) )
{
return;
}
@ -2393,7 +2393,7 @@ LedControl871x(
break;
case SW_LED_MODE2:
SwLedControlMode2(padapter, LedAction);
break;
break;
case SW_LED_MODE3:
SwLedControlMode3(padapter, LedAction);
@ -2419,4 +2419,3 @@ LedControl871x(
}
#endif

81
core/rtw_mlme.c
View file

@ -636,9 +636,9 @@ _func_enter_;
#ifdef PLATFORM_OS_XP
if ( ((uint)dst) <= 0x7fffffff ||
((uint)src) <= 0x7fffffff ||
((uint)&s_cap) <= 0x7fffffff ||
((uint)&d_cap) <= 0x7fffffff)
((uint)src) <= 0x7fffffff ||
((uint)&s_cap) <= 0x7fffffff ||
((uint)&d_cap) <= 0x7fffffff)
{
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n@@@@ error address of dst\n"));
@ -985,10 +985,10 @@ int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
}
if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {
if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {
DBG_871X("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy);
bselected = _FALSE;
}
}
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
{
@ -1026,8 +1026,8 @@ _func_enter_;
#ifdef CONFIG_RTL8712
//endian_convert
pnetwork->Length = le32_to_cpu(pnetwork->Length);
pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
pnetwork->Length = le32_to_cpu(pnetwork->Length);
pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
pnetwork->Privacy =le32_to_cpu( pnetwork->Privacy);
pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi);
pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse);
@ -1078,7 +1078,7 @@ _func_enter_;
// lock pmlmepriv->lock when you accessing network_q
if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE)
{
if ( pnetwork->Ssid.Ssid[0] == 0 )
if ( pnetwork->Ssid.Ssid[0] == 0 )
{
pnetwork->Ssid.SsidLength = 0;
}
@ -1146,12 +1146,12 @@ _func_enter_;
{
set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
if (rtw_select_and_join_from_scanned_queue(pmlmepriv)==_SUCCESS)
{
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT );
}
else
{
if (rtw_select_and_join_from_scanned_queue(pmlmepriv)==_SUCCESS)
{
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT );
}
else
{
WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network);
u8 *pibss = adapter->registrypriv.dev_network.MacAddress;
@ -1166,16 +1166,16 @@ _func_enter_;
rtw_update_registrypriv_dev_network(adapter);
rtw_generate_random_ibss(pibss);
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
if (rtw_createbss_cmd(adapter)!=_SUCCESS)
{
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error=>rtw_createbss_cmd status FAIL\n"));
RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error=>rtw_createbss_cmd status FAIL\n"));
}
pmlmepriv->to_join = _FALSE;
}
}
pmlmepriv->to_join = _FALSE;
}
}
}
else
{
@ -1184,7 +1184,7 @@ _func_enter_;
pmlmepriv->to_join = _FALSE;
if (_SUCCESS == (s_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv)))
{
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
}
else if (s_ret == 2)//there is no need to wait for join
{
@ -1305,8 +1305,8 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue)
{
_irqL irqL;
struct wlan_network* pwlan = NULL;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct wlan_network *tgt_network = &pmlmepriv->cur_network;
#ifdef CONFIG_TDLS
@ -1735,12 +1735,12 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
static u8 retry=0;
u8 timer_cancelled;
struct sta_info *ptarget_sta= NULL, *pcur_sta = NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
struct wlan_network *cur_network = &(pmlmepriv->cur_network);
struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
struct wlan_network *cur_network = &(pmlmepriv->cur_network);
struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL;
unsigned int the_same_macaddr = _FALSE;
unsigned int the_same_macaddr = _FALSE;
_func_enter_;
@ -1943,7 +1943,7 @@ ignore_joinbss_callback:
void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)
{
struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
_func_enter_;
@ -2027,7 +2027,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
struct sta_info *psta;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct stassoc_event *pstassoc = (struct stassoc_event*)pbuf;
struct wlan_network *cur_network = &(pmlmepriv->cur_network);
struct wlan_network *cur_network = &(pmlmepriv->cur_network);
struct wlan_network *ptarget_wlan = NULL;
_func_enter_;
@ -2158,8 +2158,8 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
WLAN_BSSID_EX *pdev_network=NULL;
u8* pibss = NULL;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct stadel_event *pstadel = (struct stadel_event*)pbuf;
struct sta_priv *pstapriv = &adapter->stapriv;
struct stadel_event *pstadel = (struct stadel_event*)pbuf;
struct sta_priv *pstapriv = &adapter->stapriv;
struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
_func_enter_;
@ -2369,7 +2369,7 @@ _func_enter_;
{
rtw_indicate_disconnect(adapter);
free_scanqueue(pmlmepriv);//???
}
}
_exit_critical_bh(&pmlmepriv->lock, &irqL);
@ -2590,7 +2590,7 @@ void rtw_set_scan_deny(_adapter *adapter, u32 ms)
if (0)
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter->pbuddy_adapter));
b_mlmepriv = &adapter->pbuddy_adapter->mlmepriv;
b_mlmepriv = &adapter->pbuddy_adapter->mlmepriv;
ATOMIC_SET(&b_mlmepriv->set_scan_deny, 1);
_set_timer(&b_mlmepriv->set_scan_deny_timer, ms);
#endif
@ -2685,7 +2685,7 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv )
_queue *queue = &(pmlmepriv->scanned_queue);
struct wlan_network *pnetwork = NULL;
struct wlan_network *candidate = NULL;
u8 bSupportAntDiv = _FALSE;
u8 bSupportAntDiv = _FALSE;
_func_enter_;
@ -2708,7 +2708,7 @@ _func_enter_;
rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);
}
}
if (candidate == NULL) {
DBG_871X("%s: return _FAIL(candidate == NULL)\n", __func__);
@ -2893,7 +2893,7 @@ _func_enter_;
}
}
}
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
#ifdef CONFIG_LAYER2_ROAMING
if (pmlmepriv->to_roaming>0 && roaming_candidate ){
@ -2931,7 +2931,7 @@ _func_exit_;
sint rtw_set_auth(_adapter * adapter,struct security_priv *psecuritypriv)
{
struct cmd_obj* pcmd;
struct setauth_parm *psetauthparm;
struct setauth_parm *psetauthparm;
struct cmd_priv *pcmdpriv=&(adapter->cmdpriv);
sint res=_SUCCESS;
@ -3119,7 +3119,7 @@ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, u
//
// Search by BSSID,
// Return Value:
// -1 :if there is no pre-auth key in the table
// -1 :if there is no pre-auth key in the table
// >=0 :if there is pre-auth key, and return the entry id
//
//
@ -3189,12 +3189,12 @@ sint rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie, u8 *out_ie, uint in_len)
u8 authmode, securitytype, match;
u8 sec_ie[255], uncst_oui[4], bkup_ie[255];
u8 wpa_oui[4]={0x0, 0x50, 0xf2, 0x01};
uint ielength, cnt, remove_cnt;
uint ielength, cnt, remove_cnt;
int iEntry;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct security_priv *psecuritypriv=&adapter->securitypriv;
uint ndisauthmode=psecuritypriv->ndisauthtype;
uint ndisauthmode=psecuritypriv->ndisauthtype;
uint ndissecuritytype = psecuritypriv->ndisencryptstatus;
_func_enter_;
@ -3405,7 +3405,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui
struct rtw_ieee80211_ht_cap ht_capie;
unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct qos_priv *pqospriv= &pmlmepriv->qospriv;
struct qos_priv *pqospriv= &pmlmepriv->qospriv;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
@ -3790,4 +3790,3 @@ sint check_buddy_fw_link(_adapter *padapter)
return _FALSE;
}
#endif //CONFIG_CONCURRENT_MODE

69
core/rtw_mlme_ext.c
View file

@ -603,7 +603,7 @@ static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, uni
if (ptable->func)
{
//receive the frames that ra(a1) is my address or ra(a1) is bc address.
//receive the frames that ra(a1) is my address or ra(a1) is bc address.
if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) &&
!_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
{
@ -784,7 +784,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
u8 *pframe = precv_frame->u.hdr.rx_data;
uint len = precv_frame->u.hdr.len;
u8 is_valid_p2p_probereq = _FALSE;
@ -1357,9 +1357,9 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
offset = (GetPrivacy(pframe))? 4: 0;
algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));
algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));
if (status != 0)
{
@ -1455,7 +1455,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
struct sta_priv *pstapriv = &padapter->stapriv;
u8 *pframe = precv_frame->u.hdr.rx_data;
uint pkt_len = precv_frame->u.hdr.len;
@ -1610,7 +1610,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
//check RSN/WPA/WPS
pstat->dot8021xalg = 0;
pstat->wpa_psk = 0;
pstat->wpa_psk = 0;
pstat->wpa_group_cipher = 0;
pstat->wpa2_group_cipher = 0;
pstat->wpa_pairwise_cipher = 0;
@ -1726,7 +1726,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
if (psecuritypriv->wpa_psk == 0)
{
DBG_871X("STA " MAC_FMT ": WPA/RSN IE in association "
"request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr));
"request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr));
status = WLAN_STATUS_INVALID_IE;
@ -2057,7 +2057,7 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
//WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
u8 *pframe = precv_frame->u.hdr.rx_data;
uint pkt_len = precv_frame->u.hdr.len;
PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL;
@ -2202,7 +2202,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
//_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
DBG_871X_LEVEL(_drv_always_, "ap recv deauth reason code(%d) sta:%pM\n",
reason, GetAddr2Ptr(pframe));
reason, GetAddr2Ptr(pframe));
psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
if (psta)
@ -2229,7 +2229,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
#endif
{
DBG_871X_LEVEL(_drv_always_, "sta recv deauth reason code(%d) sta:%pM\n",
reason, GetAddr3Ptr(pframe));
reason, GetAddr3Ptr(pframe));
receive_disconnect(padapter, GetAddr3Ptr(pframe) ,reason);
}
@ -4481,12 +4481,12 @@ u8 is_matched_in_profilelist( u8* peermacaddr, struct profile_info* profileinfo
u8 i, match_result = 0;
DBG_871X( "[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __func__,
peermacaddr[0], peermacaddr[1],peermacaddr[2],peermacaddr[3],peermacaddr[4],peermacaddr[5]);
peermacaddr[0], peermacaddr[1],peermacaddr[2],peermacaddr[3],peermacaddr[4],peermacaddr[5]);
for ( i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++ )
{
DBG_871X( "[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __func__,
profileinfo->peermac[0], profileinfo->peermac[1],profileinfo->peermac[2],profileinfo->peermac[3],profileinfo->peermac[4],profileinfo->peermac[5]);
profileinfo->peermac[0], profileinfo->peermac[1],profileinfo->peermac[2],profileinfo->peermac[3],profileinfo->peermac[4],profileinfo->peermac[5]);
if ( _rtw_memcmp( peermacaddr, profileinfo->peermac, ETH_ALEN ) )
{
match_result = 1;
@ -4510,7 +4510,7 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
//WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
//WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
u16 beacon_interval = 100;
u16 capInfo = 0;
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
@ -6070,7 +6070,7 @@ void issue_beacon(_adapter *padapter, int timeout_ms)
#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
@ -6386,7 +6386,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
unsigned int rate_len;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
@ -8019,7 +8019,7 @@ void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char act
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
struct registry_priv *pregpriv = &padapter->registrypriv;
struct registry_priv *pregpriv = &padapter->registrypriv;
#ifdef CONFIG_BT_COEXIST
u8 tendaAPMac[] = {0xC8, 0x3A, 0x35};
#endif
@ -8850,7 +8850,7 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
u8 *pframe = precv_frame->u.hdr.rx_data;
u32 packet_len = precv_frame->u.hdr.len;
u8 ie_offset;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -9728,7 +9728,7 @@ void report_join_res(_adapter *padapter, int res)
pjoinbss_evt = (struct joinbss_event*)(pevtcmd + sizeof(struct C2HEvent_Header));
_rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res;
pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res;
DBG_871X("report_join_res(%d)\n", res);
@ -9913,7 +9913,7 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
struct sta_info *psta, *psta_bmc;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
struct sta_priv *pstapriv = &padapter->stapriv;
u8 join_type;
u16 media_status;
@ -10351,7 +10351,7 @@ void survey_timer_hdl(_adapter *padapter)
struct cmd_obj *ph2c;
struct sitesurvey_parm *psurveyPara;
struct cmd_priv *pcmdpriv=&padapter->cmdpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo= &(padapter->wdinfo);
#endif
@ -10555,7 +10555,7 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
else if (psetop->mode == Ndis802_11Infrastructure)
{
pmlmeinfo->state &= ~(BIT(0)|BIT(1));// clear state
pmlmeinfo->state |= WIFI_FW_STATION_STATE;//set to STATION_STATE
pmlmeinfo->state |= WIFI_FW_STATION_STATE;//set to STATION_STATE
type = _HW_STATE_STATION_;
}
else if (psetop->mode == Ndis802_11IBSS)
@ -10839,7 +10839,7 @@ u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
rtw_free_uc_swdec_pending_queue(padapter);
return H2C_SUCCESS;
return H2C_SUCCESS;
}
int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
@ -11027,7 +11027,7 @@ u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf)
pmlmeinfo->auth_algo = pparm->mode;
}
return H2C_SUCCESS;
return H2C_SUCCESS;
}
u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
@ -11110,7 +11110,7 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
#endif
DBG_871X_LEVEL(_drv_always_, "set pairwise key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) camid:%d\n",
pparm->algorithm, cam_id);
pparm->algorithm, cam_id);
if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
{
@ -11188,14 +11188,14 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
{
struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf;
struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr);
if (!psta)
return H2C_SUCCESS;
return H2C_SUCCESS;
#ifdef CONFIG_80211N_HT
if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) ||
@ -11223,13 +11223,13 @@ u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid);
}
#endif //CONFIG_80211N_HT
return H2C_SUCCESS;
return H2C_SUCCESS;
}
u8 set_tx_beacon_cmd(_adapter* padapter)
{
struct cmd_obj *ph2c;
struct Tx_Beacon_param *ptxBeacon_parm;
struct Tx_Beacon_param *ptxBeacon_parm;
struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -11277,7 +11277,7 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
{
u8 evt_code, evt_seq;
u16 evt_sz;
uint *peventbuf;
uint *peventbuf;
void (*event_callback)(_adapter *dev, u8 *pbuf);
struct evt_priv *pevt_priv = &(padapter->evtpriv);
@ -12356,7 +12356,7 @@ u8 set_ch_hdl(_adapter *padapter, u8 *pbuf)
set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw);
return H2C_SUCCESS;
return H2C_SUCCESS;
}
u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
@ -12373,7 +12373,7 @@ u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set);
init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list);
return H2C_SUCCESS;
return H2C_SUCCESS;
}
u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
@ -12389,7 +12389,7 @@ u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
BlinkHandler(ledBlink_param->pLed);
#endif
return H2C_SUCCESS;
return H2C_SUCCESS;
}
u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf)
@ -12424,7 +12424,7 @@ u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf)
DBG_871X("Switched to DFS band (ch %02x) again!!\n", new_ch_no);
}
return H2C_SUCCESS;
return H2C_SUCCESS;
#else
return H2C_REJECTED;
#endif //CONFIG_DFS
@ -12606,4 +12606,3 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
#endif //CONFIG_TDLS
}

3
core/rtw_mp.c
View file

@ -891,7 +891,7 @@ static void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
static void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
{
PhySetTxPowerLevel(pAdapter);
Hal_SetOFDMContinuousTx( pAdapter, bStart);
Hal_SetOFDMContinuousTx( pAdapter, bStart);
}/* mpt_StartOfdmContTx */
void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
@ -1446,4 +1446,3 @@ exit:
#endif

9
core/rtw_mp_ioctl.c
View file

@ -176,7 +176,7 @@ _func_enter_;
path, offset, value));
_irqlevel_changed_(&oldirql, LOWER);
write_rfreg(Adapter, path, offset, value);
write_rfreg(Adapter, path, offset, value);
_irqlevel_changed_(&oldirql, RAISE);
_func_exit_;
@ -828,7 +828,7 @@ NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv
#ifdef PLATFORM_OS_XP
_irqL oldirql;
#endif
u32 bStartTest;
u32 bStartTest;
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
@ -888,7 +888,7 @@ NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv)
#ifdef PLATFORM_OS_XP
_irqL oldirql;
#endif
pRW_Reg RegRWStruct;
pRW_Reg RegRWStruct;
u32 offset, width;
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
@ -940,7 +940,7 @@ NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv)
#ifdef PLATFORM_OS_XP
_irqL oldirql;
#endif
pRW_Reg RegRWStruct;
pRW_Reg RegRWStruct;
u32 offset, width, value;
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
@ -1613,4 +1613,3 @@ NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv)
{
return 0;
}

9
core/rtw_p2p.c
View file

@ -970,7 +970,7 @@ u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
{
u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 };
u32 len=0, wfdielen = 0;
_adapter *padapter = NULL;
_adapter *padapter = NULL;
struct mlme_priv *pmlmepriv = NULL;
struct wifi_display_info *pwfd_info = NULL;
@ -2395,7 +2395,7 @@ u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint l
rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint*)&attr_contentlen);
_rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);//P2P Device Address
_rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);//P2P Device Address
pattr_content += ETH_ALEN;
@ -3278,7 +3278,7 @@ void find_phase_handler( _adapter* padapter )
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
NDIS_802_11_SSID ssid;
NDIS_802_11_SSID ssid;
_irqL irqL;
u8 _status = 0;
@ -4339,7 +4339,7 @@ static void restore_p2p_state_timer_process (void *FunctionContext)
static void pre_tx_scan_timer_process (void *FunctionContext)
{
_adapter *adapter = (_adapter *) FunctionContext;
_adapter *adapter = (_adapter *) FunctionContext;
struct wifidirect_info *pwdinfo = &adapter->wdinfo;
_irqL irqL;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
@ -4788,4 +4788,3 @@ exit:
}
#endif //CONFIG_P2P

8
core/rtw_pwrctrl.c
View file

@ -1701,9 +1701,9 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
){
DBG_8192C("%s: bDriverStopped=%d, bup=%d, hw_init_completed=%u\n"
, caller
, padapter->bDriverStopped
, padapter->bup
, padapter->hw_init_completed);
, padapter->bDriverStopped
, padapter->bup
, padapter->hw_init_completed);
ret= _FALSE;
goto exit;
}
@ -1764,5 +1764,3 @@ int rtw_pm_set_ips(_adapter *padapter, u8 mode)
}
return 0;
}

17
core/rtw_recv.c
View file

@ -368,7 +368,7 @@ using spinlock to protect
void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue)
{
union recv_frame *precvframe;
union recv_frame *precvframe;
_list *plist, *phead;
_func_enter_;
@ -493,7 +493,7 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe){
//u8 *iv,rxdata_key_idx=0;
struct sta_info *stainfo;
struct rx_pkt_attrib *prxattrib=&precvframe->u.hdr.attrib;
struct security_priv *psecuritypriv=&adapter->securitypriv;
struct security_priv *psecuritypriv=&adapter->securitypriv;
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -1112,7 +1112,7 @@ sint sta2sta_data_frame(
u8 *ptr = precv_frame->u.hdr.rx_data;
sint ret = _SUCCESS;
struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
u8 *mybssid = get_bssid(pmlmepriv);
u8 *myhwaddr = myid(&adapter->eeprompriv);
@ -1333,7 +1333,7 @@ sint ap2sta_data_frame(
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
sint ret = _SUCCESS;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
u8 *mybssid = get_bssid(pmlmepriv);
u8 *myhwaddr = myid(&adapter->eeprompriv);
@ -1489,7 +1489,7 @@ sint sta2ap_data_frame(
{
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
unsigned char *mybssid = get_bssid(pmlmepriv);
sint ret=_SUCCESS;
@ -1808,7 +1808,7 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
struct sta_info *psta = NULL;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct security_priv *psecuritypriv = &adapter->securitypriv;
sint ret = _SUCCESS;
#ifdef CONFIG_TDLS
@ -3277,7 +3277,7 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
//_enter_critical_ex(&ppending_recvframe_queue->lock, &irql);
//_rtw_spinlock_ex(&ppending_recvframe_queue->lock);
phead = get_list_head(ppending_recvframe_queue);
phead = get_list_head(ppending_recvframe_queue);
plist = get_next(phead);
// Handling some condition for forced indicate case.
@ -4012,6 +4012,3 @@ void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS){
}
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS

1
core/rtw_rf.c
View file

@ -92,4 +92,3 @@ u32 rtw_freq2ch(u32 freq)
return ch;
}

37
core/rtw_security.c
View file

@ -38,7 +38,7 @@ struct arc4context
};
static void arcfour_init(struct arc4context *parc4ctx, u8 * key,u32 key_len)
static void arcfour_init(struct arc4context *parc4ctx, u8 * key,u32 key_len)
{
u32 t, u;
u32 keyindex;
@ -173,7 +173,7 @@ void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
u8 wepkey[16];
u8 hw_hdr_offset=0;
struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
_func_enter_;
@ -245,12 +245,12 @@ void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe)
// exclude ICV
u8 crc[4];
struct arc4context mycontext;
sint length;
sint length;
u32 keylength;
u8 *pframe, *payload,*iv,wepkey[16];
u8 keyindex;
struct rx_pkt_attrib *prxattrib = &(((union recv_frame*)precvframe)->u.hdr.attrib);
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
_func_enter_;
@ -291,7 +291,7 @@ _func_exit_;
}
//3 =====TKIP related=====
//3 =====TKIP related=====
static u32 secmicgetuint32( u8 * p )
// Convert from Byte[] to Us4Byte32 in a portable way
@ -567,7 +567,7 @@ _func_enter_;
/* size on the 80-bit block P1K[], using the 128-bit key TK[] */
for (i=0; i < PHASE1_LOOP_CNT ;i++)
{ /* Each add operation here is mod 2**16 */
p1k[0] += _S_(p1k[4] ^ TK16((i&1)+0));
p1k[0] += _S_(p1k[4] ^ TK16((i&1)+0));
p1k[1] += _S_(p1k[0] ^ TK16((i&1)+2));
p1k[2] += _S_(p1k[1] ^ TK16((i&1)+4));
p1k[3] += _S_(p1k[2] ^ TK16((i&1)+6));
@ -657,14 +657,14 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
u8 crc[4];
u8 hw_hdr_offset = 0;
struct arc4context mycontext;
sint curfragnum,length;
sint curfragnum,length;
u32 prwskeylen;
u8 *pframe, *payload,*iv,*prwskey;
union pn48 dot11txpn;
struct sta_info *stainfo;
struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
u32 res=_SUCCESS;
_func_enter_;
@ -769,14 +769,14 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
u8 ttkey[16];
u8 crc[4];
struct arc4context mycontext;
sint length;
sint length;
u32 prwskeylen;
u8 *pframe, *payload,*iv,*prwskey;
union pn48 dot11txpn;
struct sta_info *stainfo;
struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
// struct recv_priv *precvpriv=&padapter->recvpriv;
u32 res=_SUCCESS;
@ -1446,7 +1446,7 @@ _func_enter_;
/* Insert MIC into payload */
for (j = 0; j < 8; j++)
pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j];
pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j];
payload_index = hdrlen + 8;
for (i=0; i< num_blocks; i++)
@ -1516,14 +1516,14 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
/*static*/
// unsigned char message[MAX_MSG_SIZE];
/* Intermediate Buffers */
sint curfragnum,length;
/* Intermediate Buffers */
sint curfragnum,length;
u32 prwskeylen;
u8 *pframe,*prwskey; //, *payload,*iv
u8 hw_hdr_offset = 0;
struct sta_info *stainfo;
struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
// uint offset = 0;
@ -1812,7 +1812,7 @@ _func_enter_;
/* Insert MIC into payload */
for (j = 0; j < 8; j++)
message[payload_index+j] = mic[j];
message[payload_index+j] = mic[j];
payload_index = hdrlen + 8;
for (i=0; i< num_blocks; i++)
@ -1891,14 +1891,14 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
// unsigned char message[MAX_MSG_SIZE];
/* Intermediate Buffers */
/* Intermediate Buffers */
sint length;
sint length;
u8 *pframe,*prwskey; //, *payload,*iv
struct sta_info *stainfo;
struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
// struct recv_priv *precvpriv=&padapter->recvpriv;
u32 res=_SUCCESS;
_func_enter_;
@ -2872,4 +2872,3 @@ _func_enter_;
_func_exit_;
}

2
core/rtw_sreset.c
View file

@ -83,5 +83,3 @@ void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
pHalData->srestpriv.Wifi_Error_Status = status;
}
#endif /* defined(DBG_CONFIG_ERROR_DETECT) */

13
core/rtw_sta_mgt.c
View file

@ -276,11 +276,11 @@ void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv)
u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
{
_irqL irqL;
_irqL irqL;
_list *phead, *plist;
struct sta_info *psta = NULL;
struct recv_reorder_ctrl *preorder_ctrl;
int index;
int index;
_func_enter_;
if (pstapriv){
@ -549,7 +549,7 @@ _func_enter_;
_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
phead = get_list_head(ppending_recvframe_queue);
phead = get_list_head(ppending_recvframe_queue);
plist = get_next(phead);
while (!rtw_is_list_empty(phead))
@ -732,7 +732,7 @@ _func_exit_;
u32 rtw_init_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct sta_info *psta;
struct tx_servq *ptxservq;
u32 res=_SUCCESS;
NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff};
@ -773,8 +773,8 @@ _func_exit_;
struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
psta = rtw_get_stainfo(pstapriv, bc_addr);
@ -833,4 +833,3 @@ u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr)
return res;
}

47
core/rtw_tdls.c
View file

@ -247,7 +247,7 @@ exit:
void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
_irqL irqL;
//free peer sta_info
@ -544,7 +544,7 @@ void issue_tdls_setup_req(_adapter *padapter, u8 *mac_addr)
struct pkt_attrib *pattrib;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *ptdls_sta= NULL;
_irqL irqL;
static u8 dialogtoken = 0;
@ -1090,7 +1090,7 @@ sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame)
struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
u8 *psa, *pmyid;
struct sta_info *ptdls_sta= NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct security_priv *psecuritypriv = &adapter->securitypriv;
@ -1288,7 +1288,7 @@ sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame)
goto exit;
}
issue_tdls_setup_rsp(adapter, precv_frame);
issue_tdls_setup_rsp(adapter, precv_frame);
if (ptdls_sta->stat_code==0)
{
@ -1308,7 +1308,7 @@ sint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame)
{
struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
struct sta_info *ptdls_sta= NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
_irqL irqL;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
@ -1483,7 +1483,7 @@ sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame)
{
struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
struct sta_info *ptdls_sta= NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
_irqL irqL;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
@ -1528,7 +1528,7 @@ sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame)
break;
case _VENDOR_SPECIFIC_IE_:
break;
case _FTIE_:
case _FTIE_:
pftie=(u8*)pIE;
break;
case _TIMEOUT_ITVL_IE_:
@ -1536,7 +1536,7 @@ sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame)
break;
case _HT_EXTRA_INFO_IE_:
break;
case _LINK_ID_IE_:
case _LINK_ID_IE_:
plinkid_ie=(u8*)pIE;
break;
default:
@ -1641,7 +1641,7 @@ sint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame)
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_info *ptdls_sta= NULL;
_irqL irqL;
@ -1771,7 +1771,7 @@ sint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame)
sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame)
{
struct sta_info *ptdls_sta= NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
u8 *psa;
@ -1807,7 +1807,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame)
break;
case _CH_SWTICH_ANNOUNCE_:
break;
case _LINK_ID_IE_:
case _LINK_ID_IE_:
break;
case _CH_SWITCH_TIMING_:
_rtw_memcpy(&ptdls_sta->ch_switch_time, pIE->data, 2);
@ -1844,7 +1844,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame)
sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame)
{
struct sta_info *ptdls_sta= NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_priv *pstapriv = &adapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
u8 *psa;
@ -1898,7 +1898,7 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame)
switch (pIE->ElementID)
{
case _LINK_ID_IE_:
case _LINK_ID_IE_:
break;
case _CH_SWITCH_TIMING_:
_rtw_memcpy(&switch_time, pIE->data, 2);
@ -2029,11 +2029,11 @@ void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmit
u8 category = RTW_WLAN_CATEGORY_TDLS;
u8 action = TDLS_SETUP_REQUEST;
u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; //Use NDIS_802_11_LENGTH_RATES_EX in order to call func.rtw_set_supported_rate
int bssrate_len = 0, i = 0 ;
int bssrate_len = 0, i = 0 ;
u8 more_supportedrates = 0;
unsigned int ie_len;
u8 *p;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 link_id_addr[18] = {0};
u8 iedata=0;
u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel
@ -2152,7 +2152,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmit
u8 more_supportedrates = 0;
unsigned int ie_len;
unsigned char *p;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 link_id_addr[18] = {0};
u8 iedata=0;
u8 timeout_itvl[5]; //setup response timeout interval will copy from request
@ -2300,7 +2300,7 @@ void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmit
unsigned int ie_len;
unsigned char *p;
u8 timeout_itvl[5]; //set timeout interval to maximum value
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 link_id_addr[18] = {0};
u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic;
@ -2367,7 +2367,7 @@ void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitf
u8 link_id_addr[18] = {0};
struct sta_info *ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst);
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
//payload type
pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
@ -2426,10 +2426,10 @@ void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitfr
u8 category = RTW_WLAN_CATEGORY_PUBLIC;
u8 action = TDLS_DISCOVERY_RESPONSE;
u8 bssrate[NDIS_802_11_LENGTH_RATES_EX];
int bssrate_len = 0;
int bssrate_len = 0;
u8 more_supportedrates = 0;
u8 *p;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 link_id_addr[18] = {0};
u8 iedata=0;
u8 timeout_itvl[5]; //set timeout interval to maximum value
@ -2518,7 +2518,7 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit
u8 link_id_addr[18] = {0};
u8 AC_queue=0;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
//payload type
@ -2557,7 +2557,7 @@ void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * p
unsigned char category = RTW_WLAN_CATEGORY_TDLS;
unsigned char action = TDLS_CHANNEL_SWITCH_REQUEST;
u8 link_id_addr[18] = {0};
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
u8 ch_switch_timing[4] = {0};
u16 switch_time= CH_SWITCH_TIME, switch_timeout=CH_SWITCH_TIMEOUT;
@ -2595,7 +2595,7 @@ void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * p
unsigned char category = RTW_WLAN_CATEGORY_TDLS;
unsigned char action = TDLS_CHANNEL_SWITCH_RESPONSE;
u8 link_id_addr[18] = {0};
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
@ -2938,4 +2938,3 @@ u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta)
}
#endif //CONFIG_TDLS

29
core/rtw_wlan_util.c
View file

@ -177,7 +177,7 @@ u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)
}
}
return network_type;
return network_type;
}
unsigned char ratetbl_val_2wifirate(unsigned char rate);
@ -707,8 +707,8 @@ unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval)
}
void CAM_empty_entry(
PADAPTER Adapter,
u8 ucIndex
PADAPTER Adapter,
u8 ucIndex
)
{
rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex));
@ -1103,7 +1103,7 @@ static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pI
if (_TRUE == pmlmeinfo->bwmode_updated)
{
struct sta_info *psta;
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
struct sta_priv *pstapriv = &padapter->stapriv;
//set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
@ -1143,9 +1143,9 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
u8 max_AMPDU_len, min_MPDU_spacing;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
if (pIE==NULL) return;
@ -1227,7 +1227,7 @@ void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
#ifdef CONFIG_80211N_HT
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
if (pIE==NULL) return;
@ -1378,7 +1378,7 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
struct HT_info_element *pht_info = NULL;
struct rtw_ieee80211_ht_cap *pht_cap = NULL;
u32 bcn_channel;
unsigned short ht_cap_info;
unsigned short ht_cap_info;
unsigned char ht_info_infos_0;
if (is_client_associated_to_ap(Adapter) == _FALSE)
@ -1430,9 +1430,9 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
if (ht_cap_info != cur_network->BcnInfo.ht_cap_info ||
((ht_info_infos_0&0x03) != (cur_network->BcnInfo.ht_info_infos_0&0x03))) {
DBG_871X("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__,
ht_cap_info, ht_info_infos_0);
ht_cap_info, ht_info_infos_0);
DBG_871X("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__,
cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0);
cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0);
DBG_871X("%s bw mode change, disconnect\n", __func__);
{
//bcn_info_update
@ -1647,7 +1647,7 @@ unsigned int is_ap_in_tkip(_adapter *padapter)
PNDIS_802_11_VARIABLE_IEs pIE;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY)
{
@ -1736,7 +1736,7 @@ unsigned int is_ap_in_wep(_adapter *padapter)
PNDIS_802_11_VARIABLE_IEs pIE;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY)
{
@ -2169,7 +2169,7 @@ void update_capinfo(PADAPTER Adapter, u16 updateCap)
//B Mode
pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
}
}
}
rtw_hal_set_hwreg( Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime );
@ -2181,7 +2181,7 @@ void update_wireless_mode(_adapter *padapter)
u32 SIFS_Timer;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
unsigned char *rate = cur_network->SupportedRates;
ratelen = rtw_get_rateset_len(cur_network->SupportedRates);
@ -2389,4 +2389,3 @@ int rtw_handle_dualmac(_adapter *adapter, bool init)
exit:
return status;
}

21
core/rtw_xmit.c
View file

@ -358,7 +358,7 @@ void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv)
rtw_mfree_xmit_priv_lock(pxmitpriv);
if (pxmitpriv->pxmit_frame_buf==NULL)
if (pxmitpriv->pxmit_frame_buf==NULL)
goto out;
for (i=0; i<NR_XMITFRAME; i++)
@ -892,13 +892,13 @@ _func_exit_;
}
static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe){
sint curfragnum,length;
sint curfragnum,length;
u8 *pframe, *payload,mic[8];
struct mic_data micdata;
struct sta_info *stainfo;
struct qos_priv *pqospriv= &(padapter->mlmepriv.qospriv);
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct security_priv *psecuritypriv=&padapter->securitypriv;
struct xmit_priv *pxmitpriv=&padapter->xmitpriv;
u8 priority[4]={0x0,0x0,0x0,0x0};
u8 hw_hdr_offset = 0;
@ -1030,7 +1030,7 @@ _func_exit_;
static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe){
struct pkt_attrib *pattrib = &pxmitframe->attrib;
//struct security_priv *psecuritypriv=&padapter->securitypriv;
//struct security_priv *psecuritypriv=&padapter->securitypriv;
_func_enter_;
@ -1077,7 +1077,7 @@ s32 rtw_make_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
u8 qos_option = _FALSE;
#ifdef CONFIG_TDLS
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *ptdls_sta=NULL, *psta_backup=NULL;
u8 direct_link=0;
#endif //CONFIG_TDLS
@ -1376,7 +1376,7 @@ s32 rtw_make_tdls_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *patt
struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct qos_priv *pqospriv = &pmlmepriv->qospriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *psta=NULL, *ptdls_sta=NULL;
u8 tdls_seq=0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@ -2253,7 +2253,7 @@ void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
{
_irqL irqL;
_list *plist, *phead;
struct xmit_frame *pxmitframe;
struct xmit_frame *pxmitframe;
_func_enter_;
@ -2604,7 +2604,7 @@ void rtw_alloc_hwxmits(_adapter *padapter)
//hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue;
hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
//pxmitpriv->be_txqueue.head = 0;
//pxmitpriv->be_txqueue.head = 0;
//hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue;
hwxmits[4] .sta_queue = &pxmitpriv->be_pending;
@ -2836,7 +2836,7 @@ u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)
case 0:
case 3:
addr = BE_QUEUE_INX;
break;
break;
case 1:
case 2:
addr = BK_QUEUE_INX;
@ -3216,7 +3216,7 @@ static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_
u8 ac_index;
struct tx_servq *ptxservq;
struct pkt_attrib *pattrib;
struct xmit_frame *pxmitframe;
struct xmit_frame *pxmitframe;
struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits;
phead = get_list_head(pframequeue);
@ -3861,4 +3861,3 @@ void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)
}
}
#endif //CONFIG_XMIT_ACK

1
hal/Hal8188EPwrSeq.c
View file

@ -94,4 +94,3 @@ WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TR
RTL8188E_TRANS_LPS_TO_ACT
RTL8188E_TRANS_END
};

87
hal/Hal8188ERateAdaptive.c
View file

@ -62,18 +62,18 @@ static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate
static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32};
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SS<TH
0x0e,0x0f,0x10,0x10,0x11,0x14,0x14,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x10,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x14, // SS>TH
static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x10,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x14, // SS>TH
0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15,
0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15};
static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
0,0,0,0,0,0x24,0x26,0x2a,
0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f,
0,0,0,0x1f,0x23,0x28,0x2a,0x2c};
@ -82,7 +82,7 @@ static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
// wilson modify
static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH
4,4,4,4,6,0x0a,0x0b,0x0d,
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01
{0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SS<TH
0x0b,0x0c,0x0d,0x0e,0x0f,0x11,0x13,0x15,
9,9,9,9,0x0c,0x0e,0x11,0x13}};
@ -106,7 +106,7 @@ static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16,
24,36,48,72,96,144,192,216,
60,80,100,160,240,400,560,640,
300,320,480,720,1000,1200,1600,2000};
static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8,
static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8,
12,18,24,36,48,72,96,108,
30,40,50,80,120,200,280,320,
150,160,240,360,500,600,800,1000};
@ -147,8 +147,8 @@ static u2Byte DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x9
static void
odm_SetTxRPTTiming_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo,
IN u1Byte extend
IN PODM_RA_INFO_T pRaInfo,
IN u1Byte extend
)
{
u1Byte idx = 0;
@ -176,7 +176,7 @@ odm_SetTxRPTTiming_8188E(
static int
odm_RateDown_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID, LowestRate, HighestRate;
@ -249,7 +249,7 @@ RateDownFinish:
static int
odm_RateUp_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID, HighestRate;
@ -324,7 +324,7 @@ static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){
static void
odm_RateDecision_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
@ -415,8 +415,8 @@ odm_RateDecision_8188E(
static int
odm_ARFBRefresh_8188E(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
)
{ // Wilson 2011/10/26
u4Byte MaskFromReg;
@ -519,7 +519,7 @@ odm_ARFBRefresh_8188E(
#if POWER_TRAINING_ACTIVE == 1
static void
odm_PTTryState_8188E(
IN PODM_RA_INFO_T pRaInfo
IN PODM_RA_INFO_T pRaInfo
)
{
pRaInfo->PTTryState=0;
@ -579,7 +579,7 @@ odm_PTTryState_8188E(
static void
odm_PTDecision_8188E(
IN PODM_RA_INFO_T pRaInfo
IN PODM_RA_INFO_T pRaInfo
)
{
u1Byte stage_BUF;
@ -623,7 +623,7 @@ odm_PTDecision_8188E(
static VOID
odm_RATxRPTTimerSetting(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
IN u2Byte minRptTime
)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n"));
@ -660,8 +660,8 @@ ODM_RASupport_Init(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
@ -748,8 +748,8 @@ ODM_RAInfo_Init_all(
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
@ -761,8 +761,8 @@ ODM_RA_GetShortGI_8188E(
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
u1Byte DecisionRate = 0;
@ -777,8 +777,8 @@ ODM_RA_GetDecisionRate_8188E(
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
u1Byte PTStage = 5;
@ -816,9 +816,9 @@ ODM_RA_UpdateRateInfo_8188E(
VOID
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
)
{
PODM_RA_INFO_T pRaInfo = NULL;
@ -835,7 +835,7 @@ ODM_RA_SetRSSI_8188E(
VOID
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
IN u2Byte minRptTime
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
@ -858,7 +858,7 @@ ODM_RA_TxRPT2Handle_8188E(
u1Byte MacId = 0;
pu1Byte pBuffer = NULL;
u4Byte valid = 0, ItemNum = 0;
u2Byte minRptTime = 0x927c;
u2Byte minRptTime = 0x927c;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n",
MacIDValidEntry0, MacIDValidEntry1, TxRPT_Len));
@ -983,7 +983,7 @@ ODM_RA_TxRPT2Handle_8188E(
static VOID
odm_RATxRPTTimerSetting(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
IN u2Byte minRptTime
)
{
return;
@ -992,7 +992,7 @@ odm_RATxRPTTimerSetting(
VOID
ODM_RASupport_Init(
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
)
{
return;
@ -1000,8 +1000,8 @@ ODM_RASupport_Init(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
return 0;
@ -1017,8 +1017,8 @@ ODM_RAInfo_Init_all(
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
return 0;
@ -1026,16 +1026,16 @@ ODM_RA_GetShortGI_8188E(
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
return 0;
}
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
)
{
return 0;
@ -1055,9 +1055,9 @@ ODM_RA_UpdateRateInfo_8188E(
VOID
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
)
{
return;
@ -1066,7 +1066,7 @@ ODM_RA_SetRSSI_8188E(
VOID
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
IN u2Byte minRptTime
)
{
return;
@ -1086,4 +1086,3 @@ ODM_RA_TxRPT2Handle_8188E(
#endif

113
hal/HalHWImg8188E_BB.c
View file

@ -193,8 +193,8 @@ u4Byte Array_AGC_TAB_1T_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_AGC_TAB_1T_8188E(
IN PDM_ODM_T pDM_Odm
)
IN PDM_ODM_T pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
@ -233,64 +233,64 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u4Byte v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
continue;
}
continue;
}
else
{ // This line is the start line of branch.
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
}
else // Configure matched pairs and skip to end of if-else.
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
{ // Discard the following (offset, data) pairs.
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
}
else // Configure matched pairs and skip to end of if-else.
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
READ_NEXT_PAIR(v1, v2, i);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
}
#ifdef CONFIG_IOL_IOREG_CFG
@ -524,8 +524,8 @@ u4Byte Array_PHY_REG_1T_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_PHY_REG_1T_8188E(
IN PDM_ODM_T pDM_Odm
)
IN PDM_ODM_T pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
@ -574,8 +574,8 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
@ -609,14 +609,14 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
cmpdata_idx++;
#endif
}
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
continue;
}
continue;
}
else
{ // This line is the start line of branch.
if ( !CheckCondition(Array[i], hex) )
@ -637,8 +637,8 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
if (v1 == 0xfe){
@ -670,11 +670,11 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
cmpdata_idx++;
#endif
}
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
READ_NEXT_PAIR(v1, v2, i);
}
@ -831,8 +831,8 @@ u4Byte Array_PHY_REG_PG_8188E[] = {
void
ODM_ReadAndConfig_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm
)
IN PDM_ODM_T pDM_Odm
)
{
u4Byte hex = 0;
u4Byte i = 0;
@ -860,9 +860,9 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3);
odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3);
continue;
continue;
}
else
{ // this line is the start of branch
@ -888,4 +888,3 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
#endif // end of HWIMG_SUPPORT

73
hal/HalHWImg8188E_MAC.c
View file

@ -153,8 +153,8 @@ u4Byte Array_MAC_REG_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_MAC_REG_8188E(
IN PDM_ODM_T pDM_Odm
)
IN PDM_ODM_T pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
@ -200,14 +200,14 @@ ODM_ReadAndConfig_MAC_REG_8188E(
for (i = 0; i < ArrayLen; i += 2 )
{
u4Byte v1 = Array[i];
u4Byte v2 = Array[i+1];
u4Byte v2 = Array[i+1];
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
@ -217,36 +217,36 @@ ODM_ReadAndConfig_MAC_REG_8188E(
cmpdata[cmpdata_idx].value= v2;
cmpdata_idx++;
#endif
}
}
else
#endif //endif CONFIG_IOL_IOREG_CFG
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
}
continue;
}
else
{ // This line is the start line of branch.
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
READ_NEXT_PAIR(v1, v2, i);
}
else
{ // This line is the start line of branch.
if ( !CheckCondition(Array[i], hex) )
{ // Discard the following (offset, data) pairs.
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; // prevent from for-loop += 2
}
else // Configure matched pairs and skip to end of if-else.
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
i -= 2; // prevent from for-loop += 2
}
else // Configure matched pairs and skip to end of if-else.
{
READ_NEXT_PAIR(v1, v2, i);
while ( v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF);
@ -255,22 +255,22 @@ ODM_ReadAndConfig_MAC_REG_8188E(
cmpdata[cmpdata_idx].value= v2;
cmpdata_idx++;
#endif
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
}
READ_NEXT_PAIR(v1, v2, i);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
}
@ -326,4 +326,3 @@ ODM_ReadAndConfig_MAC_REG_8188E(
}
#endif // end of HWIMG_SUPPORT

23
hal/HalHWImg8188E_RF.c
View file

@ -164,8 +164,8 @@ u4Byte Array_RadioA_1T_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_RadioA_1T_8188E(
IN PDM_ODM_T pDM_Odm
)
IN PDM_ODM_T pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
@ -214,8 +214,8 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
@ -247,14 +247,14 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
#endif
}
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
continue;
}
}
else
{ // This line is the start line of branch.
if ( !CheckCondition(Array[i], hex) )
@ -275,8 +275,8 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
#ifdef CONFIG_IOL_IOREG_CFG
if (biol){
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
bndy_cnt++;
@ -309,11 +309,11 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
}
}
}
else
#endif //#ifdef CONFIG_IOL_IOREG_CFG
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
}
READ_NEXT_PAIR(v1, v2, i);
}
@ -374,4 +374,3 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
}
#endif // end of HWIMG_SUPPORT

127
hal/HalPhyRf.c
View file

@ -179,7 +179,7 @@ phy_PathB_IQK_8192C(
VOID
phy_PathAFillIQKMatrix(
IN PADAPTER pAdapter,
IN BOOLEAN bIQKOK,
IN BOOLEAN bIQKOK,
IN s4Byte result[][8],
IN u1Byte final_candidate,
IN BOOLEAN bTxOnly
@ -246,7 +246,7 @@ phy_PathAFillIQKMatrix(
VOID
phy_PathBFillIQKMatrix(
IN PADAPTER pAdapter,
IN BOOLEAN bIQKOK,
IN BOOLEAN bIQKOK,
IN s4Byte result[][8],
IN u1Byte final_candidate,
IN BOOLEAN bTxOnly //do Tx only
@ -272,7 +272,7 @@ phy_PathBFillIQKMatrix(
RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
if (IS_HARDWARE_TYPE_8192D(pAdapter))
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT28, ((X* Oldval_1>>7) & 0x1));
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT28, ((X* Oldval_1>>7) & 0x1));
else
PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
@ -308,7 +308,7 @@ phy_PathBFillIQKMatrix(
BOOLEAN
phy_SimularityCompare_92C(
IN PADAPTER pAdapter,
IN s4Byte result[][8],
IN s4Byte result[][8],
IN u1Byte c1,
IN u1Byte c2
)
@ -380,7 +380,7 @@ return FALSE => do IQK again
BOOLEAN
phy_SimularityCompare(
IN PADAPTER pAdapter,
IN s4Byte result[][8],
IN s4Byte result[][8],
IN u1Byte c1,
IN u1Byte c2
)
@ -395,7 +395,7 @@ phy_SimularityCompare(
VOID
phy_IQCalibrate_8192C(
IN PADAPTER pAdapter,
IN s4Byte result[][8],
IN s4Byte result[][8],
IN u1Byte t,
IN BOOLEAN is2T
)
@ -404,21 +404,21 @@ phy_IQCalibrate_8192C(
u4Byte i;
u1Byte PathAOK, PathBOK;
u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
//since 92C & 92D have the different define in IQK_BB_REG
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
@ -445,34 +445,34 @@ phy_IQCalibrate_8192C(
u1Byte rfPathSwitch=0x0;
// Note: IQ calibration must be performed after loading
// PHY_REG.txt , and radio_a, radio_b.txt
// PHY_REG.txt , and radio_a, radio_b.txt
u4Byte bbvalue;
if (t==0)
{
bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord);
bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue));
RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
// Save ADDA parameters, turn Path A ADDA on
phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
// Save ADDA parameters, turn Path A ADDA on
phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
if (IS_HARDWARE_TYPE_8192D(pAdapter))
phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D);
phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D);
else
phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
}
phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
if (IS_HARDWARE_TYPE_8192D(pAdapter)){
//==============================
//3 Path Diversity
////Neil Chen--2011--05--20
////Neil Chen--2011--05--20
rfPathSwitch =(u1Byte) (PHY_QueryBBReg(pAdapter, 0xB30, bMaskDWord)>>27);
//rfPathSwitch = (u1Byte) DataB30;
rfPathSwitch = rfPathSwitch&(0x01);
@ -484,7 +484,7 @@ phy_IQCalibrate_8192C(
}
else
{
phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
}
//3 end
//=====================================
@ -613,22 +613,22 @@ phy_IQCalibrate_8192C(
phy_PIModeSwitch(pAdapter, FALSE);
}
// Reload ADDA power saving parameters
phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
// Reload ADDA power saving parameters
phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
// Reload MAC parameters
phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
// Reload BB parameters
if (IS_HARDWARE_TYPE_8192D(pAdapter))
{
// Reload BB parameters
if (IS_HARDWARE_TYPE_8192D(pAdapter))
{
if (is2T)
phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D);
phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D);
else
phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D -1);
}
phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D -1);
}
else
phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
if (!IS_HARDWARE_TYPE_8192D(pAdapter))
{
@ -742,21 +742,21 @@ phy_LCCalibrate(
VOID
phy_APCalibrate_8192C(
IN PADAPTER pAdapter,
IN s1Byte delta,
IN s1Byte delta,
IN BOOLEAN is2T
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u4Byte regD[PATH_NUM];
u4Byte regD[PATH_NUM];
u4Byte tmpReg, index, offset, i, apkbound;
u1Byte path, pathbound = PATH_NUM;
u4Byte BB_backup[APK_BB_REG_NUM];
u4Byte BB_REG[APK_BB_REG_NUM] = {
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
rFPGA0_RFMOD, rOFDM0_TRMuxPar,
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
rFPGA0_RFMOD, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
0x00000020, 0x00a05430, 0x02040000,
0x000800e4, 0x00204000 };
@ -766,18 +766,18 @@ phy_APCalibrate_8192C(
u4Byte AFE_backup[IQK_ADDA_REG_NUM];
u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte MAC_backup[IQK_MAC_REG_NUM];
u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
@ -1181,7 +1181,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
VOID
PHY_IQCalibrate_8192C(
IN PADAPTER pAdapter,
IN BOOLEAN bReCovery
IN BOOLEAN bReCovery
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@ -1190,12 +1190,12 @@ PHY_IQCalibrate_8192C(
BOOLEAN bPathAOK, bPathBOK;
s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
BOOLEAN is12simular, is13simular, is23simular;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_RxIQExtAnta};
if (ODM_CheckPowerStatus(pAdapter) == FALSE)
@ -1254,15 +1254,15 @@ if (pAdapter->registrypriv.mp_mode == 1)
// if (IS_HARDWARE_TYPE_8192C(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter))
if (!IS_HARDWARE_TYPE_8192D(pAdapter))
{
if (IS_92C_SERIAL( pHalData->VersionID))
if (IS_92C_SERIAL( pHalData->VersionID))
{
phy_IQCalibrate_8192C(pAdapter, result, i, TRUE);
}
else
phy_IQCalibrate_8192C(pAdapter, result, i, TRUE);
}
else
{
// For 88C 1T1R
phy_IQCalibrate_8192C(pAdapter, result, i, FALSE);
}
// For 88C 1T1R
phy_IQCalibrate_8192C(pAdapter, result, i, FALSE);
}
}
else/* if (IS_HARDWARE_TYPE_8192D(pAdapter))*/
{
@ -1394,7 +1394,7 @@ PHY_LCCalibrate_8192C(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo;
PMGNT_INFO pMgntInfoBuddyAdapter;
u4Byte timeout = 2000, timecount = 0;
@ -1459,7 +1459,7 @@ if (pAdapter->registrypriv.mp_mode == 1)
VOID
PHY_APCalibrate_8192C(
IN PADAPTER pAdapter,
IN s1Byte delta
IN s1Byte delta
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@ -1552,4 +1552,3 @@ u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
}
#endif

168
hal/HalPhyRf_8188e.c
View file

@ -71,13 +71,13 @@ ODM_TxPwrTrackAdjust88E(
if (pDM_Odm->BbSwingIdxOfdm <= pDM_Odm->BbSwingIdxOfdmBase)
{
*pDirection = 1;
pwr_value = (pDM_Odm->BbSwingIdxOfdmBase - pDM_Odm->BbSwingIdxOfdm);
*pDirection = 1;
pwr_value = (pDM_Odm->BbSwingIdxOfdmBase - pDM_Odm->BbSwingIdxOfdm);
}
else
{
*pDirection = 2;
pwr_value = (pDM_Odm->BbSwingIdxOfdm - pDM_Odm->BbSwingIdxOfdmBase);
*pDirection = 2;
pwr_value = (pDM_Odm->BbSwingIdxOfdm - pDM_Odm->BbSwingIdxOfdmBase);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
@ -91,13 +91,13 @@ ODM_TxPwrTrackAdjust88E(
if (pDM_Odm->BbSwingIdxCck <= pDM_Odm->BbSwingIdxCckBase)
{
*pDirection = 1;
pwr_value = (pDM_Odm->BbSwingIdxCckBase - pDM_Odm->BbSwingIdxCck);
*pDirection = 1;
pwr_value = (pDM_Odm->BbSwingIdxCckBase - pDM_Odm->BbSwingIdxCck);
}
else
{
*pDirection = 2;
pwr_value = (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase);
*pDirection = 2;
pwr_value = (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase);
}
}
@ -145,7 +145,7 @@ odm_TxPwrTrackSetPwr88E(
PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
#endif
pDM_Odm->BbSwingFlagOfdm = FALSE;
pDM_Odm->BbSwingFlagOfdm = FALSE;
pDM_Odm->BbSwingFlagCck = FALSE;
}
} // odm_TxPwrTrackSetPwr88E
@ -164,7 +164,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
//PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
//PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
#endif
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
@ -174,25 +174,25 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
s4Byte Y, ele_C=0;
s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
u4Byte i = 0, j = 0;
BOOLEAN is2T = FALSE;
BOOLEAN bInteralPA = FALSE;
BOOLEAN is2T = FALSE;
BOOLEAN bInteralPA = FALSE;
u1Byte OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
u1Byte Indexforchannel = 0/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/;
s1Byte OFDM_index_mapping[2][index_mapping_NUM_88E] = {
{0, 0, 2, 3, 4, 4, //2.4G, decrease power
5, 6, 7, 7, 8, 9,
5, 6, 7, 7, 8, 9,
10, 10, 11}, // For lower temperature, 20120220 updated on 20120220.
{0, 0, -1, -2, -3, -4, //2.4G, increase power
-4, -4, -4, -5, -7, -8,
-4, -4, -4, -5, -7, -8,
-9, -9, -10},
};
u1Byte Thermal_mapping[2][index_mapping_NUM_88E] = {
{0, 2, 4, 6, 8, 10, //2.4G, decrease power
12, 14, 16, 18, 20, 22,
12, 14, 16, 18, 20, 22,
24, 26, 27},
{0, 2, 4, 6, 8, 10, //2.4G,, increase power
12, 14, 16, 18, 20, 22,
{0, 2, 4, 6, 8, 10, //2.4G,, increase power
12, 14, 16, 18, 20, 22,
25, 25, 25},
};
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
@ -480,8 +480,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
//
// Revse TX power table.
//
pDM_Odm->BbSwingIdxOfdm = (u1Byte)OFDM_index[0];
pDM_Odm->BbSwingIdxCck = (u1Byte)CCK_index;
pDM_Odm->BbSwingIdxOfdm = (u1Byte)OFDM_index[0];
pDM_Odm->BbSwingIdxCck = (u1Byte)CCK_index;
//DbgPrint("pDM_Odm->BbSwingIdxOfdm = %d\n", pDM_Odm->BbSwingIdxOfdm);
@ -906,7 +906,7 @@ _PHY_PathAFillIQKMatrix(
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bIQKOK,
IN BOOLEAN bIQKOK,
IN s4Byte result[][8],
IN u1Byte final_candidate,
IN BOOLEAN bTxOnly
@ -981,7 +981,7 @@ _PHY_PathBFillIQKMatrix(
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bIQKOK,
IN BOOLEAN bIQKOK,
IN s4Byte result[][8],
IN u1Byte final_candidate,
IN BOOLEAN bTxOnly //do Tx only
@ -1053,7 +1053,7 @@ ODM_CheckPowerStatus(
/*
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
RT_RF_POWER_STATE rtState;
RT_RF_POWER_STATE rtState;
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
// 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
@ -1331,7 +1331,7 @@ phy_SimularityCompare_8188E(
#else
IN PADAPTER pAdapter,
#endif
IN s4Byte result[][8],
IN s4Byte result[][8],
IN u1Byte c1,
IN u1Byte c2
)
@ -1466,7 +1466,7 @@ phy_IQCalibrate_8188E(
#else
IN PADAPTER pAdapter,
#endif
IN s4Byte result[][8],
IN s4Byte result[][8],
IN u1Byte t,
IN BOOLEAN is2T
)
@ -1483,21 +1483,21 @@ phy_IQCalibrate_8188E(
u4Byte i;
u1Byte PathAOK, PathBOK;
u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
//since 92C & 92D have the different define in IQK_BB_REG
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
@ -1517,7 +1517,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
else
retryCount = 2;
// Note: IQ calibration must be performed after loading
// PHY_REG.txt , and radio_a, radio_b.txt
// PHY_REG.txt , and radio_a, radio_b.txt
//u4Byte bbvalue;
@ -1531,29 +1531,29 @@ else
if (t==0)
{
// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
// Save ADDA parameters, turn Path A ADDA on
// Save ADDA parameters, turn Path A ADDA on
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
_PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
#else
_PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
_PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
_PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
#else
_PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T);
_PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T);
#endif
@ -1704,21 +1704,21 @@ else
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
// Reload ADDA power saving parameters
_PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
// Reload ADDA power saving parameters
_PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
// Reload MAC parameters
_PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
_PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
#else
// Reload ADDA power saving parameters
_PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
// Reload ADDA power saving parameters
_PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
// Reload MAC parameters
_PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
_PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
#endif
@ -1837,7 +1837,7 @@ phy_APCalibrate_8188E(
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta,
IN s1Byte delta,
IN BOOLEAN is2T
)
{
@ -1850,15 +1850,15 @@ phy_APCalibrate_8188E(
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
#endif
#endif
u4Byte regD[PATH_NUM];
u4Byte regD[PATH_NUM];
u4Byte tmpReg, index, offset, apkbound;
u1Byte path, i, pathbound = PATH_NUM;
u4Byte BB_backup[APK_BB_REG_NUM];
u4Byte BB_REG[APK_BB_REG_NUM] = {
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
rFPGA0_RFMOD, rOFDM0_TRMuxPar,
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
rFPGA0_RFMOD, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
0x00000020, 0x00a05430, 0x02040000,
0x000800e4, 0x00204000 };
@ -1868,18 +1868,18 @@ phy_APCalibrate_8188E(
u4Byte AFE_backup[IQK_ADDA_REG_NUM];
u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte MAC_backup[IQK_MAC_REG_NUM];
u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
@ -2330,7 +2330,7 @@ PHY_IQCalibrate_8188E(
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bReCovery
IN BOOLEAN bReCovery
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -2353,16 +2353,16 @@ PHY_IQCalibrate_8188E(
s4Byte result[4][8]; //last is final result
u1Byte i, final_candidate, Indexforchannel;
u1Byte channelToIQK = 7;
u1Byte channelToIQK = 7;
BOOLEAN bPathAOK, bPathBOK;
s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
BOOLEAN is12simular, is13simular, is23simular;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_RxIQExtAnta};
BOOLEAN is2T;
@ -2446,9 +2446,9 @@ if (*(pDM_Odm->mp_mode) == 1)
for (i=0; i<3; i++) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
phy_IQCalibrate_8188E(pAdapter, result, i, is2T);
phy_IQCalibrate_8188E(pAdapter, result, i, is2T);
#else
phy_IQCalibrate_8188E(pDM_Odm, result, i, is2T);
phy_IQCalibrate_8188E(pDM_Odm, result, i, is2T);
#endif
@ -2598,7 +2598,7 @@ PHY_LCCalibrate_8188E(
#endif
)
{
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
u4Byte timeout = 2000, timecount = 0;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -2685,7 +2685,7 @@ PHY_APCalibrate_8188E(
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
IN s1Byte delta
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -2846,19 +2846,19 @@ phy_DigitalPredistortion(
u1Byte path, pathbound = PATH_NUM;
u4Byte AFE_backup[IQK_ADDA_REG_NUM];
u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u4Byte BB_backup[DP_BB_REG_NUM];
u4Byte BB_REG[DP_BB_REG_NUM] = {
rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XB_RFInterfaceOE};
u4Byte BB_settings[DP_BB_REG_NUM] = {
@ -2871,7 +2871,7 @@ phy_DigitalPredistortion(
u4Byte MAC_backup[IQK_MAC_REG_NUM];
u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {

4
hal/HalPwrSeqCmd.c
View file

@ -56,7 +56,7 @@ u8 HalPwrSeqCmdParsing(
u8 InterfaceType,
WLAN_PWR_CFG PwrSeqCmd[])
{
WLAN_PWR_CFG PwrCfgCmd = {0};
WLAN_PWR_CFG PwrCfgCmd = {0};
u8 bPollingBit = _FALSE;
u32 AryIdx = 0;
u8 value = 0;
@ -183,5 +183,3 @@ u8 HalPwrSeqCmdParsing(
return _TRUE;
}

25
hal/hal_com.c
View file

@ -201,15 +201,15 @@ _OneOutPipeMapping(
static VOID
_TwoOutPipeMapping(
IN PADAPTER pAdapter,
IN BOOLEAN bWIFICfg
IN BOOLEAN bWIFICfg
)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg){ //WMM
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 0, 1, 0, 1, 0, 0, 0, 0, 0 };
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 0, 1, 0, 1, 0, 0, 0, 0, 0 };
//0:H, 1:L
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO
@ -226,8 +226,8 @@ _TwoOutPipeMapping(
else{//typical setting
//BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 1, 0, 0, 0, 0, 0, 0, 0 };
//BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 1, 0, 0, 0, 0, 0, 0, 0 };
//0:H, 1:L
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
@ -246,15 +246,15 @@ _TwoOutPipeMapping(
static VOID _ThreeOutPipeMapping(
IN PADAPTER pAdapter,
IN BOOLEAN bWIFICfg
IN BOOLEAN bWIFICfg
)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg){//for WMM
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 2, 1, 0, 0, 0, 0, 0, 0 };
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H, 1:N, 2:L
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
@ -271,8 +271,8 @@ static VOID _ThreeOutPipeMapping(
else{//typical setting
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 2, 2, 1, 0, 0, 0, 0, 0, 0 };
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 2, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H, 1:N, 2:L
pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
@ -331,8 +331,8 @@ void hal_init_macaddr(_adapter *adapter)
/*
* C2H event format:
* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
*/
void c2h_evt_clear(_adapter *adapter)
@ -391,4 +391,3 @@ clear_evt:
exit:
return ret;
}

7
hal/hal_intf.c
View file

@ -113,12 +113,12 @@ uint rtw_hal_init(_adapter *padapter)
}
else
{
status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
status = padapter->HalFunc.hal_init(padapter->pbuddy_adapter);
if (status == _SUCCESS){
padapter->pbuddy_adapter->hw_init_completed = _TRUE;
}
else{
padapter->pbuddy_adapter->hw_init_completed = _FALSE;
padapter->pbuddy_adapter->hw_init_completed = _FALSE;
RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail(pbuddy_adapter)\n"));
DBG_871X("rtw_hal_init: hal__init fail(pbuddy_adapter)\n");
return status;
@ -140,7 +140,7 @@ uint rtw_hal_init(_adapter *padapter)
rtw_hal_reset_security_engine(padapter);
}
else{
padapter->hw_init_completed = _FALSE;
padapter->hw_init_completed = _FALSE;
DBG_871X("rtw_hal_init: hal__init fail\n");
}
@ -509,4 +509,3 @@ c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter)
{
return adapter->HalFunc.c2h_id_filter_ccx;
}

490
hal/odm.c
View file

File diff suppressed because it is too large Load diff

39
hal/odm_HWConfig.c
View file

@ -27,7 +27,7 @@
#if (RTL8188E_FOR_TEST_CHIP > 1)
#define READ_AND_CONFIG(ic, txt) do {\
if (pDM_Odm->bIsMPChip)\
READ_AND_CONFIG_MP(ic,txt);\
READ_AND_CONFIG_MP(ic,txt);\
else\
READ_AND_CONFIG_TC(ic,txt);\
} while (0)
@ -303,10 +303,10 @@ odm_SignalScaleMapping(
//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
IN PDM_ODM_T pDM_Odm,
IN u1Byte isCCKrate,
IN u1Byte PWDB_ALL,
IN u1Byte path,
IN u1Byte RSSI
IN u1Byte isCCKrate,
IN u1Byte PWDB_ALL,
IN u1Byte path,
IN u1Byte RSSI
)
{
u1Byte SQ;
@ -381,7 +381,7 @@ VOID
odm_RxPhyStatus92CSeries_Parsing(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -549,7 +549,7 @@ odm_RxPhyStatus92CSeries_Parsing(
else//Modification for int-LNA board
{
if (PWDB_ALL > 99)
PWDB_ALL -= 8;
PWDB_ALL -= 8;
else if (PWDB_ALL > 50 && PWDB_ALL <= 68)
PWDB_ALL += 4;
}
@ -599,7 +599,7 @@ odm_RxPhyStatus92CSeries_Parsing(
// (1)Get RSSI for HT rate
//
for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
{
// 2008/01/30 MH we will judge RF RX path now.
if (pDM_Odm->RFPathRxEnable & BIT(i))
@ -760,7 +760,7 @@ odm_Process_RSSIForDM(
u4Byte OFDM_pkt=0;
u4Byte Weighting=0;
PSTA_INFO_T pEntry;
PSTA_INFO_T pEntry;
if (pPktinfo->StationID == 0xFF)
return;
@ -972,7 +972,7 @@ VOID
ODM_PhyStatusQuery_92CSeries(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -1002,7 +1002,7 @@ VOID
ODM_PhyStatusQuery_JaguarSeries(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -1014,7 +1014,7 @@ VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
)
{
@ -1025,7 +1025,7 @@ ODM_PhyStatusQuery(
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
@ -1040,9 +1040,9 @@ ODM_MacStatusQuery(
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
)
{
//RT_STATUS rtStatus = RT_STATUS_SUCCESS;
@ -1082,8 +1082,8 @@ ODM_ConfigRFWithHeaderFile(
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
)
{
#if (RTL8723A_SUPPORT == 1)
@ -1132,7 +1132,7 @@ ODM_ConfigBBWithHeaderFile(
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
)
{
u1Byte result = HAL_STATUS_SUCCESS;
@ -1154,4 +1154,3 @@ ODM_ConfigMACWithHeaderFile(
#endif // end of (#if DM_ODM_SUPPORT_TYPE)

89
hal/odm_RTL8188E.c
View file

@ -54,10 +54,10 @@ odm_RX_HWAntDivInit(
PADAPTER Adapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1)
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
return;
}
#endif
@ -67,9 +67,9 @@ odm_RX_HWAntDivInit(
value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
//Pin Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
//OFDM Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
@ -94,11 +94,11 @@ odm_TRX_HWAntDivInit(
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1)
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
return;
}
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
return;
}
#endif
@ -108,9 +108,9 @@ odm_TRX_HWAntDivInit(
value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
//Pin Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
//OFDM Settings
ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
@ -147,9 +147,9 @@ odm_FastAntTrainingInit(
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
return;
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
return;
}
#endif
@ -175,9 +175,9 @@ odm_FastAntTrainingInit(
ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
@ -233,7 +233,7 @@ odm_FastAntTrainingInit(
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
//ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
//SW Control
@ -419,7 +419,7 @@ odm_HWAntDiv(
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
BOOLEAN bMatchBSSID;
BOOLEAN bPktFilterMacth = FALSE;
PSTA_INFO_T pEntry;
PSTA_INFO_T pEntry;
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
{
@ -482,7 +482,7 @@ odm_SetNextMACAddrTarget(
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
PSTA_INFO_T pEntry;
PSTA_INFO_T pEntry;
//u1Byte Bssid[6];
u4Byte value32, i;
@ -542,7 +542,7 @@ odm_FastAntTraining(
u1Byte TargetAnt=2;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
BOOLEAN bPktFilterMacth = FALSE;
PSTA_INFO_T pEntry;
PSTA_INFO_T pEntry;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));
@ -577,14 +577,14 @@ odm_FastAntTraining(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%d\n",TargetAnt,MaxRSSI));
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
//ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT
//ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
@ -595,7 +595,7 @@ odm_FastAntTraining(
if (TargetAnt == 0)
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
}
@ -620,7 +620,7 @@ odm_FastAntTraining(
//2 Prepare Training
pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));
ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms
@ -707,7 +707,7 @@ ODM_AntennaDiversity_88E(
if (pDM_FatTable->bBecomeLinked == TRUE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
@ -721,7 +721,7 @@ ODM_AntennaDiversity_88E(
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
//Because HW AntDiv is disabled before Link, we enable HW AntDiv after link
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv
//ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
@ -1018,7 +1018,7 @@ odm_DynamicPrimaryCCA(
//1 Dynamic Primary CCA Main Function
if (PrimaryCCA->Monitor_flag == 0)
{
if (Is40MHz) // if RFBW==40M mode which require to process primary cca
if (Is40MHz) // if RFBW==40M mode which require to process primary cca
{
//2 STA is NOT Connected
if (!bConnected)
@ -1039,9 +1039,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; // interference is in-band
}
else
{
@ -1055,9 +1055,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; // interference is in-band
}
else
{
@ -1114,9 +1114,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; // interference is in-band
}
}
else if (SecCHOffset == 2)
@ -1125,9 +1125,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; // interference is in-band
}
}
@ -1142,9 +1142,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; // interference is in-band
Delay = 1;
}
else
@ -1159,9 +1159,9 @@ odm_DynamicPrimaryCCA(
{
PrimaryCCA->intf_flag = 1;
if (FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
PrimaryCCA->intf_type = 2; // interference is in-band
Delay = 1;
}
else
@ -1226,4 +1226,3 @@ ODM_DynamicPrimaryCCA_DupRTS(
return FALSE;
}
#endif //#if (RTL8188E_SUPPORT == 1)

53
hal/odm_RegConfig8188E.c
View file

@ -24,9 +24,9 @@
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
@ -70,9 +70,9 @@ odm_ConfigRFReg_8188E(
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
@ -85,9 +85,9 @@ odm_ConfigRF_RadioA_8188E(
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
@ -101,10 +101,10 @@ odm_ConfigRF_RadioB_8188E(
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
)
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
@ -112,10 +112,10 @@ odm_ConfigMAC_8188E(
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
@ -127,10 +127,10 @@ odm_ConfigBB_AGC_8188E(
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe){
@ -167,10 +167,10 @@ odm_ConfigBB_PHY_REG_PG_8188E(
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe){
@ -202,8 +202,7 @@ odm_ConfigBB_PHY_8188E(
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
}
#endif

3
hal/odm_debug.c
View file

@ -29,7 +29,7 @@ ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
)
{
pDM_Odm->DebugLevel = ODM_DBG_TRACE;
pDM_Odm->DebugLevel = ODM_DBG_TRACE;
pDM_Odm->DebugComponents =
\
@ -37,4 +37,3 @@ pDM_Odm->DebugComponents =
}
u32 GlobalDebugLevel;

59
hal/odm_interface.c
View file

@ -29,7 +29,7 @@
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
@ -49,7 +49,7 @@ ODM_Read1Byte(
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
@ -69,7 +69,7 @@ ODM_Read2Byte(
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
@ -89,7 +89,7 @@ ODM_Read4Byte(
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
)
@ -110,7 +110,7 @@ ODM_Write1Byte(
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
)
@ -131,7 +131,7 @@ ODM_Write2Byte(
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
)
@ -152,7 +152,7 @@ ODM_Write4Byte(
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
@ -169,7 +169,7 @@ ODM_SetMACReg(
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
@ -185,7 +185,7 @@ ODM_GetMACReg(
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
@ -202,7 +202,7 @@ ODM_SetBBReg(
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
@ -218,7 +218,7 @@ ODM_GetBBReg(
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
@ -236,7 +236,7 @@ ODM_SetRFReg(
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
@ -258,7 +258,7 @@ ODM_GetRFReg(
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
)
@ -276,7 +276,7 @@ ODM_AllocateMemory(
// length could be ignored, used to detect memory leakage.
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
)
@ -291,7 +291,7 @@ ODM_FreeMemory(
#endif
}
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
@ -313,7 +313,7 @@ s4Byte ODM_CompareMemory(
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
)
{
@ -328,7 +328,7 @@ ODM_AcquireSpinLock(
}
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
)
{
@ -347,7 +347,7 @@ ODM_ReleaseSpinLock(
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
@ -506,9 +506,9 @@ ODM_sleep_us(IN u4Byte us)
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
@ -524,8 +524,8 @@ ODM_SetTimer(
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
@ -547,7 +547,7 @@ ODM_InitializeTimer(
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
)
{
@ -564,7 +564,7 @@ ODM_CancelTimer(
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
)
{
@ -596,8 +596,8 @@ ODM_ReleaseTimer(
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
)
{
@ -659,8 +659,3 @@ ODM_FillH2CCmd(
return TRUE;
}
#endif

22
hal/rtl8188e_cmd.c
View file

@ -41,7 +41,7 @@
static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)
{
u8 read_down = _FALSE;
int retry_cnts = 100;
int retry_cnts = 100;
u8 valid;
@ -65,8 +65,8 @@ static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)
/*****************************************
* H2C Msg format :
* 0x1DF - 0x1D0
*| 31 - 8 | 7-5 4 - 0 |
*| h2c_msg |Class_ID CMD_ID |
*| 31 - 8 | 7-5 4 - 0 |
*| h2c_msg |Class_ID CMD_ID |
*
* Extend 0x1FF - 0x1F0
*|31 - 0 |
@ -160,7 +160,7 @@ _func_enter_;
bcmd_down = _TRUE;
// DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n"
// ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);
// ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);
pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS;
@ -387,7 +387,7 @@ void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
u32 rate_len, pktlen;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
@ -593,7 +593,7 @@ void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr
u32 pktlen;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
//DBG_871X("%s\n", __func__);
@ -635,14 +635,14 @@ CheckFwRsvdPageContent(
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
u32 MaxBcnPageNum;
if (pHalData->FwRsvdPageStartOffset != 0)
{
/*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);
if (pHalData->FwRsvdPageStartOffset != 0)
{
/*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);
RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset),
("CheckFwRsvdPageContent(): The reserved page content has been"\
"destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!",
MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/
}
}
}
//
@ -651,7 +651,7 @@ CheckFwRsvdPageContent(
// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
// Input:
// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw,
// so we need to set the packet length to total lengh.
// so we need to set the packet length to total lengh.
// TRUE: At the second time, we should send the first packet (default:beacon)
// to Hw again and set the lengh in descriptor to the real beacon lengh.
// 2009.10.15 by tynli.

11
hal/rtl8188e_dm.c
View file

@ -283,7 +283,7 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);
}
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
#ifdef CONFIG_DISABLE_ODM
pdmpriv->InitODMFlag = 0;
@ -330,7 +330,7 @@ static void Update_ODM_ComInfo_88E(PADAPTER Adapter)
#if (MP_DRIVER==1)
if (Adapter->registrypriv.mp_mode == 1)
{
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |
ODM_RF_TX_PWR_TRACK;
}
#endif//(MP_DRIVER==1)
@ -524,7 +524,7 @@ void rtl8188e_init_dm_priv(IN PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
//_rtw_spinlock_init(&(pHalData->odm_stainfo_lock));
Init_ODM_ComInfo_88E(Adapter);
@ -539,7 +539,7 @@ void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);
@ -575,7 +575,7 @@ u8 AntDivBeforeLink8188E(PADAPTER Adapter )
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm =&pHalData->odmpriv;
PDM_ODM_T pDM_Odm =&pHalData->odmpriv;
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
@ -610,4 +610,3 @@ u8 AntDivBeforeLink8188E(PADAPTER Adapter )
}
#endif

58
hal/rtl8188e_hal_init.c
View file

@ -724,8 +724,8 @@ _WriteFW(
// Since we need dynamic decide method of dwonload fw, so we call this function to get chip version.
// We can remove _ReadChipVersion from ReadpadapterInfo8192C later.
int ret = _SUCCESS;
u32 pageNums,remainSize ;
u32 page, offset;
u32 pageNums,remainSize ;
u32 page, offset;
u8 *bufferPtr = (u8*)buffer;
#ifdef CONFIG_PCI_HCI
@ -775,7 +775,7 @@ static s32 _FWFreeToGo(PADAPTER padapter)
{
u32 counter = 0;
u32 value32;
u8 value8;
u8 value8;
// polling CheckSum report
do {
@ -1206,8 +1206,8 @@ static VOID
Hal_EfuseReadEFuse88E(
PADAPTER Adapter,
u16 _offset,
u16 _size_byte,
u8 *pbuf,
u16 _size_byte,
u8 *pbuf,
IN BOOLEAN bPseudoTest
)
{
@ -1454,8 +1454,8 @@ ReadEFuseByIC(
PADAPTER Adapter,
u8 efuseType,
u16 _offset,
u16 _size_byte,
u8 *pbuf,
u16 _size_byte,
u8 *pbuf,
IN BOOLEAN bPseudoTest
)
{
@ -1513,8 +1513,8 @@ ReadEFuse_Pseudo (
PADAPTER Adapter,
u8 efuseType,
u16 _offset,
u16 _size_byte,
u8 *pbuf,
u16 _size_byte,
u8 *pbuf,
IN BOOLEAN bPseudoTest
)
{
@ -1526,8 +1526,8 @@ rtl8188e_ReadEFuse(
PADAPTER Adapter,
u8 efuseType,
u16 _offset,
u16 _size_byte,
u8 *pbuf,
u16 _size_byte,
u8 *pbuf,
IN BOOLEAN bPseudoTest
)
{
@ -2524,7 +2524,7 @@ hal_EfusePgCheckAvailableAddr(
static VOID
hal_EfuseConstructPGPkt(
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *pData,
IN PPGPKT_STRUCT pTargetPkt
@ -2543,13 +2543,13 @@ hal_EfuseConstructPGPkt(
static BOOLEAN
hal_EfusePgPacketWrite_BT(
IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *pData,
IN BOOLEAN bPseudoTest
)
{
PGPKT_STRUCT targetPkt;
PGPKT_STRUCT targetPkt;
u16 startAddr=0;
u8 efuseType=EFUSE_BT;
@ -2573,13 +2573,13 @@ hal_EfusePgPacketWrite_BT(
static BOOLEAN
hal_EfusePgPacketWrite_8188e(
IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *pData,
IN BOOLEAN bPseudoTest
)
{
PGPKT_STRUCT targetPkt;
PGPKT_STRUCT targetPkt;
u16 startAddr=0;
u8 efuseType=EFUSE_WIFI;
@ -2603,7 +2603,7 @@ hal_EfusePgPacketWrite_8188e(
static int
Hal_EfusePgPacketWrite_Pseudo (IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *data,
IN BOOLEAN bPseudoTest)
@ -2617,7 +2617,7 @@ Hal_EfusePgPacketWrite_Pseudo (IN PADAPTER pAdapter,
static int
Hal_EfusePgPacketWrite(IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *data,
IN BOOLEAN bPseudoTest)
@ -2631,7 +2631,7 @@ Hal_EfusePgPacketWrite(IN PADAPTER pAdapter,
static int
rtl8188e_Efuse_PgPacketWrite(IN PADAPTER pAdapter,
IN u8 offset,
IN u8 offset,
IN u8 word_en,
IN u8 *data,
IN BOOLEAN bPseudoTest)
@ -3190,7 +3190,7 @@ Hal_ReadPowerValueFromPROM_8188E(
else
{
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
}
@ -3270,7 +3270,7 @@ Hal_GetChnlGroup(
}
static u8
Hal_GetChnlGroup88E(
IN u8 chnl,
IN u8 chnl,
OUT u8* pGroup
)
{
@ -3380,7 +3380,7 @@ void Hal_ReadPowerSavingMode88E(
void
Hal_ReadTxPowerInfo88E(
IN PADAPTER padapter,
IN PADAPTER padapter,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
@ -3580,9 +3580,9 @@ Hal_ReadAntennaDiversity88E(
if (registry_par->antdiv_type == 0)// If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead.
{
pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
if (pHalData->TRxAntDivType == 0xFF)
pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; // For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port)
pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
if (pHalData->TRxAntDivType == 0xFF)
pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; // For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port)
}
else{
pHalData->TRxAntDivType = registry_par->antdiv_type ;
@ -3594,7 +3594,7 @@ Hal_ReadAntennaDiversity88E(
else
{
pHalData->AntDivCfg = 0;
pHalData->TRxAntDivType = pHalData->TRxAntDivType; // The value in the driver setting of device manager.
pHalData->TRxAntDivType = pHalData->TRxAntDivType; // The value in the driver setting of device manager.
}
DBG_871X("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n",pHalData->AntDivCfg, pHalData->TRxAntDivType);
@ -3605,8 +3605,8 @@ Hal_ReadAntennaDiversity88E(
void
Hal_ReadThermalMeter_88E(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -3715,5 +3715,3 @@ void SetBcnCtrlReg(
rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
}

38
hal/rtl8188e_mp.c
View file

@ -304,7 +304,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
*/
void Hal_SetChannel(PADAPTER pAdapter)
{
u8 eRFPath;
u8 eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct mp_priv *pmp = &pAdapter->mppriv;
@ -319,7 +319,7 @@ void Hal_SetChannel(PADAPTER pAdapter)
// set RF channel register
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
{
if (IS_HARDWARE_TYPE_8192D(pAdapter))
if (IS_HARDWARE_TYPE_8192D(pAdapter))
_write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, ODM_CHANNEL, 0xFF, channel);
else
_write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
@ -530,9 +530,9 @@ void Hal_SetAntenna(PADAPTER pAdapter)
case ANTENNA_A:
p_ofdm_tx->r_tx_antenna = 0x1;
r_ofdm_tx_en_val = 0x1;
p_ofdm_tx->r_ant_l = 0x1;
p_ofdm_tx->r_ant_ht_s1 = 0x1;
p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
p_ofdm_tx->r_ant_l = 0x1;
p_ofdm_tx->r_ant_ht_s1 = 0x1;
p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
p_cck_txrx->r_ccktx_enable = 0x8;
chgTx = 1;
@ -561,9 +561,9 @@ void Hal_SetAntenna(PADAPTER pAdapter)
case ANTENNA_B:
p_ofdm_tx->r_tx_antenna = 0x2;
r_ofdm_tx_en_val = 0x2;
p_ofdm_tx->r_ant_l = 0x2;
p_ofdm_tx->r_ant_ht_s1 = 0x2;
p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
p_ofdm_tx->r_ant_l = 0x2;
p_ofdm_tx->r_ant_ht_s1 = 0x2;
p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
p_cck_txrx->r_ccktx_enable = 0x4;
chgTx = 1;
@ -594,9 +594,9 @@ void Hal_SetAntenna(PADAPTER pAdapter)
case ANTENNA_AB: // For 8192S
p_ofdm_tx->r_tx_antenna = 0x3;
r_ofdm_tx_en_val = 0x3;
p_ofdm_tx->r_ant_l = 0x3;
p_ofdm_tx->r_ant_ht_s1 = 0x3;
p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
p_ofdm_tx->r_ant_l = 0x3;
p_ofdm_tx->r_ant_ht_s1 = 0x3;
p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
p_cck_txrx->r_ccktx_enable = 0xC;
chgTx = 1;
@ -631,22 +631,22 @@ void Hal_SetAntenna(PADAPTER pAdapter)
switch (pAdapter->mppriv.antenna_rx)
{
case ANTENNA_A:
r_rx_antenna_ofdm = 0x1; // A
p_cck_txrx->r_cckrx_enable = 0x0; // default: A
r_rx_antenna_ofdm = 0x1; // A
p_cck_txrx->r_cckrx_enable = 0x0; // default: A
p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A
chgRx = 1;
break;
case ANTENNA_B:
r_rx_antenna_ofdm = 0x2; // B
p_cck_txrx->r_cckrx_enable = 0x1; // default: B
r_rx_antenna_ofdm = 0x2; // B
p_cck_txrx->r_cckrx_enable = 0x1; // default: B
p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B
chgRx = 1;
break;
case ANTENNA_AB:
r_rx_antenna_ofdm = 0x3; // AB
p_cck_txrx->r_cckrx_enable = 0x0; // default:A
r_rx_antenna_ofdm = 0x3; // AB
p_cck_txrx->r_cckrx_enable = 0x0; // default:A
p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B
chgRx = 1;
break;
@ -827,7 +827,7 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
}
if (is92C)
{
{
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
rtw_usleep_os(100);
if (rfPath == RF_PATH_A)
@ -854,7 +854,7 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
{ // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
{ // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
// <20120326, Kordan> Only in single tone mode. (asked by Edlu)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
{

67
hal/rtl8188e_phycfg.c
View file

@ -379,7 +379,7 @@ rtl8188e_PHY_QueryBBReg(
IN u32 BitMask
)
{
u32 ReturnValue = 0, OriginalValue, BitShift;
u32 ReturnValue = 0, OriginalValue, BitShift;
u16 BBWaitCounter = 0;
#if (DISABLE_BB_RF == 1)
@ -492,7 +492,7 @@ phy_RFSerialRead(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
u32 NewOffset;
u32 tmplong,tmplong2;
u32 tmplong,tmplong2;
u8 RfPiEnable=0;
//
// Make sure RF register offset is correct
@ -575,7 +575,7 @@ phy_RFSerialRead(
* serial write. Driver need to implement (1) and (2).
* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
*
* Note: For RF8256 only
* Note: For RF8256 only
* The total count of RTL8256(Zebra4) register is around 36 bit it only employs
* 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
* to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
@ -790,20 +790,20 @@ rtl8188e_PHY_SetRFReg(
* Overview: This function read BB parameters from general file format, and do register
* Read/Write
*
* Input: PADAPTER Adapter
* ps1Byte pFileName
* Input: PADAPTER Adapter
* ps1Byte pFileName
*
* Output: NONE
*
* Return: RT_STATUS_SUCCESS: configuration file exist
*
* Note: The format of MACPHY_REG.txt is different from PHY and RF.
* Note: The format of MACPHY_REG.txt is different from PHY and RF.
* [Register][Mask][Value]
*---------------------------------------------------------------------------*/
static int
phy_ConfigMACWithParaFile(
IN PADAPTER Adapter,
IN u8* pFileName
IN u8* pFileName
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -819,14 +819,14 @@ phy_ConfigMACWithParaFile(
* Overview: This function read BB parameters from Header file we gen, and do register
* Read/Write
*
* Input: PADAPTER Adapter
* ps1Byte pFileName
* Input: PADAPTER Adapter
* ps1Byte pFileName
*
* Output: NONE
*
* Return: RT_STATUS_SUCCESS: configuration file exist
*
* Note: The format of MACPHY_REG.txt is different from PHY and RF.
* Note: The format of MACPHY_REG.txt is different from PHY and RF.
* [Register][Mask][Value]
*---------------------------------------------------------------------------*/
#ifndef CONFIG_PHY_SETTING_WITH_ODM
@ -1046,8 +1046,8 @@ phy_InitBBRFRegisterDefinition(
* Overview: This function read BB parameters from general file format, and do register
* Read/Write
*
* Input: PADAPTER Adapter
* ps1Byte pFileName
* Input: PADAPTER Adapter
* ps1Byte pFileName
*
* Output: NONE
*
@ -1059,7 +1059,7 @@ phy_InitBBRFRegisterDefinition(
static int
phy_ConfigBBWithParaFile(
IN PADAPTER Adapter,
IN u8* pFileName
IN u8* pFileName
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -1098,8 +1098,8 @@ phy_ConfigBBExternalPA(
* Overview: This function read BB parameters from general file format, and do register
* Read/Write
*
* Input: PADAPTER Adapter
* u1Byte ConfigType 0 => PHY_CONFIG
* Input: PADAPTER Adapter
* u1Byte ConfigType 0 => PHY_CONFIG
* 1 =>AGC_TAB
*
* Output: NONE
@ -1111,7 +1111,7 @@ phy_ConfigBBExternalPA(
static int
phy_ConfigBBWithHeaderFile(
IN PADAPTER Adapter,
IN u8 ConfigType
IN u8 ConfigType
)
{
int i;
@ -1119,7 +1119,7 @@ phy_ConfigBBWithHeaderFile(
u32* Rtl819XAGCTAB_Array_Table;
u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
DM_ODM_T *podmpriv = &pHalData->odmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
int ret = _SUCCESS;
@ -1365,13 +1365,13 @@ storePwrIndexDiffRateOffset(
*
* Revised History:
* When Who Remark
* 11/06/2008 MHC Create Version 0.
* 11/06/2008 MHC Create Version 0.
* 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
*---------------------------------------------------------------------------*/
static int
phy_ConfigBBWithPgParaFile(
IN PADAPTER Adapter,
IN u8* pFileName)
IN u8* pFileName)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -1396,13 +1396,13 @@ phy_ConfigBBWithPgParaFile(
*
* Revised History:
* When Who Remark
* 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
* 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
* 11/10/2008 tynli Modify to mew files.
*---------------------------------------------------------------------------*/
static int
phy_ConfigBBWithPgHeaderFile(
IN PADAPTER Adapter,
IN u8 ConfigType)
IN u8 ConfigType)
{
int i;
u32* Rtl819XPHY_REGArray_Table_PG;
@ -1651,8 +1651,8 @@ PHY_RFConfig8188E(
*
* Overview: This function read RF parameters from general file format, and do RF 3-wire
*
* Input: PADAPTER Adapter
* ps1Byte pFileName
* Input: PADAPTER Adapter
* ps1Byte pFileName
* RF_RADIO_PATH_E eRFPath
*
* Output: NONE
@ -1664,7 +1664,7 @@ PHY_RFConfig8188E(
int
rtl8188e_PHY_ConfigRFWithParaFile(
IN PADAPTER Adapter,
IN u8* pFileName,
IN u8* pFileName,
RF_RADIO_PATH_E eRFPath
)
{
@ -1721,8 +1721,8 @@ PHY_ConfigRFExternalPA(
*
* Overview: This function read RF parameters from general file format, and do RF 3-wire
*
* Input: PADAPTER Adapter
* ps1Byte pFileName
* Input: PADAPTER Adapter
* ps1Byte pFileName
* RF_RADIO_PATH_E eRFPath
*
* Output: NONE
@ -1907,7 +1907,7 @@ exit:
* Overview: This function is write register and then readback to make sure whether
* BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
*
* Input: PADAPTER Adapter
* Input: PADAPTER Adapter
* HW90_BLOCK_E CheckBlock
* RF_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
*
@ -2132,7 +2132,7 @@ phy_TxPwrIdxToDbm(
VOID
PHY_GetTxPowerLevel8188E(
IN PADAPTER Adapter,
OUT u32* powerlevel
OUT u32* powerlevel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -2403,7 +2403,7 @@ PHY_ScanOperationBackup8188E(
*
* Overview: Timer callback function for SetSetBWMode
*
* Input: PRT_TIMER pTimer
* Input: PRT_TIMER pTimer
*
* Output: NONE
*
@ -2547,7 +2547,7 @@ _PHY_SetBWMode92C(
*
* Overview: This function is export to "HalCommon" moudule
*
* Input: PADAPTER Adapter
* Input: PADAPTER Adapter
* HT_CHANNEL_WIDTH Bandwidth //20M or 40M
*
* Output: NONE
@ -2564,7 +2564,7 @@ PHY_SetBWMode8188E(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
// Modified it for 20/40 mhz switch by guangan 070531
//PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
@ -2645,7 +2645,7 @@ PHY_SwChnl8188E( // Call after initialization
if (pHalData->rf_chip == RF_PSEUDO_11N)
{
//pHalData->SwChnlInProgress=FALSE;
return; //return immediately if it is peudo-phy
return; //return immediately if it is peudo-phy
}
//if (pHalData->SwChnlInProgress)
@ -2938,7 +2938,7 @@ _PHY_DumpRFReg(IN PADAPTER pAdapter)
//
// Description:
// To dump all Tx FIFO LLT related link-list table.
// To dump all Tx FIFO LLT related link-list table.
// Added by Roger, 2009.03.10.
//
VOID
@ -2978,4 +2978,3 @@ DumpBBDbgPort_92CU(
}
#endif

19
hal/rtl8188e_rf6052.c
View file

@ -34,7 +34,7 @@
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
* 11/05/2008 MHC Add API for tw power setting.
* 11/05/2008 MHC Add API for tw power setting.
*
*
******************************************************************************/
@ -88,7 +88,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
*
* Revised History:
* When Who Remark
* 09/25/2008 MHC Create Version 0.
* 09/25/2008 MHC Create Version 0.
* Firmwaer support the utility later.
*
*---------------------------------------------------------------------------*/
@ -153,7 +153,7 @@ rtl8188e_PHY_RF6052SetBandwidth(
*
* Revised History:
* When Who Remark
* 11/05/2008 MHC Simulate 8192series..
* 11/05/2008 MHC Simulate 8192series..
*
*---------------------------------------------------------------------------*/
@ -165,7 +165,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
//PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
BOOLEAN TurboScanOff = _FALSE;
@ -339,7 +339,7 @@ void getTxPowerWriteValByRegulatory88E(
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
s1Byte pwr_diff=0;
u4Byte writeVal, customer_limit, rf;
u4Byte writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory;
//
@ -498,7 +498,7 @@ void getTxPowerWriteValByRegulatory88E(
static void writeOFDMPowerReg88E(
IN PADAPTER Adapter,
IN u8 index,
IN u32* pValue
IN u32* pValue
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -570,7 +570,7 @@ static void writeOFDMPowerReg88E(
*
* Revised History:
* When Who Remark
* 11/05/2008 MHC Simulate 8192 series method.
* 11/05/2008 MHC Simulate 8192 series method.
* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
* A/B pwr difference or legacy/HT pwr diff.
* 2. We concern with path B legacy/HT OFDM difference.
@ -689,7 +689,7 @@ phy_RF6052_Config_ParaFile(
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
@ -805,7 +805,7 @@ PHY_RF6052_Config8188E(
*
* Revised History:
* When Who Remark
* 11/20/2008 MHC Create Version 0.
* 11/20/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
u32
@ -1008,4 +1008,3 @@ PHY_RFShadowRefresh(
} /* PHY_RFShadowRead */
/* End of HalRf6052.c */

7
hal/rtl8188e_rxdesc.c
View file

@ -96,7 +96,7 @@ static void process_rssi(_adapter *padapter,union recv_frame *prframe)
static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
{
u32 last_evm=0, tmpVal;
struct rx_pkt_attrib *pattrib;
struct rx_pkt_attrib *pattrib;
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
struct signal_stat * signal_stat;
#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
@ -267,10 +267,10 @@ void update_recvframe_phyinfo_88e(
union recv_frame *precvframe,
struct phy_stat *pphy_status)
{
PADAPTER padapter = precvframe->u.hdr.adapter;
PADAPTER padapter = precvframe->u.hdr.adapter;
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
u8 *wlanhdr;
ODM_PACKET_INFO_T pkt_info;
u8 *sa;
@ -346,4 +346,3 @@ void update_recvframe_phyinfo_88e(
rtl8188e_process_phy_info(padapter, precvframe);
}
}

1
hal/rtl8188e_sreset.c
View file

@ -238,4 +238,3 @@ void rtl8188e_sreset_linked_status_check(_adapter *padapter)
}
}
#endif

6
hal/rtl8188e_xmit.c
View file

@ -122,7 +122,7 @@ void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc)
struct EMInfo{
u8 EMPktNum;
u8 EMPktNum;
u16 EMPktLen[EARLY_MODE_MAX_PKT_NUM];
};
@ -229,7 +229,7 @@ void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmit
#ifdef DBG_EMINFO
DBG_8192C("\n%s ==> agg_num:%d\n",__func__, pframe->agg_num);
for (index=0;index<pframe->agg_num;index++){
offset = pxmitpriv->agg_pkt[index].offset;
offset = pxmitpriv->agg_pkt[index].offset;
pktlen = pxmitpriv->agg_pkt[index].pkt_len;
DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__func__,index,offset);
DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__func__,index,pktlen);
@ -288,5 +288,3 @@ void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmit
}
#endif

1
hal/rtl8188eu_led.c
View file

@ -159,4 +159,3 @@ rtl8188eu_DeInitSwLeds(
DeInitLed871x( &(ledpriv->SwLed0) );
DeInitLed871x( &(ledpriv->SwLed1) );
}

2
hal/rtl8188eu_recv.c
View file

@ -235,5 +235,3 @@ void rtl8188eu_free_recv_priv (_adapter *padapter)
#endif
}

5
hal/rtl8188eu_xmit.c
View file

@ -72,7 +72,7 @@ u8 urb_zero_packet_chk(_adapter *padapter, int sz)
}
else
{
if ( ( (sz + TXDESC_SIZE) % 64 ) == 0 ) {
if ( ( (sz + TXDESC_SIZE) % 64 ) == 0 ) {
blnSetTxDescOffset = 1;
} else {
blnSetTxDescOffset = 0;
@ -528,7 +528,7 @@ if (padapter->registrypriv.mp_mode == 0)
//ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number
}
@ -1338,4 +1338,3 @@ _exit:
}
#endif

91
hal/usb_halinit.c
View file

@ -72,15 +72,15 @@ _ConfigNormalChipOutEP_8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
switch (NumOutPipe){
case 3:
case 3:
pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
pHalData->OutEpNumber=3;
break;
case 2:
case 2:
pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
pHalData->OutEpNumber=2;
break;
case 1:
case 1:
pHalData->OutEpQueueSel=TX_SELE_HQ;
pHalData->OutEpNumber=1;
break;
@ -471,8 +471,8 @@ _InitNormalChipRegPriority(
{
u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
_TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
_TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
_TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
@ -576,19 +576,19 @@ _InitNormalChipThreeOutEpPriority(
if (!pregistrypriv->wifi_spec ){// typical setting
beQ = QUEUE_LOW;
bkQ = QUEUE_LOW;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
bkQ = QUEUE_LOW;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
}
else{// for WMM
beQ = QUEUE_LOW;
bkQ = QUEUE_NORMAL;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
bkQ = QUEUE_NORMAL;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
}
_InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
}
@ -1181,7 +1181,7 @@ HwSuspendModeEnable_88eu(
IN u8 Type
)
{
//PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter);
//PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter);
u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
//if (!pDevice->RegUsbSS)
@ -1753,7 +1753,7 @@ CardDisableRTL8188EU(
)
{
// PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u8 val8;
u8 val8;
u16 val16;
u32 val32;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -1826,7 +1826,7 @@ u32 rtl8188eu_hal_deinit(PADAPTER Adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
DBG_8192C("==> %s\n",__func__);
DBG_8192C("==> %s\n",__func__);
#ifdef CONFIG_SUPPORT_USB_INT
rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
@ -1834,13 +1834,13 @@ u32 rtl8188eu_hal_deinit(PADAPTER Adapter)
#endif
#ifdef SUPPORT_HW_RFOFF_DETECTED
DBG_8192C("bkeepfwalive(%x)\n",Adapter->pwrctrlpriv.bkeepfwalive);
if (Adapter->pwrctrlpriv.bkeepfwalive)
{
DBG_8192C("bkeepfwalive(%x)\n",Adapter->pwrctrlpriv.bkeepfwalive);
if (Adapter->pwrctrlpriv.bkeepfwalive)
{
_ps_close_RF(Adapter);
if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
rtl8192cu_hw_power_down(Adapter);
}
}
else
#endif
{
@ -1977,8 +1977,8 @@ _ReadLEDSetting(
static VOID
_ReadThermalMeter(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
{
}
@ -1986,8 +1986,8 @@ _ReadThermalMeter(
static VOID
_ReadRFSetting(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
{
}
@ -1995,8 +1995,8 @@ _ReadRFSetting(
static void
_ReadPROMVersion(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
IN u8* PROMContent,
IN BOOLEAN AutoloadFail
)
{
}
@ -2044,8 +2044,8 @@ Hal_EfuseParsePIDVID_8188EU(
}
else
{
pHalData->EEPROMVID = EEPROM_Default_VID;
pHalData->EEPROMPID = EEPROM_Default_PID;
pHalData->EEPROMVID = EEPROM_Default_VID;
pHalData->EEPROMPID = EEPROM_Default_PID;
// Customer ID, 0x00 and 0xff are reserved for Realtek.
pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID;
@ -2271,7 +2271,7 @@ readAdapterInfo_8188EU(
}
static void _ReadPROMContent(
IN PADAPTER Adapter
IN PADAPTER Adapter
)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
@ -2504,7 +2504,7 @@ static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val)
//BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
//enable BCN1 Function for if2
//enable BCN1 Function for if2
//don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received)
rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
@ -2986,7 +2986,7 @@ void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
_func_enter_;
switch (variable)
@ -3249,7 +3249,7 @@ _func_enter_;
{
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u16 bcn_interval = *((u16 *)val);
u16 bcn_interval = *((u16 *)val);
if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){
DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d\n",__func__,bcn_interval,bcn_interval>>1);
rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio
@ -3326,7 +3326,7 @@ _func_enter_;
case HW_VAR_DM_FUNC_SET:
if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){
pdmpriv->DMFlag = pdmpriv->InitDMFlag;
podmpriv->SupportAbility = pdmpriv->InitODMFlag;
podmpriv->SupportAbility = pdmpriv->InitODMFlag;
}
else{
podmpriv->SupportAbility |= *((u32 *)val);
@ -3574,7 +3574,7 @@ _func_enter_;
case HW_VAR_INITIAL_GAIN:
{
DIG_T *pDigTable = &podmpriv->DM_DigTable;
u32 rx_gain = ((u32 *)(val))[0];
u32 rx_gain = ((u32 *)(val))[0];
if (rx_gain == 0xff){//restore rx gain
ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
@ -3621,7 +3621,7 @@ _func_enter_;
case HW_VAR_ANTENNA_DIVERSITY_SELECT:
{
u8 Optimum_antenna = (*(u8 *)val);
u8 Ant ;
u8 Ant ;
//switch antenna to Optimum_antenna
//DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
if (pHalData->CurAntenna != Optimum_antenna)
@ -3825,7 +3825,7 @@ _func_exit_;
void GetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
DM_ODM_T *podmpriv = &pHalData->odmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
_func_enter_;
switch (variable)
@ -4042,7 +4042,7 @@ SetHalDefVar8188EUsb(
{
u8 dm_func = *(( u8*)pValue);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
if (dm_func == 0){ //disable all dynamic func
podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
@ -4167,7 +4167,7 @@ void UpdateHalRAMask8188EUsb(PADAPTER padapter, u32 mac_id, u8 rssi_level)
//struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
@ -4307,7 +4307,7 @@ void SetBeaconRelatedRegisters8188EUsb(PADAPTER padapter)
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u32 bcn_ctrl_reg = REG_BCN_CTRL;
u32 bcn_ctrl_reg = REG_BCN_CTRL;
//reset TSF, enable update TSF, correcting TSF On Beacon
//REG_BCN_INTERVAL
@ -4322,9 +4322,9 @@ void SetBeaconRelatedRegisters8188EUsb(PADAPTER padapter)
//BCN interval
#ifdef CONFIG_CONCURRENT_MODE
if (padapter->iface_type == IFACE_PORT1){
if (padapter->iface_type == IFACE_PORT1){
bcn_ctrl_reg = REG_BCN_CTRL_1;
}
}
#endif
rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms
@ -4455,8 +4455,8 @@ _func_enter_;
pHalFunc->SetHwRegHandler = &SetHwReg8188EU;
pHalFunc->GetHwRegHandler = &GetHwReg8188EU;
pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
@ -4476,4 +4476,3 @@ _func_enter_;
_func_exit_;
}

31
hal/usb_ops_linux.c
View file

@ -526,10 +526,10 @@ _func_enter_;
usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe,
precvpriv->int_in_buf,
INTERRUPT_MSG_FORMAT_LEN,
usb_read_interrupt_complete,
adapter,
1);
INTERRUPT_MSG_FORMAT_LEN,
usb_read_interrupt_complete,
adapter,
1);
err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC);
if ((err) && (err != (-EPERM)))
@ -927,7 +927,7 @@ void rtl8188eu_recv_tasklet(void *priv)
static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
{
struct recv_buf *precvbuf = (struct recv_buf *)purb->context;
_adapter *padapter =(_adapter *)precvbuf->adapter;
_adapter *padapter =(_adapter *)precvbuf->adapter;
struct recv_priv *precvpriv = &padapter->recvpriv;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
@ -1043,9 +1043,9 @@ _func_enter_;
usb_fill_bulk_urb(purb, pusbd, pipe,
precvbuf->pbuf,
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
purb->transfer_dma = precvbuf->dma_transfer_addr;
purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
@ -1339,7 +1339,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
_irqL irqL;
uint isevt, *pbuf;
struct recv_buf *precvbuf = (struct recv_buf *)purb->context;
_adapter *padapter =(_adapter *)precvbuf->adapter;
_adapter *padapter =(_adapter *)precvbuf->adapter;
struct recv_priv *precvpriv = &padapter->recvpriv;
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
@ -1502,11 +1502,11 @@ _func_enter_;
}
tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
@ -1517,7 +1517,7 @@ _func_enter_;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
precvbuf->pbuf = precvbuf->pskb->data;
precvbuf->reuse = _FALSE;
}
@ -1536,9 +1536,9 @@ _func_enter_;
usb_fill_bulk_urb(purb, pusbd, pipe,
precvbuf->pbuf,
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
MAX_RECVBUF_SZ,
usb_read_port_complete,
precvbuf);//context is precvbuf
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != (-EPERM)))
@ -1628,4 +1628,3 @@ void rtl8188eu_set_hw_type(_adapter *padapter)
padapter->HardwareType = HARDWARE_TYPE_RTL8188EU;
DBG_871X("CHIP TYPE: RTL8188E\n");
}

1
include/Hal8188EFWImg_CE.h
View file

@ -26,4 +26,3 @@
extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
#endif //__INC_HAL8188E_FW_IMG_H

41
include/Hal8188EPhyCfg.h
View file

@ -82,21 +82,21 @@ typedef enum _RF_RADIO_PATH{
#define MAX_PG_GROUP 13
#define RF_PATH_MAX 2
#define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT 4 //path numbers
#define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT 4 //path numbers
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups
#define CHANNEL_GROUP_MAX_88E 6
#define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
@ -132,10 +132,10 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
@ -147,37 +147,37 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
@ -257,7 +257,7 @@ void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8188E( IN PADAPTER Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8188E( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8188E( IN PADAPTER Adapter,
@ -424,4 +424,3 @@ VOID SIC_Init(IN PADAPTER Adapter);
#endif // __INC_HAL8192CPHYCFG_H

1091
include/Hal8188EPhyReg.h
View file

File diff suppressed because it is too large Load diff

3
include/Hal8188EPwrSeq.h
View file

@ -58,7 +58,7 @@
#define RTL8188E_TRANS_END_STEPS 1
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
@ -174,4 +174,3 @@ extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif //__HAL8188EPWRSEQ_H__

27
include/Hal8188ERateAdaptive.h
View file

@ -19,7 +19,7 @@ Major Change History:
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#define TX_RPT2_ITEM_SIZE 8
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
//
@ -52,26 +52,26 @@ ODM_RAInfo_Init_all(
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
VOID
ODM_RA_UpdateRateInfo_8188E(
@ -84,9 +84,9 @@ ODM_RA_UpdateRateInfo_8188E(
VOID
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
);
VOID
@ -102,7 +102,6 @@ ODM_RA_TxRPT2Handle_8188E(
VOID
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
IN u2Byte minRptTime
);
#endif

1
include/Hal8188EReg.h
View file

@ -44,4 +44,3 @@
#endif

39
include/Hal8192CPhyCfg.h
View file

@ -30,7 +30,7 @@
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*****************************************************************************/
@ -122,12 +122,12 @@ typedef enum _RF_RADIO_PATH{
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
@ -168,10 +168,10 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
@ -183,37 +183,37 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
@ -276,7 +276,7 @@ int PHY_BBConfig8192C( IN PADAPTER Adapter );
int PHY_RFConfig8192C( IN PADAPTER Adapter );
/* RF config */
int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_RADIO_PATH_E eRFPath);
@ -298,7 +298,7 @@ void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter,
@ -392,4 +392,3 @@ extern void PHY_Reconfig_To_1T1R(_adapter *padapter);
#define PHY_SetMacReg PHY_SetBBReg
#endif // __INC_HAL8192CPHYCFG_H

331
include/Hal8192CPhyReg.h
View file

@ -35,7 +35,7 @@
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
* 09/25/2008 MH 1. Add RL6052 register definition
*
@ -179,8 +179,8 @@
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxHP 0xa14
@ -191,20 +191,20 @@
#define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rConfig_Pmpd_AntB 0xb98
#define rAPK 0xbd8
@ -218,13 +218,13 @@
#define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
@ -255,7 +255,7 @@
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c
#define rOFDM0_XCTxIQImbalance 0xc90
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxIQImbalance 0xc98
#define rOFDM0_XDTxAFE 0xc9c
@ -298,8 +298,8 @@
#define rOFDM_LongCFOCD 0xdb8
#define rOFDM_TailCFOAB 0xdbc
#define rOFDM_TailCFOCD 0xdc0
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_BWReport 0xdcc
#define rOFDM_AGCReport 0xdd0
#define rOFDM_RxSNR 0xdd4
@ -324,7 +324,7 @@
#define rTx_IQK_PI_A 0xe38
#define rRx_IQK_PI_A 0xe3c
#define rTx_IQK 0xe40
#define rTx_IQK 0xe40
#define rRx_IQK 0xe44
#define rIQK_AGC_Pts 0xe48
#define rIQK_AGC_Rsp 0xe4c
@ -361,10 +361,10 @@
#define rRx_Power_After_IQK_B_2 0xecc
#define rRx_OFDM 0xed0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rPMPD_ANAEN 0xeec
//
@ -513,7 +513,7 @@
#define bCCKTxStatus 0x1
#define bOFDMTxStatus 0x2
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
@ -522,157 +522,157 @@
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bAntennaSelect 0x0300
#define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000
#define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
// 3. Page9(0x900)
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
// 4. PageA(0xA00)
#define bCCKBBMode 0x3 // Useless
@ -716,7 +716,7 @@
#define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly
#define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300
@ -1077,7 +1077,7 @@
//for PutRFRegsetting & GetRFRegSetting BitMask
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff
#define bRFRegOffsetMask 0xfffff
#define bEnable 0x1 // Useless
#define bDisable 0x0
@ -1120,4 +1120,3 @@
#endif //__INC_HAL8192SPHYREG_H

31
include/Hal8192DPhyCfg.h
View file

@ -31,7 +31,7 @@
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*****************************************************************************/
@ -180,7 +180,7 @@ typedef enum _MACPHY_MODE_CHANGE_ACTION{
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
typedef enum _BAND_TYPE{
BAND_ON_2_4G = 1,
BAND_ON_2_4G = 1,
BAND_ON_5G = 2,
BAND_ON_BOTH,
BANDMAX
@ -218,10 +218,10 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
@ -233,37 +233,37 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
@ -329,7 +329,7 @@ extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
/* RF config */
int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_CONTENT Content,
@ -351,7 +351,7 @@ void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
@ -439,7 +439,7 @@ PHY_UpdateBBRFConfiguration8192D(
VOID PHY_ReadMacPhyMode92D(
IN PADAPTER Adapter,
IN BOOLEAN AutoloadFail
IN BOOLEAN AutoloadFail
);
VOID PHY_ConfigMacPhyMode92D(
@ -483,4 +483,3 @@ PHY_InitPABias92D(IN PADAPTER Adapter);
#define PHY_SetMacReg PHY_SetBBReg
#endif // __INC_HAL8192SPHYCFG_H

369
include/Hal8192DPhyReg.h
View file

@ -35,7 +35,7 @@
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
* 09/25/2008 MH 1. Add RL6052 register definition
*
@ -170,8 +170,8 @@
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxHP 0xa14
@ -182,44 +182,44 @@
#define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
@ -245,13 +245,13 @@
#define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
@ -282,7 +282,7 @@
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c
#define rOFDM0_XCTxIQImbalance 0xc90
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxIQImbalance 0xc98
#define rOFDM0_XDTxAFE 0xc9c
@ -325,8 +325,8 @@
#define rOFDM_LongCFOCD 0xdb8
#define rOFDM_TailCFOAB 0xdbc
#define rOFDM_TailCFOCD 0xdc0
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_BWReport 0xdcc
#define rOFDM_AGCReport 0xdd0
#define rOFDM_RxSNR 0xdd4
@ -360,7 +360,7 @@
#define rTx_IQK_PI_A 0xe38
#define rRx_IQK_PI_A 0xe3c
#define rTx_IQK 0xe40
#define rTx_IQK 0xe40
#define rRx_IQK 0xe44
#define rIQK_AGC_Pts 0xe48
#define rIQK_AGC_Rsp 0xe4c
@ -397,10 +397,10 @@
#define rRx_Power_After_IQK_B_2 0xecc
#define rRx_OFDM 0xed0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rPMPD_ANAEN 0xeec
//
@ -556,7 +556,7 @@
#define bCCKTxStatus 0x1
#define bOFDMTxStatus 0x2
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
@ -565,157 +565,157 @@
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bAntennaSelect 0x0300
#define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000
#define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
// 3. Page9(0x900)
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
// 4. PageA(0xA00)
#define bCCKBBMode 0x3 // Useless
@ -759,7 +759,7 @@
#define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly
#define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300
@ -1118,10 +1118,10 @@
#define bMaskCCK 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff
//#define bRFRegOffsetMask 0xfff
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff
//#define bRFRegOffsetMask 0xfff
//MAC0 will wirte PHY1
#define MAC0_ACCESS_PHY1 0x4000
@ -1169,4 +1169,3 @@
#endif //__INC_HAL8192SPHYREG_H

1
include/Hal8723APhyCfg.h
View file

@ -27,4 +27,3 @@ int PHY_RFConfig8723A( IN PADAPTER Adapter );
s32 PHY_MACConfig8723A(PADAPTER padapter);
#endif

3
include/Hal8723APhyReg.h
View file

@ -36,7 +36,7 @@
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
@ -71,4 +71,3 @@
#define rPm_Rx3_AntB 0xbf8
#endif

3
include/Hal8723PwrSeq.h
View file

@ -35,7 +35,7 @@
#define RTL8723A_TRANS_END_STEPS 1
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
@ -168,4 +168,3 @@ extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
#endif

1
include/HalHWImg8188E_BB.h
View file

@ -53,4 +53,3 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
#endif
#endif // end of HWIMG_SUPPORT

1
include/HalHWImg8188E_MAC.h
View file

@ -35,4 +35,3 @@ ODM_ReadAndConfig_MAC_REG_8188E(
#endif
#endif // end of HWIMG_SUPPORT

1
include/HalHWImg8188E_RF.h
View file

@ -35,4 +35,3 @@ ODM_ReadAndConfig_RadioA_1T_8188E(
#endif
#endif // end of HWIMG_SUPPORT

5
include/HalPhyRf.h
View file

@ -37,7 +37,7 @@ void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
//
void
PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
IN BOOLEAN bReCovery);
IN BOOLEAN bReCovery);
//
// LC calibrate
@ -50,7 +50,7 @@ PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
//
void
PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
IN s1Byte delta);
IN s1Byte delta);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59
@ -67,4 +67,3 @@ ODM_GetRightChnlPlaceforIQK(
#endif // #ifndef __HAL_PHY_RF_H__

5
include/HalPhyRf_8188e.h
View file

@ -55,7 +55,7 @@ PHY_IQCalibrate_8188E(
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
IN BOOLEAN bReCovery);
//
@ -80,7 +80,7 @@ PHY_APCalibrate_8188E(
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
IN s1Byte delta);
void
PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter);
@ -132,4 +132,3 @@ _PHY_PathAStandBy(
#endif // #ifndef __HAL_PHY_RF_8188E_H__

1
include/HalPwrSeqCmd.h
View file

@ -135,4 +135,3 @@ u8 HalPwrSeqCmdParsing(
WLAN_PWR_CFG PwrCfgCmd[]);
#endif

53
include/HalVerDef.h
View file

@ -20,56 +20,56 @@
#ifndef __HAL_VERSION_DEF_H__
#define __HAL_VERSION_DEF_H__
#define TRUE _TRUE
#define TRUE _TRUE
#define FALSE _FALSE
// HAL_IC_TYPE_E
typedef enum tag_HAL_IC_Type_Definition
{
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
}HAL_IC_TYPE_E;
//HAL_CHIP_TYPE_E
typedef enum tag_HAL_CHIP_Type_Definition
{
TEST_CHIP = 0,
NORMAL_CHIP = 1,
TEST_CHIP = 0,
NORMAL_CHIP = 1,
FPGA = 2,
}HAL_CHIP_TYPE_E;
//HAL_CUT_VERSION_E
typedef enum tag_HAL_Cut_Version_Definition
{
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
}HAL_CUT_VERSION_E;
// HAL_Manufacturer
typedef enum tag_HAL_Manufacturer_Version_Definition
{
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
}HAL_VENDOR_E;
typedef enum tag_HAL_RF_Type_Definition
{
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_2T2R = 2,
RF_TYPE_2T3R = 3,
RF_TYPE_2T4R = 4,
@ -137,7 +137,7 @@ typedef struct tag_HAL_VERSION
//----------------------------------------------------------------------------
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
@ -153,4 +153,3 @@ typedef struct tag_HAL_VERSION
#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE)
#endif

41
include/autoconf.h
View file

@ -112,13 +112,13 @@
//#define CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
//#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#endif
#define CONFIG_IOL
//#else //#ifndef CONFIG_MP_INCLUDED
//#else //#ifndef CONFIG_MP_INCLUDED
//#endif //#ifndef CONFIG_MP_INCLUDED
//#endif //#ifndef CONFIG_MP_INCLUDED
#define CONFIG_AP_MODE
#ifdef CONFIG_AP_MODE
@ -204,7 +204,7 @@
#endif // CONFIG_BR_EXT
#define CONFIG_TX_MCAST2UNI // Support IP multicast->unicast
//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs.
//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs.
/*
@ -223,11 +223,11 @@
/*
* CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now!
*/
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
#ifdef CONFIG_PLATFORM_ARM_SUNxI
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
#define CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif
#endif
@ -319,20 +319,20 @@
* Outsource Related Config
*/
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8188EE_SUPPORT 0
#define RTL8188EU_SUPPORT 1
@ -340,13 +340,13 @@
#define RTL8188E_SUPPORT (RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT)
#define RTL8188E_FOR_TEST_CHIP 0
//#if (RTL8188E_SUPPORT==1)
#define RATE_ADAPTIVE_SUPPORT 1
#define RATE_ADAPTIVE_SUPPORT 1
#define POWER_TRAINING_ACTIVE 1
//#endif
#ifdef CONFIG_USB_TX_AGGREGATION
//#define CONFIG_TX_EARLY_MODE
//#define CONFIG_TX_EARLY_MODE
#endif
#ifdef CONFIG_TX_EARLY_MODE
@ -397,4 +397,3 @@
//#define CONFIG_SINGLE_XMIT_BUF
//RX use 1 urb
//#define CONFIG_SINGLE_RECV_BUF

7
include/basic_types.h
View file

@ -100,7 +100,7 @@
typedef void (*proc_t)(void*);
typedef __kernel_size_t SIZE_T;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
@ -145,7 +145,7 @@
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef __kernel_size_t SIZE_T;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
@ -171,7 +171,7 @@
// Byte Swapping routine.
//
#define EF1Byte
#define EF2Byte le16_to_cpu
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
@ -335,4 +335,3 @@
typedef unsigned char BOOLEAN,*PBOOLEAN;
#endif //__BASIC_TYPES_H__

1
include/circ_buf.h
View file

@ -25,4 +25,3 @@
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
#endif //_CIRC_BUF_H_

1
include/cmd_osdep.h
View file

@ -33,4 +33,3 @@ extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj);
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
#endif

17
include/drv_types.h
View file

@ -128,7 +128,7 @@ struct registry_priv
u8 network_mode; //infra, ad-hoc, auto
u8 channel;//ad-hoc support requirement
u8 wireless_mode;//A, B, G, auto
u8 scan_mode;//active, passive
u8 scan_mode;//active, passive
u8 radio_enable;
u8 preamble;//long, short, auto
u8 vrtl_carrier_sense;//Enable, Disable, Auto
@ -166,7 +166,7 @@ struct registry_priv
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;//for tx
u8 rx_stbc;
u8 rx_stbc;
u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted
#endif
u8 lowrate_two_xmit;
@ -353,10 +353,10 @@ struct dvobj_priv
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
// pci-e bridge */
u8 const_hostpci_aspm_setting;
u8 const_hostpci_aspm_setting;
// pci-e device */
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_backdoor;
u8 bdma64;
#endif//PLATFORM_LINUX
@ -453,7 +453,7 @@ struct _ADAPTER{
int DriverState;// for disable driver using module, use dongle to replace module.
int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd
int bDongle;//build-in module or external dongle
u16 chip_type;
u16 chip_type;
u16 HardwareType;
u16 interface_type;//USB,SDIO,SPI,PCI
@ -463,14 +463,14 @@ struct _ADAPTER{
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
//struct io_queue *pio_queue;
struct io_priv iopriv;
struct io_priv iopriv;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
struct registry_priv registrypriv;
struct pwrctrl_priv pwrctrlpriv;
struct eeprom_priv eeprompriv;
struct eeprom_priv eeprompriv;
struct led_priv ledpriv;
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
//Check BT status for BT Hung.
@ -663,4 +663,3 @@ __inline static u8 *myid(struct eeprom_priv *peepriv)
#endif //__DRV_TYPES_H__

3
include/drv_types_ce.h
View file

@ -64,7 +64,7 @@ typedef struct _MP_REG_ENTRY
typedef struct _USB_EXTENSION {
LPCUSB_FUNCS _lpUsbFuncs;
USB_HANDLE _hDevice;
PVOID pAdapter;
PVOID pAdapter;
} USB_EXTENSION, *PUSB_EXTENSION;
#endif
@ -79,4 +79,3 @@ typedef struct _OCTET_STRING{
#endif

1
include/drv_types_gspi.h
View file

@ -46,4 +46,3 @@ typedef struct gspi_data
} GSPI_DATA, *PGSPI_DATA;
#endif // #ifndef __DRV_TYPES_GSPI_H__

1
include/drv_types_linux.h
View file

@ -22,4 +22,3 @@
#endif

1
include/drv_types_sdio.h
View file

@ -68,4 +68,3 @@ typedef struct sdio_data
} SDIO_DATA, *PSDIO_DATA;
#endif

1
include/drv_types_xp.h
View file

@ -92,4 +92,3 @@ typedef struct _OCTET_STRING{
#endif

3
include/ethernet.h
View file

@ -30,7 +30,7 @@
#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address?
#define RT_ETH_IS_BROADCAST(_pAddr) ( \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[1]==0xff && \
((UCHAR *)(_pAddr))[2]==0xff && \
((UCHAR *)(_pAddr))[3]==0xff && \
@ -39,4 +39,3 @@
#endif // #ifndef __INC_ETHERNET_H

1
include/h2clbk.h
View file

@ -33,4 +33,3 @@ void _lbk_rsp(PADAPTER Adapter);
void _lbk_evt(IN PADAPTER Adapter);
void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);

1
include/hal_com.h
View file

@ -179,4 +179,3 @@ void c2h_evt_clear(_adapter *adapter);
s32 c2h_evt_read(_adapter *adapter, u8 *buf);
#endif //__HAL_COMMON_H__

17
include/hal_intf.h
View file

@ -31,8 +31,8 @@
enum RTL871X_HCI_TYPE {
RTW_PCIE = BIT0,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_GSPI = BIT3,
};
@ -233,8 +233,8 @@ struct hal_ops {
void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
u16 (*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
u8 (*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
BOOLEAN (*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
@ -275,10 +275,10 @@ typedef enum _RT_EEPROM_TYPE{
#define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
typedef enum _HARDWARE_TYPE{
HARDWARE_TYPE_RTL8180,
@ -470,4 +470,3 @@ s32 rtw_hal_c2h_handler(_adapter *adapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter);
#endif //__HAL_INTF_H__

21
include/ieee80211.h
View file

@ -127,11 +127,11 @@ enum {
#define IEEE_CRYPT_ALG_NAME_LEN 16
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_WEP104 BIT(2)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
@ -183,8 +183,8 @@ enum NETWORK_TYPE
WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only
WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck
WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only
//WIRELESS_AUTO = BIT(5),
WIRELESS_AC = BIT(6),
//WIRELESS_AUTO = BIT(5),
WIRELESS_AC = BIT(6),
//Combination
WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm
@ -228,7 +228,7 @@ typedef struct ieee_param {
} wpa_ie;
struct{
int command;
int reason_code;
int reason_code;
} mlme;
struct {
u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
@ -452,7 +452,7 @@ enum eap_type {
/* management */
#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020
#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030
#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040
@ -665,7 +665,7 @@ struct ieee80211_snap_hdr {
#define IEEE80211_24GHZ_BAND (1<<0)
#define IEEE80211_52GHZ_BAND (1<<1)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_NUM_OFDM_RATESLEN 8
@ -673,7 +673,7 @@ struct ieee80211_snap_hdr {
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
@ -1511,4 +1511,3 @@ int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *act
const char *action_public_str(u8 action);
#endif /* IEEE80211_H */

23
include/ieee80211_ext.h
View file

@ -65,24 +65,24 @@ struct rsn_ie_hdr {
struct wme_ac_parameter {
#if defined(__LITTLE_ENDIAN)
/* byte 1 */
u8 aifsn:4,
u8 aifsn:4,
acm:1,
aci:2,
reserved:1;
aci:2,
reserved:1;
/* byte 2 */
u8 eCWmin:4,
eCWmax:4;
u8 eCWmin:4,
eCWmax:4;
#elif defined(__BIG_ENDIAN)
/* byte 1 */
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
/* byte 2 */
u8 eCWmax:4,
eCWmin:4;
u8 eCWmax:4,
eCWmin:4;
#else
#error "Please fix <endian.h>"
#endif
@ -421,4 +421,3 @@ struct ieee80211_mgmt {
#endif

7
include/if_ether.h
View file

@ -73,14 +73,14 @@
#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */
#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */
#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_SNAP 0x0005 /* Internal only */
#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */
#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/
#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */
#define ETH_P_CONTROL 0x0016 /* Card specific control frames */
#define ETH_P_IRDA 0x0017 /* Linux-IrDA */
@ -110,4 +110,3 @@ struct _vlan {
#endif /* _LINUX_IF_ETHER_H */

1
include/ioctl_cfg80211.h
View file

@ -112,4 +112,3 @@ bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
#endif
#endif //__IOCTL_CFG80211_H__

3
include/ip.h
View file

@ -121,7 +121,7 @@ struct iphdr {
version:4;
#elif defined (__BIG_ENDIAN_BITFIELD)
__u8 version:4,
ihl:4;
ihl:4;
#else
#error "Please fix <asm/byteorder.h>"
#endif
@ -138,4 +138,3 @@ struct iphdr {
};
#endif /* _LINUX_IP_H */

1
include/mlme_osdep.h
View file

@ -37,4 +37,3 @@ extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie);
void rtw_reset_securitypriv( _adapter *adapter );
#endif //_MLME_OSDEP_H_

21
include/mp_custom_oid.h
View file

@ -38,7 +38,7 @@
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
@ -114,14 +114,14 @@
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
//
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
@ -240,7 +240,7 @@
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S
@ -299,7 +299,7 @@
//For SDIO INTERFACE only
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
//For USB INTERFACE only
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S
@ -314,8 +314,8 @@
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S
@ -327,7 +327,7 @@
#define OID_RT_SET_BANDWIDTH 0xFF871209 //S
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q
@ -351,4 +351,3 @@
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S
#endif //#ifndef __CUSTOM_OID_H

1
include/nic_spec.h
View file

@ -44,4 +44,3 @@
#endif // __RTL8711_SPEC_H__

285
include/odm.h
View file

@ -77,11 +77,11 @@
#define PSD_TH2 3
#define PSD_CHMIN 20 // Minimum channel number for BT AFH
#define SIR_STEP_SIZE 3
#define Smooth_Size_1 5
#define Smooth_Size_1 5
#define Smooth_TH_1 3
#define Smooth_Size_2 10
#define Smooth_Size_2 10
#define Smooth_TH_2 4
#define Smooth_Size_3 20
#define Smooth_Size_3 20
#define Smooth_TH_3 4
#define Smooth_Step_Size 5
#define Adaptive_SIR 1
@ -96,7 +96,7 @@
//8723A High Power IGI Setting
#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
// LPS define
@ -106,7 +106,7 @@
#define RSSI_OFFSET_DIG 0x05;
//ANT Test
#define ANTTESTALL 0x00 //Ant A or B will be Testing
#define ANTTESTALL 0x00 //Ant A or B will be Testing
#define ANTTESTA 0x01 //Ant A will be Testing
#define ANTTESTB 0x02 //Ant B will be testing
@ -150,8 +150,8 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
@ -304,12 +304,12 @@ typedef struct _SW_Antenna_Switch_
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte TrafficLoad;
RT_TIMER SwAntennaSwitchTimer;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte TrafficLoad;
RT_TIMER SwAntennaSwitchTimer;
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
#if USE_WORKITEM
RT_WORK_ITEM SwAntennaSwitchWorkitem;
@ -383,23 +383,23 @@ typedef struct _ODM_RATE_ADAPTIVE
//
typedef enum _HT_IOT_PEER
{
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
HT_IOT_PEER_REALTEK_92SE = 2,
HT_IOT_PEER_BROADCOM = 3,
HT_IOT_PEER_RALINK = 4,
HT_IOT_PEER_ATHEROS = 5,
HT_IOT_PEER_CISCO = 6,
HT_IOT_PEER_MERU = 7,
HT_IOT_PEER_MARVELL = 8,
HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
HT_IOT_PEER_AIRGO = 11,
HT_IOT_PEER_INTEL = 12,
HT_IOT_PEER_RTK_APCLIENT = 13,
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_MAX = 16
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
HT_IOT_PEER_REALTEK_92SE = 2,
HT_IOT_PEER_BROADCOM = 3,
HT_IOT_PEER_RALINK = 4,
HT_IOT_PEER_ATHEROS = 5,
HT_IOT_PEER_CISCO = 6,
HT_IOT_PEER_MERU = 7,
HT_IOT_PEER_MARVELL = 8,
HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
HT_IOT_PEER_AIRGO = 11,
HT_IOT_PEER_INTEL = 12,
HT_IOT_PEER_RTK_APCLIENT = 13,
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_MAX = 16
}HT_IOT_PEER_E, *PHTIOT_PEER_E;
#endif//#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
@ -510,7 +510,7 @@ typedef struct _ODM_STA_INFO{
u1Byte RXSNR[4];
//
// Please use compile flag to disable the struictrue for other IC except 88E.
// Please use compile flag to disable the struictrue for other IC except 88E.
// Move To lower layer.
//
// ODM Write Wilson will handle this part(said by Luke.Lee)
@ -651,22 +651,22 @@ typedef enum _ODM_Support_Ability_Definition
// ODM_CMNINFO_INTERFACE
typedef enum tag_ODM_Support_Interface_Definition
{
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
ODM_ITRF_SDIO = 0x4,
ODM_ITRF_ALL = 0x7,
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
ODM_ITRF_SDIO = 0x4,
ODM_ITRF_ALL = 0x7,
}ODM_INTERFACE_E;
// ODM_CMNINFO_IC_TYPE
typedef enum tag_ODM_Support_IC_Type_Definition
{
ODM_RTL8192S = BIT0,
ODM_RTL8192C = BIT1,
ODM_RTL8192D = BIT2,
ODM_RTL8723A = BIT3,
ODM_RTL8188E = BIT4,
ODM_RTL8812 = BIT5,
ODM_RTL8821 = BIT6,
ODM_RTL8192S = BIT0,
ODM_RTL8192C = BIT1,
ODM_RTL8192D = BIT2,
ODM_RTL8723A = BIT3,
ODM_RTL8188E = BIT4,
ODM_RTL8812 = BIT5,
ODM_RTL8821 = BIT6,
}ODM_IC_TYPE_E;
#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E)
@ -675,20 +675,20 @@ typedef enum tag_ODM_Support_IC_Type_Definition
//ODM_CMNINFO_CUT_VER
typedef enum tag_ODM_Cut_Version_Definition
{
ODM_CUT_A = 1,
ODM_CUT_B = 2,
ODM_CUT_C = 3,
ODM_CUT_D = 4,
ODM_CUT_E = 5,
ODM_CUT_F = 6,
ODM_CUT_TEST = 7,
ODM_CUT_A = 1,
ODM_CUT_B = 2,
ODM_CUT_C = 3,
ODM_CUT_D = 4,
ODM_CUT_E = 5,
ODM_CUT_F = 6,
ODM_CUT_TEST = 7,
}ODM_CUT_VERSION_E;
// ODM_CMNINFO_FAB_VER
typedef enum tag_ODM_Fab_Version_Definition
{
ODM_TSMC = 0,
ODM_UMC = 1,
ODM_TSMC = 0,
ODM_UMC = 1,
}ODM_FAB_E;
// ODM_CMNINFO_RF_TYPE
@ -697,8 +697,8 @@ typedef enum tag_ODM_Fab_Version_Definition
//
typedef enum tag_ODM_RF_Path_Bit_Definition
{
ODM_RF_TX_A = BIT0,
ODM_RF_TX_B = BIT1,
ODM_RF_TX_A = BIT0,
ODM_RF_TX_B = BIT1,
ODM_RF_TX_C = BIT2,
ODM_RF_TX_D = BIT3,
ODM_RF_RX_A = BIT4,
@ -710,8 +710,8 @@ typedef enum tag_ODM_RF_Path_Bit_Definition
typedef enum tag_ODM_RF_Type_Definition
{
ODM_1T1R = 0,
ODM_1T2R = 1,
ODM_1T1R = 0,
ODM_1T2R = 1,
ODM_2T2R = 2,
ODM_2T3R = 3,
ODM_2T4R = 4,
@ -741,22 +741,22 @@ typedef enum tag_ODM_MAC_PHY_Mode_Definition
typedef enum tag_BT_Coexist_Definition
{
ODM_BT_BUSY = 1,
ODM_BT_ON = 2,
ODM_BT_OFF = 3,
ODM_BT_NONE = 4,
ODM_BT_BUSY = 1,
ODM_BT_ON = 2,
ODM_BT_OFF = 3,
ODM_BT_NONE = 4,
}ODM_BT_COEXIST_E;
// ODM_CMNINFO_OP_MODE
typedef enum tag_Operation_Mode_Definition
{
ODM_NO_LINK = BIT0,
ODM_LINK = BIT1,
ODM_SCAN = BIT2,
ODM_POWERSAVE = BIT3,
ODM_AP_MODE = BIT4,
ODM_NO_LINK = BIT0,
ODM_LINK = BIT1,
ODM_SCAN = BIT2,
ODM_POWERSAVE = BIT3,
ODM_AP_MODE = BIT4,
ODM_CLIENT_MODE = BIT5,
ODM_AD_HOC = BIT6,
ODM_AD_HOC = BIT6,
ODM_WIFI_DIRECT = BIT7,
ODM_WIFI_DISPLAY = BIT8,
}ODM_OPERATION_MODE_E;
@ -777,40 +777,40 @@ typedef enum tag_Wireless_Mode_Definition
// ODM_CMNINFO_BAND
typedef enum tag_Band_Type_Definition
{
ODM_BAND_2_4G = BIT0,
ODM_BAND_5G = BIT1,
ODM_BAND_2_4G = BIT0,
ODM_BAND_5G = BIT1,
}ODM_BAND_TYPE_E;
// ODM_CMNINFO_SEC_CHNL_OFFSET
typedef enum tag_Secondary_Channel_Offset_Definition
{
ODM_DONT_CARE = 0,
ODM_BELOW = 1,
ODM_ABOVE = 2
ODM_DONT_CARE = 0,
ODM_BELOW = 1,
ODM_ABOVE = 2
}ODM_SEC_CHNL_OFFSET_E;
// ODM_CMNINFO_SEC_MODE
typedef enum tag_Security_Definition
{
ODM_SEC_OPEN = 0,
ODM_SEC_WEP40 = 1,
ODM_SEC_TKIP = 2,
ODM_SEC_RESERVE = 3,
ODM_SEC_AESCCMP = 4,
ODM_SEC_WEP104 = 5,
ODM_SEC_OPEN = 0,
ODM_SEC_WEP40 = 1,
ODM_SEC_TKIP = 2,
ODM_SEC_RESERVE = 3,
ODM_SEC_AESCCMP = 4,
ODM_SEC_WEP104 = 5,
ODM_WEP_WPA_MIXED = 6, // WEP + WPA
ODM_SEC_SMS4 = 7,
ODM_SEC_SMS4 = 7,
}ODM_SECURITY_E;
// ODM_CMNINFO_BW
typedef enum tag_Bandwidth_Definition
{
ODM_BW20M = 0,
ODM_BW40M = 1,
ODM_BW80M = 2,
ODM_BW160M = 3,
ODM_BW10M = 4,
ODM_BW20M = 0,
ODM_BW40M = 1,
ODM_BW80M = 2,
ODM_BW160M = 3,
ODM_BW10M = 4,
}ODM_BW_E;
// ODM_CMNINFO_CHNL
@ -818,9 +818,9 @@ typedef enum tag_Bandwidth_Definition
// ODM_CMNINFO_BOARD_TYPE
typedef enum tag_Board_Definition
{
ODM_BOARD_NORMAL = 0,
ODM_BOARD_NORMAL = 0,
ODM_BOARD_HIGHPWR = 1,
ODM_BOARD_MINICARD = 2,
ODM_BOARD_MINICARD = 2,
ODM_BOARD_SLIM = 3,
ODM_BOARD_COMBO = 4,
@ -871,7 +871,7 @@ typedef struct _ODM_RA_Info_
} ODM_RA_INFO_T,*PODM_RA_INFO_T;
typedef struct _IQK_MATRIX_REGS_SETTING{
BOOLEAN bIQKDone;
BOOLEAN bIQKDone;
s4Byte Value[1][IQK_Matrix_REG_NUM];
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
@ -906,22 +906,22 @@ typedef struct ODM_RF_Calibration_Structure
u4Byte RegA24; // for TempCCK
s4Byte RegE94;
s4Byte RegE9C;
s4Byte RegE9C;
s4Byte RegEB4;
s4Byte RegEBC;
//u1Byte bTXPowerTracking;
u1Byte TXPowercount;
u1Byte TXPowercount;
BOOLEAN bTXPowerTrackingInit;
BOOLEAN bTXPowerTracking;
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u1Byte TM_Trigger;
u1Byte InternalPA5G[2]; //pathA / pathB
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u1Byte TM_Trigger;
u1Byte InternalPA5G[2]; //pathA / pathB
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u1Byte ThermalValue;
u1Byte ThermalValue_LCK;
u1Byte ThermalValue_IQK;
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u1Byte ThermalValue;
u1Byte ThermalValue_LCK;
u1Byte ThermalValue_IQK;
u1Byte ThermalValue_DPK;
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
u1Byte ThermalValue_AVG_index;
@ -933,30 +933,30 @@ typedef struct ODM_RF_Calibration_Structure
BOOLEAN bDPKenable;
BOOLEAN bReloadtxpowerindex;
u1Byte bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
u1Byte bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
u1Byte bCCKinCH14;
u1Byte CCK_index;
u1Byte OFDM_index[2];
u1Byte bCCKinCH14;
u1Byte CCK_index;
u1Byte OFDM_index[2];
BOOLEAN bDoneTxpower;
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
u1Byte Delta_IQK;
u1Byte Delta_LCK;
//for IQK
u4Byte RegC04;
u4Byte Reg874;
u4Byte RegC08;
u4Byte RegB68;
u4Byte RegB6C;
u4Byte Reg870;
u4Byte Reg860;
u4Byte Reg864;
u4Byte RegC04;
u4Byte Reg874;
u4Byte RegC08;
u4Byte RegB68;
u4Byte RegB6C;
u4Byte Reg870;
u4Byte Reg860;
u4Byte Reg864;
BOOLEAN bIQKInitialized;
BOOLEAN bLCKInProgress;
@ -967,12 +967,12 @@ typedef struct ODM_RF_Calibration_Structure
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
//for APK
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
//
// ODM Dynamic common info value definition
@ -1004,15 +1004,15 @@ typedef struct _FAST_ANTENNA_TRAINNING_
typedef enum _FAT_STATE
{
FAT_NORMAL_STATE = 0,
FAT_TRAINING_STATE = 1,
FAT_TRAINING_STATE = 1,
}FAT_STATE_E, *PFAT_STATE_E;
typedef enum _ANT_DIV_TYPE
{
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
@ -1042,7 +1042,7 @@ struct DM_Out_Source_Dynamic_Mechanism_Structure
typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
#endif
{
//RT_TIMER FastAntTrainingTimer;
//RT_TIMER FastAntTrainingTimer;
//
// Add for different team use temporarily
//
@ -1142,7 +1142,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
u1Byte *pSecurity;
// BW info 20M/40M/80M = 0/1/2
u1Byte *pBandWidth;
// Central channel location Ch1/Ch2/....
// Central channel location Ch1/Ch2/....
u1Byte *pChannel; //central channel number
// Common info for 92D DMSP
@ -1164,15 +1164,15 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
BOOLEAN bWIFI_Display;
BOOLEAN bLinked;
u1Byte RSSI_Min;
u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
BOOLEAN bIsMPChip;
u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
BOOLEAN bIsMPChip;
BOOLEAN bOneEntryOnly;
// Common info for BTDM
BOOLEAN bBtDisabled; // BT is disabled
BOOLEAN bBtHsOperation; // BT HS mode is under progress
u1Byte btHsDigVal; // use BT rssi to decide the DIG value
BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
BOOLEAN bBtBusy; // BT is busy.
BOOLEAN bBtBusy; // BT is busy.
//------------CALL BY VALUE-------------//
//2 Define STA info.
@ -1181,7 +1181,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
#if (RATE_ADAPTIVE_SUPPORT == 1)
u2Byte CurrminRptTime;
u2Byte CurrminRptTime;
ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
#endif
//
@ -1251,7 +1251,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//PSD
BOOLEAN bUserAssignLevel;
RT_TIMER PSDTimer;
RT_TIMER PSDTimer;
u1Byte RSSI_BT; //come from BT
BOOLEAN bPSDinProcess;
BOOLEAN bDMInitialGainEnable;
@ -1281,10 +1281,10 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//
// ODM relative time.
RT_TIMER PathDivSwitchTimer;
RT_TIMER PathDivSwitchTimer;
//2011.09.27 add for Path Diversity
RT_TIMER CCKPathDiversityTimer;
RT_TIMER FastAntTrainingTimer;
RT_TIMER FastAntTrainingTimer;
// ODM relative workitem.
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
@ -1369,8 +1369,8 @@ typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
/*
@ -1489,8 +1489,8 @@ typedef enum tag_DIG_Connect_Definition
//3===========================================================
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
//3===========================================================
//3 BB Power Save
@ -1528,8 +1528,8 @@ typedef enum tag_SW_Antenna_Switch_Definition
//
// Extern Global Variables.
//
#define OFDM_TABLE_SIZE_92C 37
#define OFDM_TABLE_SIZE_92D 43
#define OFDM_TABLE_SIZE_92C 37
#define OFDM_TABLE_SIZE_92D 43
#define CCK_TABLE_SIZE 33
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D];
@ -1556,12 +1556,12 @@ extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
VOID ODM_Write_DIG(IN PDM_ODM_T pDM_Odm, IN u1Byte CurrentIGI);
VOID ODM_Write_DIG(IN PDM_ODM_T pDM_Odm, IN u1Byte CurrentIGI);
VOID ODM_Write_CCK_CCA_Thres(IN PDM_ODM_T pDM_Odm, IN u1Byte CurCCK_CCAThres);
VOID
ODM_SetAntenna(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN u1Byte Antenna);
@ -1572,7 +1572,7 @@ void ODM_RF_Saving( IN PDM_ODM_T pDM_Odm,
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm);
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
VOID
ODM_TXPowerTrackingCheck(
IN PDM_ODM_T pDM_Odm
@ -1670,7 +1670,7 @@ u4Byte ConvertTo_dB(u4Byte Value);
u4Byte
GetPSDData(
PDM_ODM_T pDM_Odm,
unsigned int point,
unsigned int point,
u1Byte initial_gain_psd);
#endif
@ -1685,8 +1685,8 @@ odm_DIGbyRSSI_LPS(
u4Byte ODM_Get_Rate_Bitmap(
IN PDM_ODM_T pDM_Odm,
IN u4Byte macid,
IN u4Byte ra_mask,
IN u1Byte rssi_level);
IN u4Byte ra_mask,
IN u1Byte rssi_level);
#endif
@ -1704,14 +1704,14 @@ VOID
PatchDCTone(
IN PDM_ODM_T pDM_Odm,
pu4Byte PSD_report,
u1Byte initial_gain_psd
u1Byte initial_gain_psd
);
VOID
ODM_PSDMonitor(
IN PDM_ODM_T pDM_Odm
);
VOID odm_PSD_Monitor(PDM_ODM_T pDM_Odm);
VOID odm_PSDMonitorInit(PDM_ODM_T pDM_Odm);
VOID odm_PSDMonitorInit(PDM_ODM_T pDM_Odm);
VOID
ODM_PSDDbgControl(
@ -1802,7 +1802,7 @@ VOID ODM_PathDivRestAfterLink(
#define TRAFFIC_LOW 0
#define TRAFFIC_HIGH 1
//#define PATHDIV_ENABLE 1
//#define PATHDIV_ENABLE 1
//VOID odm_PathDivChkAntSwitch(PADAPTER Adapter,u1Byte Step);
VOID ODM_PathDivRestAfterLink(
@ -1935,4 +1935,3 @@ void odm_dtc(PDM_ODM_T pDM_Odm);
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
#endif

81
include/odm_HWConfig.h
View file

@ -80,39 +80,39 @@ typedef struct _Phy_Rx_AGC_Info
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#ifdef __LITTLE_ENDIAN
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
@ -120,30 +120,30 @@ typedef struct _Phy_Status_Rpt_8192cd
typedef struct _Phy_Status_Rpt_8195
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
s1Byte sig_evm;
u1Byte rsvd_4;
#ifdef __LITTLE_ENDIAN
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // __BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
@ -157,14 +157,14 @@ VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
@ -174,22 +174,21 @@ ODM_MacStatusQuery(
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
IN ODM_RF_RADIO_PATH_E Content,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
);
#endif
#endif

1
include/odm_RTL8188E.h
View file

@ -106,4 +106,3 @@ odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm);
#endif

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