mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-15 09:29:35 +00:00
715 lines
20 KiB
C
715 lines
20 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#include "odm_precomp.h"
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#include <phy.h>
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#define read_next_pair(array, v1, v2, i) \
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do { \
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i += 2; \
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v1 = array[i]; \
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v2 = array[i+1]; \
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} while (0)
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/* AGC_TAB_1T.TXT */
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static u32 array_agc_tab_1t_8188e[] = {
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0xC78, 0xFB000001,
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0xC78, 0xFB010001,
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0xC78, 0xFB020001,
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0xC78, 0xFB030001,
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0xC78, 0xFB040001,
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0xC78, 0xFB050001,
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0xC78, 0xFA060001,
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0xC78, 0xF9070001,
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0xC78, 0xF8080001,
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0xC78, 0xF7090001,
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0xC78, 0xF60A0001,
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0xC78, 0xF50B0001,
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0xC78, 0xF40C0001,
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0xC78, 0xF30D0001,
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0xC78, 0xF20E0001,
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0xC78, 0xF10F0001,
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0xC78, 0xF0100001,
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0xC78, 0xEF110001,
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0xC78, 0xEE120001,
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0xC78, 0xED130001,
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0xC78, 0xEC140001,
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0xC78, 0xEB150001,
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0xC78, 0xEA160001,
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0xC78, 0xE9170001,
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0xC78, 0xE8180001,
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0xC78, 0xE7190001,
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0xC78, 0xE61A0001,
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0xC78, 0xE51B0001,
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0xC78, 0xE41C0001,
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0xC78, 0xE31D0001,
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0xC78, 0xE21E0001,
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0xC78, 0xE11F0001,
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0xC78, 0x8A200001,
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0xC78, 0x89210001,
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0xC78, 0x88220001,
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0xC78, 0x87230001,
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0xC78, 0x86240001,
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0xC78, 0x85250001,
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0xC78, 0x84260001,
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0xC78, 0x83270001,
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0xC78, 0x82280001,
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0xC78, 0x6B290001,
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0xC78, 0x6A2A0001,
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0xC78, 0x692B0001,
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0xC78, 0x682C0001,
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0xC78, 0x672D0001,
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0xC78, 0x662E0001,
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0xC78, 0x652F0001,
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0xC78, 0x64300001,
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0xC78, 0x63310001,
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0xC78, 0x62320001,
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0xC78, 0x61330001,
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0xC78, 0x46340001,
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0xC78, 0x45350001,
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0xC78, 0x44360001,
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0xC78, 0x43370001,
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0xC78, 0x42380001,
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0xC78, 0x41390001,
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0xC78, 0x403A0001,
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0xC78, 0x403B0001,
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0xC78, 0x403C0001,
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0xC78, 0x403D0001,
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0xC78, 0x403E0001,
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0xC78, 0x403F0001,
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0xC78, 0xFB400001,
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0xC78, 0xFB410001,
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0xC78, 0xFB420001,
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0xC78, 0xFB430001,
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0xC78, 0xFB440001,
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0xC78, 0xFB450001,
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0xC78, 0xFB460001,
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0xC78, 0xFB470001,
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0xC78, 0xFB480001,
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0xC78, 0xFA490001,
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0xC78, 0xF94A0001,
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0xC78, 0xF84B0001,
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0xC78, 0xF74C0001,
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0xC78, 0xF64D0001,
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0xC78, 0xF54E0001,
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0xC78, 0xF44F0001,
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0xC78, 0xF3500001,
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0xC78, 0xF2510001,
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0xC78, 0xF1520001,
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0xC78, 0xF0530001,
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0xC78, 0xEF540001,
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0xC78, 0xEE550001,
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0xC78, 0xED560001,
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0xC78, 0xEC570001,
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0xC78, 0xEB580001,
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0xC78, 0xEA590001,
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0xC78, 0xE95A0001,
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0xC78, 0xE85B0001,
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0xC78, 0xE75C0001,
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0xC78, 0xE65D0001,
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0xC78, 0xE55E0001,
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0xC78, 0xE45F0001,
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0xC78, 0xE3600001,
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0xC78, 0xE2610001,
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0xC78, 0xC3620001,
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0xC78, 0xC2630001,
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0xC78, 0xC1640001,
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0xC78, 0x8B650001,
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0xC78, 0x8A660001,
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0xC78, 0x89670001,
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0xC78, 0x88680001,
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0xC78, 0x87690001,
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0xC78, 0x866A0001,
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0xC78, 0x856B0001,
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0xC78, 0x846C0001,
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0xC78, 0x676D0001,
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0xC78, 0x666E0001,
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0xC78, 0x656F0001,
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0xC78, 0x64700001,
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0xC78, 0x63710001,
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0xC78, 0x62720001,
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0xC78, 0x61730001,
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0xC78, 0x60740001,
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0xC78, 0x46750001,
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0xC78, 0x45760001,
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0xC78, 0x44770001,
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0xC78, 0x43780001,
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0xC78, 0x42790001,
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0xC78, 0x417A0001,
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0xC78, 0x407B0001,
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0xC78, 0x407C0001,
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0xC78, 0x407D0001,
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0xC78, 0x407E0001,
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0xC78, 0x407F0001,
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};
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static bool set_baseband_agc_config(struct adapter *adapt)
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{
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u32 i;
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u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32);
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u32 *array = array_agc_tab_1t_8188e;
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for (i = 0; i < arraylen; i += 2) {
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u32 v1 = array[i];
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u32 v2 = array[i+1];
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if (v1 < 0xCDCDCDCD) {
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phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
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udelay(1);
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}
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}
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return true;
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}
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/* PHY_REG_1T.TXT */
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static u32 array_phy_reg_1t_8188e[] = {
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0x800, 0x80040000,
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0x804, 0x00000003,
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0x808, 0x0000FC00,
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0x80C, 0x0000000A,
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0x810, 0x10001331,
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0x814, 0x020C3D10,
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0x818, 0x02200385,
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0x81C, 0x00000000,
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0x820, 0x01000100,
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0x824, 0x00390204,
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0x828, 0x00000000,
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0x82C, 0x00000000,
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0x830, 0x00000000,
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0x834, 0x00000000,
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0x838, 0x00000000,
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0x83C, 0x00000000,
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0x840, 0x00010000,
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0x844, 0x00000000,
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0x848, 0x00000000,
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0x84C, 0x00000000,
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0x850, 0x00000000,
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0x854, 0x00000000,
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0x858, 0x569A11A9,
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0x85C, 0x01000014,
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0x860, 0x66F60110,
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0x864, 0x061F0649,
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0x868, 0x00000000,
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0x86C, 0x27272700,
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0x870, 0x07000760,
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0x874, 0x25004000,
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0x878, 0x00000808,
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0x87C, 0x00000000,
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0x880, 0xB0000C1C,
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0x884, 0x00000001,
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0x888, 0x00000000,
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0x88C, 0xCCC000C0,
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0x890, 0x00000800,
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0x894, 0xFFFFFFFE,
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0x898, 0x40302010,
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0x89C, 0x00706050,
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0x900, 0x00000000,
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0x904, 0x00000023,
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0x908, 0x00000000,
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0x90C, 0x81121111,
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0x910, 0x00000002,
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0x914, 0x00000201,
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0xA00, 0x00D047C8,
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0xA04, 0x80FF000C,
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0xA08, 0x8C838300,
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0xA0C, 0x2E7F120F,
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0xA10, 0x9500BB78,
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0xA14, 0x1114D028,
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0xA18, 0x00881117,
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0xA1C, 0x89140F00,
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0xA20, 0x1A1B0000,
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0xA24, 0x090E1317,
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0xA28, 0x00000204,
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0xA2C, 0x00D30000,
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0xA70, 0x101FBF00,
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0xA74, 0x00000007,
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0xA78, 0x00000900,
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0xA7C, 0x225B0606,
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0xA80, 0x218075B1,
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0xB2C, 0x80000000,
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0xC00, 0x48071D40,
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0xC04, 0x03A05611,
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0xC08, 0x000000E4,
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0xC0C, 0x6C6C6C6C,
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0xC10, 0x08800000,
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0xC14, 0x40000100,
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0xC18, 0x08800000,
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0xC1C, 0x40000100,
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0xC20, 0x00000000,
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0xC24, 0x00000000,
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0xC28, 0x00000000,
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0xC2C, 0x00000000,
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0xC30, 0x69E9AC47,
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0xC34, 0x469652AF,
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0xC38, 0x49795994,
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0xC3C, 0x0A97971C,
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0xC40, 0x1F7C403F,
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0xC44, 0x000100B7,
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0xC48, 0xEC020107,
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0xC4C, 0x007F037F,
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0xC50, 0x69553420,
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0xC54, 0x43BC0094,
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0xC58, 0x00013169,
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0xC5C, 0x00250492,
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0xC60, 0x00000000,
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0xC64, 0x7112848B,
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0xC68, 0x47C00BFF,
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0xC6C, 0x00000036,
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0xC70, 0x2C7F000D,
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0xC74, 0x020610DB,
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0xC78, 0x0000001F,
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0xC7C, 0x00B91612,
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0xC80, 0x390000E4,
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0xC84, 0x20F60000,
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0xC88, 0x40000100,
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0xC8C, 0x20200000,
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0xC90, 0x00091521,
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0xC94, 0x00000000,
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0xC98, 0x00121820,
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0xC9C, 0x00007F7F,
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0xCA0, 0x00000000,
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0xCA4, 0x000300A0,
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0xCA8, 0x00000000,
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0xCAC, 0x00000000,
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0xCB0, 0x00000000,
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0xCB4, 0x00000000,
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0xCB8, 0x00000000,
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0xCBC, 0x28000000,
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0xCC0, 0x00000000,
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0xCC4, 0x00000000,
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0xCC8, 0x00000000,
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0xCCC, 0x00000000,
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0xCD0, 0x00000000,
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0xCD4, 0x00000000,
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0xCD8, 0x64B22427,
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0xCDC, 0x00766932,
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0xCE0, 0x00222222,
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0xCE4, 0x00000000,
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0xCE8, 0x37644302,
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0xCEC, 0x2F97D40C,
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0xD00, 0x00000740,
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0xD04, 0x00020401,
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0xD08, 0x0000907F,
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0xD0C, 0x20010201,
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0xD10, 0xA0633333,
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0xD14, 0x3333BC43,
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0xD18, 0x7A8F5B6F,
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0xD2C, 0xCC979975,
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0xD30, 0x00000000,
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0xD34, 0x80608000,
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0xD38, 0x00000000,
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0xD3C, 0x00127353,
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0xD40, 0x00000000,
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0xD44, 0x00000000,
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0xD48, 0x00000000,
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0xD4C, 0x00000000,
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0xD50, 0x6437140A,
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0xD54, 0x00000000,
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0xD58, 0x00000282,
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0xD5C, 0x30032064,
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0xD60, 0x4653DE68,
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0xD64, 0x04518A3C,
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0xD68, 0x00002101,
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0xD6C, 0x2A201C16,
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0xD70, 0x1812362E,
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0xD74, 0x322C2220,
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0xD78, 0x000E3C24,
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0xE00, 0x2D2D2D2D,
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0xE04, 0x2D2D2D2D,
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0xE08, 0x0390272D,
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0xE10, 0x2D2D2D2D,
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0xE14, 0x2D2D2D2D,
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0xE18, 0x2D2D2D2D,
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0xE1C, 0x2D2D2D2D,
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0xE28, 0x00000000,
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0xE30, 0x1000DC1F,
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0xE34, 0x10008C1F,
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0xE38, 0x02140102,
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0xE3C, 0x681604C2,
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0xE40, 0x01007C00,
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0xE44, 0x01004800,
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0xE48, 0xFB000000,
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0xE4C, 0x000028D1,
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0xE50, 0x1000DC1F,
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0xE54, 0x10008C1F,
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0xE58, 0x02140102,
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0xE5C, 0x28160D05,
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0xE60, 0x00000008,
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0xE68, 0x001B25A4,
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0xE6C, 0x00C00014,
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0xE70, 0x00C00014,
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0xE74, 0x01000014,
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0xE78, 0x01000014,
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0xE7C, 0x01000014,
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0xE80, 0x01000014,
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0xE84, 0x00C00014,
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0xE88, 0x01000014,
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0xE8C, 0x00C00014,
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0xED0, 0x00C00014,
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0xED4, 0x00C00014,
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0xED8, 0x00C00014,
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0xEDC, 0x00000014,
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0xEE0, 0x00000014,
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0xEEC, 0x01C00014,
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0xF14, 0x00000003,
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0xF4C, 0x00000000,
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0xF00, 0x00000300,
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};
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static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
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{
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if (addr == 0xfe) {
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msleep(50);
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} else if (addr == 0xfd) {
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mdelay(5);
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} else if (addr == 0xfc) {
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mdelay(1);
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} else if (addr == 0xfb) {
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udelay(50);
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} else if (addr == 0xfa) {
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udelay(5);
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} else if (addr == 0xf9) {
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udelay(1);
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} else {
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phy_set_bb_reg(adapt, addr, bMaskDWord, data);
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/* Add 1us delay between BB/RF register setting. */
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udelay(1);
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}
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}
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static bool set_baseband_phy_config(struct adapter *adapt)
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{
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u32 i;
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u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32);
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u32 *array = array_phy_reg_1t_8188e;
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for (i = 0; i < arraylen; i += 2) {
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u32 v1 = array[i];
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u32 v2 = array[i+1];
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if (v1 < 0xCDCDCDCD)
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rtl_bb_delay(adapt, v1, v2);
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}
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return true;
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}
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/* PHY_REG_PG.TXT */
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static u32 array_phy_reg_pg_8188e[] = {
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0xE00, 0xFFFFFFFF, 0x06070809,
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0xE04, 0xFFFFFFFF, 0x02020405,
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0xE08, 0x0000FF00, 0x00000006,
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0x86C, 0xFFFFFF00, 0x00020400,
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0xE10, 0xFFFFFFFF, 0x08090A0B,
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0xE14, 0xFFFFFFFF, 0x01030607,
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0xE18, 0xFFFFFFFF, 0x08090A0B,
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0xE1C, 0xFFFFFFFF, 0x01030607,
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0xE00, 0xFFFFFFFF, 0x00000000,
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0xE04, 0xFFFFFFFF, 0x00000000,
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0xE08, 0x0000FF00, 0x00000000,
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0x86C, 0xFFFFFF00, 0x00000000,
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0xE10, 0xFFFFFFFF, 0x00000000,
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0xE14, 0xFFFFFFFF, 0x00000000,
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0xE18, 0xFFFFFFFF, 0x00000000,
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0xE1C, 0xFFFFFFFF, 0x00000000,
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0xE00, 0xFFFFFFFF, 0x02020202,
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0xE04, 0xFFFFFFFF, 0x00020202,
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0xE08, 0x0000FF00, 0x00000000,
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0x86C, 0xFFFFFF00, 0x00000000,
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0xE10, 0xFFFFFFFF, 0x04040404,
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0xE14, 0xFFFFFFFF, 0x00020404,
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0xE18, 0xFFFFFFFF, 0x00000000,
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0xE1C, 0xFFFFFFFF, 0x00000000,
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0xE00, 0xFFFFFFFF, 0x02020202,
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0xE04, 0xFFFFFFFF, 0x00020202,
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0xE08, 0x0000FF00, 0x00000000,
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0x86C, 0xFFFFFF00, 0x00000000,
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0xE10, 0xFFFFFFFF, 0x04040404,
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0xE14, 0xFFFFFFFF, 0x00020404,
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0xE18, 0xFFFFFFFF, 0x00000000,
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0xE1C, 0xFFFFFFFF, 0x00000000,
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0xE00, 0xFFFFFFFF, 0x00000000,
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0xE04, 0xFFFFFFFF, 0x00000000,
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0xE08, 0x0000FF00, 0x00000000,
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0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x00000000,
|
|
0xE14, 0xFFFFFFFF, 0x00000000,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
0xE00, 0xFFFFFFFF, 0x02020202,
|
|
0xE04, 0xFFFFFFFF, 0x00020202,
|
|
0xE08, 0x0000FF00, 0x00000000,
|
|
0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x04040404,
|
|
0xE14, 0xFFFFFFFF, 0x00020404,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
0xE00, 0xFFFFFFFF, 0x00000000,
|
|
0xE04, 0xFFFFFFFF, 0x00000000,
|
|
0xE08, 0x0000FF00, 0x00000000,
|
|
0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x00000000,
|
|
0xE14, 0xFFFFFFFF, 0x00000000,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
0xE00, 0xFFFFFFFF, 0x00000000,
|
|
0xE04, 0xFFFFFFFF, 0x00000000,
|
|
0xE08, 0x0000FF00, 0x00000000,
|
|
0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x00000000,
|
|
0xE14, 0xFFFFFFFF, 0x00000000,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
0xE00, 0xFFFFFFFF, 0x00000000,
|
|
0xE04, 0xFFFFFFFF, 0x00000000,
|
|
0xE08, 0x0000FF00, 0x00000000,
|
|
0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x00000000,
|
|
0xE14, 0xFFFFFFFF, 0x00000000,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
0xE00, 0xFFFFFFFF, 0x00000000,
|
|
0xE04, 0xFFFFFFFF, 0x00000000,
|
|
0xE08, 0x0000FF00, 0x00000000,
|
|
0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x00000000,
|
|
0xE14, 0xFFFFFFFF, 0x00000000,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
0xE00, 0xFFFFFFFF, 0x00000000,
|
|
0xE04, 0xFFFFFFFF, 0x00000000,
|
|
0xE08, 0x0000FF00, 0x00000000,
|
|
0x86C, 0xFFFFFF00, 0x00000000,
|
|
0xE10, 0xFFFFFFFF, 0x00000000,
|
|
0xE14, 0xFFFFFFFF, 0x00000000,
|
|
0xE18, 0xFFFFFFFF, 0x00000000,
|
|
0xE1C, 0xFFFFFFFF, 0x00000000,
|
|
|
|
};
|
|
|
|
static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data)
|
|
{
|
|
struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
|
|
|
|
if (regaddr == rTxAGC_A_Rate18_06)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][0] = data;
|
|
if (regaddr == rTxAGC_A_Rate54_24)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][1] = data;
|
|
if (regaddr == rTxAGC_A_CCK1_Mcs32)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][6] = data;
|
|
if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][7] = data;
|
|
if (regaddr == rTxAGC_A_Mcs03_Mcs00)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][2] = data;
|
|
if (regaddr == rTxAGC_A_Mcs07_Mcs04)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][3] = data;
|
|
if (regaddr == rTxAGC_A_Mcs11_Mcs08)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][4] = data;
|
|
if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][5] = data;
|
|
if (hal_data->rf_type == RF_1T1R)
|
|
hal_data->pwrGroupCnt++;
|
|
}
|
|
if (regaddr == rTxAGC_B_Rate18_06)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][8] = data;
|
|
if (regaddr == rTxAGC_B_Rate54_24)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][9] = data;
|
|
if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][14] = data;
|
|
if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][15] = data;
|
|
if (regaddr == rTxAGC_B_Mcs03_Mcs00)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][10] = data;
|
|
if (regaddr == rTxAGC_B_Mcs07_Mcs04)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][11] = data;
|
|
if (regaddr == rTxAGC_B_Mcs11_Mcs08)
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][12] = data;
|
|
if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
|
|
hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][13] = data;
|
|
if (hal_data->rf_type != RF_1T1R)
|
|
hal_data->pwrGroupCnt++;
|
|
}
|
|
}
|
|
|
|
static void rtl_addr_delay(struct adapter *adapt, u32 addr, u32 bit_mask, u32 data)
|
|
{
|
|
if (addr == 0xfe) {
|
|
msleep(50);
|
|
} else if (addr == 0xfd) {
|
|
mdelay(5);
|
|
} else if (addr == 0xfc) {
|
|
mdelay(1);
|
|
} else if (addr == 0xfb) {
|
|
udelay(50);
|
|
} else if (addr == 0xfa) {
|
|
udelay(5);
|
|
} else if (addr == 0xf9) {
|
|
udelay(1);
|
|
} else{
|
|
store_pwrindex_offset(adapt, addr, bit_mask, data);
|
|
}
|
|
}
|
|
|
|
static bool config_bb_with_pgheader(struct adapter *adapt)
|
|
{
|
|
u32 i = 0;
|
|
u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32);
|
|
u32 *array = array_phy_reg_pg_8188e;
|
|
|
|
for (i = 0; i < arraylen; i += 3) {
|
|
u32 v1 = array[i];
|
|
u32 v2 = array[i+1];
|
|
u32 v3 = array[i+2];
|
|
|
|
if (v1 < 0xCDCDCDCD)
|
|
rtl_addr_delay(adapt, v1, v2, v3);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter)
|
|
{
|
|
struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
|
|
hal_data->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
|
|
hal_data->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
|
|
hal_data->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
|
|
|
|
hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
|
|
hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
|
|
}
|
|
|
|
static bool config_parafile(struct adapter *adapt)
|
|
{
|
|
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt);
|
|
struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
|
|
|
|
set_baseband_phy_config(adapt);
|
|
|
|
/* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
|
|
if (!pEEPROM->bautoload_fail_flag) {
|
|
hal_data->pwrGroupCnt = 0;
|
|
config_bb_with_pgheader(adapt);
|
|
}
|
|
set_baseband_agc_config(adapt);
|
|
return true;
|
|
}
|
|
|
|
bool rtl88eu_phy_bb_config(struct adapter *adapt)
|
|
{
|
|
int rtstatus = true;
|
|
struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
|
|
u32 regval;
|
|
u8 crystal_cap;
|
|
|
|
rtl88e_phy_init_bb_rf_register_definition(adapt);
|
|
|
|
/* Enable BB and RF */
|
|
regval = usb_read16(adapt, REG_SYS_FUNC_EN);
|
|
usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1));
|
|
|
|
usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
|
|
|
|
usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
|
|
|
|
/* Config BB and AGC */
|
|
rtstatus = config_parafile(adapt);
|
|
|
|
/* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
|
|
crystal_cap = hal_data->CrystalCap & 0x3F;
|
|
phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6)));
|
|
|
|
return rtstatus;
|
|
}
|